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arch: riscv: the s0 dumped during a fatal error is not correct #79298

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ycsin opened this issue Oct 2, 2024 · 1 comment · Fixed by #79096 or #79299
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arch: riscv: the s0 dumped during a fatal error is not correct #79298

ycsin opened this issue Oct 2, 2024 · 1 comment · Fixed by #79096 or #79299
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@kgugala @tgorochowik @fkokosinski
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area: RISCV RISCV Architecture (32-bit & 64-bit) bug The issue is a bug, or the PR is fixing a bug

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@ycsin
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ycsin commented Oct 2, 2024

Describe the bug
The content of the s0 register dump during a fatal error is not the one at the time of the crash. On exception the isr.S, made a copy of the s0 register and then made some changes to the reg, but it didn't restore the s0 to the saved value before it jumps to the z_riscv_fatal_error_csf().

To Reproduce

  1. Run the test added in arch: riscv: isr.S: restore s0 before jumping to z_riscv_fatal_error_csf #79096 with Zephyr v3.7-branch
  2. The test will fail

Expected behavior
The test should pass

Impact
Incorrect s0 content shown in the fatal error message
@ycsin ycsin added the bug The issue is a bug, or the PR is fixing a bug label Oct 2, 2024
@ycsin ycsin linked a pull request Oct 2, 2024 that will close this issue
arch: riscv: isr.S: restore s0 before jumping to z_riscv_fatal_error_csf #79096
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This was referenced Oct 2, 2024
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@ycsin ycsin linked a pull request Oct 2, 2024 that will close this issue
[Backport v3.7-branch] arch: riscv: isr.S: restore s0 before jumping to z_riscv_fatal_error_csf #79299
Merged
@henrikbrixandersen henrikbrixandersen added the area: RISCV RISCV Architecture (32-bit & 64-bit) label Oct 3, 2024
@fkokosinski
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I believe this one should have been closed automaically when #79299 and #79096 were merged.

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@kgugala kgugala

@tgorochowik tgorochowik

@fkokosinski fkokosinski

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area: RISCV RISCV Architecture (32-bit & 64-bit) bug The issue is a bug, or the PR is fixing a bug
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@henrikbrixandersen @ycsin @kgugala @tgorochowik @fkokosinski