diff --git a/src/hardware/cpu/mesi.c b/src/hardware/cpu/mesi.c
index 961b814..a36b447 100644
--- a/src/hardware/cpu/mesi.c
+++ b/src/hardware/cpu/mesi.c
@@ -30,8 +30,8 @@ typedef struct
 
 cacheline_t cache[NUM_PROCESSOR];
 
-// the value on L3 shared cache
-int l3_value = 15213;
+// the value on mem shared cache
+int mem_value = 15213;
 
 // count the number of each state: MESI
 int state_count[4];
@@ -116,7 +116,7 @@ int read_cacheline(int i)
                 if (cache[j].state == SHARED)
                 {
                     // there exists multiple copies in the chip
-                    // copy from here to avoid I/O to l3
+                    // copy from here to avoid I/O to mem
                     cache[i].state = SHARED;
                     cache[i].value = cache[j].value;
 #ifdef DEBUG
@@ -127,7 +127,7 @@ int read_cacheline(int i)
                 else if (cache[j].state == EXCLUSIVE)
                 {
                     // there exists only one copy in the chip here
-                    // copy from here to avoid I/O to l3
+                    // copy from here to avoid I/O to mem
                     cache[i].state = SHARED;
                     cache[i].value = cache[j].value;
 
@@ -140,12 +140,12 @@ int read_cacheline(int i)
                 else if (cache[j].state == MODIFIED)
                 {
                     // there exists only one copy in the chip here
-                    // but it's DIRTY! write it back to l3
-                    // do I/O transaction over the bus to l3
-                    // copy from here to avoid I/O to l3
+                    // but it's DIRTY! write it back to mem
+                    // do I/O transaction over the bus to mem
+                    // copy from here to avoid I/O to mem
 
                     // write back the dirty data
-                    l3_value = cache[j].value;
+                    mem_value = cache[j].value;
                     cache[j].state = SHARED;
 
                     // copy from the NOW shared cache line
@@ -162,9 +162,9 @@ int read_cacheline(int i)
         // no return before means:
         // all other cache lines are invalid
         cache[i].state = EXCLUSIVE;     // so I am the only copy among all processors
-        cache[i].value = l3_value;      // do one I/O transaction over bus to l3
+        cache[i].value = mem_value;      // do one I/O transaction over bus to mem
 #ifdef DEBUG
-        printf("[%d] read miss; L3 shared cache supplies data %d ** BUS READ **\n", i, l3_value);
+        printf("[%d] read miss; mem shared cache supplies data %d ** BUS READ **\n", i, mem_value);
 #endif
         return 1;
     }
@@ -227,11 +227,14 @@ int write_cacheline(int i, int value)
             {
                 if (cache[j].state == MODIFIED)
                 {
+                    // RWITM: read with intent to modify
+                    cache[i].value = mem_value;
                     // existing only one modified copy, just invalid it
-                    // no bus transaction here, no I/O to l3
+                    // no bus transaction here, no I/O to mem
                     cache[j].state = INVALID;
                     cache[j].value = 0;
                     // update the current cache
+                    // re-issue RWITM
                     cache[i].state = MODIFIED;
                     cache[i].value = value;
 #ifdef DEBUG
@@ -241,8 +244,10 @@ int write_cacheline(int i, int value)
                 }
                 else if (cache[j].state == EXCLUSIVE)
                 {
+                    // RWITM: read with intent to modify
+                    cache[i].value = mem_value;
                     // existing only one Exclusive copy, just invalid it
-                    // no bus transaction here, no I/O to l3
+                    // no bus transaction here, no I/O to mem
                     cache[j].state = INVALID;
                     cache[j].value = 0;
                     // update the current cache
@@ -255,6 +260,8 @@ int write_cacheline(int i, int value)
                 }
                 else if (cache[j].state == SHARED)
                 {
+                    // RWITM: read with intent to modify
+                    cache[i].value = mem_value;
                     // existing multiple clean copies, must invalid all of them
                     for (int k = 0; k < NUM_PROCESSOR; ++ k)
                     {
@@ -276,7 +283,9 @@ int write_cacheline(int i, int value)
         }
 
         // all other processors are not holding any copy
-        // need to load from l3
+        // why protocol needs to load from mem in this case?
+        cache[i].value = mem_value;
+        // then update to modified with value
         cache[i].state = MODIFIED;
         cache[i].value = value;
 #ifdef DEBUG
@@ -293,14 +302,14 @@ int evict_cacheline(int i)
 {
     if (cache[i].state == MODIFIED)
     {
-        // write back to l3 and transit to invalid
-        l3_value = cache[i].value;
+        // write back to mem and transit to invalid
+        mem_value = cache[i].value;
 
         // invalid this cache line since the physical address is no longer in the cache
         cache[i].state = INVALID;
         cache[i].value = 0;
 #ifdef DEBUG
-        printf("[%d] evict; write back value %d ** BUS WRITE **\n", i, l3_value);
+        printf("[%d] evict; write back value %d ** BUS WRITE **\n", i, mem_value);
 #endif 
         return 1;
     }
@@ -346,7 +355,7 @@ void print_cache()
 
         printf("\t[%4d]   state %c   value %d\n", i, c, cache[i].value);
     }
-        printf("                            L3 Shared cache copy: %d\n", l3_value);
+        printf("                            mem Shared cache copy: %d\n", mem_value);
 }
 #endif
 
@@ -365,7 +374,7 @@ int main()
 #endif
 
     int pc = 0;
-    for (int i = 0; i < 20000; ++ i)
+    for (int i = 0; i < 200000; ++ i)
     {
         int op_case = rand() % 3;
         int index_proc = rand() % NUM_PROCESSOR;
@@ -399,4 +408,4 @@ int main()
 
     printf("Pass\n");
     return 0;
-}
\ No newline at end of file
+}