RISC SoftCore is a dyadic-purpose VHDL implementation of the RISCV RV32IM instruction set. This particular version does not implement a pipeline. The idea is to create a microcontroller with common peripherals such as I2C, USART, SPI and GPIOs initially used for the discipline of Programmable Logic Devices.
Programming/compiler tools can be obtained from this link.
Check in-depth architecture here: Virgularor, a minimum RISC-V
Check here a assembly simulator based on Mars
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Simulation:
- Run this script testbench.do in Modelsim (Altera Edition).
- Main testbench: testbench.vhd.Simulates the core, a timer and general purpose pins (gpio and 7-segment display).
- Check that the program file is pointed correctly (i.e.: ./software/quartus_blink.hex) in module iram_quartus.vhdl.
- See this complete diagram
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Synthesis: Quartus 19.1 or higher (tested in the DE10- Lite development Kit)
- Open the generic project at ./peripherals/gpio/sint/de10_lite/
- For post-synthesis software programming :
- Quartus Main Menu: Tools -> In-System Memory Editor
Compilation requires the toolchain riscv-none-elf (or riscv-none-embed) supporting the subset RV32IM, without ABI. At ./software/ folder, there are several examples. Note that in the current phase of the project we use a custom linker script (sections.ld). libc has not yet been tested/supported.
See here more information in order to install gcc compiler.