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ARM-Cortex-M, STM32 and RP2040 MCUs

ARM-Cortex-M

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Limited. These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices.[1] Though they are most often the main component of microcontroller chips, sometimes they are embedded inside other types of chips too.

ARM Cortex-M has three groups:

• Cortex-M series for microcontrollers (M stands for microcontroller) • Cortex-R series for real-time embedded systems (R stands for real-time) • Cortex-A series for high-performance applications (A stands for application)

STM32

STM32 is a family of 32-bit MCU by STMicroelectronics. The STM32 chips are grouped into related series that are based around the same 32-bit ARM processor core, such as:

  • Cortex-M33F
  • Cortex-M7F
  • Cortex-M4F
  • Cortex-M3
  • Cortex-M0+
  • Cortex-M0

The F means with FPU (Floating Point Unit).

Internally, each MCU consists of the processor core, static RAM, flash memory, debugging interface, and various peripherals.

The company behind the ARM trademark (Arm Holdings) doesn’t actually manufacture chips for purchase. Instead, their primary business model is to just design parts of chips. They will then license those designs to manufacturers, who will in turn implement the designs (perhaps with some of their own tweaks) in the form of physical hardware that can then be sold.

Raspberry Pi RP2040

RP2040 is the debut microcontroller from Raspberry Pi. It brings our signature values of high performance, low cost, and ease of use to the microcontroller space.

With a large on-chip memory, symmetric dual-core processor complex, deterministic bus fabric, and rich peripheral set augmented with our unique Programmable I/O (PIO) subsystem, it provides professional users with unrivalled power and flexibility. With detailed documentation, a polished MicroPython port, and a UF2 bootloader in ROM, it has the lowest possible barrier to entry for beginner and hobbyist users.

RP2040 is a stateless device, with support for cached execute-in-place from external QSPI memory. This design decision allows you to choose the appropriate density of non-volatile storage for your application, and to benefit from the low pricing of commodity Flash parts.

RP2040 is manufactured on a modern 40nm process node, delivering high performance, low dynamic power consumption, and low leakage, with a variety of low-power modes to support extended-duration operation on battery power

Key features:

  • Dual ARM Cortex-M0+ @ 133MHz
  • 264kB on-chip SRAM in six independent banks
  • Support for up to 16MB of off-chip Flash memory via dedicated QSPI bus
  • DMA controller
  • Fully-connected AHB crossbar
  • Interpolator and integer divider peripherals
  • On-chip programmable LDO to generate core voltage
  • 2 on-chip PLLs to generate USB and core clocks
  • 30 GPIO pins, 4 of which can be used as analogue inputs
  • Peripherals
    • 2 UARTs
    • 2 SPI controllers
    • 2 I2C controllers
    • 16 PWM channels
    • USB 1.1 controller and PHY, with host and device support
    • 8 PIO state machine

Cortex-M0+

RP2040 has 2 of this processor, that means RP2040 is 32bit RISC architecture.

The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools.

The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer.

The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.

Key features of the Cortex-M0+ core are:

  • ARMv6-M architecture (as a subset of the ARMv7-M profile with fewer instructions.)
  • 2-stage pipeline (one fewer than Cortex-M0)
  • Instruction sets: (same as Cortex-M0)
  • Thumb-1 (most), missing CBZ, CBNZ, IT
  • Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR
  • 32-bit hardware integer multiply with 32-bit result
  • 1 to 32 interrupts, plus NMI

Silicon options:

  • Hardware integer multiply speed: 1 or 32 cycles
  • 8-region memory protection unit (MPU) (same as M3 and M4)
  • Vector table relocation (same as M3, M4)
  • Single-cycle I/O port (available in M0+/M23)
  • Micro Trace Buffer (MTB) (available in M0+/M23/M33/M35P)