diff --git a/src/main/scala/rift2Core/backend/Commit.scala b/src/main/scala/rift2Core/backend/Commit.scala index 02cd3b17..d07895ac 100644 --- a/src/main/scala/rift2Core/backend/Commit.scala +++ b/src/main/scala/rift2Core/backend/Commit.scala @@ -601,12 +601,12 @@ trait CommitInfoMMU{ this: CommitState => trait CommitInfoLsu{ this: CommitState => io.cmm_lsu.is_amo_pending := { - io.rod(0).valid & io.rod(0).bits.is_amo & ~io.xCommit(0).is_writeback //only pending amo in rod0 is send out + io.rod(0).valid & ( io.rod(0).bits.is_amo | io.rod(0).bits.is_sc) & ~io.xCommit(0).is_writeback //only pending amo in rod0 is send out } println("Warning, amo_pending can only emmit at chn0") ( 0 until cmChn ).map{ i => - io.cmm_lsu.is_store_commit(i) := io.rod(i).bits.isXFStore & commit_state_is_comfirm(i) + io.cmm_lsu.is_store_commit(i) := ( io.rod(i).bits.isXFStore & ~io.rod(i).bits.is_sc )& commit_state_is_comfirm(i) } diff --git a/src/main/scala/rift2Core/backend/LSU/Dcache.scala b/src/main/scala/rift2Core/backend/LSU/Dcache.scala index 298bc55f..e53a4582 100644 --- a/src/main/scala/rift2Core/backend/LSU/Dcache.scala +++ b/src/main/scala/rift2Core/backend/LSU/Dcache.scala @@ -46,11 +46,11 @@ class Cache_op extends Lsu_isa { def is_atom = is_amo def is_access = is_atom | is_lu | is_su | is_lr | is_sc | isVLoad | isVStore def is_tag_r = is_atom | is_lu | is_su | is_lr | is_sc | isVLoad | isVStore | grant | probe | preft - def is_dat_r = is_atom | is_lu | isVLoad | is_lr | grant | probe + // def is_dat_r = is_atom | is_lu | isVLoad | is_lr | grant | probe def is_tag_w = grant def is_dat_w = is_atom | is_su | is_sc | isVStore | grant def isDirtyOp = is_atom | is_su | is_sc | isVStore - def is_wb = is_atom | is_lu | is_lr | isVStore + def is_wb = is_atom | is_lu | is_lr | is_sc | isVStore } diff --git a/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala b/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala index 7d73838a..00a41523 100644 --- a/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala +++ b/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala @@ -162,7 +162,7 @@ trait DcacheStageLRSC { this: DcacheStageBase => assert( pipeStage1Bits.fun.isDubl | pipeStage1Bits.fun.isWord ) } .elsewhen( pipeStage1Bits.fun.is_sc ) { is_pending_lr := false.B - } .elsewhen( (pipeStage1Bits.fun.is_su | (pipeStage1Bits.fun.is_amo & ~pipeStage1Bits.fun.is_lrsc)) ) { + } .elsewhen( pipeStage1Bits.fun.is_su | pipeStage1Bits.fun.is_amo ) { when( tagInfoW === lr_addr(plen-1,plen-tag_w) ) { is_pending_lr := false.B } diff --git a/src/main/scala/rift2Core/backend/LSU/Lsu.scala b/src/main/scala/rift2Core/backend/LSU/Lsu.scala index d4c37b1e..bdbd26d2 100644 --- a/src/main/scala/rift2Core/backend/LSU/Lsu.scala +++ b/src/main/scala/rift2Core/backend/LSU/Lsu.scala @@ -216,7 +216,7 @@ trait LSU_OpMux { this: LsuBase => opStIO.bits := 0.U.asTypeOf(new Lsu_iss_info) } - when( addrTransIO.bits.fun.is_amo ) { + when( addrTransIO.bits.fun.is_amo | addrTransIO.bits.fun.is_sc ) { opAmIO.valid := addrTransIO.valid opAmIO.bits := addrTransIO.bits addrTransIO.ready := opAmIO.ready diff --git a/src/main/scala/rift2Core/backend/LSU/Store_queue.scala b/src/main/scala/rift2Core/backend/LSU/Store_queue.scala index 05c2a4e6..c917d6d4 100644 --- a/src/main/scala/rift2Core/backend/LSU/Store_queue.scala +++ b/src/main/scala/rift2Core/backend/LSU/Store_queue.scala @@ -154,7 +154,7 @@ trait Stq_Overlap{ this: Stq_Base => when( (ro_ptr >= rd_ptr || ro_ptr < wr_ptr) && (buff(ro_ptr).param.dat.op1(plen-1,3) === io.overlapReq.bits.paddr(plen-1,3)) ) { overlap_buff(i) := buff(ro_ptr) - when( buff(ro_ptr).fun.is_amo ) { io.overlapResp.valid := false.B } + when( buff(ro_ptr).fun.is_amo | buff(ro_ptr).fun.is_sc ) { io.overlapResp.valid := false.B } // assert( ~(buff(ro_ptr).fun.is_amo & io.overlapResp.valid), "Assert Failed at Store-queue, overlapping an amo-instr, that is not allow!" ) } .otherwise { overlap_buff(i) := 0.U.asTypeOf(new Lsu_iss_info) @@ -167,7 +167,7 @@ trait Stq_Overlap{ this: Stq_Base => when( ro_ptr >= rd_ptr && ro_ptr < wr_ptr && (buff(ro_ptr).param.dat.op1(plen-1,3) === io.overlapReq.bits.paddr(plen-1,3)) ) { overlap_buff(i) := buff(ro_ptr) - when( buff(ro_ptr).fun.is_amo ) { io.overlapResp.valid := false.B } + when( buff(ro_ptr).fun.is_amo | buff(ro_ptr).fun.is_sc ) { io.overlapResp.valid := false.B } // assert( ~(buff(ro_ptr).fun.is_amo & io.overlapResp.valid), "Assert Failed at Store-queue, overlapping an amo-instr, that is not allow!" ) } .otherwise { overlap_buff(i) := 0.U.asTypeOf(new Lsu_iss_info) diff --git a/src/main/scala/rift2Core/backend/Rename.scala b/src/main/scala/rift2Core/backend/Rename.scala index 5c371359..7382d675 100644 --- a/src/main/scala/rift2Core/backend/Rename.scala +++ b/src/main/scala/rift2Core/backend/Rename.scala @@ -169,6 +169,7 @@ trait LoadRob{ this: RenameBase => reOrder_fifo_i.io.enq(i).bits.is_lu := io.rnReq(i).bits.lsuIsa.is_lu reOrder_fifo_i.io.enq(i).bits.isXFStore := io.rnReq(i).bits.lsuIsa.isXStore | io.rnReq(i).bits.lsuIsa.isFStore reOrder_fifo_i.io.enq(i).bits.is_amo := io.rnReq(i).bits.lsuIsa.is_amo + reOrder_fifo_i.io.enq(i).bits.is_sc := io.rnReq(i).bits.lsuIsa.is_sc reOrder_fifo_i.io.enq(i).bits.is_fence := io.rnReq(i).bits.lsuIsa.fence reOrder_fifo_i.io.enq(i).bits.is_fence_i := io.rnReq(i).bits.lsuIsa.fence_i reOrder_fifo_i.io.enq(i).bits.is_sfence_vma := io.rnReq(i).bits.lsuIsa.sfence_vma diff --git a/src/main/scala/rift2Core/define/riscv_isa.scala b/src/main/scala/rift2Core/define/riscv_isa.scala index e59357c0..864466ef 100644 --- a/src/main/scala/rift2Core/define/riscv_isa.scala +++ b/src/main/scala/rift2Core/define/riscv_isa.scala @@ -205,7 +205,7 @@ class Lsu_isa extends Bundle { def is_xls = lb | lh | lw | ld | lbu | lhu | lwu | sb | sh | sw | sd def is_lrsc = is_sc | is_lr def is_amo = - amoswap_w | amoadd_w | amoxor_w | amoand_w | amoor_w | amomin_w | amomax_w | amominu_w | amomaxu_w | amoswap_d | amoadd_d | amoxor_d | amoand_d | amoor_d | amomin_d | amomax_d | amominu_d | amomaxu_d | is_sc + amoswap_w | amoadd_w | amoxor_w | amoand_w | amoor_w | amomin_w | amomax_w | amominu_w | amomaxu_w | amoswap_d | amoadd_d | amoxor_d | amoand_d | amoor_d | amomin_d | amomax_d | amominu_d | amomaxu_d def is_fls = flw | fsw | fld | fsd def is_vls = vle | vse | vlm | vsm | vlse | vsse | vloxei | vsoxei | vlre | vsr | vleNff @@ -1302,6 +1302,7 @@ class Info_reorder_i(implicit p: Parameters) extends RiftBundle { val is_lu = Bool() val isXFStore = Bool() val is_amo = Bool() + val is_sc = Bool() val is_fence = Bool() val is_fence_i = Bool() val is_sfence_vma = Bool()