| Discipline | Electronics and Communication Engineering |
|---|---|
| Lab | Analog and Digital Electronics-I |
| Experiment | 7. To design a 3-bit even/odd parity generator circuit. |
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| Name of Developer | Prof RS Anand |
|---|---|
| Institute | IIT Roorkee |
| Email id | anandfee@gmail.com |
| Department | Electrical Engineering |
| SrNo | Name | Faculty or Student | Department | Institute | Email id |
|---|---|---|---|---|---|
| 1 | Rajeev Kumar | Senior Research Fellow | Electrical Engineering | IIT Roorkee | rajeevkumar.rke@gmail.com |
| 2 | Nipun Jain | Project Associate | Electrical Engineering | IIT Roorkee | nipunjain1305@gmail.com |
| 3 | Pragya Daksh | Project Associate | Electrical Engineering | IIT Roorkee | prgdaksh@gmail.com |
| 4 | Piyush Rawat | Project Associate | Electrical Engineering | IIT Roorkee | rawatpiyush72@gmail.com |