VPR failed when running with the architecture description file that comes with VTR in COFFE_22nm

[luck-codeer]

Hello, Professor Betz. Thank you for your reply last time, I have already understood the meaning of the critical path delay in COFFE. Now I have encountered a problem, which is exactly the same as this author's problem(verilog-to-routing/vtr-verilog-to-routing#2248), but no one has answered his question for five months. The Stratix10 architecture is an important architecture in the COFFE tool, it is needed in our experiments, so I would like to ask the author of COFFE if he has time to look at this problem. Here's the content of the question:
When I use the arch in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml and benchmark in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/doc/src/quickstart/blink.v as the input to run vtr by instruction:

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py
$VTR_ROOT/doc/src/quickstart/blink.v
$VTR_ROOT/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml
-temp_dir .
--route_chan_width 300

, VPR failed because

This is the part of the specific error in vpr.out:

When I use the arch in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml and benchmark in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/benchmarks/verilog/single_ff.v as the input to run vtr by instruction:

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py
$VTR_ROOT/vtr_flow/benchmarks/verilog/single_ff.v
$VTR_ROOT/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml
-temp_dir .
--route_chan_width 300

, VPR failed because

This is the part of the specific error in vpr.out:

Here is the vpr.out files mentioned above：
vpr_out.zip