[root] type=Root children=system eventq_index=0 full_system=true sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=System children=bridge clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler iobridge iobus l2_caches l3 lint mem_ctrls membus mmcs tol2bus_list tol3bus uartlite voltage_domain workload arch_db=Null auto_unlink_shared_backstore=false cache_line_size=64 enable_difftest=false enable_mem_dedup=false enable_riscv_vector=true eventq_index=0 exit_on_work_items=false gcpt_file=/home/liuzhe/nexus-am/apps/gemm/build/gemm_noprint-riscv64-xs.bin gcpt_restorer_file= gcpt_restorer_size_limit=1792 init_param=0 m5ops_base=0 map_to_raw_cpt=true mem_mode=timing mem_ranges=2147483648:10737418240 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_cpus=1 num_work_ids=16 readfile= redirect_paths= restore_from_gcpt=true shadow_rom_ranges= shared_backstore= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 workload=system.workload xiangshan_system=true system_port=system.membus.cpu_side_ports[0] [system.bridge] type=Bridge children=power_state clk_domain=system.clk_domain delay=50000 eventq_index=0 power_model= power_state=system.bridge.power_state ranges=1080033280:1080033293 939524096:939573248 1073750016:1073750144 req_size=16 resp_size=16 cpu_side_port=system.membus.mem_side_ports[0] mem_side_port=system.iobus.cpu_side_ports[0] [system.bridge.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.clk_domain] type=SrcClockDomain clock=417 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu] type=BaseO3CPU children=branchPred dcache decoder dtb_walker_cache fuPool icache interrupts isa itb_walker_cache mmu power_state scheduler tracer BankConflictCheck=true ConstSquashCycle=1 LFSTEntrySize=4 LFSTSize=256 LQEntries=80 LSQCheckLoads=true LSQDepCheckShift=0 SQEntries=64 SSITSize=1024 SbufferEntries=16 SbufferEvictThreshold=12 activity=0 arch_db=Null backComSize=10 branchPred=system.cpu.branchPred cacheLoadPorts=200 cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=3 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=6 cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=6 decoder=system.cpu.decoder difftest_ref_so= dispatchWidth=6 do_checkpoint_insts=true do_statistics_insts=true dump_commit=false dump_start=0 enable_difftest=false enable_mem_dedup=false enable_riscv_vector=true eventq_index=0 executeToWriteBackDelay=1 fetchBufferSize=64 fetchQueueSize=48 fetchToDecodeDelay=4 fetchTrapLatency=1 fetchWidth=16 forwardComSize=10 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 interrupts=system.cpu.interrupts isa=system.cpu.isa issueWidth=8 max_insts_all_threads=0 max_insts_any_thread=40000000 mmu=system.cpu.mmu needsTSO=false nemuSDCptBin= nemuSDimg= numDQEntries=16 numPhysCCRegs=0 numPhysFloatRegs=192 numPhysIntRegs=192 numPhysRMiscRegs=40 numPhysVecPredRegs=32 numPhysVecRegs=192 numROBEntries=256 numRobs=1 numThreads=1 power_gating_on_idle=false power_model= power_state=system.cpu.power_state progress_interval=0 pwr_gating_latency=300 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=1 renameToROBDelay=1 renameWidth=6 replayWidth=6 robWalkPolicy=Replay scheduler=system.cpu.scheduler simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=RoundRobin smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 socket_id=0 squashWidth=6 storeBufferInactiveThreshold=100 store_prefetch_train=true store_set_clear_period=250000 store_set_clear_thres=1048576 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 warmupInstCount=20000000 wbWidth=8 workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] type=DecoupledBPUWithFTB children=ftb indirectBranchPred ittage ras tage uftb uras BTBEntries=4096 BTBTagSize=16 RASSize=16 bpDBSwitches= enableJumpAheadPredictor=false enableLoopBuffer=true enableLoopPredictor=true eventq_index=0 fsq_size=64 ftb=system.cpu.branchPred.ftb ftq_size=128 indirectBranchPred=system.cpu.branchPred.indirectBranchPred instShiftAmt=2 isDumpMisspredPC=true ittage=system.cpu.branchPred.ittage maxHistLen=970 numBr=2 numStages=3 numThreads=1 ras=system.cpu.branchPred.ras tage=system.cpu.branchPred.tage uftb=system.cpu.branchPred.uftb uras=system.cpu.branchPred.uras [system.cpu.branchPred.ftb] type=DefaultFTB eventq_index=0 instShiftAmt=1 numBr=2 numDelay=1 numEntries=2048 numThreads=1 numWays=4 tagBits=20 [system.cpu.branchPred.indirectBranchPred] type=ITTAGE TTagBitSizes=9 9 13 13 13 13 13 13 13 13 15 15 15 15 15 TTagPcShifts=2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 eventq_index=0 histLengths=4 10 16 27 44 60 96 109 219 449 487 indirectPathLength=3 numPredictors=11 numThreads=1 simpleBTBSize=512 tableSizes=256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 [system.cpu.branchPred.ittage] type=FTBITTAGE TTagBitSizes=9 9 9 9 9 TTagPcShifts=1 1 1 1 1 eventq_index=0 histLengths=4 8 13 16 32 maxHistLen=970 numBr=2 numDelay=2 numPredictors=5 numTablesToAlloc=1 tableSizes=256 256 512 512 512 [system.cpu.branchPred.ras] type=RAS ctrWidth=8 eventq_index=0 numBr=2 numDelay=1 numEntries=32 numInflightEntries=384 [system.cpu.branchPred.tage] type=FTBTAGE TTagBitSizes=8 8 8 8 TTagPcShifts=1 1 1 1 eventq_index=0 histLengths=8 13 32 119 maxHistLen=970 numBr=2 numDelay=1 numPredictors=4 numTablesToAlloc=1 tableSizes=2048 2048 2048 2048 [system.cpu.branchPred.uftb] type=DefaultFTB eventq_index=0 instShiftAmt=1 numBr=2 numDelay=0 numEntries=32 numThreads=1 numWays=32 tagBits=38 [system.cpu.branchPred.uras] type=uRAS ctrWidth=2 eventq_index=0 numBr=2 numDelay=0 numEntries=4 [system.cpu.dcache] type=Cache children=power_state prefetcher replacement_policy tags way_indexing_policy way_replacement_policy addr_ranges=0:18446744073709551615 arch_db=Null assoc=8 cache_level=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=1 demand_mshr_reserve=8 enable_wayprediction=true eventq_index=0 force_hit=false is_read_only=false max_miss_count=0 move_contractions=true mshrs=32 power_model= power_state=system.cpu.dcache.power_state prefetcher=system.cpu.dcache.prefetcher replace_expansions=true replacement_policy=system.cpu.dcache.replacement_policy response_latency=4 sequential_access=false size=65536 system=system tag_latency=1 tags=system.cpu.dcache.tags tgts_per_mshr=20 warmup_percentage=0 way_entries=64 way_indexing_policy=system.cpu.dcache.way_indexing_policy way_replacement_policy=system.cpu.dcache.way_replacement_policy write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.tol2bus_list.cpu_side_ports[1] [system.cpu.dcache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher] type=XSCompositePrefetcher children=act_indexing_policy act_replacement_policy berti bop_large bop_learned bop_small cmc filter_indexing_policy filter_replacement_policy ipcp non_stride_indexing_policy non_stride_replacement_policy opt pf_gen_indexing_policy pf_gen_replacement_policy pht_indexing_policy pht_replacement_policy power_state re_act_indexing_policy re_act_replacement_policy spp sstride stride_indexing_policy stride_replacement_policy xsstream act_entries=32 act_indexing_policy=system.cpu.dcache.prefetcher.act_indexing_policy act_replacement_policy=system.cpu.dcache.prefetcher.act_replacement_policy arch_db=Null berti=system.cpu.dcache.prefetcher.berti block_size=64 bop_large=system.cpu.dcache.prefetcher.bop_large bop_learned=system.cpu.dcache.prefetcher.bop_learned bop_small=system.cpu.dcache.prefetcher.bop_small cache_snoop=true clk_domain=system.cpu_clk_domain cmc=system.cpu.dcache.prefetcher.cmc enable_activepage=true enable_berti=true enable_cplx=false enable_non_stride_filter=false enable_opt=false enable_spp=false enable_sstride=false enable_temporal=false enable_xsstream=false eventq_index=0 filter_entries=16 filter_indexing_policy=system.cpu.dcache.prefetcher.filter_indexing_policy filter_replacement_policy=system.cpu.dcache.prefetcher.filter_replacement_policy fuzzy_stride_matching=false ipcp=system.cpu.dcache.prefetcher.ipcp is_sub_prefetcher=false latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=128 neighbor_pht_update=true non_stride_assoc=4 non_stride_entries=256 non_stride_indexing_policy=system.cpu.dcache.prefetcher.non_stride_indexing_policy non_stride_replacement_policy=system.cpu.dcache.prefetcher.non_stride_replacement_policy on_data=true on_inst=false on_miss=false on_read=true on_write=false opt=system.cpu.dcache.prefetcher.opt page_bytes=4096 pf_gen_entries=16 pf_gen_indexing_policy=system.cpu.dcache.prefetcher.pf_gen_indexing_policy pf_gen_replacement_policy=system.cpu.dcache.prefetcher.pf_gen_replacement_policy pht_assoc=4 pht_early_update=true pht_entries=64 pht_indexing_policy=system.cpu.dcache.prefetcher.pht_indexing_policy pht_pf_ahead=true pht_pf_level=1 pht_replacement_policy=system.cpu.dcache.prefetcher.pht_replacement_policy power_model= power_state=system.cpu.dcache.prefetcher.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=128 queue_squash=true re_act_entries=32 re_act_indexing_policy=system.cpu.dcache.prefetcher.re_act_indexing_policy re_act_replacement_policy=system.cpu.dcache.prefetcher.re_act_replacement_policy region_size=1024 short_stride_thres=0 spp=system.cpu.dcache.prefetcher.spp sstride=system.cpu.dcache.prefetcher.sstride stream_pf_ahead=true stride_dyn_depth=true stride_entries=32 stride_indexing_policy=system.cpu.dcache.prefetcher.stride_indexing_policy stride_replacement_policy=system.cpu.dcache.prefetcher.stride_replacement_policy sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=true xsstream=system.cpu.dcache.prefetcher.xsstream [system.cpu.dcache.prefetcher.act_indexing_policy] type=SetAssociative assoc=32 entry_size=1 eventq_index=0 size=32 [system.cpu.dcache.prefetcher.act_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.berti] type=BertiPrefetcher children=history_table_indexing_policy history_table_replacement_policy power_state addrlist_size=6 aggressive_pf=false arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain deltalist_size=4 dump_top_deltas=true eventq_index=0 history_table_assoc=4 history_table_entries=64 history_table_indexing_policy=system.cpu.dcache.prefetcher.berti.history_table_indexing_policy history_table_replacement_policy=system.cpu.dcache.prefetcher.berti.history_table_replacement_policy is_sub_prefetcher=true latency=1 max_deltafound=4 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.berti.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true sys=system tag_prefetch=true throttle_control_percentage=0 trigger_pht=true use_byte_addr=true use_virtual_addresses=true [system.cpu.dcache.prefetcher.berti.history_table_indexing_policy] type=SetAssociative assoc=4 entry_size=1 eventq_index=0 size=64 [system.cpu.dcache.prefetcher.berti.history_table_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.berti.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.bop_large] type=BOPPrefetcher children=power_state arch_db=Null autoLearning=false bad_score=10 block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain delay_queue_cycles=150 delay_queue_enable=true delay_queue_size=64 eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 negative_offsets_enable=false offsets=72 75 80 81 90 96 100 108 120 125 128 135 144 150 160 162 180 192 200 216 225 240 243 250 256 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.bop_large.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true restoreCycle=250000 round_max=50 rr_size=256 score_max=20 sys=system tag_bits=24 tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=false victimOffsetsListSize=10 [system.cpu.dcache.prefetcher.bop_large.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.bop_learned] type=BOPPrefetcher children=power_state arch_db=Null autoLearning=true bad_score=8 block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain delay_queue_cycles=30 delay_queue_enable=true delay_queue_size=16 eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 negative_offsets_enable=true offsets=64 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.bop_learned.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true restoreCycle=250000 round_max=30 rr_size=256 score_max=31 sys=system tag_bits=24 tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=false victimOffsetsListSize=10 [system.cpu.dcache.prefetcher.bop_learned.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.bop_small] type=BOPPrefetcher children=power_state arch_db=Null autoLearning=false bad_score=5 block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain delay_queue_cycles=150 delay_queue_enable=true delay_queue_size=64 eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 negative_offsets_enable=true offsets=1 2 3 4 5 6 8 9 10 12 15 16 18 20 24 25 27 30 32 36 40 45 48 50 54 60 64 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.bop_small.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true restoreCycle=250000 round_max=30 rr_size=256 score_max=31 sys=system tag_bits=24 tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=false victimOffsetsListSize=10 [system.cpu.dcache.prefetcher.bop_small.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.cmc] type=CMCPrefetcher children=power_state storage_indexing_policy storage_replacement_policy arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain degree=4 enablePrefetchDB=false eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.cmc.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true storage_assoc=16 storage_entries=16384 storage_indexing_policy=system.cpu.dcache.prefetcher.cmc.storage_indexing_policy storage_replacement_policy=system.cpu.dcache.prefetcher.cmc.storage_replacement_policy sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=true [system.cpu.dcache.prefetcher.cmc.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.cmc.storage_indexing_policy] type=SetAssociative assoc=16 entry_size=1 eventq_index=0 size=16384 [system.cpu.dcache.prefetcher.cmc.storage_replacement_policy] type=BRRIPRP btp=3 eventq_index=0 hit_priority=false num_bits=2 [system.cpu.dcache.prefetcher.filter_indexing_policy] type=SetAssociative assoc=16 entry_size=1 eventq_index=0 size=16 [system.cpu.dcache.prefetcher.filter_replacement_policy] type=FIFORP eventq_index=0 [system.cpu.dcache.prefetcher.ipcp] type=IPCPrefetcher children=power_state arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain cspt_size=256 degree=4 eventq_index=0 ipt_size=64 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 on_data=true on_inst=true on_miss=false on_read=true on_write=true page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.ipcp.power_state prefetch_on_access=false prefetch_on_pf_hit=false queue_filter=true queue_size=32 queue_squash=true sys=system tag_prefetch=true throttle_control_percentage=0 use_rrf=false use_virtual_addresses=false [system.cpu.dcache.prefetcher.ipcp.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.non_stride_indexing_policy] type=SetAssociative assoc=4 entry_size=1 eventq_index=0 size=256 [system.cpu.dcache.prefetcher.non_stride_replacement_policy] type=TreePLRURP eventq_index=0 num_leaves=4 [system.cpu.dcache.prefetcher.opt] type=OptPrefetcher children=act_64_indexing_policy act_64_replacement_policy opt_indexing_policy opt_replacement_policy power_state act_64_entries=64 act_64_indexing_policy=system.cpu.dcache.prefetcher.opt.act_64_indexing_policy act_64_replacement_policy=system.cpu.dcache.prefetcher.opt.act_64_replacement_policy arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 on_data=true on_inst=true on_miss=false on_read=true on_write=true opt_entries=64 opt_indexing_policy=system.cpu.dcache.prefetcher.opt.opt_indexing_policy opt_pf_level=3 opt_replacement_policy=system.cpu.dcache.prefetcher.opt.opt_replacement_policy page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.opt.power_state prefetch_on_access=false prefetch_on_pf_hit=false queue_filter=true queue_size=32 queue_squash=true region_size_64=4096 sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=false [system.cpu.dcache.prefetcher.opt.act_64_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.cpu.dcache.prefetcher.opt.act_64_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.opt.opt_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.cpu.dcache.prefetcher.opt.opt_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.opt.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.pf_gen_indexing_policy] type=SetAssociative assoc=16 entry_size=1 eventq_index=0 size=16 [system.cpu.dcache.prefetcher.pf_gen_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.pht_indexing_policy] type=SetAssociative assoc=4 entry_size=1 eventq_index=0 size=64 [system.cpu.dcache.prefetcher.pht_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.re_act_indexing_policy] type=SetAssociative assoc=32 entry_size=1 eventq_index=0 size=32 [system.cpu.dcache.prefetcher.re_act_replacement_policy] type=FIFORP eventq_index=0 [system.cpu.dcache.prefetcher.spp] type=SignaturePathPrefetcher children=pattern_table_indexing_policy pattern_table_replacement_policy power_state signature_table_indexing_policy signature_table_replacement_policy arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain eventq_index=0 is_sub_prefetcher=true latency=1 lookahead_confidence_threshold=0.75 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 num_counter_bits=3 on_data=true on_inst=true on_miss=false on_read=true on_write=true page_bytes=4096 pattern_table_assoc=1 pattern_table_entries=4096 pattern_table_indexing_policy=system.cpu.dcache.prefetcher.spp.pattern_table_indexing_policy pattern_table_replacement_policy=system.cpu.dcache.prefetcher.spp.pattern_table_replacement_policy power_model= power_state=system.cpu.dcache.prefetcher.spp.power_state prefetch_confidence_threshold=0.5 prefetch_on_access=false prefetch_on_pf_hit=false queue_filter=true queue_size=32 queue_squash=true signature_bits=12 signature_shift=3 signature_table_assoc=2 signature_table_entries=1024 signature_table_indexing_policy=system.cpu.dcache.prefetcher.spp.signature_table_indexing_policy signature_table_replacement_policy=system.cpu.dcache.prefetcher.spp.signature_table_replacement_policy strides_per_pattern_entry=4 sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=false [system.cpu.dcache.prefetcher.spp.pattern_table_indexing_policy] type=SetAssociative assoc=1 entry_size=1 eventq_index=0 size=4096 [system.cpu.dcache.prefetcher.spp.pattern_table_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.spp.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.spp.signature_table_indexing_policy] type=SetAssociative assoc=2 entry_size=1 eventq_index=0 size=1024 [system.cpu.dcache.prefetcher.spp.signature_table_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.sstride] type=XSStridePrefetcher children=non_stride_indexing_policy non_stride_replacement_policy power_state stride_indexing_policy stride_replacement_policy arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain enable_non_stride_filter=false eventq_index=0 fuzzy_stride_matching=false is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 non_stride_assoc=4 non_stride_entries=256 non_stride_indexing_policy=system.cpu.dcache.prefetcher.sstride.non_stride_indexing_policy non_stride_replacement_policy=system.cpu.dcache.prefetcher.sstride.non_stride_replacement_policy on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.sstride.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true short_stride_thres=512 stride_dyn_depth=false stride_entries=32 stride_indexing_policy=system.cpu.dcache.prefetcher.sstride.stride_indexing_policy stride_replacement_policy=system.cpu.dcache.prefetcher.sstride.stride_replacement_policy sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=true use_xs_depth=true [system.cpu.dcache.prefetcher.sstride.non_stride_indexing_policy] type=SetAssociative assoc=4 entry_size=1 eventq_index=0 size=256 [system.cpu.dcache.prefetcher.sstride.non_stride_replacement_policy] type=TreePLRURP eventq_index=0 num_leaves=4 [system.cpu.dcache.prefetcher.sstride.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.sstride.stride_indexing_policy] type=SetAssociative assoc=32 entry_size=1 eventq_index=0 size=32 [system.cpu.dcache.prefetcher.sstride.stride_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.stride_indexing_policy] type=SetAssociative assoc=32 entry_size=1 eventq_index=0 size=32 [system.cpu.dcache.prefetcher.stride_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.prefetcher.xsstream] type=XsStreamPrefetcher children=power_state xs_stream_indexing_policy xs_stream_replacement_policy arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain enable_auto_depth=false enable_l3_stream_pre=false eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.cpu.dcache.prefetcher.xsstream.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=true xs_stream_depth=32 xs_stream_entries=16 xs_stream_indexing_policy=system.cpu.dcache.prefetcher.xsstream.xs_stream_indexing_policy xs_stream_replacement_policy=system.cpu.dcache.prefetcher.xsstream.xs_stream_replacement_policy [system.cpu.dcache.prefetcher.xsstream.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.prefetcher.xsstream.xs_stream_indexing_policy] type=SetAssociative assoc=16 entry_size=1 eventq_index=0 size=16 [system.cpu.dcache.prefetcher.xsstream.xs_stream_replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.replacement_policy] type=LRURP eventq_index=0 [system.cpu.dcache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=8 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu.dcache.tags.indexing_policy power_model= power_state=system.cpu.dcache.tags.power_state replacement_policy=system.cpu.dcache.replacement_policy sequential_access=false size=65536 system=system tag_latency=1 warmup_percentage=0 [system.cpu.dcache.tags.indexing_policy] type=SetAssociative assoc=8 entry_size=64 eventq_index=0 size=65536 [system.cpu.dcache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dcache.way_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.cpu.dcache.way_replacement_policy] type=LRURP eventq_index=0 [system.cpu.decoder] type=RiscvDecoder eventq_index=0 isa=system.cpu.isa [system.cpu.dtb_walker_cache] type=Cache children=power_state replacement_policy tags way_indexing_policy way_replacement_policy addr_ranges=0:18446744073709551615 arch_db=Null assoc=2 cache_level=0 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 enable_wayprediction=false eventq_index=0 force_hit=false is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu.dtb_walker_cache.power_state prefetcher=Null replace_expansions=true replacement_policy=system.cpu.dtb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu.dtb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 way_entries=64 way_indexing_policy=system.cpu.dtb_walker_cache.way_indexing_policy way_replacement_policy=system.cpu.dtb_walker_cache.way_replacement_policy write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.cpu.mmu.dtb.walker.port mem_side=system.tol2bus_list.cpu_side_ports[3] [system.cpu.dtb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dtb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu.dtb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu.dtb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu.dtb_walker_cache.tags.power_state replacement_policy=system.cpu.dtb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu.dtb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu.dtb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.dtb_walker_cache.way_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.cpu.dtb_walker_cache.way_replacement_policy] type=LRURP eventq_index=0 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 opClass=IntDiv opLat=20 pipelined=false [system.cpu.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=2 eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=3 pipelined=true [system.cpu.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=3 pipelined=true [system.cpu.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 opClass=FloatMisc opLat=2 pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 [system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=19 pipelined=false [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc children=opList0 opList1 count=4 eventq_index=0 opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 [system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=FMAMul opLat=3 pipelined=true [system.cpu.fuPool.FUList4.opList1] type=OpDesc eventq_index=0 opClass=FloatMult opLat=3 pipelined=true [system.cpu.fuPool.FUList5] type=FUDesc children=opList0 opList1 count=4 eventq_index=0 opList=system.cpu.fuPool.FUList5.opList0 system.cpu.fuPool.FUList5.opList1 [system.cpu.fuPool.FUList5.opList0] type=OpDesc eventq_index=0 opClass=FMAAcc opLat=2 pipelined=true [system.cpu.fuPool.FUList5.opList1] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=3 pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 count=2 eventq_index=0 opList=system.cpu.fuPool.FUList6.opList00 system.cpu.fuPool.FUList6.opList01 system.cpu.fuPool.FUList6.opList02 system.cpu.fuPool.FUList6.opList03 system.cpu.fuPool.FUList6.opList04 system.cpu.fuPool.FUList6.opList05 system.cpu.fuPool.FUList6.opList06 system.cpu.fuPool.FUList6.opList07 system.cpu.fuPool.FUList6.opList08 system.cpu.fuPool.FUList6.opList09 system.cpu.fuPool.FUList6.opList10 system.cpu.fuPool.FUList6.opList11 [system.cpu.fuPool.FUList6.opList00] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu.fuPool.FUList6.opList01] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu.fuPool.FUList6.opList02] type=OpDesc eventq_index=0 opClass=VectorUnitStrideLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList03] type=OpDesc eventq_index=0 opClass=VectorSegUnitStrideLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList04] type=OpDesc eventq_index=0 opClass=VectorUnitStrideMaskLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList05] type=OpDesc eventq_index=0 opClass=VectorSegUnitStrideMaskLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList06] type=OpDesc eventq_index=0 opClass=VectorStridedLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList07] type=OpDesc eventq_index=0 opClass=VectorSegStridedLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList08] type=OpDesc eventq_index=0 opClass=VectorIndexedLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList09] type=OpDesc eventq_index=0 opClass=VectorSegIndexedLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList10] type=OpDesc eventq_index=0 opClass=VectorUnitStrideFaultOnlyFirstLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList6.opList11] type=OpDesc eventq_index=0 opClass=VectorWholeRegisterLoad opLat=2 pipelined=true [system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 opList2 opList3 opList4 opList5 opList6 opList7 count=2 eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 system.cpu.fuPool.FUList7.opList4 system.cpu.fuPool.FUList7.opList5 system.cpu.fuPool.FUList7.opList6 system.cpu.fuPool.FUList7.opList7 [system.cpu.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=4 pipelined=true [system.cpu.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu.fuPool.FUList7.opList2] type=OpDesc eventq_index=0 opClass=VectorUnitStrideStore opLat=1 pipelined=true [system.cpu.fuPool.FUList7.opList3] type=OpDesc eventq_index=0 opClass=VectorSegUnitStrideStore opLat=1 pipelined=true [system.cpu.fuPool.FUList7.opList4] type=OpDesc eventq_index=0 opClass=VectorUnitStrideMaskStore opLat=1 pipelined=true [system.cpu.fuPool.FUList7.opList5] type=OpDesc eventq_index=0 opClass=VectorStridedStore opLat=1 pipelined=true [system.cpu.fuPool.FUList7.opList6] type=OpDesc eventq_index=0 opClass=VectorIndexedStore opLat=1 pipelined=true [system.cpu.fuPool.FUList7.opList7] type=OpDesc eventq_index=0 opClass=VectorWholeRegisterStore opLat=1 pipelined=true [system.cpu.fuPool.FUList8] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 opList28 opList29 opList30 opList31 opList32 opList33 count=2 eventq_index=0 opList=system.cpu.fuPool.FUList8.opList00 system.cpu.fuPool.FUList8.opList01 system.cpu.fuPool.FUList8.opList02 system.cpu.fuPool.FUList8.opList03 system.cpu.fuPool.FUList8.opList04 system.cpu.fuPool.FUList8.opList05 system.cpu.fuPool.FUList8.opList06 system.cpu.fuPool.FUList8.opList07 system.cpu.fuPool.FUList8.opList08 system.cpu.fuPool.FUList8.opList09 system.cpu.fuPool.FUList8.opList10 system.cpu.fuPool.FUList8.opList11 system.cpu.fuPool.FUList8.opList12 system.cpu.fuPool.FUList8.opList13 system.cpu.fuPool.FUList8.opList14 system.cpu.fuPool.FUList8.opList15 system.cpu.fuPool.FUList8.opList16 system.cpu.fuPool.FUList8.opList17 system.cpu.fuPool.FUList8.opList18 system.cpu.fuPool.FUList8.opList19 system.cpu.fuPool.FUList8.opList20 system.cpu.fuPool.FUList8.opList21 system.cpu.fuPool.FUList8.opList22 system.cpu.fuPool.FUList8.opList23 system.cpu.fuPool.FUList8.opList24 system.cpu.fuPool.FUList8.opList25 system.cpu.fuPool.FUList8.opList26 system.cpu.fuPool.FUList8.opList27 system.cpu.fuPool.FUList8.opList28 system.cpu.fuPool.FUList8.opList29 system.cpu.fuPool.FUList8.opList30 system.cpu.fuPool.FUList8.opList31 system.cpu.fuPool.FUList8.opList32 system.cpu.fuPool.FUList8.opList33 [system.cpu.fuPool.FUList8.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList08] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList09] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList10] type=OpDesc eventq_index=0 opClass=SimdDiv opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList11] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList12] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList20] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList21] type=OpDesc eventq_index=0 opClass=SimdReduceAdd opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList22] type=OpDesc eventq_index=0 opClass=SimdReduceAlu opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList23] type=OpDesc eventq_index=0 opClass=SimdReduceCmp opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList24] type=OpDesc eventq_index=0 opClass=SimdFloatReduceAdd opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList25] type=OpDesc eventq_index=0 opClass=SimdFloatReduceCmp opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList26] type=OpDesc eventq_index=0 opClass=VectorIntegerArith opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList27] type=OpDesc eventq_index=0 opClass=VectorFloatArith opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList28] type=OpDesc eventq_index=0 opClass=VectorFloatConvert opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList29] type=OpDesc eventq_index=0 opClass=VectorIntegerReduce opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList30] type=OpDesc eventq_index=0 opClass=VectorFloatReduce opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList31] type=OpDesc eventq_index=0 opClass=VectorMisc opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList32] type=OpDesc eventq_index=0 opClass=VectorIntegerExtension opLat=1 pipelined=true [system.cpu.fuPool.FUList8.opList33] type=OpDesc eventq_index=0 opClass=VectorConfig opLat=1 pipelined=true [system.cpu.icache] type=Cache children=power_state replacement_policy tags way_indexing_policy way_replacement_policy addr_ranges=0:18446744073709551615 arch_db=Null assoc=4 cache_level=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=1 demand_mshr_reserve=1 enable_wayprediction=false eventq_index=0 force_hit=false is_read_only=true max_miss_count=0 move_contractions=true mshrs=2 power_model= power_state=system.cpu.icache.power_state prefetcher=Null replace_expansions=true replacement_policy=system.cpu.icache.replacement_policy response_latency=4 sequential_access=false size=65536 system=system tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=20 warmup_percentage=0 way_entries=64 way_indexing_policy=system.cpu.icache.way_indexing_policy way_replacement_policy=system.cpu.icache.way_replacement_policy write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu.icache_port mem_side=system.tol2bus_list.cpu_side_ports[0] [system.cpu.icache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.icache.replacement_policy] type=LRURP eventq_index=0 [system.cpu.icache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=4 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu.icache.tags.indexing_policy power_model= power_state=system.cpu.icache.tags.power_state replacement_policy=system.cpu.icache.replacement_policy sequential_access=false size=65536 system=system tag_latency=1 warmup_percentage=0 [system.cpu.icache.tags.indexing_policy] type=SetAssociative assoc=4 entry_size=64 eventq_index=0 size=65536 [system.cpu.icache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.icache.way_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.cpu.icache.way_replacement_policy] type=LRURP eventq_index=0 [system.cpu.interrupts] type=RiscvInterrupts eventq_index=0 [system.cpu.isa] type=RiscvISA eventq_index=0 [system.cpu.itb_walker_cache] type=Cache children=power_state replacement_policy tags way_indexing_policy way_replacement_policy addr_ranges=0:18446744073709551615 arch_db=Null assoc=2 cache_level=0 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 enable_wayprediction=false eventq_index=0 force_hit=false is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu.itb_walker_cache.power_state prefetcher=Null replace_expansions=true replacement_policy=system.cpu.itb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu.itb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 way_entries=64 way_indexing_policy=system.cpu.itb_walker_cache.way_indexing_policy way_replacement_policy=system.cpu.itb_walker_cache.way_replacement_policy write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.cpu.mmu.itb.walker.port mem_side=system.tol2bus_list.cpu_side_ports[2] [system.cpu.itb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.itb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu.itb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu.itb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu.itb_walker_cache.tags.power_state replacement_policy=system.cpu.itb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu.itb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu.itb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.itb_walker_cache.way_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.cpu.itb_walker_cache.way_replacement_policy] type=LRURP eventq_index=0 [system.cpu.mmu] type=RiscvMMU children=dtb itb l2_shared pma_checker pmp dtb=system.cpu.mmu.dtb eventq_index=0 itb=system.cpu.mmu.itb pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp [system.cpu.mmu.dtb] type=RiscvTLB children=walker entry_type=data eventq_index=0 forward_pre_size=32 initial_back_pre_precision_value=false initial_forward_pre_precision_value=false is_L1tlb=true is_dtlb=true is_open_nextline=true is_stage2=false is_the_sharedL2=false l2tlb_l1_size=16 l2tlb_l2_size=64 l2tlb_l3_size=512 l2tlb_line_size=8 l2tlb_sp_size=16 next_level=system.cpu.mmu.l2_shared open_back_pre=false open_forward_pre=false pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp regulation_num=70000 size=64 walker=system.cpu.mmu.dtb.walker [system.cpu.mmu.dtb.walker] type=RiscvPagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 open_nextline=true pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp power_model= power_state=system.cpu.mmu.dtb.walker.power_state ptw_squash=false system=system port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.mmu.dtb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.mmu.itb] type=RiscvTLB children=walker entry_type=instruction eventq_index=0 forward_pre_size=32 initial_back_pre_precision_value=false initial_forward_pre_precision_value=false is_L1tlb=true is_dtlb=false is_open_nextline=true is_stage2=false is_the_sharedL2=false l2tlb_l1_size=16 l2tlb_l2_size=64 l2tlb_l3_size=512 l2tlb_line_size=8 l2tlb_sp_size=16 next_level=system.cpu.mmu.l2_shared open_back_pre=false open_forward_pre=false pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp regulation_num=70000 size=32 walker=system.cpu.mmu.itb.walker [system.cpu.mmu.itb.walker] type=RiscvPagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 open_nextline=true pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp power_model= power_state=system.cpu.mmu.itb.walker.power_state ptw_squash=false system=system port=system.cpu.itb_walker_cache.cpu_side [system.cpu.mmu.itb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.mmu.l2_shared] type=RiscvTLB children=walker entry_type=unified eventq_index=0 forward_pre_size=32 initial_back_pre_precision_value=false initial_forward_pre_precision_value=false is_L1tlb=false is_dtlb=false is_open_nextline=true is_stage2=false is_the_sharedL2=true l2tlb_l1_size=16 l2tlb_l2_size=64 l2tlb_l3_size=512 l2tlb_line_size=8 l2tlb_sp_size=16 next_level=Null open_back_pre=false open_forward_pre=false pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp regulation_num=70000 size=64 walker=system.cpu.mmu.l2_shared.walker [system.cpu.mmu.l2_shared.walker] type=RiscvPagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 open_nextline=true pma_checker=system.cpu.mmu.pma_checker pmp=system.cpu.mmu.pmp power_model= power_state=system.cpu.mmu.l2_shared.walker.power_state ptw_squash=false system=system [system.cpu.mmu.l2_shared.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu.mmu.pma_checker] type=PMAChecker eventq_index=0 uncacheable=0:2147483648 [system.cpu.mmu.pmp] type=PMP eventq_index=0 pmp_entries=16 [system.cpu.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states=ON CLK_GATED OFF [system.cpu.scheduler] type=Scheduler children=IQs0 IQs1 IQs2 IQs3 IQs4 IQs5 IQs6 IQs=system.cpu.scheduler.IQs0 system.cpu.scheduler.IQs1 system.cpu.scheduler.IQs2 system.cpu.scheduler.IQs3 system.cpu.scheduler.IQs4 system.cpu.scheduler.IQs5 system.cpu.scheduler.IQs6 eventq_index=0 slotNum=12 specWakeupNetwork= xbarWakeup=true [system.cpu.scheduler.IQs0] type=IssueQue children=fuType eventq_index=0 fuType=system.cpu.scheduler.IQs0.fuType inoutPorts=1 name=IQ_misc scheduleToExecDelay=2 size=24 [system.cpu.scheduler.IQs0.fuType] type=FUDesc children=opList count=2 eventq_index=0 opList=system.cpu.scheduler.IQs0.fuType.opList [system.cpu.scheduler.IQs0.fuType.opList] type=OpDesc eventq_index=0 opClass=IntDiv opLat=20 pipelined=true [system.cpu.scheduler.IQs1] type=IssueQue children=fuType eventq_index=0 fuType=system.cpu.scheduler.IQs1.fuType inoutPorts=2 name=IQ_br scheduleToExecDelay=2 size=48 [system.cpu.scheduler.IQs1.fuType] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu.scheduler.IQs1.fuType.opList [system.cpu.scheduler.IQs1.fuType.opList] type=OpDesc eventq_index=0 opClass=IntBr opLat=1 pipelined=true [system.cpu.scheduler.IQs2] type=IssueQue children=fuType eventq_index=0 fuType=system.cpu.scheduler.IQs2.fuType inoutPorts=2 name=IQ_si scheduleToExecDelay=2 size=48 [system.cpu.scheduler.IQs2.fuType] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu.scheduler.IQs2.fuType.opList [system.cpu.scheduler.IQs2.fuType.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu.scheduler.IQs3] type=IssueQue children=fuType0 fuType1 eventq_index=0 fuType=system.cpu.scheduler.IQs3.fuType0 system.cpu.scheduler.IQs3.fuType1 inoutPorts=2 name=IQ_ci scheduleToExecDelay=2 size=48 [system.cpu.scheduler.IQs3.fuType0] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu.scheduler.IQs3.fuType0.opList [system.cpu.scheduler.IQs3.fuType0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu.scheduler.IQs3.fuType1] type=FUDesc children=opList count=2 eventq_index=0 opList=system.cpu.scheduler.IQs3.fuType1.opList [system.cpu.scheduler.IQs3.fuType1.opList] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true [system.cpu.scheduler.IQs4] type=IssueQue children=fuType eventq_index=0 fuType=system.cpu.scheduler.IQs4.fuType inoutPorts=2 name=IQ_stu scheduleToExecDelay=2 size=48 [system.cpu.scheduler.IQs4.fuType] type=FUDesc children=opList0 opList1 opList2 opList3 opList4 opList5 opList6 opList7 count=2 eventq_index=0 opList=system.cpu.scheduler.IQs4.fuType.opList0 system.cpu.scheduler.IQs4.fuType.opList1 system.cpu.scheduler.IQs4.fuType.opList2 system.cpu.scheduler.IQs4.fuType.opList3 system.cpu.scheduler.IQs4.fuType.opList4 system.cpu.scheduler.IQs4.fuType.opList5 system.cpu.scheduler.IQs4.fuType.opList6 system.cpu.scheduler.IQs4.fuType.opList7 [system.cpu.scheduler.IQs4.fuType.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=4 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList1] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList2] type=OpDesc eventq_index=0 opClass=VectorUnitStrideStore opLat=1 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList3] type=OpDesc eventq_index=0 opClass=VectorSegUnitStrideStore opLat=1 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList4] type=OpDesc eventq_index=0 opClass=VectorUnitStrideMaskStore opLat=1 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList5] type=OpDesc eventq_index=0 opClass=VectorStridedStore opLat=1 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList6] type=OpDesc eventq_index=0 opClass=VectorIndexedStore opLat=1 pipelined=true [system.cpu.scheduler.IQs4.fuType.opList7] type=OpDesc eventq_index=0 opClass=VectorWholeRegisterStore opLat=1 pipelined=true [system.cpu.scheduler.IQs5] type=IssueQue children=fuType eventq_index=0 fuType=system.cpu.scheduler.IQs5.fuType inoutPorts=2 name=IQ_ldu scheduleToExecDelay=2 size=48 [system.cpu.scheduler.IQs5.fuType] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 count=2 eventq_index=0 opList=system.cpu.scheduler.IQs5.fuType.opList00 system.cpu.scheduler.IQs5.fuType.opList01 system.cpu.scheduler.IQs5.fuType.opList02 system.cpu.scheduler.IQs5.fuType.opList03 system.cpu.scheduler.IQs5.fuType.opList04 system.cpu.scheduler.IQs5.fuType.opList05 system.cpu.scheduler.IQs5.fuType.opList06 system.cpu.scheduler.IQs5.fuType.opList07 system.cpu.scheduler.IQs5.fuType.opList08 system.cpu.scheduler.IQs5.fuType.opList09 system.cpu.scheduler.IQs5.fuType.opList10 system.cpu.scheduler.IQs5.fuType.opList11 [system.cpu.scheduler.IQs5.fuType.opList00] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList01] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList02] type=OpDesc eventq_index=0 opClass=VectorUnitStrideLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList03] type=OpDesc eventq_index=0 opClass=VectorSegUnitStrideLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList04] type=OpDesc eventq_index=0 opClass=VectorUnitStrideMaskLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList05] type=OpDesc eventq_index=0 opClass=VectorSegUnitStrideMaskLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList06] type=OpDesc eventq_index=0 opClass=VectorStridedLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList07] type=OpDesc eventq_index=0 opClass=VectorSegStridedLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList08] type=OpDesc eventq_index=0 opClass=VectorIndexedLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList09] type=OpDesc eventq_index=0 opClass=VectorSegIndexedLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList10] type=OpDesc eventq_index=0 opClass=VectorUnitStrideFaultOnlyFirstLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs5.fuType.opList11] type=OpDesc eventq_index=0 opClass=VectorWholeRegisterLoad opLat=2 pipelined=true [system.cpu.scheduler.IQs6] type=IssueQue children=fuType0 fuType1 fuType2 fuType3 fuType4 eventq_index=0 fuType=system.cpu.scheduler.IQs6.fuType0 system.cpu.scheduler.IQs6.fuType1 system.cpu.scheduler.IQs6.fuType2 system.cpu.scheduler.IQs6.fuType3 system.cpu.scheduler.IQs6.fuType4 inoutPorts=2 name=IQ_cplx scheduleToExecDelay=3 size=48 [system.cpu.scheduler.IQs6.fuType0] type=FUDesc children=opList0 opList1 opList2 count=2 eventq_index=0 opList=system.cpu.scheduler.IQs6.fuType0.opList0 system.cpu.scheduler.IQs6.fuType0.opList1 system.cpu.scheduler.IQs6.fuType0.opList2 [system.cpu.scheduler.IQs6.fuType0.opList0] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=3 pipelined=true [system.cpu.scheduler.IQs6.fuType0.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=3 pipelined=true [system.cpu.scheduler.IQs6.fuType0.opList2] type=OpDesc eventq_index=0 opClass=FloatMisc opLat=2 pipelined=true [system.cpu.scheduler.IQs6.fuType1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu.scheduler.IQs6.fuType1.opList0 system.cpu.scheduler.IQs6.fuType1.opList1 [system.cpu.scheduler.IQs6.fuType1.opList0] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=19 pipelined=false [system.cpu.scheduler.IQs6.fuType1.opList1] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false [system.cpu.scheduler.IQs6.fuType2] type=FUDesc children=opList0 opList1 count=4 eventq_index=0 opList=system.cpu.scheduler.IQs6.fuType2.opList0 system.cpu.scheduler.IQs6.fuType2.opList1 [system.cpu.scheduler.IQs6.fuType2.opList0] type=OpDesc eventq_index=0 opClass=FMAMul opLat=3 pipelined=true [system.cpu.scheduler.IQs6.fuType2.opList1] type=OpDesc eventq_index=0 opClass=FloatMult opLat=3 pipelined=true [system.cpu.scheduler.IQs6.fuType3] type=FUDesc children=opList0 opList1 count=4 eventq_index=0 opList=system.cpu.scheduler.IQs6.fuType3.opList0 system.cpu.scheduler.IQs6.fuType3.opList1 [system.cpu.scheduler.IQs6.fuType3.opList0] type=OpDesc eventq_index=0 opClass=FMAAcc opLat=2 pipelined=true [system.cpu.scheduler.IQs6.fuType3.opList1] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=3 pipelined=true [system.cpu.scheduler.IQs6.fuType4] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 opList28 opList29 opList30 opList31 opList32 opList33 count=2 eventq_index=0 opList=system.cpu.scheduler.IQs6.fuType4.opList00 system.cpu.scheduler.IQs6.fuType4.opList01 system.cpu.scheduler.IQs6.fuType4.opList02 system.cpu.scheduler.IQs6.fuType4.opList03 system.cpu.scheduler.IQs6.fuType4.opList04 system.cpu.scheduler.IQs6.fuType4.opList05 system.cpu.scheduler.IQs6.fuType4.opList06 system.cpu.scheduler.IQs6.fuType4.opList07 system.cpu.scheduler.IQs6.fuType4.opList08 system.cpu.scheduler.IQs6.fuType4.opList09 system.cpu.scheduler.IQs6.fuType4.opList10 system.cpu.scheduler.IQs6.fuType4.opList11 system.cpu.scheduler.IQs6.fuType4.opList12 system.cpu.scheduler.IQs6.fuType4.opList13 system.cpu.scheduler.IQs6.fuType4.opList14 system.cpu.scheduler.IQs6.fuType4.opList15 system.cpu.scheduler.IQs6.fuType4.opList16 system.cpu.scheduler.IQs6.fuType4.opList17 system.cpu.scheduler.IQs6.fuType4.opList18 system.cpu.scheduler.IQs6.fuType4.opList19 system.cpu.scheduler.IQs6.fuType4.opList20 system.cpu.scheduler.IQs6.fuType4.opList21 system.cpu.scheduler.IQs6.fuType4.opList22 system.cpu.scheduler.IQs6.fuType4.opList23 system.cpu.scheduler.IQs6.fuType4.opList24 system.cpu.scheduler.IQs6.fuType4.opList25 system.cpu.scheduler.IQs6.fuType4.opList26 system.cpu.scheduler.IQs6.fuType4.opList27 system.cpu.scheduler.IQs6.fuType4.opList28 system.cpu.scheduler.IQs6.fuType4.opList29 system.cpu.scheduler.IQs6.fuType4.opList30 system.cpu.scheduler.IQs6.fuType4.opList31 system.cpu.scheduler.IQs6.fuType4.opList32 system.cpu.scheduler.IQs6.fuType4.opList33 [system.cpu.scheduler.IQs6.fuType4.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList08] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList09] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList10] type=OpDesc eventq_index=0 opClass=SimdDiv opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList11] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList12] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList20] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList21] type=OpDesc eventq_index=0 opClass=SimdReduceAdd opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList22] type=OpDesc eventq_index=0 opClass=SimdReduceAlu opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList23] type=OpDesc eventq_index=0 opClass=SimdReduceCmp opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList24] type=OpDesc eventq_index=0 opClass=SimdFloatReduceAdd opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList25] type=OpDesc eventq_index=0 opClass=SimdFloatReduceCmp opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList26] type=OpDesc eventq_index=0 opClass=VectorIntegerArith opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList27] type=OpDesc eventq_index=0 opClass=VectorFloatArith opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList28] type=OpDesc eventq_index=0 opClass=VectorFloatConvert opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList29] type=OpDesc eventq_index=0 opClass=VectorIntegerReduce opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList30] type=OpDesc eventq_index=0 opClass=VectorFloatReduce opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList31] type=OpDesc eventq_index=0 opClass=VectorMisc opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList32] type=OpDesc eventq_index=0 opClass=VectorIntegerExtension opLat=1 pipelined=true [system.cpu.scheduler.IQs6.fuType4.opList33] type=OpDesc eventq_index=0 opClass=VectorConfig opLat=1 pipelined=true [system.cpu.tracer] type=ExeTracer eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=333 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.cpu_voltage_domain [system.cpu_voltage_domain] type=VoltageDomain eventq_index=0 voltage=1.0 [system.dvfs_handler] type=DVFSHandler domains= enable=false eventq_index=0 sys_clk_domain=system.clk_domain transition_latency=100000000 [system.iobridge] type=Bridge children=power_state clk_domain=system.clk_domain delay=50000 eventq_index=0 power_model= power_state=system.iobridge.power_state ranges=2147483648:10737418240 req_size=16 resp_size=16 cpu_side_port=system.iobus.mem_side_ports[3] mem_side_port=system.membus.cpu_side_ports[1] [system.iobridge.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.iobus] type=NoncoherentXBar children=power_state clk_domain=system.clk_domain eventq_index=0 forward_latency=1 frontend_latency=2 header_latency=1 power_model= power_state=system.iobus.power_state response_latency=2 use_default_range=false width=16 cpu_side_ports=system.bridge.mem_side_port mem_side_ports=system.uartlite.pio system.lint.pio system.mmcs.pio system.iobridge.cpu_side_port [system.iobus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l2_caches] type=Cache children=power_state prefetcher replacement_policy tags way_indexing_policy way_replacement_policy addr_ranges=0:18446744073709551615 arch_db=Null assoc=8 cache_level=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=13 demand_mshr_reserve=1 enable_wayprediction=false eventq_index=0 force_hit=false is_read_only=false max_miss_count=0 move_contractions=true mshrs=64 power_model= power_state=system.l2_caches.power_state prefetcher=system.l2_caches.prefetcher replace_expansions=true replacement_policy=system.l2_caches.replacement_policy response_latency=15 sequential_access=true size=1048576 system=system tag_latency=2 tags=system.l2_caches.tags tgts_per_mshr=20 warmup_percentage=0 way_entries=64 way_indexing_policy=system.l2_caches.way_indexing_policy way_replacement_policy=system.l2_caches.way_replacement_policy write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.tol2bus_list.mem_side_ports[0] mem_side=system.tol3bus.cpu_side_ports[0] [system.l2_caches.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l2_caches.prefetcher] type=L2CompositeWithWorkerPrefetcher children=cdp power_state arch_db=Null block_size=64 cache_snoop=true cdp=system.l2_caches.prefetcher.cdp clk_domain=system.cpu_clk_domain eventq_index=0 is_sub_prefetcher=false latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=128 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.l2_caches.prefetcher.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=64 queue_squash=true sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=true [system.l2_caches.prefetcher.cdp] type=CDP children=power_state arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain eventq_index=0 is_sub_prefetcher=true latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=32 on_data=true on_inst=false on_miss=false on_read=true on_write=false page_bytes=4096 power_model= power_state=system.l2_caches.prefetcher.cdp.power_state prefetch_on_access=false prefetch_on_pf_hit=true queue_filter=true queue_size=32 queue_squash=true sys=system tag_prefetch=true throttle_aggressiveness=2.0 throttle_control_percentage=0 use_byteorder=true use_virtual_addresses=true [system.l2_caches.prefetcher.cdp.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l2_caches.prefetcher.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l2_caches.replacement_policy] type=LRURP eventq_index=0 [system.l2_caches.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=8 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.l2_caches.tags.indexing_policy power_model= power_state=system.l2_caches.tags.power_state replacement_policy=system.l2_caches.replacement_policy sequential_access=true size=1048576 system=system tag_latency=2 warmup_percentage=0 [system.l2_caches.tags.indexing_policy] type=SetAssociative assoc=8 entry_size=64 eventq_index=0 size=1048576 [system.l2_caches.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l2_caches.way_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.l2_caches.way_replacement_policy] type=LRURP eventq_index=0 [system.l3] type=Cache children=power_state prefetcher replacement_policy tags way_indexing_policy way_replacement_policy addr_ranges=0:18446744073709551615 arch_db=Null assoc=16 cache_level=3 clk_domain=system.cpu_clk_domain clusivity=mostly_excl compressor=Null data_latency=17 demand_mshr_reserve=1 enable_wayprediction=false eventq_index=0 force_hit=false is_read_only=false max_miss_count=0 move_contractions=true mshrs=128 power_model= power_state=system.l3.power_state prefetcher=system.l3.prefetcher replace_expansions=true replacement_policy=system.l3.replacement_policy response_latency=66 sequential_access=true size=16777216 system=system tag_latency=2 tags=system.l3.tags tgts_per_mshr=20 warmup_percentage=0 way_entries=64 way_indexing_policy=system.l3.way_indexing_policy way_replacement_policy=system.l3.way_replacement_policy write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.tol3bus.mem_side_ports[0] mem_side=system.membus.cpu_side_ports[2] [system.l3.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l3.prefetcher] type=WorkerPrefetcher children=power_state arch_db=Null block_size=64 cache_snoop=true clk_domain=system.cpu_clk_domain eventq_index=0 is_sub_prefetcher=false latency=1 max_pfahead_recv=1 max_prefetch_requests_with_pending_translation=128 on_data=true on_inst=false on_miss=false on_read=true on_write=true page_bytes=4096 power_model= power_state=system.l3.prefetcher.power_state prefetch_on_access=true prefetch_on_pf_hit=true queue_filter=true queue_size=64 queue_squash=true sys=system tag_prefetch=true throttle_control_percentage=0 use_virtual_addresses=true [system.l3.prefetcher.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l3.replacement_policy] type=LRURP eventq_index=0 [system.l3.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=16 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.l3.tags.indexing_policy power_model= power_state=system.l3.tags.power_state replacement_policy=system.l3.replacement_policy sequential_access=true size=16777216 system=system tag_latency=2 warmup_percentage=0 [system.l3.tags.indexing_policy] type=SetAssociative assoc=16 entry_size=64 eventq_index=0 size=16777216 [system.l3.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l3.way_indexing_policy] type=SetAssociative assoc=64 entry_size=1 eventq_index=0 size=64 [system.l3.way_replacement_policy] type=LRURP eventq_index=0 [system.lint] type=Clint children=power_state clk_domain=system.clk_domain eventq_index=0 num_threads=1 pio_addr=939524096 pio_latency=100000 pio_size=49152 power_model= power_state=system.lint.power_state system=system pio=system.iobus.mem_side_ports[1] [system.lint.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.mem_ctrls] type=DRAMsim3 children=power_state clk_domain=system.clk_domain conf_table_reported=true configFile=/home/liuzhe/GEM5/ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_2ch.ini eventq_index=0 filePath=ext/dramsim3/DRAMsim3/ image_file= in_addr_map=true kvm_map=true null=false power_model= power_state=system.mem_ctrls.power_state range=2147483648:10737418240 port=system.membus.mem_side_ports[1] [system.mem_ctrls.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.membus] type=CoherentXBar children=badaddr_responder power_state snoop_filter clk_domain=system.clk_domain eventq_index=0 forward_latency=0 frontend_latency=0 header_latency=0 max_outstanding_snoops=512 max_routing_table_size=512 point_of_coherency=true point_of_unification=true power_model= power_state=system.membus.power_state response_latency=0 snoop_filter=system.membus.snoop_filter snoop_response_latency=0 system=system use_default_range=false width=128 cpu_side_ports=system.system_port system.iobridge.mem_side_port system.l3.mem_side default=system.membus.badaddr_responder.pio mem_side_ports=system.bridge.cpu_side_port system.mem_ctrls.port [system.membus.badaddr_responder] type=IsaFake children=power_state clk_domain=system.clk_domain eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 pio_size=8 power_model= power_state=system.membus.badaddr_responder.power_state ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.membus.default [system.membus.badaddr_responder.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.membus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.membus.snoop_filter] type=SnoopFilter eventq_index=0 lookup_latency=1 max_capacity=8388608 system=system [system.mmcs] type=NemuMMC children=power_state clk_domain=system.clk_domain cpt_bin_path=/the/mid/of/nowhere.xhit eventq_index=0 img_path=/the/mid/of/nowhere.xhit pio_addr=1073750016 pio_latency=100000 pio_size=128 power_model= power_state=system.mmcs.power_state system=system pio=system.iobus.mem_side_ports[2] [system.mmcs.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.tol2bus_list] type=CoherentXBar children=power_state snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 header_latency=1 max_outstanding_snoops=512 max_routing_table_size=512 point_of_coherency=false point_of_unification=true power_model= power_state=system.tol2bus_list.power_state response_latency=1 snoop_filter=system.tol2bus_list.snoop_filter snoop_response_latency=1 system=system use_default_range=false width=256 cpu_side_ports=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side mem_side_ports=system.l2_caches.cpu_side [system.tol2bus_list.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.tol2bus_list.snoop_filter] type=SnoopFilter eventq_index=0 lookup_latency=0 max_capacity=8388608 system=system [system.tol3bus] type=CoherentXBar children=power_state snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 header_latency=1 max_outstanding_snoops=512 max_routing_table_size=512 point_of_coherency=false point_of_unification=true power_model= power_state=system.tol3bus.power_state response_latency=1 snoop_filter=system.tol3bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false width=256 cpu_side_ports=system.l2_caches.mem_side mem_side_ports=system.l3.cpu_side [system.tol3bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.tol3bus.snoop_filter] type=SnoopFilter eventq_index=0 lookup_latency=0 max_capacity=8388608 system=system [system.uartlite] type=UartLite children=power_state clk_domain=system.clk_domain eventq_index=0 pio_addr=1080033280 pio_latency=100000 pio_size=13 power_model= power_state=system.uartlite.power_state system=system pio=system.iobus.mem_side_ports[0] [system.uartlite.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.voltage_domain] type=VoltageDomain eventq_index=0 voltage=1.0 [system.workload] type=RiscvBareMetal bare_metal=true bootloader= eventq_index=0 raw_bootloader=true reset_vect=2147483648 wait_for_remote_gdb=false xiangshan_cpt=true