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wifi.h
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#ifndef __WIFI_H__
#define __WIFI_H__
#include <linux/types.h>
#include "usb.h"
#include "efuse.h" /* ULLI : Note this belongs to base.h we doesn't have */
#include "debug.h"
#define TOTAL_CAM_ENTRY 32
#define MAX_RF_PATH_NUM 2
#define MAX_CHNL_GROUP 3+9
enum intf_type {
INTF_PCI = 0,
INTF_USB = 1,
};
enum radio_path {
RF90_PATH_A = 0,
RF90_PATH_B = 1,
RF90_PATH_C = 2,
RF90_PATH_D = 3,
};
enum regulation_txpwr_lmt {
TXPWR_LMT_FCC = 0,
TXPWR_LMT_MKK = 1,
TXPWR_LMT_ETSI = 2,
TXPWR_LMT_WW = 3,
TXPWR_LMT_MAX_REGULATION_NUM = 4
};
enum rate_section {
CCK = 0,
OFDM,
HT_MCS0_MCS7,
HT_MCS8_MCS15,
HT_MCS16_MCS23,
HT_MCS24_MCS31,
VHT_1SSMCS0_1SSMCS9,
VHT_2SSMCS0_2SSMCS9,
VHT_3SSMCS0_3SSMCS9,
VHT_4SSMCS0_4SSMCS9,
};
enum rf_tx_num {
RF_1TX = 0,
RF_2TX,
RF_3TX,
RF_4TX,
RF_MAX_TX_NUM,
RF_TX_NUM_NONIMPLEMENT,
};
enum rtl_desc92_rate {
DESC_RATE1M = 0x00,
DESC_RATE2M = 0x01,
DESC_RATE5_5M = 0x02,
DESC_RATE11M = 0x03,
DESC_RATE6M = 0x04,
DESC_RATE9M = 0x05,
DESC_RATE12M = 0x06,
DESC_RATE18M = 0x07,
DESC_RATE24M = 0x08,
DESC_RATE36M = 0x09,
DESC_RATE48M = 0x0a,
DESC_RATE54M = 0x0b,
DESC_RATEMCS0 = 0x0c,
DESC_RATEMCS1 = 0x0d,
DESC_RATEMCS2 = 0x0e,
DESC_RATEMCS3 = 0x0f,
DESC_RATEMCS4 = 0x10,
DESC_RATEMCS5 = 0x11,
DESC_RATEMCS6 = 0x12,
DESC_RATEMCS7 = 0x13,
DESC_RATEMCS8 = 0x14,
DESC_RATEMCS9 = 0x15,
DESC_RATEMCS10 = 0x16,
DESC_RATEMCS11 = 0x17,
DESC_RATEMCS12 = 0x18,
DESC_RATEMCS13 = 0x19,
DESC_RATEMCS14 = 0x1a,
DESC_RATEMCS15 = 0x1b,
DESC_RATEMCS15_SG = 0x1c,
DESC_RATEMCS32 = 0x20,
DESC_RATEVHT1SS_MCS0 = 0x2c,
DESC_RATEVHT1SS_MCS1 = 0x2d,
DESC_RATEVHT1SS_MCS2 = 0x2e,
DESC_RATEVHT1SS_MCS3 = 0x2f,
DESC_RATEVHT1SS_MCS4 = 0x30,
DESC_RATEVHT1SS_MCS5 = 0x31,
DESC_RATEVHT1SS_MCS6 = 0x32,
DESC_RATEVHT1SS_MCS7 = 0x33,
DESC_RATEVHT1SS_MCS8 = 0x34,
DESC_RATEVHT1SS_MCS9 = 0x35,
DESC_RATEVHT2SS_MCS0 = 0x36,
DESC_RATEVHT2SS_MCS1 = 0x37,
DESC_RATEVHT2SS_MCS2 = 0x38,
DESC_RATEVHT2SS_MCS3 = 0x39,
DESC_RATEVHT2SS_MCS4 = 0x3a,
DESC_RATEVHT2SS_MCS5 = 0x3b,
DESC_RATEVHT2SS_MCS6 = 0x3c,
DESC_RATEVHT2SS_MCS7 = 0x3d,
DESC_RATEVHT2SS_MCS8 = 0x3e,
DESC_RATEVHT2SS_MCS9 = 0x3f,
};
/* Ref: 802.11i sepc D10.0 7.3.2.25.1
Cipher Suites Encryption Algorithms */
enum rt_enc_alg {
NO_ENCRYPTION = 0,
WEP40_ENCRYPTION = 1,
TKIP_ENCRYPTION = 2,
RSERVED_ENCRYPTION = 3,
AESCCMP_ENCRYPTION = 4,
WEP104_ENCRYPTION = 5,
AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
};
enum rtl_var_map {
/*reg map */
SYS_ISO_CTRL = 0,
#if 0
SYS_FUNC_EN,
SYS_CLK,
MAC_RCR_AM,
MAC_RCR_AB,
MAC_RCR_ACRC32,
MAC_RCR_ACF,
MAC_RCR_AAP,
MAC_HIMR,
MAC_HIMRE,
MAC_HSISR,
#endif
/*efuse map */
EFUSE_TEST,
EFUSE_CTRL,
EFUSE_CLK,
EFUSE_CLK_CTRL,
EFUSE_PWC_EV12V,
EFUSE_FEN_ELDR,
EFUSE_LOADER_CLK_EN,
EFUSE_ANA8M,
EFUSE_HWSET_MAX_SIZE,
EFUSE_MAX_SECTION_MAP,
EFUSE_REAL_CONTENT_SIZE,
EFUSE_OOB_PROTECT_BYTES_LEN,
EFUSE_ACCESS,
/*CAM map */
RWCAM,
WCAMI,
RCAMO,
CAMDBG,
SECR,
SEC_CAM_NONE,
SEC_CAM_WEP40,
SEC_CAM_TKIP,
SEC_CAM_AES,
SEC_CAM_WEP104,
#if 0
/*IMR map */
RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
RTL_IMR_RDU, /*Receive Descriptor Unavailable */
RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
RTL_IMR_ROK, /*Receive DMA OK Interrupt */
RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
* RTL_IMR_TBDER) */
RTL_IMR_C2HCMD, /*fw interrupt*/
#endif
/*CCK Rates, TxHT = 0 */
RTL_RC_CCK_RATE1M,
RTL_RC_CCK_RATE2M,
RTL_RC_CCK_RATE5_5M,
RTL_RC_CCK_RATE11M,
/*OFDM Rates, TxHT = 0 */
RTL_RC_OFDM_RATE6M,
RTL_RC_OFDM_RATE9M,
RTL_RC_OFDM_RATE12M,
RTL_RC_OFDM_RATE18M,
RTL_RC_OFDM_RATE24M,
RTL_RC_OFDM_RATE36M,
RTL_RC_OFDM_RATE48M,
RTL_RC_OFDM_RATE54M,
RTL_RC_HT_RATEMCS7,
RTL_RC_HT_RATEMCS15,
RTL_RC_VHT_RATE_1SS_MCS7,
RTL_RC_VHT_RATE_1SS_MCS8,
RTL_RC_VHT_RATE_1SS_MCS9,
RTL_RC_VHT_RATE_2SS_MCS7,
RTL_RC_VHT_RATE_2SS_MCS8,
RTL_RC_VHT_RATE_2SS_MCS9,
/*keep it last */
RTL_VAR_MAP_MAX,
};
struct rtl_hal_ops;
#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
#define CHANNEL_MAX_NUMBER_2G 14
#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
*"phy_GetChnlGroup8812A" and
* "Hal_ReadTxPowerInfo8812A"
*/
#define CHANNEL_MAX_NUMBER_5G_80M 7
#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
*"phy_GetChnlGroup8812A" and
* "Hal_ReadTxPowerInfo8812A"
*/
#define CHANNEL_MAX_NUMBER_5G_80M 7
#define MAX_PG_GROUP 13
#define CHANNEL_GROUP_MAX_2G 3
#define CHANNEL_GROUP_IDX_5GL 3
#define CHANNEL_GROUP_IDX_5GM 6
#define CHANNEL_GROUP_IDX_5GH 9
#define CHANNEL_GROUP_MAX_5G 9
#define CHANNEL_MAX_NUMBER_2G 14
#define AVG_THERMAL_NUM 8
#define AVG_THERMAL_NUM_88E 4
#define AVG_THERMAL_NUM_8723BE 4
#define AVG_THERMAL_NUM_8812A 4
#define MAX_TID_COUNT 9
#define MAX_REGULATION_NUM 3
#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
#define MAX_2_4G_BANDWITH_NUM 2
#define MAX_2_4G_RATE_SECTION_NUM 3
#define MAX_2_4G_CHANNEL_NUM 5 // adopt channel group instead of individual channel
#define MAX_5G_BANDWITH_NUM 4
#define MAX_5G_RATE_SECTION_NUM 4
#define MAX_5G_CHANNEL_NUM 14 // adopt channel group instead of individual channel
/*
* ULLI : big remark
* ULLI : in rtl8821ae there is no use of external_pa_2g or
* ULLI : external_pa_5g in the phy.c file.
* ULLI : But we need to configure the external_pa* here, because
* ULLI : it is used here in the original source, and we don't want to
* ULLI : drop this.
* ULLI :
* ULLI : Thus we do transmit some values use in rtl_dm (now _rtw_dm) and
* ULLI : dm_priv into appreciate struct's (rtl_phy, rtl_hal, rtl_efuse)
* ULLI : and use them, to select features.
*/
#define MAX_RF_PATH 4
#define RF_PATH_MAX MAX_RF_PATH
#define MAX_CHNL_GROUP_24G 6
#define MAX_CHNL_GROUP_5G 14
//It must always set to 4, otherwise read efuse table secquence will be wrong.
#define MAX_TX_COUNT 4
struct txpower_info_2g {
u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
/*If only one tx, only BW20 and OFDM are used.*/
u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
};
struct txpower_info_5g {
u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
/*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
};
#define EFUSE_MAX_LOGICAL_SIZE 512
struct rtl_efuse { bool autoLoad_ok;
bool bootfromefuse;
u16 max_physical_size;
u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
u16 efuse_usedbytes;
u8 efuse_usedpercentage;
#ifdef EFUSE_REPG_WORKAROUND
bool efuse_re_pg_sec1flag;
u8 efuse_re_pg_data[8];
#endif
u8 autoload_failflag;
u8 autoload_status;
short epromtype;
u16 eeprom_vid;
u16 eeprom_did;
u16 eeprom_svid;
u16 eeprom_smid;
u8 eeprom_oemid;
u16 eeprom_channelplan;
u8 eeprom_version;
u8 board_type;
u8 external_pa;
u8 dev_addr[6];
u8 wowlan_enable;
u8 antenna_div_cfg;
u8 antenna_div_type;
bool txpwr_fromeprom;
u8 eeprom_crystalcap;
u8 eeprom_tssi[2];
u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 eeprom_c9;
u8 eeprom_cc;
/*For power group */
u8 eeprom_pwrgroup[2][3];
u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
/*For HT 40MHZ pwr */
u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
/*For HT 40MHZ pwr */
u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
/*--------------------------------------------------------*
* 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
* other ICs (8188EE\8723BE\8192EE\8812AE...)
* define new arrays in Windows code.
* BUT, in linux code, we use the same array for all ICs.
*
* The Correspondance relation between two arrays is:
* txpwr_cckdiff[][] == CCK_24G_Diff[][]
* txpwr_ht20diff[][] == BW20_24G_Diff[][]
* txpwr_ht40diff[][] == BW40_24G_Diff[][]
* txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
*
* Sizes of these arrays are decided by the larger ones.
*/
char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 txpwr_safetyflag; /* Band edge enable flag */
u16 eeprom_txpowerdiff;
u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
u8 antenna_txpwdiff[3];
u8 eeprom_regulatory;
u8 eeprom_thermalmeter;
u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
u16 tssi_13dbm;
u8 crystalcap; /* CrystalCap. */
u8 delta_iqk;
u8 delta_lck;
u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
bool apk_thermalmeterignore;
bool b1x1_recvcombine;
bool b1ss_support;
/*channel plan */
u8 channel_plan;
};
#define KEY_BUF_SIZE 5
#define MAX_KEY_LEN 61
struct rtl_security {
/*default 0 */
bool use_sw_sec;
bool being_setkey;
bool use_defaultkey;
/*Encryption Algorithm for Unicast Packet */
enum rt_enc_alg pairwise_enc_algorithm;
/*Encryption Algorithm for Brocast/Multicast */
enum rt_enc_alg group_enc_algorithm;
/*Cam Entry Bitmap */
u32 hwsec_cam_bitmap;
u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
/*local Key buffer, indx 0 is for
pairwise key 1-4 is for agoup key. */
u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
u8 key_len[KEY_BUF_SIZE];
/*The pointer of Pairwise Key,
it always points to KeyBuf[4] */
u8 *pairwise_key;
};
enum hw_variables {
HW_VAR_ETHER_ADDR,
HW_VAR_MULTICAST_REG,
HW_VAR_BASIC_RATE,
HW_VAR_BSSID,
HW_VAR_MEDIA_STATUS,
HW_VAR_SECURITY_CONF,
HW_VAR_BEACON_INTERVAL,
HW_VAR_ATIM_WINDOW,
HW_VAR_LISTEN_INTERVAL,
HW_VAR_CS_COUNTER,
HW_VAR_DEFAULTKEY0,
HW_VAR_DEFAULTKEY1,
HW_VAR_DEFAULTKEY2,
HW_VAR_DEFAULTKEY3,
HW_VAR_SIFS,
HW_VAR_R2T_SIFS,
HW_VAR_DIFS,
HW_VAR_EIFS,
HW_VAR_SLOT_TIME,
HW_VAR_ACK_PREAMBLE,
HW_VAR_CW_CONFIG,
HW_VAR_CW_VALUES,
HW_VAR_RATE_FALLBACK_CONTROL,
HW_VAR_CONTENTION_WINDOW,
HW_VAR_RETRY_COUNT,
HW_VAR_TR_SWITCH,
HW_VAR_COMMAND,
HW_VAR_WPA_CONFIG,
HW_VAR_AMPDU_MIN_SPACE,
HW_VAR_SHORTGI_DENSITY,
HW_VAR_AMPDU_FACTOR,
HW_VAR_MCS_RATE_AVAILABLE,
HW_VAR_AC_PARAM,
HW_VAR_ACM_CTRL,
HW_VAR_DIS_Req_Qsize,
HW_VAR_CCX_CHNL_LOAD,
HW_VAR_CCX_NOISE_HISTOGRAM,
HW_VAR_CCX_CLM_NHM,
HW_VAR_TxOPLimit,
HW_VAR_TURBO_MODE,
HW_VAR_RF_STATE,
HW_VAR_RF_OFF_BY_HW,
HW_VAR_BUS_SPEED,
HW_VAR_SET_DEV_POWER,
HW_VAR_RCR,
HW_VAR_RATR_0,
HW_VAR_RRSR,
HW_VAR_CPU_RST,
HW_VAR_CHECK_BSSID,
HW_VAR_LBK_MODE,
HW_VAR_AES_11N_FIX,
HW_VAR_USB_RX_AGGR,
HW_VAR_USER_CONTROL_TURBO_MODE,
HW_VAR_RETRY_LIMIT,
HW_VAR_INIT_TX_RATE,
HW_VAR_TX_RATE_REG,
HW_VAR_EFUSE_USAGE,
HW_VAR_EFUSE_BYTES,
HW_VAR_AUTOLOAD_STATUS,
HW_VAR_RF_2R_DISABLE,
HW_VAR_SET_RPWM,
HW_VAR_H2C_FW_PWRMODE,
HW_VAR_H2C_FW_JOINBSSRPT,
HW_VAR_H2C_FW_MEDIASTATUSRPT,
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
HW_VAR_FW_PSMODE_STATUS,
HW_VAR_INIT_RTS_RATE,
HW_VAR_RESUME_CLK_ON,
HW_VAR_FW_LPS_ACTION,
HW_VAR_1X1_RECV_COMBINE,
HW_VAR_STOP_SEND_BEACON,
HW_VAR_TSF_TIMER,
HW_VAR_IO_CMD,
HW_VAR_RF_RECOVERY,
HW_VAR_H2C_FW_UPDATE_GTK,
HW_VAR_WF_MASK,
HW_VAR_WF_CRC,
HW_VAR_WF_IS_MAC_ADDR,
HW_VAR_H2C_FW_OFFLOAD,
HW_VAR_RESET_WFCRC,
HW_VAR_HANDLE_FW_C2H,
HW_VAR_DL_FW_RSVD_PAGE,
HW_VAR_AID,
HW_VAR_HW_SEQ_ENABLE,
HW_VAR_CORRECT_TSF,
HW_VAR_BCN_VALID,
HW_VAR_FWLPS_RF_ON,
HW_VAR_DUAL_TSF_RST,
HW_VAR_SWITCH_EPHY_WoWLAN,
HW_VAR_INT_MIGRATION,
HW_VAR_INT_AC,
HW_VAR_RF_TIMING,
HAL_DEF_WOWLAN,
HW_VAR_MRC,
HW_VAR_KEEP_ALIVE,
HW_VAR_NAV_UPPER,
HW_VAR_MGT_FILTER,
HW_VAR_CTRL_FILTER,
HW_VAR_DATA_FILTER,
/* ULLI : HW VARS rtlwifi end */
HW_VAR_MEDIA_STATUS1,
HW_VAR_TXPAUSE,
HW_VAR_BCN_FUNC,
HW_VAR_MLME_DISCONNECT,
HW_VAR_MLME_SITESURVEY,
HW_VAR_MLME_JOIN,
HW_VAR_ON_RCR_AM,
HW_VAR_OFF_RCR_AM,
HW_VAR_RESP_SIFS,
HW_VAR_SEC_CFG,
HW_VAR_CAM_WRITE,
HW_VAR_CAM_READ,
HW_VAR_AC_PARAM_VO,
HW_VAR_AC_PARAM_VI,
HW_VAR_AC_PARAM_BE,
HW_VAR_AC_PARAM_BK,
HW_VAR_RXDMA_AGG_PG_TH,
HW_VAR_H2C_PS_TUNE_PARAM,
HW_VAR_TDLS_WRCR,
HW_VAR_TDLS_INIT_CH_SEN,
HW_VAR_TDLS_RS_RCR,
HW_VAR_TDLS_DONE_CH_SEN,
HW_VAR_INITIAL_GAIN,
HW_VAR_TRIGGER_GPIO_0,
HW_VAR_BT_SET_COEXIST,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_CURRENT_ANTENNA,
HW_VAR_ANTENNA_DIVERSITY_LINK,
HW_VAR_ANTENNA_DIVERSITY_SELECT,
HW_VAR_EFUSE_BT_USAGE,
HW_VAR_EFUSE_BT_BYTES,
HW_VAR_FIFO_CLEARN_UP,
HW_VAR_CHECK_TXBUF,
HW_VAR_C2H_HANDLE,
HW_VAR_RPT_TIMER_SETTING,
HW_VAR_TX_RPT_MAX_MACID,
HW_VAR_H2C_MEDIA_STATUS_RPT,
HW_VAR_CHK_HI_QUEUE_EMPTY,
HW_VAR_DL_BCN_SEL,
HW_VAR_AMPDU_MAX_TIME,
HW_VAR_WIRELESS_MODE,
};
typedef enum tag_Board_Definition
{
ODM_BOARD_DEFAULT = 0, // The DEFAULT case.
ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.
ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card
ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT
ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA
ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA
ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW
ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA
ODM_BOARD_EXT_LNA_5G = BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA
}ODM_BOARD_TYPE_E;
enum band_type {
BAND_ON_2_4G = 0,
BAND_ON_5G,
BAND_ON_BOTH,
BANDMAX
};
/*mlme related.*/
enum wireless_mode {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_B = 0x02,
WIRELESS_MODE_G = 0x04,
WIRELESS_MODE_AUTO = 0x08,
WIRELESS_MODE_N_24G = 0x10,
WIRELESS_MODE_N_5G = 0x20,
WIRELESS_MODE_AC_5G = 0x40,
WIRELESS_MODE_AC_24G = 0x80,
WIRELESS_MODE_AC_ONLY = 0x100,
#if 0 /* ULLI : we can't enable this,but this is not used in rtlwifi */
WIRELESS_MODE_MAX = 0x800
#endif
};
struct rtl_hal {
#if 0
struct ieee80211_hw *hw;
#endif
bool driver_is_goingto_unload;
bool up_first_time;
bool first_init;
bool being_init_adapter;
bool bbrf_ready;
bool mac_func_enable;
bool pre_edcca_enable;
#if 0
struct bt_coexist_8723 hal_coex_8723;
#endif
enum intf_type interface;
u16 hw_type; /*92c or 92d or 92s and so on */
u8 ic_class;
u8 oem_id;
u32 version; /*version of chip */
u8 state; /*stop 0, start 1 */
u8 board_type;
u8 external_pa;
u8 pa_mode;
u8 pa_type_2g;
u8 pa_type_5g;
u8 lna_type_2g;
u8 lna_type_5g;
u8 external_pa_2g;
u8 external_lna_2g;
u8 external_pa_5g;
u8 external_lna_5g;
u8 rfe_type;
/*firmware */
u32 fwsize;
u8 *pfirmware;
u16 fw_version;
u16 fw_subversion;
bool h2c_setinprogress;
u8 last_hmeboxnum;
bool fw_ready;
/*Reserve page start offset except beacon in TxQ. */
u8 fw_rsvdpage_startoffset;
u8 h2c_txcmd_seq;
u8 current_ra_rate;
/* FW Cmd IO related */
u16 fwcmd_iomap;
u32 fwcmd_ioparam;
bool set_fwcmd_inprogress;
u8 current_fwcmd_io;
#if 0
struct p2p_ps_offload_t p2p_ps_offload;
#endif
bool fw_clk_change_in_progress;
bool allow_sw_to_change_hwclc;
u8 fw_ps_state;
/**/
bool driver_going2unload;
/*AMPDU init min space*/
u8 minspace_cfg; /*For Min spacing configurations */
/* Dual mac */
#if 0
enum macphy_mode macphymode;
#endif
enum band_type current_bandtype; /* 0:2.4G, 1:5G */
#if 0
enum band_type current_bandtypebackup;
#endif
enum band_type bandset;
/* dual MAC 0--Mac0 1--Mac1 */
u32 interfaceindex;
/* just for DualMac S3S4 */
u8 macphyctl_reg;
bool earlymode_enable;
u8 max_earlymode_num;
/* Dual mac*/
bool during_mac0init_radiob;
bool during_mac1init_radioa;
bool reloadtxpowerindex;
/* true if IMR or IQK have done
for 2.4G in scan progress */
bool load_imrandiqk_setting_for2g;
bool disable_amsdu_8k;
bool master_of_dmsp;
bool slave_of_dmsp;
u16 rx_tag;/*for 92ee*/
u8 rts_en;
/*for wowlan*/
bool wow_enable;
bool enter_pnp_sleep;
bool wake_from_pnp_sleep;
bool wow_enabled;
u32 wowlan_fwsize;
u8 *wowlan_firmware;
u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
bool real_wow_v2_enable;
bool re_init_llt_table;
};
#define MAX_TX_COUNT 4
#define MAX_RATE_SECTION_NUM 6
#define MAX_5G_BANDWITH_NUM 4
#define MAX_RF_PATH 4
#define MAX_CHNL_GROUP_24G 6
#define MAX_CHNL_GROUP_5G 14
#define TX_PWR_BY_RATE_NUM_BAND 2
#define TX_PWR_BY_RATE_NUM_RF 4
#define TX_PWR_BY_RATE_NUM_SECTION 12
#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
//###### duplicate code,will move to ODM #########
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 10
#define IQK_BB_REG_NUM_92C 9
#define IQK_BB_REG_NUM_92D 10
#define IQK_BB_REG_NUM_test 6
#define IQK_MATRIX_REG_NUM 8
#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
enum rt_polarity_ctl {
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
};
struct iqk_matrix_regs {
bool iqk_done;
long value[1][IQK_MATRIX_REG_NUM];
};
struct phy_parameters {
u16 length;
u32 *pdata;
};
enum hw_param_tab_index {
PHY_REG_2T,
PHY_REG_1T,
PHY_REG_PG,
RADIOA_2T,
RADIOB_2T,
RADIOA_1T,
RADIOB_1T,
MAC_REG,
AGCTAB_2T,
AGCTAB_1T,
MAX_TAB
};
enum io_type {
IO_CMD_PAUSE_DM_BY_SCAN = 0,
IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
IO_CMD_RESUME_DM_BY_SCAN = 2,
};
struct bb_reg_def {
u32 rfintfs;
u32 rfintfi;
u32 rfintfo;
u32 rfintfe;
u32 rf3wire_offset;
u32 rflssi_select;
u32 rftxgain_stage;
u32 rfhssi_para1;
u32 rfhssi_para2;
u32 rfsw_ctrl;
u32 rfagc_control1;
u32 rfagc_control2;
u32 rfrxiq_imbal;
u32 rfrx_afe;
u32 rftxiq_imbal;
u32 rftx_afe;
u32 rf_rb; /* rflssi_readback */
u32 rf_rbpi; /* rflssi_readbackpi */
};
struct init_gain {
u8 xaagccore1;
u8 xbagccore1;
u8 xcagccore1;
u8 xdagccore1;
u8 cca;
};
struct rtl_phy {
struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
struct init_gain initgain_backup;
enum io_type current_io_type;
u8 rf_mode;
u8 rf_type;
u8 current_chan_bw;
u8 set_bwmode_inprogress;
u8 sw_chnl_inprogress;
u8 sw_chnl_stage;
u8 sw_chnl_step;
u8 current_channel;
u8 h2c_box_num;
u8 set_io_inprogress;
u8 lck_inprogress;
/* record for power tracking */
s32 reg_e94;
s32 reg_e9c;
s32 reg_ea4;
s32 reg_eac;
s32 reg_eb4;
s32 reg_ebc;
s32 reg_ec4;
s32 reg_ecc;
u8 rfpienable;
u8 reserve_0;
u16 reserve_1;
u32 reg_c04, reg_c08, reg_874;
u32 adda_backup[16];
u32 iqk_mac_backup[IQK_MAC_REG_NUM];
u32 iqk_bb_backup[10];
bool iqk_initialized;
bool rfpath_rx_enable[MAX_RF_PATH];
u8 reg_837;
/* Dual mac */
bool need_iqk;
struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
bool rfpi_enable;
bool iqk_in_progress;
u8 pwrgroup_cnt;
u8 cck_high_power;
/* this is for 88E & 8723A */
u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
/* MAX_PG_GROUP groups of pwr diff by rates */
u32 mcs_offset[MAX_PG_GROUP][16];
u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_SECTION];
u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_24G];
u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
u8 default_initialgain[4];
/* the current Tx power level */
u8 cur_cck_txpwridx;
u8 cur_ofdm24g_txpwridx;
u8 cur_bw20_txpwridx;
u8 cur_bw40_txpwridx;
char txpwr_limit_2_4g[MAX_REGULATION_NUM]
[MAX_2_4G_BANDWITH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_2G]
[MAX_RF_PATH_NUM];
char txpwr_limit_5g[MAX_REGULATION_NUM]
[MAX_5G_BANDWITH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_5G]
[MAX_RF_PATH_NUM];
u32 rfreg_chnlval[2];
bool apk_done;
u32 reg_rf3c[2]; /* pathA / pathB */
u32 backup_rf_0x1a;/*92ee*/
/* bfsync */
u8 framesync;
u32 framesync_c34;
u8 num_total_rfpath;
struct phy_parameters hwparam_tables[MAX_TAB];
u16 rf_pathmap;
u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
enum rt_polarity_ctl polarity_ctl;
/* ULLI : Border from old (struct rtw_hal) */
#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 4 // CCK:1,OFDM:2, HT:2
#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 // OFDM:1, HT:2, VHT:2
/* ULLI: neded to convert this */
//---------------------------------------------------------------------------------//
// Power Limit Table for 2.4G
};
#define AVG_THERMAL_NUM 8
#define IQK_Matrix_REG_NUM 8
#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[].
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
struct fast_ant_training {
u8 bssid[6];
u8 antsel_rx_keep_0;
u8 antsel_rx_keep_1;
u8 antsel_rx_keep_2;
u32 ant_sum[7];
u32 ant_cnt[7];
u32 ant_ave[7];
u8 fat_state;
u32 train_idx;
u8 antsel_a[ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ASSOCIATE_ENTRY_NUM];
u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
u8 rx_idle_ant;
bool becomelinked;
};
struct dm_phy_dbg_info {
char rx_snrdb[4];
u64 num_qry_phy_status;
u64 num_qry_phy_status_cck;
u64 num_qry_phy_status_ofdm;
u16 num_qry_beacon_pkt;
u16 num_non_be_pkt;
s32 rx_evm[4];
};