From 37caf26a23e55f35d4d5afa45b615c0b97fd3cfd Mon Sep 17 00:00:00 2001 From: John Patrick Drab Date: Mon, 8 Apr 2024 00:18:38 -0700 Subject: [PATCH 1/2] Fixed file path error when no output dir specified --- src/main/scala/Compiler.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/main/scala/Compiler.scala b/src/main/scala/Compiler.scala index 53a0c6f..b55df96 100644 --- a/src/main/scala/Compiler.scala +++ b/src/main/scala/Compiler.scala @@ -335,7 +335,7 @@ class EssentCompiler(opt: OptFlags) { def compileAndEmit(circuit: Circuit): Unit = { val topName = circuit.main if (opt.writeHarness) { - val harnessFilename = new File(opt.outputDir(), s"$topName-harness.cc") + val harnessFilename = new File(opt.outputDir, s"$topName-harness.cc") val harnessWriter = new FileWriter(harnessFilename) if (opt.withVCD) { HarnessGenerator.topFile(topName, harnessWriter," | dut.genWaveHeader();") } else { HarnessGenerator.topFile(topName, harnessWriter, "")} @@ -344,11 +344,16 @@ class EssentCompiler(opt: OptFlags) { val firrtlCompiler = new transforms.Compiler(readyForEssent) val resultState = firrtlCompiler.execute(CircuitState(circuit, Seq())) if (opt.dumpLoFirrtl) { - val debugWriter = new FileWriter(new File(opt.outputDir(), s"$topName.lo.fir")) + val debugFilename = new File(opt.outputDir, s"$topName.lo.fir") + val debugWriter = new FileWriter(debugFilename) debugWriter.write(resultState.circuit.serialize) debugWriter.close() } - val dutWriter = new FileWriter(new File(opt.outputDir(), s"$topName.h")) + + val outputDir = if (opt.outputDir.nonEmpty) opt.outputDir else System.getProperty("user.dir") + val dutFile = new File(outputDir, s"$topName.h") + + val dutWriter = new FileWriter(dutFile) val emitter = new EssentEmitter(opt, dutWriter,resultState.circuit) emitter.execute(resultState.circuit) dutWriter.close() From de62c16c65420a01ab9e3f67113cd9a3d3cb3433 Mon Sep 17 00:00:00 2001 From: John Patrick Drab Date: Mon, 8 Apr 2024 00:28:42 -0700 Subject: [PATCH 2/2] Specified empty list for outputDir --- src/main/scala/Compiler.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/Compiler.scala b/src/main/scala/Compiler.scala index b55df96..3d80439 100644 --- a/src/main/scala/Compiler.scala +++ b/src/main/scala/Compiler.scala @@ -335,7 +335,7 @@ class EssentCompiler(opt: OptFlags) { def compileAndEmit(circuit: Circuit): Unit = { val topName = circuit.main if (opt.writeHarness) { - val harnessFilename = new File(opt.outputDir, s"$topName-harness.cc") + val harnessFilename = new File(opt.outputDir(), s"$topName-harness.cc") val harnessWriter = new FileWriter(harnessFilename) if (opt.withVCD) { HarnessGenerator.topFile(topName, harnessWriter," | dut.genWaveHeader();") } else { HarnessGenerator.topFile(topName, harnessWriter, "")} @@ -344,13 +344,13 @@ class EssentCompiler(opt: OptFlags) { val firrtlCompiler = new transforms.Compiler(readyForEssent) val resultState = firrtlCompiler.execute(CircuitState(circuit, Seq())) if (opt.dumpLoFirrtl) { - val debugFilename = new File(opt.outputDir, s"$topName.lo.fir") + val debugFilename = new File(opt.outputDir(), s"$topName.lo.fir") val debugWriter = new FileWriter(debugFilename) debugWriter.write(resultState.circuit.serialize) debugWriter.close() } - val outputDir = if (opt.outputDir.nonEmpty) opt.outputDir else System.getProperty("user.dir") + val outputDir = if (opt.outputDir().nonEmpty) opt.outputDir() else System.getProperty("user.dir") val dutFile = new File(outputDir, s"$topName.h") val dutWriter = new FileWriter(dutFile)