From 1d52899736a01ed27b4415d5e33c9ec73a4e0568 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 00:27:11 -0700 Subject: [PATCH 1/9] Remove GenerateSimFiles and use make instead --- build.sbt | 8 +- common.mk | 8 +- .../src/main/resources/csrc/emulator.cc | 0 .../src/main/scala/ConfigFragments.scala | 3 +- .../utilities/src/main/resources/bootrom | 1 - .../utilities/src/main/scala/Simulator.scala | 143 ------------------ sims/common-sim-flags.mk | 16 ++ sims/vcs/Makefile | 16 ++ sims/verilator/Makefile | 21 ++- variables.mk | 13 +- 10 files changed, 69 insertions(+), 160 deletions(-) rename generators/{utilities => chipyard}/src/main/resources/csrc/emulator.cc (100%) delete mode 120000 generators/utilities/src/main/resources/bootrom delete mode 100644 generators/utilities/src/main/scala/Simulator.scala diff --git a/build.sbt b/build.sbt index f44eeb66b8..3123c4b803 100644 --- a/build.sbt +++ b/build.sbt @@ -183,7 +183,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) @@ -192,14 +192,10 @@ lazy val chipyard = (project in file("generators/chipyard")) lazy val tracegen = (project in file("generators/tracegen")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(rocketchip, sifive_cache, boom, utilities) + .dependsOn(rocketchip, sifive_cache, boom) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val utilities = (project in file("generators/utilities")) - .sourceDependency(testchipip, testchipipLib) - .settings(commonSettings) - lazy val icenet = (project in file("generators/icenet")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) diff --git a/common.mk b/common.mk index 89e998bdaf..b876340edd 100644 --- a/common.mk +++ b/common.mk @@ -20,7 +20,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client" -EXTRA_GENERATOR_REQS ?= +EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= @@ -85,10 +85,10 @@ else endif ######################################################################################### -# create list of simulation file inputs +# copy over bootrom files ######################################################################################### -$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS) - $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name)) +$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) + cp -f $< $@ ######################################################################################### # create firrtl file rule and variables diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/chipyard/src/main/resources/csrc/emulator.cc similarity index 100% rename from generators/utilities/src/main/resources/csrc/emulator.cc rename to generators/chipyard/src/main/resources/csrc/emulator.cc diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index a36285ebeb..a887bc1c6d 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.tilelink.{HasTLBusParams} import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ +import freechips.rocketchip.stage.phases.TargetDirKey import testchipip._ import tracegen.{TraceGenSystem} @@ -36,7 +37,7 @@ import chipyard._ // ----------------------- class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")) + case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) }) // DOC include start: gpio config fragment diff --git a/generators/utilities/src/main/resources/bootrom b/generators/utilities/src/main/resources/bootrom deleted file mode 120000 index fb0b1375ae..0000000000 --- a/generators/utilities/src/main/resources/bootrom +++ /dev/null @@ -1 +0,0 @@ -../../../../rocket-chip/bootrom \ No newline at end of file diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala deleted file mode 100644 index fa157a3652..0000000000 --- a/generators/utilities/src/main/scala/Simulator.scala +++ /dev/null @@ -1,143 +0,0 @@ -package utilities - -import java.io.File - -case class GenerateSimConfig( - targetDir: String = ".", - dotFName: String = "sim_files.f", - simulator: Option[Simulator] = Some(VerilatorSimulator) -) - -sealed trait Simulator -object VerilatorSimulator extends Simulator -object VCSSimulator extends Simulator - -trait HasGenerateSimConfig { - val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { - head("GenerateSimFiles", "0.1") - - opt[String]("simulator") - .abbr("sim") - .valueName("") - .action((x, c) => x match { - case "verilator" => c.copy(simulator = Some(VerilatorSimulator)) - case "vcs" => c.copy(simulator = Some(VCSSimulator)) - case "none" => c.copy(simulator = None) - case _ => throw new Exception(s"Unrecognized simulator $x") - }) - .text("Name of simulator to generate files for (verilator, vcs, none)") - - opt[String]("target-dir") - .abbr("td") - .valueName("") - .action((x, c) => c.copy(targetDir = x)) - .text("Target directory to put files") - - opt[String]("dotFName") - .abbr("df") - .valueName("") - .action((x, c) => c.copy(dotFName = x)) - .text("Name of generated dot-f file") - } -} - -object GenerateSimFiles extends App with HasGenerateSimConfig { - def addOption(file: File, cfg: GenerateSimConfig): String = { - val fname = file.getCanonicalPath - // deal with header files - if (fname.takeRight(2) == ".h") { - cfg.simulator match { - // verilator needs to explicitly include verilator.h, so use the -FI option - case Some(VerilatorSimulator) => s"-FI ${fname}" - // vcs pulls headers in with +incdir, doesn't have anything like verilator.h - case Some(VCSSimulator) => "" - case None => "" - } - } else { // do nothing otherwise - fname - } - } - def writeDotF(lines: Seq[String], cfg: GenerateSimConfig): Unit = { - writeTextToFile(lines.mkString("\n"), new File(cfg.targetDir, cfg.dotFName)) - } - // From FIRRTL - def safeFile[A](fileName: String)(code: => A) = try { code } catch { - case e@ (_: java.io.FileNotFoundException | _: NullPointerException) => throw new Exception(fileName, e) - case t: Throwable => throw t - } - // From FIRRTL - def writeResource(name: String, targetDir: String): File = { - val in = getClass.getResourceAsStream(name) - val p = java.nio.file.Paths.get(name) - val fname = p.getFileName().toString(); - - val f = new File(targetDir, fname) - val out = new java.io.FileOutputStream(f) - safeFile(name)(Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write)) - out.close() - f - } - // From FIRRTL - def writeTextToFile(text: String, file: File) { - val out = new java.io.PrintWriter(file) - out.write(text) - out.close() - } - def resources(sim: Option[Simulator]): Seq[String] = Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/testchip_tsi.cc", - "/testchipip/csrc/testchip_tsi.h", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", - "/vsrc/EICG_wrapper.v", - ) ++ (sim match { - case None => Seq() - case _ => Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", - ) - }) ++ (sim match { // simulator specific files to include - case Some(VerilatorSimulator) => Seq( - "/csrc/emulator.cc", - "/csrc/verilator.h", - ) - case Some(VCSSimulator) => Seq( - "/vsrc/TestDriver.v", - ) - case None => Seq() - }) - - def writeBootrom(): Unit = { - firrtl.FileUtils.makeDirectory("./bootrom/") - writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") - writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/") - writeResource("/bootrom/bootrom.img", "./bootrom/") - } - - def writeFiles(cfg: GenerateSimConfig): Unit = { - writeBootrom() - firrtl.FileUtils.makeDirectory(cfg.targetDir) - val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) } - writeDotF(files.map(addOption(_, cfg)), cfg) - } - - parser.parse(args, GenerateSimConfig()) match { - case Some(cfg) => writeFiles(cfg) - case _ => // error message already shown - } -} diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 766dd0d31e..25af4dafee 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -21,3 +21,19 @@ SIM_LDFLAGS = \ -lfesvr \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) + +SIM_FILE_REQS += \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 405cda5441..a268c3ce8b 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -31,6 +31,22 @@ include $(base_dir)/vcs.mk default: $(sim) debug: $(sim_debug) +######################################################################################### +# simulaton requirements +######################################################################################### +SIM_FILE_REQS += \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v + +# ignore *.h files since vcs has +incdir +$(sim_files): $(SIM_FILE_REQS) + mkdir -p $(dir $(sim_files)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + ######################################################################################### # import other necessary rules and variables ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 2b250ee964..1cb3cf86b5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -30,6 +30,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug WAVEFORM_FLAG=-v$(sim_out_name).vcd +include $(base_dir)/sims/common-sim-flags.mk + # If verilator seed unspecified, verilator uses srand as random seed ifdef RANDOM_SEED SEED_FLAG=+verilator+seed+I$(RANDOM_SEED) @@ -41,6 +43,23 @@ endif default: $(sim) debug: $(sim_debug) +######################################################################################### +# simulaton requirements +######################################################################################### +SIM_FILE_REQS += \ + $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h + +# add -FI for *.h files +$(sim_files): $(SIM_FILE_REQS) + mkdir -p $(dir $(sim_files)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + ######################################################################################### # import other necessary rules and variables ######################################################################################### @@ -141,8 +160,6 @@ VERILATOR_NONCC_OPTS = \ #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- -include $(base_dir)/sims/common-sim-flags.mk - VERILATOR_CXXFLAGS = \ $(SIM_CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ diff --git a/variables.mk b/variables.mk index 2843e53e54..5d1e7d7fc0 100644 --- a/variables.mk +++ b/variables.mk @@ -106,9 +106,12 @@ endif ######################################################################################### # path to rocket-chip and testchipip ######################################################################################### -ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip -CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl +ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip +ROCKETCHIP_RSRCS_DIR = $(ROCKETCHIP_DIR)/src/main/resources +TESTCHIP_DIR = $(base_dir)/generators/testchipip +TESTCHIP_RSRCS_DIR = $(TESTCHIP_DIR)/src/main/resources +CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl +CHIPYARD_RSRCS_DIR = $(base_dir)/generators/chipyard/src/main/resources ######################################################################################### # names of various files needed to compile and run things @@ -135,7 +138,11 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img +BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) + # files that contain lists of files needed for VCS or Verilator simulation +SIM_FILE_REQS = sim_files ?= $(build_dir)/sim_files.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f From 9cdd0e1ff21c4a831c3d9bb4f0cc8b5ac27e4150 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 00:30:46 -0700 Subject: [PATCH 2/9] Replace spaces with tabs --- sims/common-sim-flags.mk | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 25af4dafee..d305d392bc 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -32,8 +32,7 @@ SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc - + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc From 95f55a667f0b8f49c6dd63bc8f9b1011e01a774c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 14:45:45 -0700 Subject: [PATCH 3/9] Elaborate comments a bit more | Remove BB'ed files that are auto-copied/added --- sims/common-sim-flags.mk | 14 +------------- sims/vcs/Makefile | 2 +- sims/verilator/Makefile | 2 +- 3 files changed, 3 insertions(+), 15 deletions(-) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index d305d392bc..7c6c580d6e 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -23,16 +23,4 @@ SIM_LDFLAGS = \ $(EXTRA_SIM_LDFLAGS) SIM_FILE_REQS += \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index a268c3ce8b..f0fc90e546 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -37,7 +37,7 @@ debug: $(sim_debug) SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v -# ignore *.h files since vcs has +incdir +# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) $(sim_files): $(SIM_FILE_REQS) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 1cb3cf86b5..9c8f3fa6f8 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -50,7 +50,7 @@ SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h -# add -FI for *.h files +# copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) From eb85415783f25f0cf51b624b4cf1f6f8ba6a20c4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 15:09:40 -0700 Subject: [PATCH 4/9] Have Verilator build with unused simulation files --- sims/verilator/Makefile | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9c8f3fa6f8..00c0f1bb37 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -46,9 +46,21 @@ debug: $(sim_debug) ######################################################################################### # simulaton requirements ######################################################################################### +# past emulator.cc and verilator.h, the other files may not be used in the simulation but +# are needed for emulator.cc to compile SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h + $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) From a0de9a0cfbbdc22aed9217111a7ca7b4b116067c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 20:36:28 -0700 Subject: [PATCH 5/9] Depend on build_dir --- common.mk | 3 +++ sims/vcs/Makefile | 2 +- sims/verilator/Makefile | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index b876340edd..6ab88d7ecb 100644 --- a/common.mk +++ b/common.mk @@ -87,6 +87,9 @@ endif ######################################################################################### # copy over bootrom files ######################################################################################### +$(build_dir): + mkdir -p $@ + $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) cp -f $< $@ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index f0fc90e546..cc4d231722 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -38,7 +38,7 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 00c0f1bb37..6510090efc 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -63,7 +63,7 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f -$(sim_files): $(SIM_FILE_REQS) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ From 453b1b5d9506e4dc6eac73735ccb3fa2840d90a7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 22:11:02 -0700 Subject: [PATCH 6/9] Fix tutorial patch --- scripts/tutorial-patches/build.sbt.patch | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 62cecb8df4..325bdfaee1 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,17 +1,17 @@ diff --git a/build.sbt b/build.sbt -index e80b2a5..b1989d9 100644 +index 3123c4b8..487fc428 100644 --- a/build.sbt +++ b/build.sbt @@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(libraryDependencies ++= rocketLibDeps.value) -@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) +@@ -223,11 +223,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From 2874c988024335f6325f51652809c020d2996e3f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 22:11:58 -0700 Subject: [PATCH 7/9] Add sim_files.f to fpga --- fpga/Makefile | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/fpga/Makefile b/fpga/Makefile index 1437d8bc76..a7166347bf 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -73,6 +73,22 @@ default: $(mcs) fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND) fpga_common_script_dir := $(fpga_dir)/common/tcl +######################################################################################### +# setup misc. sim files +######################################################################################### +SIM_FILE_REQS += \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v + +# copy files but ignore *.h files in *.f (match vcs) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) + mkdir -p $(dir $(sim_files)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + ######################################################################################### # import other necessary rules and variables ######################################################################################### From 383d11c2ad1825f11f446593ba039809c70a3ccd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 22:32:40 -0700 Subject: [PATCH 8/9] Forgot to add testchip_tsi.* to verilator --- sims/verilator/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 6510090efc..26cae3e431 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -52,6 +52,8 @@ SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ From 16cdc88c520b491035f24f8e56fef5dba07a3105 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 12 May 2021 16:42:05 -0700 Subject: [PATCH 9/9] Small comment + org. fix | Remove extra mkdirs --- fpga/Makefile | 1 - sims/vcs/Makefile | 1 - sims/verilator/Makefile | 6 +++--- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index a7166347bf..8b2ed28bcd 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -81,7 +81,6 @@ SIM_FILE_REQS += \ # copy files but ignore *.h files in *.f (match vcs) $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ $^,\ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index cc4d231722..e364830be0 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -39,7 +39,6 @@ SIM_FILE_REQS += \ # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ $^,\ diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 26cae3e431..a1186acc74 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -46,11 +46,12 @@ debug: $(sim_debug) ######################################################################################### # simulaton requirements ######################################################################################### -# past emulator.cc and verilator.h, the other files may not be used in the simulation but -# are needed for emulator.cc to compile SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ + +# the following files are needed for emulator.cc to compile +SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ @@ -66,7 +67,6 @@ SIM_FILE_REQS += \ # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ $^,\