From ad838f0c83495a26f8f7ec9e445b6798974d2dde Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Mar 2024 23:42:01 -0700 Subject: [PATCH 1/6] Ignore uvm_macros.svh | we don't support UVM in included veriog --- scripts/insert-includes.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index 8262c251c1..c54821967d 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -34,7 +34,8 @@ def process(inF, outF): # for each include found, search through all dirs and replace if found, error if not for num, line in enumerate(inFile, 1): match = re.match(r"^ *`include +\"(.*)\"", line) - if match: + if match and match.group(1) != "uvm_macros.svh": + print("[INFO] Replacing includes for {}".format(match.group(1))) # search for include and replace found = False for d in incDirs: From 78adbc670b9faf448bad0796116c941386ea7662 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Mar 2024 23:42:23 -0700 Subject: [PATCH 2/6] Add print INFO to header modification script --- scripts/insert-includes.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index c54821967d..b939878aad 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -42,6 +42,7 @@ def process(inF, outF): potentialIncFileName = d + "/" + match.group(1) if os.path.exists(potentialIncFileName): found = True + print("[INFO] Found missing include in {}".format(potentialIncFileName)) with open(potentialIncFileName, 'r') as incFile: for iline in incFile: outFile.write(iline) From edf6d9ed195e3c1df12382996392b0960f1b88a6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Mar 2024 23:45:38 -0700 Subject: [PATCH 3/6] Append EXT_FILELISTS to sim_common.f --- common.mk | 9 +++++++-- variables.mk | 6 ++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 34c0878623..a2e31b5140 100644 --- a/common.mk +++ b/common.mk @@ -310,8 +310,13 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_S # note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated, # however it is really unneeded since ALL_MODS_FILELIST includes all BB files ######################################################################################## -$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) - sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@ +$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) $(EXT_FILELISTS) +ifneq (,$(EXT_FILELISTS)) + cat $(EXT_FILELISTS) > $@ +else + rm -f $@ +endif + sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' >> $@ echo "$(TOP_SMEMS_FILE)" >> $@ echo "$(MODEL_SMEMS_FILE)" >> $@ diff --git a/variables.mk b/variables.mk index 20154c2468..3bebdb1acb 100644 --- a/variables.mk +++ b/variables.mk @@ -213,6 +213,12 @@ BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f # all module files to include (top, model, bb included) ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f +# external filelists. Users, or project-supplied make fragments can append filelists +# with absolute paths here +EXT_FILELISTS ?= +# external verilog incdirs. Users, or project-supplied make fragments can append to this +EXT_INCDIRS ?= + BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) From 7b3d3e54bdd59c0ad5a7f97cf51c56ef7f4b0102 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Mar 2024 23:48:51 -0700 Subject: [PATCH 4/6] Add incdirs to vcs/verilator flows --- sims/vcs/vcs.mk | 3 ++- sims/verilator/Makefile | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/sims/vcs/vcs.mk b/sims/vcs/vcs.mk index 0a26a48788..984301bc0b 100644 --- a/sims/vcs/vcs.mk +++ b/sims/vcs/vcs.mk @@ -51,7 +51,8 @@ VCS_NONCC_OPTS = \ -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ - +incdir+$(GEN_COLLATERAL_DIR) + +incdir+$(GEN_COLLATERAL_DIR) \ + $(addprefix +incdir+,$(EXT_INCDIRS)) VCS_PREPROC_DEFINES = \ +define+VCS diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 86463fa1a5..d7b1f14879 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -154,6 +154,7 @@ VERILATOR_NONCC_OPTS = \ $(VERILATOR_PREPROC_DEFINES) \ --top-module $(TB) \ --vpi \ + $(addprefix +incdir+,$(EXT_INCDIRS)) \ -f $(sim_common_files) #---------------------------------------------------------------------------------------- From 4ce6198b863cff5c7b986bc562233d6c23d6ee6b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Mar 2024 23:49:08 -0700 Subject: [PATCH 5/6] Pass -top flag to VCS to avoid simulating non-tops --- sims/vcs/vcs.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/sims/vcs/vcs.mk b/sims/vcs/vcs.mk index 984301bc0b..a910106718 100644 --- a/sims/vcs/vcs.mk +++ b/sims/vcs/vcs.mk @@ -51,6 +51,7 @@ VCS_NONCC_OPTS = \ -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ + -top $(TB) \ +incdir+$(GEN_COLLATERAL_DIR) \ $(addprefix +incdir+,$(EXT_INCDIRS)) From 39f28aeaacf478928540ad4f81b4d3f675d12f83 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 20 Mar 2024 13:57:04 -0700 Subject: [PATCH 6/6] Append EXT_FILELISTS to VLSI deps --- vlsi/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 14feb6fbd7..ef9e2282bd 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -72,7 +72,7 @@ VLSI_RTL = $(build_dir)/syn.f ifneq ($(CUSTOM_VLOG), ) RTL_DEPS = $(CUSTOM_VLOG) else - RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) + RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) $(EXT_FILELISTS) endif $(VLSI_RTL): $(RTL_DEPS) @@ -82,6 +82,9 @@ ifneq ($(CUSTOM_VLOG), ) else cat $(TOP_MODS_FILELIST) | sort -u > $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) +ifneq ($(EXT_FILELISTS),) + cat $(EXT_FILELISTS) >> $(VLSI_RTL) +endif endif #########################################################################################