diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 4a0fb293a4..213425f57b 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -21,17 +21,19 @@ class WithNoDesignKey extends Config((site, here, up) => {
   case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
 })
 
-class WithArty100TTweaks extends Config(
+class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
   new WithNoDesignKey ++
   new testchipip.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
-  new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithFrontBusFrequency(50.0) ++
-  new chipyard.config.WithSystemBusFrequency(50.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+  new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
+  new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
+  new chipyard.config.WithFrontBusFrequency(freqMHz) ++
+  new chipyard.config.WithSystemBusFrequency(freqMHz) ++
+  new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
+  new chipyard.config.WithControlBusFrequency(freqMHz) ++
+  new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithNoDebug ++ // no jtag
@@ -45,22 +47,14 @@ class RocketArty100TConfig extends Config(
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.RocketConfig)
 
-class UART230400RocketArty100TConfig extends Config(
-  new WithArty100TUARTTSI(uartBaudRate = 230400) ++
-  new RocketArty100TConfig)
-
-class UART460800RocketArty100TConfig extends Config(
-  new WithArty100TUARTTSI(uartBaudRate = 460800) ++
-  new RocketArty100TConfig)
-
-class UART921600RocketArty100TConfig extends Config(
-  new WithArty100TUARTTSI(uartBaudRate = 921600) ++
-  new RocketArty100TConfig)
-
-
 class NoCoresArty100TConfig extends Config(
   new WithArty100TTweaks ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(50.0) ++  // Match the sbus and pbus frequency
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.NoCoresConfig)
+
+// This will fail to close timing above 50 MHz
+class BringupArty100TConfig extends Config(
+  new WithArty100TSerialTLToGPIO ++
+  new WithArty100TTweaks(freqMHz = 50) ++
+  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new chipyard.ChipBringupHostConfig)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index e313c6e176..4c82197081 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -1,6 +1,7 @@
 package chipyard.fpga.arty100t
 
 import chisel3._
+import chisel3.experimental.{DataMirror, Direction}
 
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
@@ -11,16 +12,17 @@ import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
 import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}
-
-import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
-
+import sifive.fpgashells.shell._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.clocks._
 import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
 
 import testchipip._
 
-class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
+class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     ath.io_uart_bb.bundle <> port.io.uart
@@ -41,3 +43,43 @@ class WithArty100TDDRTL extends HarnessBinder({
     ddrClientBundle <> port.io
   }
 })
+
+// Uses PMOD JA/JB
+class WithArty100TSerialTLToGPIO extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+    val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
+    harnessIO <> port.io
+    val clkIO = IOPin(harnessIO.clock)
+    val packagePinsWithPackageIOs = Seq(
+      ("G13", clkIO),
+      ("B11", IOPin(harnessIO.bits.out.valid)),
+      ("A11", IOPin(harnessIO.bits.out.ready)),
+      ("D12", IOPin(harnessIO.bits.in.valid)),
+      ("D13", IOPin(harnessIO.bits.in.ready)),
+      ("B18", IOPin(harnessIO.bits.out.bits, 0)),
+      ("A18", IOPin(harnessIO.bits.out.bits, 1)),
+      ("K16", IOPin(harnessIO.bits.out.bits, 2)),
+      ("E15", IOPin(harnessIO.bits.out.bits, 3)),
+      ("E16", IOPin(harnessIO.bits.in.bits, 0)),
+      ("D15", IOPin(harnessIO.bits.in.bits, 1)),
+      ("C15", IOPin(harnessIO.bits.in.bits, 2)),
+      ("J17", IOPin(harnessIO.bits.in.bits, 3))
+    )
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      artyTh.xdc.addPackagePin(io, pin)
+      artyTh.xdc.addIOStandard(io, "LVCMOS33")
+    }}
+
+    // Don't add IOB to the clock, if its an input
+    if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
+      packagePinsWithPackageIOs foreach { case (pin, io) => {
+        artyTh.xdc.addIOB(io)
+      }}
+    }
+
+    artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
+    artyTh.sdc.addGroup(pins = Seq(clkIO))
+    artyTh.xdc.clockDedicatedRouteFalse(clkIO)
+  }
+})
diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index 2da9fbf283..567cc2f75b 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
 
 import chipyard._
 import chipyard.clocking._
+import testchipip.{OffchipBusKey}
 
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
@@ -103,6 +104,9 @@ class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) =>
 class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
   case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
+class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
+  case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+})
 
 class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
 class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())