From 74f4c8c1d711e1d78f9f265c8d74974cf692f3dd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 13 Feb 2023 18:46:20 -0800 Subject: [PATCH 1/3] Add a NoCore config - useful for testing --- .../chipyard/src/main/scala/Subsystem.scala | 17 +++++++++++++++++ .../main/scala/clocking/TileResetSetter.scala | 7 ++++--- .../src/main/scala/config/NoCoreConfigs.scala | 9 +++++++++ .../config/fragments/PeripheralFragments.scala | 8 ++++++-- generators/rocket-chip | 2 +- 5 files changed, 37 insertions(+), 6 deletions(-) create mode 100644 generators/chipyard/src/main/scala/config/NoCoreConfigs.scala diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 703b404e72..1ef19b3926 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -54,6 +54,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem case b: BoomTile => b.module.core.coreMonitorBundle }.toList + // No-tile configs have to be handled specially. + if (tiles.size == 0) { + // no PLIC, so sink interrupts to nowhere + require(!p(PLICKey).isDefined) + val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head) + val intSink = IntSinkNode(IntSinkPortSimple()) + intSink := intNexus :=* ibus.toPLIC + + // Need to have at least 1 driver to the tile notification sinks + tileHaltXbarNode := IntSourceNode(IntSourcePortSimple()) + tileWFIXbarNode := IntSourceNode(IntSourcePortSimple()) + tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple()) + + // Sink reset vectors to nowhere + val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W))) + resetVectorSink := tileResetVectorNode + } // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for // bus-couplings that are not asynchronous strips the bus name from the sink diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index 84b8883044..b67371d520 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -33,9 +33,10 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0))) } }) - tlNode.regmap((0 until nTiles).map({ i => - i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) - }): _*) + if (nTiles > 0) + tlNode.regmap((0 until nTiles).map({ i => + i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) + }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => n -> (tile_async_resets(i), r_tile_resets(i).io.q) diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala new file mode 100644 index 0000000000..9d0c4132e5 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -0,0 +1,9 @@ +package chipyard + +import freechips.rocketchip.config.{Config} + +// A empty config with no cores. Useful for testing +class NoCoresConfig extends Config( + new chipyard.config.WithNoDebug ++ + new chipyard.config.WithNoPLIC ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index b12abe706e..eec0d15dd2 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -5,7 +5,7 @@ import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Config} -import freechips.rocketchip.devices.tilelink.{BootROMLocated} +import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ @@ -77,5 +77,9 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => { }) class WithExtMemIdBits(n: Int) extends Config((site, here, up) => { - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n))) + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n))) +}) + +class WithNoPLIC extends Config((site, here, up) => { + case PLICKey => None }) diff --git a/generators/rocket-chip b/generators/rocket-chip index 3b5fb3c043..ab9adc006c 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 3b5fb3c043ccc2cea81ed7a44b295f4652d0ba02 +Subproject commit ab9adc006c5789baeac6930c5e83a81c2723a305 From 0cc583e67ac0bea9489b42494c8b4cab5cd9b31e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 13 Feb 2023 18:48:09 -0800 Subject: [PATCH 2/3] Add no-cores config to CI --- .github/scripts/defaults.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index e6671996c7..a938188f7f 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -26,7 +26,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif chipyard-nocores" grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -55,6 +55,7 @@ mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" +mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" From 2096ffa7afd5be6b08421dc813798ddbf15d814a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 14 Feb 2023 00:35:30 -0800 Subject: [PATCH 3/3] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index ab9adc006c..f5ebf26b36 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit ab9adc006c5789baeac6930c5e83a81c2723a305 +Subproject commit f5ebf26b369922b2924d71e185c473c0385bf54e