class AbstractConfig extends Config(
    // The HarnessBinders control generation of hardware in the TestHarness
     new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display ART on stdout, if wart is present
     new chipyard.harness.WithGPIOTiedoff ++ // tie-off chiptop GPIOs, if GPIOs are present
     new chipyard.harness.WithSimSPIFlashModel++ // add simulated SPI flash memory, if SPI is enabled
     new chipyard.harness.WithTieoffInterrupts++   // tie-off interrupt ports, if present
     new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
     new chipyard.harness.WithTieOffCustomBootPin++
     // The IOBinders instantiate ChipTop Is to match desired digital IOs
     // I0Cells are generated for "Chip-like" I0s, while simulation-only I0s are directly punched through
     new chipyard.iobinders.WithAXI4MemPunchthrough++
     new chipyard.iobinders.WithAXI4MMIOPunchthrough++
     new chipyard.iobinders.WithL2FBusAXI4Punchthrough++
     new chipyard.iobinders.WithBlockDeviceIOPunchthrough++
     new chipyard.iobinders.WithNICIOPunchthrough++
     new chipyard.iobinders.WithSerialTLIOCells++
     new chipyard.iobinders.WithDebugIOCells++
     new chipyard.iobinders.WithUARTIOCells++
     new chipyard.iobinders.WithGPIOCells++
     new chipyard.iobinders.WithUARTIOCells++
     new chipyard.iobinders.WithSPIIOCells++
     new chipyard.iobinders.WithTraceIOPunchthrough++
     new chipyard.iobinders.WithExtInterruptIOCells++
     new chipyard.iobinders.WithCustomBootPin++
     
     new testchipip.WithDefaultSerialTL++ // use serialized tilelink port to external serialadapter/harnessRAM
     new chipyard.config.WithBootROM++ // use default bootrom
     new chipyard.config.WithUART++ // add a UART
     //new chipyard.config.WithL2TLBs (1024) ++ // use L2 TLBS
     new chipyard.config.WithNoSubsystemDrivenClocks++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
     new chipyard.config.WithInheritBusFrequencyAssignments++ // Unspecified clocks within a bus will receive the bus frequency if set
     new chipyard.config.WithperipheryBusFrequencyAsDefault++ // Unspecified frequencies with match the pus frequency (which is always set)
    new chipyard.config.WithMemoryBusFrequency(100.0)++ // Default 100 MHz mbus
    new chipyard.config.WithPeripheryBusFrequency(100.0)++// Default 100 MHz pbus
    new freechips.rocketchip.subsystem.WithJtagTM++ // set the debug module to expose a JAG port
    new freechips.rocketchip.subsystem.WithNoMMIOPort++// no top-level MMIO master port (overrides default set in rocketchip)
    new freechips.rocketchip.subsystem.WithNoslavePort++// no top-level MMO slave port (overrides default set in rocketchip)
    new freechips.rocketchip.subsystem.WithInclusiveCache++// use Sifive L2 cache
    new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0)++//noexternalinterrupts
    new chipyard.WithMulticlockCoherentBusTopology++ //hierarchical buses including


class WithArtyTweaks extends Config(
  new WithUART ++
  new WithDDRMem ++
  new WithArty100TJTAGHarnessBinder ++
  new WithDebugResetPassthrough ++
  new WithTLIOPassthrough ++
  new WithUARTIOPassthrough ++
  new WithDefaultPeripherals ++
  new chipyard.config.WithTLBackingMemory ++
  new WithSystemModifications ++
  new WithArtyResetHarnessBinder ++
  //new chipyard.config.WithNoDebug ++
  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
  //new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
  new WithFPGAFrequency(50))