From f6836f74c97dc604773c72c01ac850b643326943 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 4 Jan 2023 01:46:45 -0800 Subject: [PATCH] Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip --- build.sbt | 25 +++++------ fpga/fpga-shells | 2 +- generators/boom | 2 +- .../src/main/scala/HarnessBinders.scala | 14 ++++++- .../chipyard/src/main/scala/IOBinders.scala | 6 +-- .../chipyard/src/main/scala/TestSuites.scala | 4 ++ .../clocking/DividerOnlyClockGenerator.scala | 3 +- .../main/scala/clocking/TileResetSetter.scala | 2 +- .../config/fragments/TileFragments.scala | 4 +- .../src/main/scala/example/TutorialTile.scala | 5 +++ .../scala/stage/phases/AddDefaultTests.scala | 2 +- generators/constellation | 2 +- generators/cva6 | 2 +- generators/fft-generator | 2 +- .../src/main/scala/BridgeBinders.scala | 6 +-- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/ibex | 2 +- generators/icenet | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/sha3 | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- generators/testchipip | 2 +- project/plugins.sbt | 2 +- scripts/build-setup.sh | 41 ++++++++++--------- sims/firesim | 2 +- toolchains/riscv-tools/riscv-tests | 2 +- tools/barstools | 2 +- tools/dsptools | 2 +- tools/rocket-dsp-utils | 2 +- 32 files changed, 85 insertions(+), 69 deletions(-) diff --git a/build.sbt b/build.sbt index ec36a85fe0..e8f999c005 100644 --- a/build.sbt +++ b/build.sbt @@ -7,13 +7,12 @@ lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.6", - scalaVersion := "2.12.10", + scalaVersion := "2.13.10", assembly / test := {}, assembly / assemblyMergeStrategy := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, - scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), + scalacOptions ++= Seq("-deprecation","-unchecked"), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop specific maven dependencies in subprojects in favor of Chipyard's version @@ -60,7 +59,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.2" +val chiselVersion = "3.5.5" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, @@ -68,9 +67,6 @@ lazy val chiselSettings = Seq( "org.apache.commons" % "commons-text" % "1.9"), addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) -val firrtlVersion = "1.5.1" - -lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion)) val chiselTestVersion = "2.5.1" @@ -88,7 +84,7 @@ lazy val hardfloat = (project in rocketChipDir / "hardfloat") .settings( libraryDependencies ++= Seq( "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.json4s" %% "json4s-jackson" % "3.6.6", "org.scalatest" %% "scalatest" % "3.2.0" % "test" ) ) @@ -98,7 +94,7 @@ lazy val rocketMacros = (project in rocketChipDir / "macros") .settings( libraryDependencies ++= Seq( "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.json4s" %% "json4s-jackson" % "3.6.6", "org.scalatest" %% "scalatest" % "3.2.0" % "test" ) ) @@ -108,7 +104,7 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings( libraryDependencies ++= Seq( "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.json4s" %% "json4s-jackson" % "3.6.6", "org.scalatest" %% "scalatest" % "3.2.0" % "test" ) ) @@ -120,15 +116,14 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) .settings( libraryDependencies ++= Seq( "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.1", - "org.apache.commons" % "commons-lang3" % "3.12.0", + "org.json4s" %% "json4s-jackson" % "3.6.6", "org.scalatest" %% "scalatest" % "3.2.0" % "test" ) ) .settings( // Settings for scalafix semanticdbEnabled := true, semanticdbVersion := scalafixSemanticdb.revision, - scalacOptions += "-Ywarn-unused-import" + scalacOptions += "-Ywarn-unused" ) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) @@ -185,7 +180,7 @@ lazy val hwacha = (project in file("generators/hwacha")) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) - .dependsOn(testchipip, rocketchip) + .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -242,7 +237,7 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) commonSettings, libraryDependencies ++= Seq( "org.scalatest" %% "scalatest" % "3.2.+" % "test", - "org.typelevel" %% "spire" % "0.16.2", + "org.typelevel" %% "spire" % "0.17.0", "org.scalanlp" %% "breeze" % "1.1", "junit" % "junit" % "4.13" % "test", "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", diff --git a/fpga/fpga-shells b/fpga/fpga-shells index f1187f21a0..6a496d7463 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit f1187f21a0e0a36366e43994f936d04329bfc630 +Subproject commit 6a496d74633744e6600e708ce066fd5e7da22f67 diff --git a/generators/boom b/generators/boom index 9e4269088e..0a887434ab 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 9e4269088ed7f83ad57b75d62082170c2c502952 +Subproject commit 0a887434abcbfa6ef3e4a5a8bbfbc5fcfd062462 diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 1cc138f315..5ff78a65d5 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -234,7 +234,14 @@ class WithTieOffInterrupts extends OverrideHarnessBinder({ class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { - ports.foreach({ p => p := DontCare; p.bits.tieoff() }) + ports.foreach({ p => + p.bits := DontCare + p.bits.aw.valid := false.B + p.bits.w.valid := false.B + p.bits.b.ready := false.B + p.bits.ar.valid := false.B + p.bits.r.ready := false.B + }) } }) @@ -274,7 +281,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ d.dmiClock := false.B.asClock d.dmiReset := true.B case a: ClockedAPBBundle => - a.tieoff() + a.pready := false.B + a.pslverr := false.B + a.prdata := 0.U + a.pduser := DontCare a.clock := false.B.asClock a.reset := true.B.asAsyncReset a.psel := false.B diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1903ddc355..efbe542d0f 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -287,7 +287,7 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({ p.clock := clockBundle.clock p.reset := clockBundle.reset p - }) + }).toSeq (ports, Nil) } } @@ -307,7 +307,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({ p.clock := clockBundle.clock p.reset := clockBundle.reset p - }) + }).toSeq (ports, Nil) } } @@ -326,7 +326,7 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({ m <> p.bits p.clock := clockBundle.clock p - }) + }).toSeq (ports, Nil) } } diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 596337c077..a47ae4250b 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -74,11 +74,15 @@ class TestSuiteHelper addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) addSuites(env.map(rv32ud)) + if (cfg.minFLen <= 16) + addSuites(env.map(rv32uzfh)) } else { addSuite(rv32udBenchmarks) addSuites(env.map(rv64uf)) if (cfg.fLen >= 64) addSuites(env.map(rv64ud)) + if (cfg.minFLen <= 16) + addSuites(env.map(rv64uzfh)) } } if (coreParams.useAtomics) { diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index b272c80ce3..d72b2a7017 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -119,7 +119,8 @@ case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValN class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { val node = DividerOnlyClockGeneratorNode(pllName) - lazy val module = new LazyRawModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyRawModuleImp(this) { require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator") val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index 41f6d3172f..84b8883044 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -34,7 +34,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i } }) tlNode.regmap((0 until nTiles).map({ i => - i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)), + i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index bebb2619a1..eac274f090 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -25,7 +25,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - trace = true)) + core = tp.tileParams.core.copy(trace = true))) case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( trace = true)) case other => other @@ -36,7 +36,7 @@ class WithTraceIO extends Config((site, here, up) => { class WithNoTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - trace = false)) + core = tp.tileParams.core.copy(trace = false))) case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( trace = false)) case other => other diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 6303e31a23..3d8e1ae108 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -62,6 +62,11 @@ case class MyCoreParams( val decodeWidth: Int = 1 // TODO: Check val fetchWidth: Int = 1 // TODO: Check val retireWidth: Int = 2 + val useBitManip: Boolean = false + val useBitManipCrypto: Boolean = false + val useCryptoNIST: Boolean = false + val useCryptoSM: Boolean = false + val traceHasWdata: Boolean = false } // DOC include start: CanAttachTile diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 25a6fa6157..03aa0b5638 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -40,7 +40,7 @@ class AddDefaultTests extends Phase with HasRocketChipStageUtils { // If a custom test suite is set up, use the custom test suite annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p)) - RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations + RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq } diff --git a/generators/constellation b/generators/constellation index b93fde3e28..55b1899a3b 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit b93fde3e2824f728c404e08984046d41679ec31f +Subproject commit 55b1899a3bc997734dbd589b46fcf14246d5361b diff --git a/generators/cva6 b/generators/cva6 index 31fd9cdf80..737fd83b82 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 31fd9cdf801b407acee3989622902db59e474f90 +Subproject commit 737fd83b820aea6d615f372a97766b1d390a18d5 diff --git a/generators/fft-generator b/generators/fft-generator index 40357f00a8..a31bd038dd 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit 40357f00a8f091e97be9dbf39256e511dac6c494 +Subproject commit a31bd038ddf3c941634cb830608edb0bdd6442db diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bf1ff6805d..d442c95909 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -76,7 +76,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) { SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) } - SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) + SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool) } Nil } @@ -97,7 +97,7 @@ class WithUARTBridge extends OverrideHarnessBinder({ val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode val pbusClock = pbusClockNode.in.head._1.clock BoringUtils.bore(pbusClock, Seq(uartSyncClock)) - ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil + ports.map { p => UARTBridge(uartSyncClock, p, th.buildtopReset.asBool)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ @@ -134,7 +134,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ axiClockBundle, th.buildtopReset) } - SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName)) + SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool) // connect SimAxiMem (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) => diff --git a/generators/gemmini b/generators/gemmini index 6f57972db9..49494fcfce 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 6f57972db9b0815462cc0569f922792f83e35c5d +Subproject commit 49494fcfce24798cd6da9afc7918135286e158d3 diff --git a/generators/hwacha b/generators/hwacha index b0795a3aaf..e1be8e2a41 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit b0795a3aafd3b22b00061c1c3e2e710d73b4f112 +Subproject commit e1be8e2a41c6bc2239aed4e23355cf34a224f380 diff --git a/generators/ibex b/generators/ibex index a5214d0a0a..5a512227d8 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit a5214d0a0a6351dc2e03930750f831b0f28df8bf +Subproject commit 5a512227d8f6d2929cc354c02d40200002e661e5 diff --git a/generators/icenet b/generators/icenet index e14c1e8c54..fb23840eab 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit e14c1e8c54851d3fa7bc55fbbc6fc48873a3b2a9 +Subproject commit fb23840eab7a33249eaa23cad7bed4137055e8dd diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 510dea7407..9265d02d3c 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 510dea7407d8bca5eef18175530ffffa8e0774ce +Subproject commit 9265d02d3c32d56065427ec76c41b3c5a37f78dd diff --git a/generators/rocket-chip b/generators/rocket-chip index 44b0b82492..53adf18d88 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 44b0b8249279d25bd75ea693b725d9ff1b96e2ab +Subproject commit 53adf18d881ebc00190ae86c5f4d807aaca96e79 diff --git a/generators/sha3 b/generators/sha3 index 88ada85a84..98089ba372 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 88ada85a84253434ea5cef729d90cd74796aa442 +Subproject commit 98089ba372a847d62024d36db62429a8bcdfd7ea diff --git a/generators/sifive-blocks b/generators/sifive-blocks index e8adf0e3ef..1943f289a5 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit e8adf0e3ef94f76f73001fbeda767d6899c60eb3 +Subproject commit 1943f289a5960dd47035a68f872ef25fdd6254d3 diff --git a/generators/sifive-cache b/generators/sifive-cache index 2e47c707e0..2dfeb818fb 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 2e47c707e04dbbbdbf81561a979c055f87ac8df2 +Subproject commit 2dfeb818fb13a091b948cb4cd4de318959a4d4da diff --git a/generators/testchipip b/generators/testchipip index 70cdc3f020..791853c3ba 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 70cdc3f0206453aa9cbb76ba9619b87d7e10266a +Subproject commit 791853c3ba78170aa43f4455159429a9206d88b3 diff --git a/project/plugins.sbt b/project/plugins.sbt index 216a060ddf..2425544f63 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,3 +1,3 @@ addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") -addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") +addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3") diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 1b8bc36de9..77a988c363 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -4,10 +4,10 @@ set -e set -o pipefail -RDIR=$(git rev-parse --show-toplevel) +CYDIR=$(git rev-parse --show-toplevel) # get helpful utilities -source $RDIR/scripts/utils.sh +source $CYDIR/scripts/utils.sh common_setup @@ -90,7 +90,7 @@ run_step() { # setup and install conda environment if run_step "1"; then # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 - CONDA_REQS=$RDIR/conda-reqs + CONDA_REQS=$CYDIR/conda-reqs CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml @@ -100,10 +100,10 @@ if run_step "1"; then fi # use conda-lock to create env - conda-lock install -p $RDIR/.conda-env $LOCKFILE + conda-lock install -p $CYDIR/.conda-env $LOCKFILE - source $RDIR/.conda-env/etc/profile.d/conda.sh - conda activate $RDIR/.conda-env + source $CYDIR/.conda-env/etc/profile.d/conda.sh + conda activate $CYDIR/.conda-env fi if [ -z "$FORCE_FLAG" ]; then @@ -115,8 +115,8 @@ fi # initialize all submodules (without the toolchain submodules) if run_step "2"; then - $RDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG - $RDIR/scripts/init-fpga.sh $FORCE_FLAG + $CYDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG + $CYDIR/scripts/init-fpga.sh $FORCE_FLAG fi # build extra toolchain collateral (i.e. spike, pk, riscv-tests, libgloss) @@ -130,17 +130,17 @@ if run_step "3"; then fi PREFIX=$RISCV fi - $RDIR/scripts/build-toolchain-extra.sh $TOOLCHAIN_TYPE -p $PREFIX + $CYDIR/scripts/build-toolchain-extra.sh $TOOLCHAIN_TYPE -p $PREFIX fi # run ctags for code navigation if run_step "4"; then - $RDIR/scripts/gen-tags.sh + $CYDIR/scripts/gen-tags.sh fi # precompile chipyard scala sources if run_step "5"; then - pushd $RDIR/sims/verilator + pushd $CYDIR/sims/verilator make launch-sbt SBT_COMMAND=";project chipyard; compile" make launch-sbt SBT_COMMAND=";project tapeout; compile" popd @@ -148,16 +148,17 @@ fi # setup firesim if run_step "6"; then - $RDIR/scripts/firesim-setup.sh - $RDIR/sims/firesim/gen-tags.sh + $CYDIR/scripts/firesim-setup.sh + $CYDIR/sims/firesim/gen-tags.sh # precompile firesim scala sources if run_step "7"; then - pushd $RDIR/sims/firesim + pushd $CYDIR/sims/firesim ( + echo $CYDIR source sourceme-f1-manager.sh --skip-ssh-setup pushd sim - make sbt SBT_COMMAND="project firechip; compile" TARGET_PROJECT=firesim + make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim popd ) popd @@ -166,12 +167,12 @@ fi # setup firemarshal if run_step "8"; then - pushd $RDIR/software/firemarshal + pushd $CYDIR/software/firemarshal ./init-submodules.sh # precompile firemarshal buildroot sources if run_step "9"; then - source $RDIR/scripts/fix-open-files.sh + source $CYDIR/scripts/fix-open-files.sh ./marshal $VERBOSE_FLAG build br-base.json ./marshal $VERBOSE_FLAG clean br-base.json fi @@ -180,13 +181,13 @@ fi # do misc. cleanup for a "clean" git status if run_step "10"; then - $RDIR/scripts/repo-clean.sh + $CYDIR/scripts/repo-clean.sh fi cat <> env.sh # line auto-generated by $0 -conda activate $RDIR/.conda-env -source $RDIR/scripts/fix-open-files.sh +conda activate $CYDIR/.conda-env +source $CYDIR/scripts/fix-open-files.sh EOT echo "Setup complete!" diff --git a/sims/firesim b/sims/firesim index 8176b657ee..1602d4d5e4 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8176b657ee779ac4901b6b03aea0ac23a0b8874d +Subproject commit 1602d4d5e4199c5a0d828917394b96ac2fd21bce diff --git a/toolchains/riscv-tools/riscv-tests b/toolchains/riscv-tools/riscv-tests index c84daca882..a6ab6ae600 160000 --- a/toolchains/riscv-tools/riscv-tests +++ b/toolchains/riscv-tools/riscv-tests @@ -1 +1 @@ -Subproject commit c84daca8824635b7d896003c78f9c6245997cf7a +Subproject commit a6ab6ae6008ffc2ea907ea9f6d2b8379583e7d56 diff --git a/tools/barstools b/tools/barstools index 06db605902..b71c31e66e 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 06db6059022c55df8e6943702653798c43ead3d8 +Subproject commit b71c31e66e4ea3575df23e7f851d79744ab5331e diff --git a/tools/dsptools b/tools/dsptools index a1809fbae9..5b1e733596 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit a1809fbae9e49de7213116bbec79252645292e39 +Subproject commit 5b1e733596a39f6960bf9a7c1897d82912372766 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 4448e06138..46d6ed7798 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 4448e06138a1d9281621f349c306c8a066589e67 +Subproject commit 46d6ed77981ef18789636426cc23f0bd7edc64d9