diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index d20bade96d..6711eac7b5 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink._
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
-  with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register
+  with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index ef02f468ed..b96ccbec7d 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -46,6 +46,8 @@ class AbstractConfig extends Config(
   // This should get replaced with a PLL-like config instead
   new chipyard.clocking.WithDividerOnlyClockGenerator ++
 
+  new testchipip.WithCustomBootPin ++                               // add a custom-boot-pin to support pin-driven boot address
+  new testchipip.WithBootAddrReg ++                                 // add a boot-addr-reg for configurable boot address
   new testchipip.WithSerialTLWidth(32) ++                           // fatten the serialTL interface to improve testing performance
   new testchipip.WithDefaultSerialTL ++                             // use serialized tilelink port to external serialadapter/harnessRAM
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
diff --git a/generators/testchipip b/generators/testchipip
index 2bbf3a2fe4..cf1157e32b 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 2bbf3a2fe4a7b079bc591584b8eee12234433104
+Subproject commit cf1157e32b762a3e1a21ce2907b549aed5e69ccc