From 40369c5d4252489afc8cc17de71fe16830dbce1a Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 7 Aug 2024 16:49:54 -0700
Subject: [PATCH] Disable verilator builds of Ara

---
 .github/scripts/run-tests.sh             |  7 ++++---
 .github/workflows/chipyard-run-tests.yml | 24 ------------------------
 docs/Generators/Ara.rst                  |  2 ++
 3 files changed, 6 insertions(+), 27 deletions(-)

diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index 5fee986da..afa221fb7 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -142,11 +142,12 @@ case $1 in
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
         ;;
     chipyard-shuttleara)
-        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
+        # Ara does not work with verilator
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
         # Ara cannot run strcmp
         # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
-        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
-        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
         ;;
     tracegen)
         run_tracegen
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index bd3bda146..6de3f9e66 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -844,29 +844,6 @@ jobs:
           group-key: "group-accels"
           project-key: "chipyard-shuttlevector"
 
-  chipyard-shuttleara-run-tests:
-    name: chipyard-shuttleara-run-tests
-    needs: prepare-chipyard-accels
-    runs-on: as4
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-accels"
-          project-key: "chipyard-shuttleara"
-
   chipyard-gemmini-run-tests:
     name: chipyard-gemmini-run-tests
     needs: prepare-chipyard-accels
@@ -1259,7 +1236,6 @@ jobs:
             chipyard-rerocc-run-tests,
             chipyard-rocketvector-run-tests,
             chipyard-shuttlevector-run-tests,
-            chipyard-shuttleara-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
             chipyard-prefetchers-run-tests,
diff --git a/docs/Generators/Ara.rst b/docs/Generators/Ara.rst
index 41c35dd12..08c17c5d0 100644
--- a/docs/Generators/Ara.rst
+++ b/docs/Generators/Ara.rst
@@ -9,6 +9,8 @@ Example Ara configurations are listed in ``generators/chipyard/src/main/scala/co
 
 To compile simulators using Ara, you must pass an additional ``USE_ARA`` flag to the makefile.
 
+.. Note:: Ara only supports VCS for simulation
+
 .. code-block:: shell
 
      make CONFIG=V4096Ara2LaneRocketConfig USE_ARA=1