-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathPLAYMODM.ASM
3738 lines (3269 loc) · 90.8 KB
/
PLAYMODM.ASM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
; ****************************************************************************
; playmod2.asm (for MSDOS)
; ----------------------------------------------------------------------------
; PLAYMOD2.COM ! ICH AC97 MOD PLAYER & VGA DEMO program by Erdogan TAN
;
; 18/02/2017
;
; [ Last Modification: 20/05/2024 ]
;
; Derived from source code of 'PLAYWAV.COM' ('PLAYWAV.ASM') by Erdogan Tan
; (17/02/2017)
; Modified from 'PLAYMOD.COM' ('playmod.asm') source code
; VIA VT8237 MOD PLAYER & VGA DEMO program by Erdogan TAN
; (15/02/2017)
;
; Derived from source code of 'PLAY.EXE' (TINYPLAY) by Carlos Hasan (1993)
; PLAY.EXE: PLAY.ASM, MODLOAD.ASM, MODPLAY.ASM, SB.ASM
;
; Assembler: NASM 2.11
; ----------------------------------------------------------------------------
; nasm playmod2.asm -l playmod2.lst -o PLAYMOD2.COM
; ****************************************************************************
; Tiny MOD Player v0.1b by Carlos Hasan.
; July 14th, 1993.
;=============================================================================
; PLAYWAV.ASM / PLAYER.ASM / TINYPLAY.ASM
;=============================================================================
; Audio controller, codec & PCI functions are derived from '.wav file player
; for DOS' source code by Jeff Leyda (PLAYER.EXE), Sep 02, 2002.
; TUNELOOP version ; 12/05/2024
; PLAYMODM.ASM (15/04/2024)
[BITS 16]
[org 100h]
Start:
call DetectICH ; Detect AC97 Audio Device
GetFileName: ; Parse the Command line...
mov si, 80h
mov bl, [si]
xor bh, bh
inc bx
mov byte [si+bx], 0 ; make AsciiZ filename.
inc si
ScanName:
lodsb
test al, al
je pmsg_2017
cmp al, 20h
je short ScanName ; scan start of name.
mov di, si
dec di
ScanPeriod:
lodsb
cmp al, '.' ; if period NOT found,
je short PrintMesg ; then add a .MOD extension.
test al, al
jnz short ScanPeriod
dec si
SetExt:
;mov byte [si+0], '.'
;mov byte [si+1], 'M'
;mov byte [si+2], 'O'
;mov byte [si+3], 'D'
mov dword [si], '.MOD'
mov byte [si+4], 0
PrintMesg:
mov ax, 0900h ; Prints the Credits Text.
;lea dx, [Credits]
mov dx, Credits
int 21h
; 13/05/2024
call write_ac97_dev_info
mov ax, 0900h ; Prints the Credits Text.
mov dx, CRLF
int 21h
LoadMod:
; es:di = Filename address
push es
push di
call LoadModule ; Load the MODule...
cmp word [ErrorInfo], 0 ; any error loading?
je short init_codec
mov ax, 0900h ; yes, print error and Exit.
;lea dx, [ErrorMesg]
mov dx, ErrorMesg
int 21h
jmp Exit
init_codec:
; 13/05/2024
;call write_ac97_dev_info
; 08/05/2024
; 17/02/2017
;mov dx, [stats_cmd]
;or dl, IO_ENA+BM_ENA ; enable IO and bus master
;call pciRegWrite16 ; pciRegWrite8
; 18/02/2017
;mov word [sample_rate], 22050 ; Mixing at 22.050 kHz
; 14/05/2024
mov word [sample_rate], 24000
; 08/05/2024
; (48 kHZ mixing is necessary
; if the AC97 hardware/codec has not got VRA feature)
; ((or frequency converting code would be needed))
;mov word [sample_rate], 48000 ; Mixing at 48 kHz
; setup the Codec (actually mixer registers)
call codecConfig ; unmute codec, set rates.
jnc short PlayNow
_codec_err:
push cs
pop ds
mov dx, CodecErrMsg
mov ah, 9
int 21h
jmp Exit
CodecErrMsg db "Codec Error!"
db CR,LF,"$"
PlayNow:
mov ax, BdlBuffer
mov [BDL_BUFFER], ax
mov ax, DmaBuffer ; DmaBuffer (4096 bytes) buff addr
mov [DMA_BUFFER1], ax ; 2048 byte half buffer 1
add ax, BUFFERSIZE ; code/current segment
mov [DMA_BUFFER2], ax ; 2048 byte half buffer 2
;mov word [MixSpeed], 22050 ; Mixing at 22.050 kHz
call StartPlaying
mov ax, 0013h ; Set Mode 320x200x256
int 10h
mov cx, 128 ; Make a lookup table
xor bx, bx ; for fastest pixel
mov dx, 320*(100-64) ; addressing.
MakeOfs:
mov [RowOfs+bx], dx
mov [RowOfs+bx+2], dx
add dx, 320
add bx, 4
loop MakeOfs
; Note: Normally IRQ 0 calls the ModPlay Polling at 18.2Hz thru
; the software interrupt 1Ch. If the IRQ 0 is disabled, then
; the INT 1Ch MUST BE CALLED at least MixSpeed/1024 times per
; second, or the module will sound "looped".
; Because we need better sync with the ModPlayer to draw the scope,
; the polling is called from my routine, and then the irq 0 must be
; disabled. The [DmaBuffer] points to the current buffer of 8-bit
; samples played by the Sound Blaster. Note that some samples are
; discarded in the next code, just for fun!
;in al, 21h ; disable irq 0!
;or al, 00000001b
;out 21h, al
call ModPlay ; 13/02/2017
;in al, 21h ; enable irq 0!
;and al, 11111110b
;out 21h, al
mov ax, 0003h ; Set Text Mode 80x25x16
int 10h
call StopPlaying ; STOP!
Exit:
;call FreeModule ; Free MODule core.
error_exit:
mov ax, 4C00h ; Bye!
int 21h
here:
jmp short here
pmsg_2017:
mov ax, 0900h ; Prints the Credits Text.
;lea dx, [msg_2017]
mov dx, msg_2017
int 21h
jmp short Exit
DetectICH:
; 18/02/2017
; Detech Intel ICH based AC97 Audio Device
call pciFindDevice ; AC97.ASM (PLAYWAV.COM)
jnc short _1
; couldn't find the audio device!
;push cs
;pop ds
mov dx, noDevMsg
mov ah, 9
int 21h
jmp short error_exit
noDevMsg db "Error: Unable to find Intel ICH based audio device!",CR,LF,"$"
_1:
; 18/02/2017
; eax = BUS/DEV/FN
; 00000000BBBBBBBBDDDDDFFF00000000
; edx = DEV/VENDOR
; DDDDDDDDDDDDDDDDVVVVVVVVVVVVVVVV
mov [bus_dev_fn], eax
mov [dev_vendor], edx
; get ICH base address regs for mixer and bus master
mov al, NAMBAR_REG
call pciRegRead16 ; read PCI registers 10-11
;and dx, IO_ADDR_MASK ; mask off BIT0
; 14/05/2024
and dl, 0FEh
mov [NAMBAR], dx ; save audio mixer base addr
mov al, NABMBAR_REG
call pciRegRead16
;and dx, IO_ADDR_MASK
;/14/05/2024
and dl, 0C0h
mov [NABMBAR], dx ; save bus master base addr
; 08/05/2024
; 06/11/2023
;; init controller
;; 17/02/2017
;mov al, PCI_CMD_REG ; command register (04h)
;call pciRegRead16 ; pciRegRead8
;
;; eax = BUS/DEV/FN/REG
;; dx = PCI Command Register Content ; 17/02/2017
;; 00000000CCCCCCCC
;mov [stats_cmd], dx
;
; 06/11/2023
;mov al, PCI_IO_BASE ; IO base address register (10h)
;call pciRegRead32
;
;and dx, 0FFC0h ; IO_ADDR_MASK (0FFFE) ?
;mov [ac97_io_base], dx
mov al, AC97_INT_LINE ; Interrupt line register (3Ch)
call pciRegRead8 ; 17/02/2017
mov [ac97_int_ln_reg], dl
; 12/05/2024 (tuneloop version)
%if 0
; 28/11/2016
;mov bx, 1 ; 08/05/2024
xor dh, dh ; 17/02/2017
; 10/11/2023
;mov cx, dx
;shl bx, cl
; 04/11/2023
cli
;not bx
in al, 0A1h ; irq 8-15
mov ah, al
in al, 21h ; irq 0-7
; 04/11/2023
; save IRQ status
mov [IRQ_status], ax
; 08/05/2024
;mov dx, 4D1h ;8259 ELCR1
;in al, dx
;mov ah, al
;mov dx, 4D0h
;in al, dx
;;or ax, bx
;bts ax, cx
;mov dx, 4D0h
;out dx, al ;set level-triggered mode
;mov al, ah
;mov dx, 4D1h
;out dx, al ;set level-triggered mode
; 24/11/2016 - Erdogan Tan
;mov bx, cx
; 10/11/2023
mov bx, dx
mov bl, [bx+irq_int]
shl bx, 2 ; * 4
; set up interrupt vector
; 30/11/2016
push es
xor ax, ax
mov es, ax
; 04/11/2023
; save interrupt vector
mov ax, [es:bx]
mov [IRQ_vector], ax
mov ax, [es:bx+2]
mov [IRQ_vector+2], ax
mov word [es:bx], ac97_int_handler
mov ax, cs
mov [es:bx+2], ax
pop es
; 04/11/2023
sti
%endif
retn
; 12/05/2024 (tuneloop version)
%if 0
ac97_int_handler:
; 11/05/2024
; 11/11/2023
; 10/11/2023
; 17/02/2016
push eax ; 11/11/2023
push dx
; 05/11/2023
;push cx
;push bx
;push si
;push di
; 10/11/2023
; EOI at first
mov al, 20h
test byte [ac97_int_ln_reg], 8
jz short _ih_0
out 0A0h, al ; 20h ; EOI
_ih_0:
out 20h, al ; 20h ; EOI
; 11/11/2023
; 09/11/2023
mov dx, GLOB_STS_REG
add dx, [NABMBAR]
in eax, dx
; 12/05/2024
; 09/11/2023,
;cmp eax, 0FFFFFFFFh ; -1
;je short _ih_2
; 12/05/2024
;test al, 40h ; PCM Out Interrupt
;jnz short _ih_1
;test eax, eax
;jz short _ih_2
; 12/05/2024
test ax, PCM_OUT_IRQ+BCIS
jnz short _ih_1
;mov dx, GLOB_STS_REG
;add dx, [NABMBAR]
out dx, eax
jmp short _ih_2
; .....
;mov al, 1
; 10/11/2023
;mov [tLoop], al ; 1
;cmp [inside], al ; 1
;jnb short _ih_3 ; busy
;mov [inside], al ; 1
;
;; 09/11/2023
;mov dx, [NABMBAR]
;add dx, PO_SR_REG ; set pointer to Status reg
;in al, dx
;; 10/11/2023
;;;out dx, eax
;;out dx, al ; clear interrupt event
; ; (by writing 1 to same bits)
;
;;mov [pcm_irq_status], al ; 05/11/2023
;test al, BCIS ; Buffer Completion Interrupt Status (Bit 3)
;jz short _ih_2
; .....
_ih_1:
; 11/11/2023
push eax
;mov ax, 1Ch ; FIFOE(=16)+BCIS(=8)+LVBCI(=4)
;mov dx, PO_SR_REG
;add dx, [NABMBAR]
;out dx, ax
; 10/11/2023
; 28/11/2016 - Erdogan Tan
call tuneLoop
; 11/11/2023
pop eax
mov dx, GLOB_STS_REG
add dx, [NABMBAR]
out dx, eax
_ih_2:
; 11/11/2023
mov dx, [NABMBAR]
add dx, PO_SR_REG ; set pointer to Status reg
mov ax, 1Ch
out dx, ax
; ; 10/11/2023
; mov al, 20h
; test byte [ac97_int_ln_reg], 8
; jz short _ih_3
; out 0A0h, al ; 20h ; EOI
;_ih_3:
; out 20h, al ; 20h ; EOI
;_ih_4:
;mov byte [inside], 0
;pop di
;pop si
;pop bx
;pop cx
pop dx
pop eax ; 11/11/2023
iret
%endif
;=============================================================================
; PCI.ASM
;=============================================================================
; EQUATES
;constants of stuff that seem hard to remember at times.
TRUE EQU 1
FALSE EQU 0
ENABLED EQU 1
DISABLED EQU 0
BIT0 EQU 1
BIT1 EQU 2
BIT2 EQU 4
BIT3 EQU 8
BIT4 EQU 10h
BIT5 EQU 20h
BIT6 EQU 40h
BIT7 EQU 80h
BIT8 EQU 100h
BIT9 EQU 200h
BIT10 EQU 400h
BIT11 EQU 800h
BIT12 EQU 1000h
BIT13 EQU 2000h
BIT14 EQU 4000h
BIT15 EQU 8000h
BIT16 EQU 10000h
BIT17 EQU 20000h
BIT18 EQU 40000h
BIT19 EQU 80000h
BIT20 EQU 100000h
BIT21 EQU 200000h
BIT22 EQU 400000h
BIT23 EQU 800000h
BIT24 EQU 1000000h
BIT25 EQU 2000000h
BIT26 EQU 4000000h
BIT27 EQU 8000000h
BIT28 EQU 10000000h
BIT29 EQU 20000000h
BIT30 EQU 40000000h
BIT31 EQU 80000000h
;special characters
NUL EQU 0
NULL EQU 0
BELL EQU 07
BS EQU 08
TAB EQU 09
LF EQU 10
CR EQU 13
ESCAPE EQU 27 ;ESC is a reserved word....
;file stuff
READONLY EQU BIT0
HIDDEN EQU BIT1
SYSTEM EQU BIT2
VOLUME EQU BIT3 ;ignored for file access
DIRECTORY EQU BIT4 ;must be 0 for file access
ARCHIVE EQU BIT5
SHAREABLE EQU BIT7 ;for novell networks
OPEN EQU 2 ; open existing file
CREATE EQU 1 ; create new file
; PCI equates
; PCI function address (PFA)
; bit 31 = 1
; bit 23:16 = bus number (0-255)
; bit 15:11 = device number (0-31)
; bit 10:8 = function number (0-7)
; bit 7:0 = register number (0-255)
IO_ADDR_MASK EQU 0FFFEh ; mask off bit 0 for reading BARs
PCI_INDEX_PORT EQU 0CF8h
PCI_DATA_PORT EQU 0CFCh
PCI32 EQU BIT31 ; bitflag to signal 32bit access
PCI16 EQU BIT30 ; bitflag for 16bit access
PCI_FN0 EQU 0 << 8
PCI_FN1 EQU 1 << 8
PCI_FN2 EQU 2 << 8
PCI_FN3 EQU 3 << 8
PCI_FN4 EQU 4 << 8
PCI_FN5 EQU 5 << 8
PCI_FN6 EQU 6 << 8
PCI_FN7 EQU 7 << 8
PCI_CMD_REG EQU 04h ; reg 04, command reg
IO_ENA EQU BIT0 ; i/o decode enable
MEM_ENA EQU BIT1 ; memory decode enable
BM_ENA EQU BIT2 ; bus master enable
; CODE
; AC97.ASM
; PCI device register reader/writers.
; NASM version: Erdogan Tan (29/11/2016)
; Last Update: 17/02/2017
;===============================================================
; 8/16/32bit PCI reader
;
; Entry: EAX=PCI Bus/Device/fn/register number
; BIT30 set if 32 bit access requested
; BIT29 set if 16 bit access requested
; otherwise defaults to 8bit read
;
; Exit: DL,DX,EDX register data depending on requested read size
;
; Note: this routine is meant to be called via pciRegRead8, pciRegread16,
; or pciRegRead32, listed below.
;
; Note2: don't attempt to read 32bits of data from a non dword aligned reg
; number. Likewise, don't do 16bit reads from non word aligned reg #
;
pciRegRead:
push ebx
push cx
mov ebx, eax ; save eax, dh
mov cl, dh
and eax, (~PCI32)+PCI16 ; clear out data size request
or eax, BIT31 ; make a PCI access request
and al, ~3 ; NOT 3 ; force index to be dword
mov dx, PCI_INDEX_PORT
out dx, eax ; write PCI selector
mov dx, PCI_DATA_PORT
mov al, bl
and al, 3 ; figure out which port to
add dl, al ; read to
in eax, dx ; do 32bit read
test ebx, PCI32
jz short _pregr1
mov edx, eax ; return 32bits of data
_pregr1:
mov dx, ax ; return 16bits of data
test ebx, PCI32+PCI16
jnz short _pregr2
mov dh, cl ; restore dh for 8 bit read
_pregr2:
mov eax, ebx ; restore eax
and eax, (~PCI32)+PCI16 ; clear out data size request
pop cx
pop ebx
retn
pciRegRead8:
and eax, (~PCI16)+PCI32 ; set up 8 bit read size
jmp short pciRegRead ; call generic PCI access
pciRegRead16:
and eax, (~PCI16)+PCI32 ; set up 16 bit read size
or eax, PCI16 ; call generic PCI access
jmp short pciRegRead
pciRegRead32:
and eax, (~PCI16)+PCI32 ; set up 32 bit read size
or eax, PCI32 ; call generic PCI access
jmp short pciRegRead
;===============================================================
; 8/16/32bit PCI writer
;
; Entry: EAX=PCI Bus/Device/fn/register number
; BIT31 set if 32 bit access requested
; BIT30 set if 16 bit access requested
; otherwise defaults to 8bit read
; DL/DX/EDX data to write depending on size
;
;
; note: this routine is meant to be called via pciRegWrite8, pciRegWrite16,
; or pciRegWrite32 as detailed below.
;
; Note2: don't attempt to write 32bits of data from a non dword aligned reg
; number. Likewise, don't do 16bit writes from non word aligned reg #
;
pciRegWrite:
push ebx
push cx
mov ebx, eax ; save eax, dx
mov cx, dx
or eax, BIT31 ; make a PCI access request
and eax, ~PCI16 ; NOT PCI16 ; clear out data size request
and al, ~3 ; NOT 3 ; force index to be dword
mov dx, PCI_INDEX_PORT
out dx, eax ; write PCI selector
mov dx, PCI_DATA_PORT
mov al, bl
and al, 3 ; figure out which port to
add dl, al ; write to
mov eax, edx ; put data into eax
mov ax, cx
out dx, al
test ebx, PCI16+PCI32 ; only 8bit access? bail
jz short _pregw1
out dx, ax ; write 16 bit value
test ebx, PCI16 ; 16bit requested? bail
jnz short _pregw1
out dx, eax ; write full 32bit
_pregw1:
mov eax, ebx ; restore eax
and eax, (~PCI32)+PCI16 ; clear out data size request
mov dx, cx ; restore dx
pop cx
pop ebx
ret
pciRegWrite8:
and eax, (~PCI16)+PCI32 ; set up 8 bit write size
jmp short pciRegWrite ; call generic PCI access
pciRegWrite16:
and eax, (~PCI16)+PCI32 ; set up 16 bit write size
or eax, PCI16 ; call generic PCI access
jmp short pciRegWrite
pciRegWrite32:
and eax, (~PCI16)+PCI32 ; set up 32 bit write size
or eax, PCI32 ; call generic PCI access
jmp short pciRegWrite
; AC97.ASM (PLAYWAV.COM)
; 17/02/2017 (Modifed by Erdogan Tan for various ICH device IDs)
;===============================================================
; PCIFindDevice: scan through PCI space looking for a device+vendor ID
;
; ENTRY: none
;; Entry: EAX=Device+Vendor ID
;
; Exit: EAX=PCI address if device found
; EDX=Device+Vendor ID
; CY clear if found, set if not found. EAX invalid if CY set.
;
; [old stackless] Destroys: ebx, esi, edi, cl
;
pciFindDevice:
;push cx
;push eax ; *
;push esi
;push edi
;mov esi, eax ; save off vend+device ID
; 17/02/2017
mov si, valid_ids ; address of Valid ICH (AC97) Device IDs
mov cx, valid_id_count
pfd_0:
mov edi, (80000000h - 100h) ; start with bus 0, dev 0 func 0
nextPCIdevice:
add edi, 100h
cmp edi, 80FFF800h ; scanned all devices?
;stc
;je short PCIScanExit ; not found
jb short pfd_1
mov edi, 80000000h
add si, 4 ; scan for next device ID
loop pfd_1
stc
;jmp short PCIScanExit
retn
pfd_1:
mov eax, edi ; read PCI registers
call pciRegRead32
;cmp edx, esi ; found device?
cmp edx, dword [si]
jne short nextPCIdevice
;clc
PCIScanExit:
;pushf
mov eax, BIT31
not eax
and eax, edi ; return only bus/dev/fn #
;popf
;pop edi
;pop esi
;pop edx ; *
;pop cx
retn
;=============================================================================
; CODEC.ASM
;=============================================================================
; EQUATES
;Codec registers.
;
;Not all codecs are created equal. Refer to the spec for your specific codec.
;
;All registers are 16bits wide. Access to codec registers over the AC97 link
;is defined by the OEM.
;
;Secondary codec's are accessed by ORing in BIT7 of all register accesses.
;
; each codec/mixer register is 16bits
CODEC_RESET_REG equ 00 ; reset codec
CODEC_MASTER_VOL_REG equ 02 ; master volume
CODEC_HP_VOL_REG equ 04 ; headphone volume
CODEC_MASTER_MONO_VOL_REG equ 06 ; master mono volume
CODEC_MASTER_TONE_REG equ 08 ; master tone (R+L)
CODEC_PCBEEP_VOL_REG equ 0ah ; PC beep volume
CODEC_PHONE_VOL_REG equ 0bh ; phone volume
CODEC_MIC_VOL_REG equ 0eh ; MIC volume
CODEC_LINE_IN_VOL_REG equ 10h ; line input volume
CODEC_CD_VOL_REG equ 12h ; CD volume
CODEC_VID_VOL_REG equ 14h ; video volume
CODEC_AUX_VOL_REG equ 16h ; aux volume
CODEC_PCM_OUT_REG equ 18h ; PCM output volume
CODEC_RECORD_SELECT_REG equ 1ah ; record select input
CODEC_RECORD_VOL_REG equ 1ch ; record volume
CODEC_RECORD_MIC_VOL_REG equ 1eh ; record mic volume
CODEC_GP_REG equ 20h ; general purpose
CODEC_3D_CONTROL_REG equ 22h ; 3D control
; 24h is reserved
CODEC_POWER_CTRL_REG equ 26h ; powerdown control
CODEC_EXT_AUDIO_REG equ 28h ; extended audio
CODEC_EXT_AUDIO_CTRL_REG equ 2ah ; extended audio control
CODEC_PCM_FRONT_DACRATE_REG equ 2ch ; PCM out sample rate
CODEC_PCM_SURND_DACRATE_REG equ 2eh ; surround sound sample rate
CODEC_PCM_LFE_DACRATE_REG equ 30h ; LFE sample rate
CODEC_LR_ADCRATE_REG equ 32h ; PCM in sample rate
CODEC_MIC_ADCRATE_REG equ 34h ; mic in sample rate
; registers 36-7a are reserved on the ICH
CODEC_VENDORID1_REG equ 7ch ; codec vendor ID 1
CODEC_VENDORID2_REG equ 7eh ; codec vendor ID 2
; Mixer registers 0 through 51h reside in the ICH and are not forwarded over
; the AC97 link to the codec, which I think is a little weird. Looks like
; the ICH makes it so you don't need a fully functional codec to play audio?
;
; whenever 2 codecs are present in the system, use BIT7 to access the 2nd
; set of registers, ie 80h-feh
PRIMARY_CODEC equ 0 ; 0-7F for primary codec
SECONDARY_CODEC equ BIT7 ; 80-8f registers for 2ndary
SAMPLE_RATE_441khz equ 44100 ; 44.1Khz (cd quality) rate
; ----------------------------------------------------------------------------
; 17/02/2017
PCI_IO_BASE equ 10h ; = NAMBAR register offset
AC97_INT_LINE equ 3Ch ; AC97 Interrupt Line register offset
; ----------------------------------------------------------------------------
; ICH2AC97.INC
; ----------------------------------------------------------------------------
; PCI stuff
; Intel ICH2 equates. It is assumed that ICH0 and plain ole ICH are compatible.
INTEL_VID equ 8086h ; Intel's PCI vendor ID
; 08/05/2024
; 03/11/2023 - Erdogan Tan (Ref: MenuetOS AC97 WAV Player source code, 2004)
SIS_VID equ 1039h
NVIDIA_VID equ 10DEh ; Ref: MPXPLAY/SBEMU/KOLIBRIOS AC97 source c.
AMD_VID equ 1022h
ICH_DID equ 2415h ; ICH device ID
ICH0_DID equ 2425h ; ICH0
ICH2_DID equ 2445h ; ICH2 I think there are more ICHes.
; they all should be compatible.
; 08/05/2024
; 17/02/2017 (Erdogan Tan, ref: ALSA Device IDs, ALSA project)
ICH3_DID equ 2485h ; ICH3
ICH4_DID equ 24C5h ; ICH4
ICH5_DID equ 24D5h ; ICH5
ICH6_DID equ 266Eh ; ICH6
ESB6300_DID equ 25A6h ; 6300ESB
ESB631X_DID equ 2698h ; 631XESB
ICH7_DID equ 27DEh ; ICH7
; 03/11/2023 - Erdogan Tan (Ref: MenuetOS AC97 WAV Player source code, 2004)
MX82440_DID equ 7195h
SI7012_DID equ 7012h
NFORCE_DID equ 01B1h
NFORCE2_DID equ 006Ah
AMD8111_DID equ 746Dh
AMD768_DID equ 7445h
; 03/11/2023 - Erdogan Tan - Ref: MPXPLAY/SBEMU/KOLIBRIOS AC97 source code
CK804_DID equ 0059h
MCP04_DID equ 003Ah
CK8_DID equ 008Ah
NFORCE3_DID equ 00DAh
CK8S_DID equ 00EAh
NAMBAR_REG equ 10h ; native audio mixer BAR
NAM_SIZE equ 256 ; 256 bytes required.
NABMBAR_REG equ 14h ; native audio bus mastering BAR
NABM_SIZE equ 64 ; 64 bytes
; BUS master registers, accessed via NABMBAR+offset
; ICH supports 3 different types of register sets for three types of things
; it can do, thus:
;
; PCM in (for recording) aka PI
; PCM out (for playback) aka PO
; MIC in (for recording) aka MC
PI_BDBAR_REG equ 0 ; PCM in buffer descriptor BAR
PO_BDBAR_REG equ 10h ; PCM out buffer descriptor BAR
MC_BDBAR_REG equ 20h ; MIC in buffer descriptor BAR
; each buffer descriptor BAR holds a pointer which has entries to the buffer
; contents of the .WAV file we're going to play. Each entry is 8 bytes long
; (more on that later) and can contain 32 entries total, so each BAR is
; 256 bytes in length, thus:
BDL_SIZE equ 32*8 ; Buffer Descriptor List size
INDEX_MASK equ 31 ; indexes must be 0-31
PI_CIV_REG equ 4 ; PCM in current Index value (RO)
PO_CIV_REG equ 14h ; PCM out current Index value (RO)
MC_CIV_REG equ 24h ; MIC in current Index value (RO)
;8bit read only
; each current index value is simply a pointer showing us which buffer
; (0-31) the codec is currently processing. Once this counter hits 31, it
; wraps back to 0.
; this can be handy to know, as once it hits 31, we're almost out of data to
; play back or room to record!
PI_LVI_REG equ 5 ; PCM in Last Valid Index
PO_LVI_REG equ 15h ; PCM out Last Valid Index
MC_LVI_REG equ 25h ; MIC in Last Valid Index
;8bit read/write
; The Last Valid Index is a number (0-31) to let the codec know what buffer
; number to stop on after processing. It could be very nasty to play audio
; from buffers that aren't filled with the audio we want to play.
PI_SR_REG equ 6 ; PCM in Status register
PO_SR_REG equ 16h ; PCM out Status register
MC_SR_REG equ 26h ; MIC in Status register
;16bit read/write
; status registers. Bitfields follow:
FIFO_ERR equ BIT4 ; FIFO Over/Underrun W1TC.
BCIS equ BIT3 ; buffer completion interrupt status.
; Set whenever the last sample in ANY
; buffer is finished. Bit is only
; set when the Interrupt on Complete
; (BIT4 of control reg) is set.
LVBCI equ BIT2 ; Set whenever the codec has processed
; the last buffer in the buffer list.
; Will fire an interrupt if IOC bit is
; set. Probably set after the last
; sample in the last buffer is
; processed. W1TC
;
CELV equ BIT1 ; Current buffer == last valid.
; Bit is RO and remains set until LVI is
; cleared. Probably set up the start
; of processing for the last buffer.
DCH equ BIT0 ; DMA controller halted.
; set whenever audio stream is stopped
; or something else goes wrong.
PI_PICB_REG equ 8 ; PCM in position in current buffer(RO)
PO_PICB_REG equ 18h ; PCM out position in current buffer(RO)
MC_PICB_REG equ 28h ; MIC in position in current buffer (RO)
;16bit read only
; position in current buffer regs show the number of dwords left to be
; processed in the current buffer.
;
PI_PIV_REG equ 0ah ; PCM in Prefected index value
PO_PIV_REG equ 1ah ; PCM out Prefected index value
MC_PIV_REG equ 2ah ; MIC in Prefected index value
;8bit, read only
; Prefetched index value register.
; tells which buffer number (0-31) has be prefetched. I'd imagine this
; value follows the current index value fairly closely. (CIV+1)
;
PI_CR_REG equ 0bh ; PCM in Control Register
PO_CR_REG equ 1bh ; PCM out Control Register
MC_CR_REG equ 2bh ; MIC in Control Register
; 8bit
; Control register *MUST* only be accessed as an 8bit value.
; Control register. See bitfields below.
;
IOCE equ BIT4 ; interrupt on complete enable.
; set this bit if you want an intrtpt
; to fire whenever LVBCI is set.
FEIFE equ BIT3 ; set if you want an interrupt to fire
; whenever there is a FIFO (over or
; under) error.
LVBIE equ BIT2 ; last valid buffer interrupt enable.
; set if you want an interrupt to fire
; whenever the completion of the last
; valid buffer.
RR equ BIT1 ; reset registers. Nukes all regs
; except bits 4:2 of this register.
; Only set this bit if BIT 0 is 0
RPBM equ BIT0 ; Run/Pause
; set this bit to start the codec!
GLOB_CNT_REG equ 2ch ; Global control register
SEC_RES_EN equ BIT5 ; secondary codec resume event
; interrupt enable. Not used here.
PRI_RES_EN equ BIT4 ; ditto for primary. Not used here.
ACLINK_OFF equ BIT3 ; Turn off the AC97 link
ACWARM_RESET equ BIT2 ; Awaken the AC97 link from sleep.
; registers preserved, bit self clears
ACCOLD_RESET equ BIT1 ; Reset everything in the AC97 and
; reset all registers. Not self clearing
GPIIE equ BIT0 ; GPI Interrupt enable.
; set if you want an interrupt to
; fire upon ANY of the bits in the
; GPI (general pursose inputs?) not used.
GLOB_STS_REG equ 30h ; Global Status register (RO)
MD3 equ BIT17 ; modem powerdown status (yawn)
AD3 equ BIT16 ; Audio powerdown status (yawn)
RD_COMPLETE_STS equ BIT15 ; Codec read timed out. 0=normal
BIT3SLOT12 equ BIT14 ; shadowed status of bit 3 in slot 12
BIT2SLOT12 equ BIT13 ; shadowed status of bit 2 in slot 12
BIT1SLOT12 equ BIT12 ; shadowed status of bit 1 in slot 12