diff --git a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp index 7f4d40f97011..595a30e8d8ce 100644 --- a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp @@ -22,6 +22,7 @@ #include "FoldInitTypeCheck.h" #include "ForwardDeclarationNamespaceCheck.h" #include "ForwardingReferenceOverloadCheck.h" +#include "ImplicitWideningOfMultiplicationResultCheck.h" #include "InaccurateEraseCheck.h" #include "IncorrectRoundingsCheck.h" #include "InfiniteLoopCheck.h" @@ -60,6 +61,7 @@ #include "TooSmallLoopVariableCheck.h" #include "UndefinedMemoryManipulationCheck.h" #include "UndelegatedConstructorCheck.h" +#include "UnhandledExceptionAtNewCheck.h" #include "UnhandledSelfAssignmentCheck.h" #include "UnusedRaiiCheck.h" #include "UnusedReturnValueCheck.h" @@ -97,6 +99,8 @@ class BugproneModule : public ClangTidyModule { "bugprone-forward-declaration-namespace"); CheckFactories.registerCheck( "bugprone-forwarding-reference-overload"); + CheckFactories.registerCheck( + "bugprone-implicit-widening-of-multiplication-result"); CheckFactories.registerCheck( "bugprone-inaccurate-erase"); CheckFactories.registerCheck( @@ -175,6 +179,8 @@ class BugproneModule : public ClangTidyModule { "bugprone-undelegated-constructor"); CheckFactories.registerCheck( "bugprone-unhandled-self-assignment"); + CheckFactories.registerCheck( + "bugprone-unhandled-exception-at-new"); CheckFactories.registerCheck( "bugprone-unused-raii"); CheckFactories.registerCheck( diff --git a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt index b3684a5c101b..022e5c5842ee 100644 --- a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt @@ -17,6 +17,7 @@ add_clang_library(clangTidyBugproneModule FoldInitTypeCheck.cpp ForwardDeclarationNamespaceCheck.cpp ForwardingReferenceOverloadCheck.cpp + ImplicitWideningOfMultiplicationResultCheck.cpp InaccurateEraseCheck.cpp IncorrectRoundingsCheck.cpp InfiniteLoopCheck.cpp @@ -55,6 +56,7 @@ add_clang_library(clangTidyBugproneModule TooSmallLoopVariableCheck.cpp UndefinedMemoryManipulationCheck.cpp UndelegatedConstructorCheck.cpp + UnhandledExceptionAtNewCheck.cpp UnhandledSelfAssignmentCheck.cpp UnusedRaiiCheck.cpp UnusedReturnValueCheck.cpp diff --git a/clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.cpp new file mode 100644 index 000000000000..29b2bdfc66c0 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.cpp @@ -0,0 +1,277 @@ +//===--- ImplicitWideningOfMultiplicationResultCheck.cpp - clang-tidy -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ImplicitWideningOfMultiplicationResultCheck.h" +#include "clang/AST/ASTContext.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" + +using namespace clang::ast_matchers; + +namespace clang { +namespace { +AST_MATCHER(ImplicitCastExpr, isPartOfExplicitCast) { + return Node.isPartOfExplicitCast(); +} +} // namespace +} // namespace clang + +namespace clang { +namespace tidy { +namespace bugprone { + +static const Expr *getLHSOfMulBinOp(const Expr *E) { + assert(E == E->IgnoreParens() && "Already skipped all parens!"); + // Is this: long r = int(x) * int(y); ? + // FIXME: shall we skip brackets/casts/etc? + const auto *BO = dyn_cast(E); + if (!BO || BO->getOpcode() != BO_Mul) + // FIXME: what about: long r = int(x) + (int(y) * int(z)); ? + return nullptr; + return BO->getLHS()->IgnoreParens(); +} + +ImplicitWideningOfMultiplicationResultCheck:: + ImplicitWideningOfMultiplicationResultCheck(StringRef Name, + ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + UseCXXStaticCastsInCppSources( + Options.get("UseCXXStaticCastsInCppSources", true)), + UseCXXHeadersInCppSources(Options.get("UseCXXHeadersInCppSources", true)), + IncludeInserter(Options.getLocalOrGlobal("IncludeStyle", + utils::IncludeSorter::IS_LLVM)) { +} + +void ImplicitWideningOfMultiplicationResultCheck::registerPPCallbacks( + const SourceManager &SM, Preprocessor *PP, Preprocessor *ModuleExpanderPP) { + IncludeInserter.registerPreprocessor(PP); +} + +void ImplicitWideningOfMultiplicationResultCheck::storeOptions( + ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "UseCXXStaticCastsInCppSources", + UseCXXStaticCastsInCppSources); + Options.store(Opts, "UseCXXHeadersInCppSources", UseCXXHeadersInCppSources); + Options.store(Opts, "IncludeStyle", IncludeInserter.getStyle()); +} + +llvm::Optional +ImplicitWideningOfMultiplicationResultCheck::includeStddefHeader( + SourceLocation File) { + return IncludeInserter.createIncludeInsertion( + Result->SourceManager->getFileID(File), + ShouldUseCXXHeader ? "" : ""); +} + +void ImplicitWideningOfMultiplicationResultCheck::handleImplicitCastExpr( + const ImplicitCastExpr *ICE) { + ASTContext *Context = Result->Context; + + const Expr *E = ICE->getSubExpr()->IgnoreParens(); + QualType Ty = ICE->getType(); + QualType ETy = E->getType(); + + assert(!ETy->isDependentType() && !Ty->isDependentType() && + "Don't expect to ever get here in template Context."); + + // This must be a widening cast. Else we do not care. + unsigned SrcWidth = Context->getIntWidth(ETy); + unsigned TgtWidth = Context->getIntWidth(Ty); + if (TgtWidth <= SrcWidth) + return; + + // Does the index expression look like it might be unintentionally computed + // in a narrower-than-wanted type? + const Expr *LHS = getLHSOfMulBinOp(E); + if (!LHS) + return; + + // Ok, looks like we should diagnose this. + diag(E->getBeginLoc(), "performing an implicit widening conversion to type " + "%0 of a multiplication performed in type %1") + << Ty << E->getType(); + + { + auto Diag = diag(E->getBeginLoc(), + "make conversion explicit to silence this warning", + DiagnosticIDs::Note) + << E->getSourceRange(); + + if (ShouldUseCXXStaticCast) + Diag << FixItHint::CreateInsertion( + E->getBeginLoc(), "static_cast<" + Ty.getAsString() + ">(") + << FixItHint::CreateInsertion(E->getEndLoc(), ")"); + else + Diag << FixItHint::CreateInsertion(E->getBeginLoc(), + "(" + Ty.getAsString() + ")(") + << FixItHint::CreateInsertion(E->getEndLoc(), ")"); + Diag << includeStddefHeader(E->getBeginLoc()); + } + + QualType WideExprTy; + // Get Ty of the same signedness as ExprTy, because we only want to suggest + // to widen the computation, but not change it's signedness domain. + if (Ty->isSignedIntegerType() == ETy->isSignedIntegerType()) + WideExprTy = Ty; + else if (Ty->isSignedIntegerType()) { + assert(ETy->isUnsignedIntegerType() && + "Expected source type to be signed."); + WideExprTy = Context->getCorrespondingUnsignedType(Ty); + } else { + assert(Ty->isUnsignedIntegerType() && + "Expected target type to be unsigned."); + assert(ETy->isSignedIntegerType() && + "Expected source type to be unsigned."); + WideExprTy = Context->getCorrespondingSignedType(Ty); + } + + { + auto Diag = diag(E->getBeginLoc(), "perform multiplication in a wider type", + DiagnosticIDs::Note) + << LHS->getSourceRange(); + + if (ShouldUseCXXStaticCast) + Diag << FixItHint::CreateInsertion(LHS->getBeginLoc(), + "static_cast<" + + WideExprTy.getAsString() + ">(") + << FixItHint::CreateInsertion(LHS->getEndLoc(), ")"); + else + Diag << FixItHint::CreateInsertion(LHS->getBeginLoc(), + "(" + WideExprTy.getAsString() + ")"); + Diag << includeStddefHeader(LHS->getBeginLoc()); + } +} + +void ImplicitWideningOfMultiplicationResultCheck::handlePointerOffsetting( + const Expr *E) { + ASTContext *Context = Result->Context; + + // We are looking for a pointer offset operation, + // with one hand being a pointer, and another one being an offset. + const Expr *PointerExpr, *IndexExpr; + if (const auto *BO = dyn_cast(E)) { + PointerExpr = BO->getLHS(); + IndexExpr = BO->getRHS(); + } else if (const auto *ASE = dyn_cast(E)) { + PointerExpr = ASE->getLHS(); + IndexExpr = ASE->getRHS(); + } else + return; + + if (IndexExpr->getType()->isPointerType()) + std::swap(PointerExpr, IndexExpr); + + if (!PointerExpr->getType()->isPointerType() || + IndexExpr->getType()->isPointerType()) + return; + + IndexExpr = IndexExpr->IgnoreParens(); + + QualType IndexExprType = IndexExpr->getType(); + + // If the index expression's type is not known (i.e. we are in a template), + // we can't do anything here. + if (IndexExprType->isDependentType()) + return; + + QualType SSizeTy = Context->getPointerDiffType(); + QualType USizeTy = Context->getSizeType(); + QualType SizeTy = IndexExprType->isSignedIntegerType() ? SSizeTy : USizeTy; + // FIXME: is there a way to actually get the QualType for size_t/ptrdiff_t? + // Note that SizeTy.getAsString() will be unsigned long/..., NOT size_t! + StringRef TyAsString = + IndexExprType->isSignedIntegerType() ? "ptrdiff_t" : "size_t"; + + // So, is size_t actually wider than the result of the multiplication? + if (Context->getIntWidth(IndexExprType) >= Context->getIntWidth(SizeTy)) + return; + + // Does the index expression look like it might be unintentionally computed + // in a narrower-than-wanted type? + const Expr *LHS = getLHSOfMulBinOp(IndexExpr); + if (!LHS) + return; + + // Ok, looks like we should diagnose this. + diag(E->getBeginLoc(), + "result of multiplication in type %0 is used as a pointer offset after " + "an implicit widening conversion to type '%1'") + << IndexExprType << TyAsString; + + { + auto Diag = diag(IndexExpr->getBeginLoc(), + "make conversion explicit to silence this warning", + DiagnosticIDs::Note) + << IndexExpr->getSourceRange(); + + if (ShouldUseCXXStaticCast) + Diag << FixItHint::CreateInsertion( + IndexExpr->getBeginLoc(), + (Twine("static_cast<") + TyAsString + ">(").str()) + << FixItHint::CreateInsertion(IndexExpr->getEndLoc(), ")"); + else + Diag << FixItHint::CreateInsertion(IndexExpr->getBeginLoc(), + (Twine("(") + TyAsString + ")(").str()) + << FixItHint::CreateInsertion(IndexExpr->getEndLoc(), ")"); + Diag << includeStddefHeader(IndexExpr->getBeginLoc()); + } + + { + auto Diag = + diag(IndexExpr->getBeginLoc(), "perform multiplication in a wider type", + DiagnosticIDs::Note) + << LHS->getSourceRange(); + + if (ShouldUseCXXStaticCast) + Diag << FixItHint::CreateInsertion( + LHS->getBeginLoc(), + (Twine("static_cast<") + TyAsString + ">(").str()) + << FixItHint::CreateInsertion(LHS->getEndLoc(), ")"); + else + Diag << FixItHint::CreateInsertion(LHS->getBeginLoc(), + (Twine("(") + TyAsString + ")").str()); + Diag << includeStddefHeader(LHS->getBeginLoc()); + } +} + +void ImplicitWideningOfMultiplicationResultCheck::registerMatchers( + MatchFinder *Finder) { + Finder->addMatcher(implicitCastExpr(unless(anyOf(isInTemplateInstantiation(), + isPartOfExplicitCast())), + hasCastKind(CK_IntegralCast)) + .bind("x"), + this); + Finder->addMatcher( + arraySubscriptExpr(unless(isInTemplateInstantiation())).bind("x"), this); + Finder->addMatcher(binaryOperator(unless(isInTemplateInstantiation()), + hasType(isAnyPointer()), + hasAnyOperatorName("+", "-", "+=", "-=")) + .bind("x"), + this); +} + +void ImplicitWideningOfMultiplicationResultCheck::check( + const MatchFinder::MatchResult &Result) { + this->Result = &Result; + ShouldUseCXXStaticCast = + UseCXXStaticCastsInCppSources && Result.Context->getLangOpts().CPlusPlus; + ShouldUseCXXHeader = + UseCXXHeadersInCppSources && Result.Context->getLangOpts().CPlusPlus; + + if (const auto *MatchedDecl = Result.Nodes.getNodeAs("x")) + handleImplicitCastExpr(MatchedDecl); + else if (const auto *MatchedDecl = + Result.Nodes.getNodeAs("x")) + handlePointerOffsetting(MatchedDecl); + else if (const auto *MatchedDecl = + Result.Nodes.getNodeAs("x")) + handlePointerOffsetting(MatchedDecl); +} + +} // namespace bugprone +} // namespace tidy +} // namespace clang diff --git a/clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.h b/clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.h new file mode 100644 index 000000000000..9688ee18278e --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.h @@ -0,0 +1,52 @@ +//===--- ImplicitWideningOfMultiplicationResultCheck.h ----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_IMPLICITWIDENINGOFMULTIPLICATIONRESULTCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_IMPLICITWIDENINGOFMULTIPLICATIONRESULTCHECK_H + +#include "../ClangTidyCheck.h" +#include "../utils/IncludeInserter.h" + +namespace clang { +namespace tidy { +namespace bugprone { + +/// Diagnoses instances of an implicit widening of multiplication result. +/// +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/bugprone-implicit-widening-of-multiplication-result.html +class ImplicitWideningOfMultiplicationResultCheck : public ClangTidyCheck { + const ast_matchers::MatchFinder::MatchResult *Result; + bool ShouldUseCXXStaticCast; + bool ShouldUseCXXHeader; + + llvm::Optional includeStddefHeader(SourceLocation File); + + void handleImplicitCastExpr(const ImplicitCastExpr *ICE); + void handlePointerOffsetting(const Expr *E); + +public: + ImplicitWideningOfMultiplicationResultCheck(StringRef Name, + ClangTidyContext *Context); + void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP, + Preprocessor *ModuleExpanderPP) override; + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + +private: + const bool UseCXXStaticCastsInCppSources; + const bool UseCXXHeadersInCppSources; + utils::IncludeInserter IncludeInserter; +}; + +} // namespace bugprone +} // namespace tidy +} // namespace clang + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_IMPLICITWIDENINGOFMULTIPLICATIONRESULTCHECK_H diff --git a/clang-tools-extra/clang-tidy/bugprone/UnhandledExceptionAtNewCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/UnhandledExceptionAtNewCheck.cpp new file mode 100644 index 000000000000..c558b3148c9d --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/UnhandledExceptionAtNewCheck.cpp @@ -0,0 +1,78 @@ +//===--- UnhandledExceptionAtNewCheck.cpp - clang-tidy --------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "UnhandledExceptionAtNewCheck.h" +#include "clang/AST/ASTContext.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" + +using namespace clang::ast_matchers; + +namespace clang { +namespace tidy { +namespace bugprone { + +AST_MATCHER_P(CXXTryStmt, hasHandlerFor, + ast_matchers::internal::Matcher, InnerMatcher) { + for (unsigned NH = Node.getNumHandlers(), I = 0; I < NH; ++I) { + const CXXCatchStmt *CatchS = Node.getHandler(I); + // Check for generic catch handler (match anything). + if (CatchS->getCaughtType().isNull()) + return true; + ast_matchers::internal::BoundNodesTreeBuilder Result(*Builder); + if (InnerMatcher.matches(CatchS->getCaughtType(), Finder, &Result)) { + *Builder = std::move(Result); + return true; + } + } + return false; +} + +AST_MATCHER(CXXNewExpr, mayThrow) { + FunctionDecl *OperatorNew = Node.getOperatorNew(); + if (!OperatorNew) + return false; + return !OperatorNew->getType()->castAs()->isNothrow(); +} + +UnhandledExceptionAtNewCheck::UnhandledExceptionAtNewCheck( + StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context) {} + +void UnhandledExceptionAtNewCheck::registerMatchers(MatchFinder *Finder) { + auto BadAllocType = + recordType(hasDeclaration(cxxRecordDecl(hasName("::std::bad_alloc")))); + auto ExceptionType = + recordType(hasDeclaration(cxxRecordDecl(hasName("::std::exception")))); + auto BadAllocReferenceType = referenceType(pointee(BadAllocType)); + auto ExceptionReferenceType = referenceType(pointee(ExceptionType)); + + auto CatchBadAllocType = + qualType(hasCanonicalType(anyOf(BadAllocType, BadAllocReferenceType, + ExceptionType, ExceptionReferenceType))); + auto BadAllocCatchingTryBlock = cxxTryStmt(hasHandlerFor(CatchBadAllocType)); + + auto FunctionMayNotThrow = functionDecl(isNoThrow()); + + Finder->addMatcher(cxxNewExpr(mayThrow(), + unless(hasAncestor(BadAllocCatchingTryBlock)), + hasAncestor(FunctionMayNotThrow)) + .bind("new-expr"), + this); +} + +void UnhandledExceptionAtNewCheck::check( + const MatchFinder::MatchResult &Result) { + const auto *MatchedExpr = Result.Nodes.getNodeAs("new-expr"); + if (MatchedExpr) + diag(MatchedExpr->getBeginLoc(), + "missing exception handler for allocation failure at 'new'"); +} + +} // namespace bugprone +} // namespace tidy +} // namespace clang diff --git a/clang-tools-extra/clang-tidy/bugprone/UnhandledExceptionAtNewCheck.h b/clang-tools-extra/clang-tidy/bugprone/UnhandledExceptionAtNewCheck.h new file mode 100644 index 000000000000..d8839919b838 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/UnhandledExceptionAtNewCheck.h @@ -0,0 +1,38 @@ +//===--- UnhandledExceptionAtNewCheck.h - clang-tidy ------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_UNHANDLEDEXCEPTIONATNEWCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_UNHANDLEDEXCEPTIONATNEWCHECK_H + +#include "../ClangTidyCheck.h" + +namespace clang { +namespace tidy { +namespace bugprone { + +/// Finds calls to 'new' that may throw unhandled exception at allocation +/// failure. +/// +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/bugprone-unhandled-exception-at-new.html +class UnhandledExceptionAtNewCheck : public ClangTidyCheck { +public: + UnhandledExceptionAtNewCheck(StringRef Name, ClangTidyContext *Context); + + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus && LangOpts.CXXExceptions; + } + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; +}; + +} // namespace bugprone +} // namespace tidy +} // namespace clang + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_UNHANDLEDEXCEPTIONATNEWCHECK_H diff --git a/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.cpp b/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.cpp index dffb03f76a3d..3d5c86493ed1 100644 --- a/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.cpp +++ b/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.cpp @@ -16,6 +16,22 @@ namespace clang { namespace tidy { namespace misc { +UniqueptrResetReleaseCheck::UniqueptrResetReleaseCheck( + StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + Inserter(Options.getLocalOrGlobal("IncludeStyle", + utils::IncludeSorter::IS_LLVM)) {} + +void UniqueptrResetReleaseCheck::storeOptions( + ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "IncludeStyle", Inserter.getStyle()); +} + +void UniqueptrResetReleaseCheck::registerPPCallbacks( + const SourceManager &SM, Preprocessor *PP, Preprocessor *ModuleExpanderPP) { + Inserter.registerPreprocessor(PP); +} + void UniqueptrResetReleaseCheck::registerMatchers(MatchFinder *Finder) { Finder->addMatcher( cxxMemberCallExpr( @@ -103,12 +119,15 @@ void UniqueptrResetReleaseCheck::check(const MatchFinder::MatchResult &Result) { StringRef AssignmentText = " = "; StringRef TrailingText = ""; + bool NeedsUtilityInclude = false; if (ReleaseMember->isArrow()) { AssignmentText = " = std::move(*"; TrailingText = ")"; + NeedsUtilityInclude = true; } else if (!Right->isRValue()) { AssignmentText = " = std::move("; TrailingText = ")"; + NeedsUtilityInclude = true; } auto D = diag(ResetMember->getExprLoc(), @@ -123,8 +142,11 @@ void UniqueptrResetReleaseCheck::check(const MatchFinder::MatchResult &Result) { CharSourceRange::getTokenRange(ReleaseMember->getOperatorLoc(), ResetCall->getEndLoc()), TrailingText); + if (NeedsUtilityInclude) + D << Inserter.createIncludeInsertion( + Result.SourceManager->getFileID(ResetMember->getBeginLoc()), + ""); } - } // namespace misc } // namespace tidy } // namespace clang diff --git a/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.h b/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.h index 8a085322e209..6744de2be56b 100644 --- a/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.h +++ b/clang-tools-extra/clang-tidy/misc/UniqueptrResetReleaseCheck.h @@ -10,6 +10,7 @@ #define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_UNIQUEPTRRESETRELEASECHECK_H #include "../ClangTidyCheck.h" +#include "../utils/IncludeInserter.h" namespace clang { namespace tidy { @@ -28,8 +29,7 @@ namespace misc { /// be `std::unique_ptr*`. class UniqueptrResetReleaseCheck : public ClangTidyCheck { public: - UniqueptrResetReleaseCheck(StringRef Name, ClangTidyContext *Context) - : ClangTidyCheck(Name, Context) {} + UniqueptrResetReleaseCheck(StringRef Name, ClangTidyContext *Context); bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { // Only register the matchers for C++11; the functionality currently does @@ -37,8 +37,14 @@ class UniqueptrResetReleaseCheck : public ClangTidyCheck { // provide any benefit to other languages, despite being benign. return LangOpts.CPlusPlus11; } + void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP, + Preprocessor *ModuleExpanderPP) override; void registerMatchers(ast_matchers::MatchFinder *Finder) override; void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + +private: + utils::IncludeInserter Inserter; }; } // namespace misc diff --git a/clang-tools-extra/clangd/CMakeLists.txt b/clang-tools-extra/clangd/CMakeLists.txt index 11b8c7eadd1d..671e55e8622d 100644 --- a/clang-tools-extra/clangd/CMakeLists.txt +++ b/clang-tools-extra/clangd/CMakeLists.txt @@ -76,6 +76,7 @@ add_clang_library(clangDaemon HeuristicResolver.cpp Hover.cpp IncludeFixer.cpp + InlayHints.cpp JSONTransport.cpp PathMapping.cpp Protocol.cpp diff --git a/clang-tools-extra/clangd/ClangdLSPServer.cpp b/clang-tools-extra/clangd/ClangdLSPServer.cpp index aef849d8d8d9..4916dfaafd5a 100644 --- a/clang-tools-extra/clangd/ClangdLSPServer.cpp +++ b/clang-tools-extra/clangd/ClangdLSPServer.cpp @@ -571,6 +571,7 @@ void ClangdLSPServer::onInitialize(const InitializeParams &Params, {"referencesProvider", true}, {"astProvider", true}, // clangd extension {"typeHierarchyProvider", true}, + {"clangdInlayHintsProvider", true}, {"memoryUsageProvider", true}, // clangd extension {"compilationDatabase", // clangd extension llvm::json::Object{{"automaticReload", true}}}, @@ -1208,6 +1209,11 @@ void ClangdLSPServer::onCallHierarchyOutgoingCalls( Reply(std::vector{}); } +void ClangdLSPServer::onInlayHints(const InlayHintsParams &Params, + Callback> Reply) { + Server->inlayHints(Params.textDocument.uri.file(), std::move(Reply)); +} + void ClangdLSPServer::applyConfiguration( const ConfigurationSettings &Settings) { // Per-file update to the compilation database. @@ -1471,6 +1477,7 @@ void ClangdLSPServer::bindMethods(LSPBinder &Bind, Bind.method("textDocument/documentLink", this, &ClangdLSPServer::onDocumentLink); Bind.method("textDocument/semanticTokens/full", this, &ClangdLSPServer::onSemanticTokens); Bind.method("textDocument/semanticTokens/full/delta", this, &ClangdLSPServer::onSemanticTokensDelta); + Bind.method("clangd/inlayHints", this, &ClangdLSPServer::onInlayHints); Bind.method("$/memoryUsage", this, &ClangdLSPServer::onMemoryUsage); if (Opts.FoldingRanges) Bind.method("textDocument/foldingRange", this, &ClangdLSPServer::onFoldingRange); diff --git a/clang-tools-extra/clangd/ClangdLSPServer.h b/clang-tools-extra/clangd/ClangdLSPServer.h index fc13c6257ee6..577ee66b3424 100644 --- a/clang-tools-extra/clangd/ClangdLSPServer.h +++ b/clang-tools-extra/clangd/ClangdLSPServer.h @@ -145,6 +145,7 @@ class ClangdLSPServer : private ClangdServer::Callbacks, void onCallHierarchyOutgoingCalls( const CallHierarchyOutgoingCallsParams &, Callback>); + void onInlayHints(const InlayHintsParams &, Callback>); void onChangeConfiguration(const DidChangeConfigurationParams &); void onSymbolInfo(const TextDocumentPositionParams &, Callback>); diff --git a/clang-tools-extra/clangd/ClangdServer.cpp b/clang-tools-extra/clangd/ClangdServer.cpp index 557689774b14..86eb53130d55 100644 --- a/clang-tools-extra/clangd/ClangdServer.cpp +++ b/clang-tools-extra/clangd/ClangdServer.cpp @@ -15,6 +15,7 @@ #include "Format.h" #include "HeaderSourceSwitch.h" #include "Headers.h" +#include "InlayHints.h" #include "ParsedAST.h" #include "Preamble.h" #include "Protocol.h" @@ -231,6 +232,7 @@ void ClangdServer::addDocument(PathRef File, llvm::StringRef Contents, Inputs.Opts = std::move(Opts); Inputs.Index = Index; Inputs.ClangTidyProvider = ClangTidyProvider; + Inputs.FeatureModules = FeatureModules; bool NewFile = WorkScheduler->update(File, Inputs, WantDiags); // If we loaded Foo.h, we want to make sure Foo.cpp is indexed. if (NewFile && BackgroundIdx) @@ -573,8 +575,9 @@ void ClangdServer::enumerateTweaks( static constexpr trace::Metric TweakAvailable( "tweak_available", trace::Metric::Counter, "tweak_id"); auto Action = [File = File.str(), Sel, CB = std::move(CB), - Filter = - std::move(Filter)](Expected InpAST) mutable { + Filter = std::move(Filter), + FeatureModules(this->FeatureModules)]( + Expected InpAST) mutable { if (!InpAST) return CB(InpAST.takeError()); auto Selections = tweakSelection(Sel, *InpAST); @@ -587,7 +590,7 @@ void ClangdServer::enumerateTweaks( return Filter(T) && !PreparedTweaks.count(T.id()); }; for (const auto &Sel : *Selections) { - for (auto &T : prepareTweaks(*Sel, DeduplicatingFilter)) { + for (auto &T : prepareTweaks(*Sel, DeduplicatingFilter, FeatureModules)) { Res.push_back({T->id(), T->title(), T->kind()}); PreparedTweaks.insert(T->id()); TweakAvailable.record(1, T->id()); @@ -622,7 +625,7 @@ void ClangdServer::applyTweak(PathRef File, Range Sel, StringRef TweakID, // Try each selection, take the first one that prepare()s. // If they all fail, Effect will hold get the last error. for (const auto &Selection : *Selections) { - auto T = prepareTweak(TweakID, *Selection); + auto T = prepareTweak(TweakID, *Selection, FeatureModules); if (T) { Effect = (*T)->apply(*Selection); break; @@ -749,6 +752,17 @@ void ClangdServer::incomingCalls( }); } +void ClangdServer::inlayHints(PathRef File, + Callback> CB) { + auto Action = [File = File.str(), + CB = std::move(CB)](Expected InpAST) mutable { + if (!InpAST) + return CB(InpAST.takeError()); + CB(clangd::inlayHints(InpAST->AST)); + }; + WorkScheduler->runWithAST("InlayHints", File, std::move(Action)); +} + void ClangdServer::onFileEvent(const DidChangeWatchedFilesParams &Params) { // FIXME: Do nothing for now. This will be used for indexing and potentially // invalidating other caches. diff --git a/clang-tools-extra/clangd/ClangdServer.h b/clang-tools-extra/clangd/ClangdServer.h index 37ac30f70cb4..dc1ce22463f4 100644 --- a/clang-tools-extra/clangd/ClangdServer.h +++ b/clang-tools-extra/clangd/ClangdServer.h @@ -38,6 +38,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/ADT/StringRef.h" #include +#include #include #include #include @@ -261,6 +262,9 @@ class ClangdServer { void incomingCalls(const CallHierarchyItem &Item, Callback>); + /// Resolve inlay hints for a given document. + void inlayHints(PathRef File, Callback>); + /// Retrieve the top symbols from the workspace matching a query. void workspaceSymbols(StringRef Query, int Limit, Callback> CB); diff --git a/clang-tools-extra/clangd/Compiler.h b/clang-tools-extra/clangd/Compiler.h index 13fd4da33e3c..035106968315 100644 --- a/clang-tools-extra/clangd/Compiler.h +++ b/clang-tools-extra/clangd/Compiler.h @@ -15,6 +15,7 @@ #ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_COMPILER_H #define LLVM_CLANG_TOOLS_EXTRA_CLANGD_COMPILER_H +#include "FeatureModule.h" #include "GlobalCompilationDatabase.h" #include "TidyProvider.h" #include "index/Index.h" @@ -22,6 +23,8 @@ #include "clang/Frontend/CompilerInstance.h" #include "clang/Frontend/PrecompiledPreamble.h" #include "clang/Tooling/CompilationDatabase.h" +#include +#include namespace clang { namespace clangd { @@ -54,6 +57,8 @@ struct ParseInputs { const SymbolIndex *Index = nullptr; ParseOptions Opts = ParseOptions(); TidyProviderRef ClangTidyProvider = {}; + // Used to acquire ASTListeners when parsing files. + FeatureModuleSet *FeatureModules = nullptr; }; /// Builds compiler invocation that could be used to build AST or preamble. diff --git a/clang-tools-extra/clangd/ConfigCompile.cpp b/clang-tools-extra/clangd/ConfigCompile.cpp index a5745727dca7..31beb6ac10cb 100644 --- a/clang-tools-extra/clangd/ConfigCompile.cpp +++ b/clang-tools-extra/clangd/ConfigCompile.cpp @@ -101,6 +101,7 @@ struct FragmentCompiler { llvm::SourceMgr *SourceMgr; // Normalized Fragment::SourceInfo::Directory. std::string FragmentDirectory; + bool Trusted = false; llvm::Optional compileRegex(const Located &Text, @@ -183,6 +184,7 @@ struct FragmentCompiler { } void compile(Fragment &&F) { + Trusted = F.Source.Trusted; if (!F.Source.Directory.empty()) { FragmentDirectory = llvm::sys::path::convert_to_slash(F.Source.Directory); if (FragmentDirectory.back() != '/') @@ -320,6 +322,13 @@ struct FragmentCompiler { void compile(Fragment::IndexBlock::ExternalBlock &&External, llvm::SMRange BlockRange) { + if (External.Server && !Trusted) { + diag(Error, + "Remote index may not be specified by untrusted configuration. " + "Copy this into user config to use it.", + External.Server->Range); + return; + } #ifndef CLANGD_ENABLE_REMOTE if (External.Server) { elog("Clangd isn't compiled with remote index support, ignoring Server: " @@ -510,8 +519,8 @@ CompiledFragment Fragment::compile(DiagnosticCallback D) && { trace::Span Tracer("ConfigCompile"); SPAN_ATTACH(Tracer, "ConfigFile", ConfigFile); auto Result = std::make_shared(); - vlog("Config fragment: compiling {0}:{1} -> {2}", ConfigFile, LineCol.first, - Result.get()); + vlog("Config fragment: compiling {0}:{1} -> {2} (trusted={3})", ConfigFile, + LineCol.first, Result.get(), Source.Trusted); FragmentCompiler{*Result, D, Source.Manager.get()}.compile(std::move(*this)); // Return as cheaply-copyable wrapper. diff --git a/clang-tools-extra/clangd/ConfigFragment.h b/clang-tools-extra/clangd/ConfigFragment.h index 6b58b88dfd49..8e4110e6dba1 100644 --- a/clang-tools-extra/clangd/ConfigFragment.h +++ b/clang-tools-extra/clangd/ConfigFragment.h @@ -94,6 +94,9 @@ struct Fragment { /// Absolute path to directory the fragment is associated with. Relative /// paths mentioned in the fragment are resolved against this. std::string Directory; + /// Whether this fragment is allowed to make critical security/privacy + /// decisions. + bool Trusted = false; }; SourceInfo Source; diff --git a/clang-tools-extra/clangd/ConfigProvider.cpp b/clang-tools-extra/clangd/ConfigProvider.cpp index 3b705d8f4a82..2b8e406b60d5 100644 --- a/clang-tools-extra/clangd/ConfigProvider.cpp +++ b/clang-tools-extra/clangd/ConfigProvider.cpp @@ -36,7 +36,7 @@ class FileConfigCache : public FileCache { : FileCache(Path), Directory(Directory) {} void get(const ThreadsafeFS &TFS, DiagnosticCallback DC, - std::chrono::steady_clock::time_point FreshTime, + std::chrono::steady_clock::time_point FreshTime, bool Trusted, std::vector &Out) const { read( TFS, FreshTime, @@ -45,6 +45,7 @@ class FileConfigCache : public FileCache { if (Data) for (auto &Fragment : Fragment::parseYAML(*Data, path(), DC)) { Fragment.Source.Directory = Directory; + Fragment.Source.Trusted = Trusted; CachedValue.push_back(std::move(Fragment).compile(DC)); } }, @@ -54,35 +55,38 @@ class FileConfigCache : public FileCache { std::unique_ptr Provider::fromYAMLFile(llvm::StringRef AbsPath, llvm::StringRef Directory, - const ThreadsafeFS &FS) { + const ThreadsafeFS &FS, + bool Trusted) { class AbsFileProvider : public Provider { mutable FileConfigCache Cache; // threadsafe const ThreadsafeFS &FS; + bool Trusted; std::vector getFragments(const Params &P, DiagnosticCallback DC) const override { std::vector Result; - Cache.get(FS, DC, P.FreshTime, Result); + Cache.get(FS, DC, P.FreshTime, Trusted, Result); return Result; }; public: AbsFileProvider(llvm::StringRef Path, llvm::StringRef Directory, - const ThreadsafeFS &FS) - : Cache(Path, Directory), FS(FS) { + const ThreadsafeFS &FS, bool Trusted) + : Cache(Path, Directory), FS(FS), Trusted(Trusted) { assert(llvm::sys::path::is_absolute(Path)); } }; - return std::make_unique(AbsPath, Directory, FS); + return std::make_unique(AbsPath, Directory, FS, Trusted); } std::unique_ptr Provider::fromAncestorRelativeYAMLFiles(llvm::StringRef RelPath, - const ThreadsafeFS &FS) { + const ThreadsafeFS &FS, bool Trusted) { class RelFileProvider : public Provider { std::string RelPath; const ThreadsafeFS &FS; + bool Trusted; mutable std::mutex Mu; // Keys are the (posix-style) ancestor directory, not the config within it. @@ -124,18 +128,19 @@ Provider::fromAncestorRelativeYAMLFiles(llvm::StringRef RelPath, // This will take a (per-file) lock for each file that actually exists. std::vector Result; for (FileConfigCache *Cache : llvm::reverse(Caches)) - Cache->get(FS, DC, P.FreshTime, Result); + Cache->get(FS, DC, P.FreshTime, Trusted, Result); return Result; }; public: - RelFileProvider(llvm::StringRef RelPath, const ThreadsafeFS &FS) - : RelPath(RelPath), FS(FS) { + RelFileProvider(llvm::StringRef RelPath, const ThreadsafeFS &FS, + bool Trusted) + : RelPath(RelPath), FS(FS), Trusted(Trusted) { assert(llvm::sys::path::is_relative(RelPath)); } }; - return std::make_unique(RelPath, FS); + return std::make_unique(RelPath, FS, Trusted); } std::unique_ptr diff --git a/clang-tools-extra/clangd/ConfigProvider.h b/clang-tools-extra/clangd/ConfigProvider.h index 25d9450f28a7..428438b67f14 100644 --- a/clang-tools-extra/clangd/ConfigProvider.h +++ b/clang-tools-extra/clangd/ConfigProvider.h @@ -69,7 +69,8 @@ class Provider { /// Directory will be used to resolve relative paths in the fragments. static std::unique_ptr fromYAMLFile(llvm::StringRef AbsPath, llvm::StringRef Directory, - const ThreadsafeFS &); + const ThreadsafeFS &, + bool Trusted = false); // Reads fragments from YAML files found relative to ancestors of Params.Path. // // All fragments that exist are returned, starting from distant ancestors. @@ -78,7 +79,8 @@ class Provider { // // If Params does not specify a path, no fragments are returned. static std::unique_ptr - fromAncestorRelativeYAMLFiles(llvm::StringRef RelPath, const ThreadsafeFS &); + fromAncestorRelativeYAMLFiles(llvm::StringRef RelPath, const ThreadsafeFS &, + bool Trusted = false); /// A provider that includes fragments from all the supplied providers. /// Order is preserved; later providers take precedence over earlier ones. diff --git a/clang-tools-extra/clangd/Diagnostics.cpp b/clang-tools-extra/clangd/Diagnostics.cpp index d2982636c807..453b5a644d09 100644 --- a/clang-tools-extra/clangd/Diagnostics.cpp +++ b/clang-tools-extra/clangd/Diagnostics.cpp @@ -476,6 +476,10 @@ void toLSPDiags( Res.message = noteMessage(D, Note, Opts); OutFn(std::move(Res), llvm::ArrayRef()); } + + // FIXME: Get rid of the copies here by taking in a mutable clangd::Diag. + for (auto &Entry : D.OpaqueData) + Main.data.insert({Entry.first, Entry.second}); } int getSeverity(DiagnosticsEngine::Level L) { @@ -744,6 +748,8 @@ void StoreDiags::HandleDiagnostic(DiagnosticsEngine::Level DiagLevel, LastDiag->Fixes.insert(LastDiag->Fixes.end(), ExtraFixes.begin(), ExtraFixes.end()); } + if (DiagCB) + DiagCB(Info, *LastDiag); } else { // Handle a note to an existing diagnostic. diff --git a/clang-tools-extra/clangd/Diagnostics.h b/clang-tools-extra/clangd/Diagnostics.h index 6a432db23cc2..9c2235dce9a9 100644 --- a/clang-tools-extra/clangd/Diagnostics.h +++ b/clang-tools-extra/clangd/Diagnostics.h @@ -20,9 +20,14 @@ #include "llvm/ADT/Optional.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSet.h" +#include "llvm/Support/JSON.h" #include "llvm/Support/SourceMgr.h" #include +#include +#include #include +#include +#include namespace clang { namespace tidy { @@ -67,6 +72,10 @@ struct DiagBase { // diags from the main file. bool InsideMainFile = false; unsigned ID; // e.g. member of clang::diag, or clang-tidy assigned ID. + // Feature modules can make use of this field to propagate data from a + // diagnostic to a CodeAction request. Each module should only append to the + // list. + llvm::json::Object OpaqueData; }; llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const DiagBase &D); @@ -136,18 +145,24 @@ class StoreDiags : public DiagnosticConsumer { const clang::Diagnostic &)>; using LevelAdjuster = std::function; + using DiagCallback = + std::function; /// If set, possibly adds fixes for diagnostics using \p Fixer. void contributeFixes(DiagFixer Fixer) { this->Fixer = Fixer; } /// If set, this allows the client of this class to adjust the level of /// diagnostics, such as promoting warnings to errors, or ignoring /// diagnostics. void setLevelAdjuster(LevelAdjuster Adjuster) { this->Adjuster = Adjuster; } + /// Invokes a callback every time a diagnostics is completely formed. Handler + /// of the callback can also mutate the diagnostic. + void setDiagCallback(DiagCallback CB) { DiagCB = std::move(CB); } private: void flushLastDiag(); DiagFixer Fixer = nullptr; LevelAdjuster Adjuster = nullptr; + DiagCallback DiagCB = nullptr; std::vector Output; llvm::Optional LangOpts; llvm::Optional LastDiag; diff --git a/clang-tools-extra/clangd/FeatureModule.h b/clang-tools-extra/clangd/FeatureModule.h index 337fa24e9454..82c9134f9272 100644 --- a/clang-tools-extra/clangd/FeatureModule.h +++ b/clang-tools-extra/clangd/FeatureModule.h @@ -11,6 +11,7 @@ #include "support/Function.h" #include "support/Threading.h" +#include "clang/Basic/Diagnostic.h" #include "llvm/ADT/FunctionExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Compiler.h" @@ -21,10 +22,12 @@ namespace clang { namespace clangd { +struct Diag; class LSPBinder; class SymbolIndex; class ThreadsafeFS; class TUScheduler; +class Tweak; /// A FeatureModule contributes a vertical feature to clangd. /// @@ -91,6 +94,26 @@ class FeatureModule { /// Called by the server when shutting down, and also by tests. virtual bool blockUntilIdle(Deadline) { return true; } + /// Tweaks implemented by this module. Can be called asynchronously when + /// enumerating or applying code actions. + virtual void contributeTweaks(std::vector> &Out) {} + + /// Extension point that allows modules to observe and modify an AST build. + /// One instance is created each time clangd produces a ParsedAST or + /// PrecompiledPreamble. For a given instance, lifecycle methods are always + /// called on a single thread. + struct ASTListener { + /// Listeners are destroyed once the AST is built. + virtual ~ASTListener() = default; + + /// Called everytime a diagnostic is encountered. Modules can use this + /// modify the final diagnostic, or store some information to surface code + /// actions later on. + virtual void sawDiagnostic(const clang::Diagnostic &, clangd::Diag &) {} + }; + /// Can be called asynchronously before building an AST. + virtual std::unique_ptr astListeners() { return nullptr; } + protected: /// Accessors for modules to access shared server facilities they depend on. Facilities &facilities(); diff --git a/clang-tools-extra/clangd/InlayHints.cpp b/clang-tools-extra/clangd/InlayHints.cpp new file mode 100644 index 000000000000..54b109443b30 --- /dev/null +++ b/clang-tools-extra/clangd/InlayHints.cpp @@ -0,0 +1,221 @@ +//===--- InlayHints.cpp ------------------------------------------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#include "InlayHints.h" +#include "ParsedAST.h" +#include "support/Logger.h" +#include "clang/AST/DeclarationName.h" +#include "clang/AST/ExprCXX.h" +#include "clang/AST/RecursiveASTVisitor.h" +#include "clang/Basic/SourceManager.h" + +namespace clang { +namespace clangd { + +class InlayHintVisitor : public RecursiveASTVisitor { +public: + InlayHintVisitor(std::vector &Results, ParsedAST &AST) + : Results(Results), AST(AST.getASTContext()) {} + + bool VisitCXXConstructExpr(CXXConstructExpr *E) { + // Weed out constructor calls that don't look like a function call with + // an argument list, by checking the validity of getParenOrBraceRange(). + // Also weed out std::initializer_list constructors as there are no names + // for the individual arguments. + if (!E->getParenOrBraceRange().isValid() || + E->isStdInitListInitialization()) { + return true; + } + + processCall(E->getParenOrBraceRange().getBegin(), E->getConstructor(), + {E->getArgs(), E->getNumArgs()}); + return true; + } + + bool VisitCallExpr(CallExpr *E) { + // Do not show parameter hints for operator calls written using operator + // syntax or user-defined literals. (Among other reasons, the resulting + // hints can look awkard, e.g. the expression can itself be a function + // argument and then we'd get two hints side by side). + if (isa(E) || isa(E)) + return true; + + processCall(E->getRParenLoc(), + dyn_cast_or_null(E->getCalleeDecl()), + {E->getArgs(), E->getNumArgs()}); + return true; + } + + // FIXME: Handle RecoveryExpr to try to hint some invalid calls. + +private: + // The purpose of Anchor is to deal with macros. It should be the call's + // opening or closing parenthesis or brace. (Always using the opening would + // make more sense but CallExpr only exposes the closing.) We heuristically + // assume that if this location does not come from a macro definition, then + // the entire argument list likely appears in the main file and can be hinted. + void processCall(SourceLocation Anchor, const FunctionDecl *Callee, + llvm::ArrayRef Args) { + if (Args.size() == 0 || !Callee) + return; + + // If the anchor location comes from a macro defintion, there's nowhere to + // put hints. + if (!AST.getSourceManager().getTopMacroCallerLoc(Anchor).isFileID()) + return; + + // The parameter name of a move or copy constructor is not very interesting. + if (auto *Ctor = dyn_cast(Callee)) + if (Ctor->isCopyOrMoveConstructor()) + return; + + // FIXME: Exclude setters (i.e. functions with one argument whose name + // begins with "set"), as their parameter name is also not likely to be + // interesting. + + // Don't show hints for variadic parameters. + size_t FixedParamCount = getFixedParamCount(Callee); + size_t ArgCount = std::min(FixedParamCount, Args.size()); + + NameVec ParameterNames = chooseParameterNames(Callee, ArgCount); + + for (size_t I = 0; I < ArgCount; ++I) { + StringRef Name = ParameterNames[I]; + if (!shouldHint(Args[I], Name)) + continue; + + addInlayHint(Args[I]->getSourceRange(), InlayHintKind::ParameterHint, + Name.str() + ": "); + } + } + + bool shouldHint(const Expr *Arg, StringRef ParamName) { + if (ParamName.empty()) + return false; + + // If the argument expression is a single name and it matches the + // parameter name exactly, omit the hint. + if (ParamName == getSpelledIdentifier(Arg)) + return false; + + // FIXME: Exclude argument expressions preceded by a /*paramName=*/ comment. + + return true; + } + + // If "E" spells a single unqualified identifier, return that name. + // Otherwise, return an empty string. + static StringRef getSpelledIdentifier(const Expr *E) { + E = E->IgnoreUnlessSpelledInSource(); + + if (auto *DRE = dyn_cast(E)) + if (!DRE->getQualifier()) + return getSimpleName(*DRE->getDecl()); + + if (auto *ME = dyn_cast(E)) + if (!ME->getQualifier() && ME->isImplicitAccess()) + return getSimpleName(*ME->getMemberDecl()); + + return {}; + } + + using NameVec = SmallVector; + + NameVec chooseParameterNames(const FunctionDecl *Callee, size_t ArgCount) { + // The current strategy here is to use all the parameter names from the + // canonical declaration, unless they're all empty, in which case we + // use all the parameter names from the definition (in present in the + // translation unit). + // We could try a bit harder, e.g.: + // - try all re-declarations, not just canonical + definition + // - fall back arg-by-arg rather than wholesale + + NameVec ParameterNames = getParameterNamesForDecl(Callee, ArgCount); + + if (llvm::all_of(ParameterNames, std::mem_fn(&StringRef::empty))) { + if (const FunctionDecl *Def = Callee->getDefinition()) { + ParameterNames = getParameterNamesForDecl(Def, ArgCount); + } + } + assert(ParameterNames.size() == ArgCount); + + // Standard library functions often have parameter names that start + // with underscores, which makes the hints noisy, so strip them out. + for (auto &Name : ParameterNames) + stripLeadingUnderscores(Name); + + return ParameterNames; + } + + static void stripLeadingUnderscores(StringRef &Name) { + Name = Name.ltrim('_'); + } + + // Return the number of fixed parameters Function has, that is, not counting + // parameters that are variadic (instantiated from a parameter pack) or + // C-style varargs. + static size_t getFixedParamCount(const FunctionDecl *Function) { + if (FunctionTemplateDecl *Template = Function->getPrimaryTemplate()) { + FunctionDecl *F = Template->getTemplatedDecl(); + size_t Result = 0; + for (ParmVarDecl *Parm : F->parameters()) { + if (Parm->isParameterPack()) { + break; + } + ++Result; + } + return Result; + } + // C-style varargs don't need special handling, they're already + // not included in getNumParams(). + return Function->getNumParams(); + } + + static StringRef getSimpleName(const NamedDecl &D) { + if (IdentifierInfo *Ident = D.getDeclName().getAsIdentifierInfo()) { + return Ident->getName(); + } + + return StringRef(); + } + + NameVec getParameterNamesForDecl(const FunctionDecl *Function, + size_t ArgCount) { + NameVec Result; + for (size_t I = 0; I < ArgCount; ++I) { + const ParmVarDecl *Parm = Function->getParamDecl(I); + assert(Parm); + Result.emplace_back(getSimpleName(*Parm)); + } + return Result; + } + + void addInlayHint(SourceRange R, InlayHintKind Kind, llvm::StringRef Label) { + auto FileRange = + toHalfOpenFileRange(AST.getSourceManager(), AST.getLangOpts(), R); + if (!FileRange) + return; + Results.push_back(InlayHint{ + Range{ + sourceLocToPosition(AST.getSourceManager(), FileRange->getBegin()), + sourceLocToPosition(AST.getSourceManager(), FileRange->getEnd())}, + Kind, Label.str()}); + } + + std::vector &Results; + ASTContext &AST; +}; + +std::vector inlayHints(ParsedAST &AST) { + std::vector Results; + InlayHintVisitor Visitor(Results, AST); + Visitor.TraverseAST(AST.getASTContext()); + return Results; +} + +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/InlayHints.h b/clang-tools-extra/clangd/InlayHints.h new file mode 100644 index 000000000000..7fff916a24c0 --- /dev/null +++ b/clang-tools-extra/clangd/InlayHints.h @@ -0,0 +1,31 @@ +//===--- InlayHints.h --------------------------------------------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Support for the proposed "inlay hints" LSP feature. +// The version currently implemented is the one proposed here: +// https://github.com/microsoft/vscode-languageserver-node/pull/609/. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_INLAY_HINTS_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANGD_INLAY_HINTS_H + +#include "Protocol.h" +#include + +namespace clang { +namespace clangd { +class ParsedAST; + +// Compute and return all inlay hints for a file. +std::vector inlayHints(ParsedAST &AST); + +} // namespace clangd +} // namespace clang + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANGD_INLAY_HINTS_H diff --git a/clang-tools-extra/clangd/ParsedAST.cpp b/clang-tools-extra/clangd/ParsedAST.cpp index fca19428192e..6cb76f32ced0 100644 --- a/clang-tools-extra/clangd/ParsedAST.cpp +++ b/clang-tools-extra/clangd/ParsedAST.cpp @@ -14,6 +14,7 @@ #include "Compiler.h" #include "Config.h" #include "Diagnostics.h" +#include "FeatureModule.h" #include "Headers.h" #include "IncludeFixer.h" #include "Preamble.h" @@ -25,6 +26,7 @@ #include "support/Trace.h" #include "clang/AST/ASTContext.h" #include "clang/AST/Decl.h" +#include "clang/Basic/Diagnostic.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/SourceManager.h" @@ -261,7 +263,19 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs, // breaks many features. Disable it for the main-file (not preamble). CI->getLangOpts()->DelayedTemplateParsing = false; + std::vector> ASTListeners; + if (Inputs.FeatureModules) { + for (auto &M : *Inputs.FeatureModules) { + if (auto Listener = M.astListeners()) + ASTListeners.emplace_back(std::move(Listener)); + } + } StoreDiags ASTDiags; + ASTDiags.setDiagCallback( + [&ASTListeners](const clang::Diagnostic &D, clangd::Diag &Diag) { + llvm::for_each(ASTListeners, + [&](const auto &L) { L->sawDiagnostic(D, Diag); }); + }); llvm::Optional Patch; bool PreserveDiags = true; @@ -318,7 +332,7 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs, Check->registerMatchers(&CTFinder); } - const Config& Cfg = Config::current(); + const Config &Cfg = Config::current(); ASTDiags.setLevelAdjuster([&](DiagnosticsEngine::Level DiagLevel, const clang::Diagnostic &Info) { if (Cfg.Diagnostics.SuppressAll || diff --git a/clang-tools-extra/clangd/Preamble.cpp b/clang-tools-extra/clangd/Preamble.cpp index 88cc0b3a2905..73b1c900cfa5 100644 --- a/clang-tools-extra/clangd/Preamble.cpp +++ b/clang-tools-extra/clangd/Preamble.cpp @@ -325,7 +325,19 @@ buildPreamble(PathRef FileName, CompilerInvocation CI, trace::Span Tracer("BuildPreamble"); SPAN_ATTACH(Tracer, "File", FileName); + std::vector> ASTListeners; + if (Inputs.FeatureModules) { + for (auto &M : *Inputs.FeatureModules) { + if (auto Listener = M.astListeners()) + ASTListeners.emplace_back(std::move(Listener)); + } + } StoreDiags PreambleDiagnostics; + PreambleDiagnostics.setDiagCallback( + [&ASTListeners](const clang::Diagnostic &D, clangd::Diag &Diag) { + llvm::for_each(ASTListeners, + [&](const auto &L) { L->sawDiagnostic(D, Diag); }); + }); llvm::IntrusiveRefCntPtr PreambleDiagsEngine = CompilerInstance::createDiagnostics(&CI.getDiagnosticOpts(), &PreambleDiagnostics, false); diff --git a/clang-tools-extra/clangd/Protocol.cpp b/clang-tools-extra/clangd/Protocol.cpp index de2f34c6bd84..543239264909 100644 --- a/clang-tools-extra/clangd/Protocol.cpp +++ b/clang-tools-extra/clangd/Protocol.cpp @@ -600,6 +600,8 @@ llvm::json::Value toJSON(const Diagnostic &D) { Diag["source"] = D.source; if (D.relatedInformation) Diag["relatedInformation"] = *D.relatedInformation; + if (!D.data.empty()) + Diag["data"] = llvm::json::Object(D.data); // FIXME: workaround for older gcc/clang return std::move(Diag); } @@ -607,7 +609,11 @@ llvm::json::Value toJSON(const Diagnostic &D) { bool fromJSON(const llvm::json::Value &Params, Diagnostic &R, llvm::json::Path P) { llvm::json::ObjectMapper O(Params, P); - return O && O.map("range", R.range) && O.map("message", R.message) && + if (!O) + return false; + if (auto *Data = Params.getAsObject()->getObject("data")) + R.data = *Data; + return O.map("range", R.range) && O.map("message", R.message) && mapOptOrNull(Params, "severity", R.severity, P) && mapOptOrNull(Params, "category", R.category, P) && mapOptOrNull(Params, "code", R.code, P) && @@ -1297,6 +1303,25 @@ llvm::json::Value toJSON(const CallHierarchyOutgoingCall &C) { return llvm::json::Object{{"to", C.to}, {"fromRanges", C.fromRanges}}; } +bool fromJSON(const llvm::json::Value &Params, InlayHintsParams &R, + llvm::json::Path P) { + llvm::json::ObjectMapper O(Params, P); + return O && O.map("textDocument", R.textDocument); +} + +llvm::json::Value toJSON(InlayHintKind K) { + switch (K) { + case InlayHintKind::ParameterHint: + return "parameter"; + } + llvm_unreachable("Unknown clang.clangd.InlayHintKind"); +} + +llvm::json::Value toJSON(const InlayHint &H) { + return llvm::json::Object{ + {"range", H.range}, {"kind", H.kind}, {"label", H.label}}; +} + static const char *toString(OffsetEncoding OE) { switch (OE) { case OffsetEncoding::UTF8: diff --git a/clang-tools-extra/clangd/Protocol.h b/clang-tools-extra/clangd/Protocol.h index 8e90f1f47831..8ee0bb00396d 100644 --- a/clang-tools-extra/clangd/Protocol.h +++ b/clang-tools-extra/clangd/Protocol.h @@ -844,6 +844,13 @@ struct Diagnostic { /// Only with capability textDocument.publishDiagnostics.codeActionsInline. /// (These actions can also be obtained using textDocument/codeAction). llvm::Optional> codeActions; + + /// A data entry field that is preserved between a + /// `textDocument/publishDiagnostics` notification + /// and`textDocument/codeAction` request. + /// Mutating users should associate their data with a unique key they can use + /// to retrieve later on. + llvm::json::Object data; }; llvm::json::Value toJSON(const Diagnostic &); @@ -1478,6 +1485,48 @@ struct CallHierarchyOutgoingCall { }; llvm::json::Value toJSON(const CallHierarchyOutgoingCall &); +/// The parameter of a `textDocument/inlayHints` request. +struct InlayHintsParams { + /// The text document for which inlay hints are requested. + TextDocumentIdentifier textDocument; +}; +bool fromJSON(const llvm::json::Value &, InlayHintsParams &, llvm::json::Path); + +/// A set of predefined hint kinds. +enum class InlayHintKind { + /// The hint corresponds to parameter information. + /// An example of a parameter hint is a hint in this position: + /// func(^arg); + /// which shows the name of the corresponding parameter. + ParameterHint, + + /// Other ideas for hints that are not currently implemented: + /// + /// * Type hints, showing deduced types. + /// * Chaining hints, showing the types of intermediate expressions + /// in a chain of function calls. + /// * Hints indicating implicit conversions or implicit constructor calls. +}; +llvm::json::Value toJSON(InlayHintKind); + +/// An annotation to be displayed inline next to a range of source code. +struct InlayHint { + /// The range of source code to which the hint applies. + /// We provide the entire range, rather than just the endpoint + /// relevant to `position` (e.g. the start of the range for + /// InlayHintPosition::Before), to give clients the flexibility + /// to make choices like only displaying the hint while the cursor + /// is over the range, rather than displaying it all the time. + Range range; + + /// The type of hint. + InlayHintKind kind; + + /// The label that is displayed in the editor. + std::string label; +}; +llvm::json::Value toJSON(const InlayHint &); + struct ReferenceContext { /// Include the declaration of the current symbol. bool includeDeclaration = false; diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp index 65bbbcd28b40..e4c8db24eb20 100644 --- a/clang-tools-extra/clangd/XRefs.cpp +++ b/clang-tools-extra/clangd/XRefs.cpp @@ -30,6 +30,7 @@ #include "clang/AST/DeclObjC.h" #include "clang/AST/DeclTemplate.h" #include "clang/AST/ExprCXX.h" +#include "clang/AST/ExternalASTSource.h" #include "clang/AST/RecursiveASTVisitor.h" #include "clang/AST/Stmt.h" #include "clang/AST/StmtCXX.h" @@ -1980,5 +1981,6 @@ llvm::DenseSet getNonLocalDeclRefs(ParsedAST &AST, AST.getHeuristicResolver()); return DeclRefs; } + } // namespace clangd -} // namespace clang +} // namespace clang \ No newline at end of file diff --git a/clang-tools-extra/clangd/refactor/Tweak.cpp b/clang-tools-extra/clangd/refactor/Tweak.cpp index 34b5b2b544df..8ccb28f236bd 100644 --- a/clang-tools-extra/clangd/refactor/Tweak.cpp +++ b/clang-tools-extra/clangd/refactor/Tweak.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// #include "Tweak.h" +#include "FeatureModule.h" #include "SourceCode.h" #include "index/Index.h" #include "support/Logger.h" @@ -20,6 +21,7 @@ #include #include #include +#include LLVM_INSTANTIATE_REGISTRY(llvm::Registry) @@ -43,6 +45,18 @@ void validateRegistry() { } #endif } + +std::vector> +getAllTweaks(const FeatureModuleSet *Modules) { + std::vector> All; + for (const auto &E : TweakRegistry::entries()) + All.emplace_back(E.instantiate()); + if (Modules) { + for (auto &M : *Modules) + M.contributeTweaks(All); + } + return All; +} } // namespace Tweak::Selection::Selection(const SymbolIndex *Index, ParsedAST &AST, @@ -57,12 +71,12 @@ Tweak::Selection::Selection(const SymbolIndex *Index, ParsedAST &AST, std::vector> prepareTweaks(const Tweak::Selection &S, - llvm::function_ref Filter) { + llvm::function_ref Filter, + const FeatureModuleSet *Modules) { validateRegistry(); std::vector> Available; - for (const auto &E : TweakRegistry::entries()) { - std::unique_ptr T = E.instantiate(); + for (auto &T : getAllTweaks(Modules)) { if (!Filter(*T) || !T->prepare(S)) continue; Available.push_back(std::move(T)); @@ -74,17 +88,17 @@ prepareTweaks(const Tweak::Selection &S, return Available; } -llvm::Expected> prepareTweak(StringRef ID, - const Tweak::Selection &S) { - auto It = llvm::find_if( - TweakRegistry::entries(), - [ID](const TweakRegistry::entry &E) { return E.getName() == ID; }); - if (It == TweakRegistry::end()) - return error("tweak ID {0} is invalid", ID); - std::unique_ptr T = It->instantiate(); - if (!T->prepare(S)) - return error("failed to prepare() tweak {0}", ID); - return std::move(T); +llvm::Expected> +prepareTweak(StringRef ID, const Tweak::Selection &S, + const FeatureModuleSet *Modules) { + for (auto &T : getAllTweaks(Modules)) { + if (T->id() != ID) + continue; + if (!T->prepare(S)) + return error("failed to prepare() tweak {0}", ID); + return std::move(T); + } + return error("tweak ID {0} is invalid", ID); } llvm::Expected> diff --git a/clang-tools-extra/clangd/refactor/Tweak.h b/clang-tools-extra/clangd/refactor/Tweak.h index f991b78d8960..b381bdb2b799 100644 --- a/clang-tools-extra/clangd/refactor/Tweak.h +++ b/clang-tools-extra/clangd/refactor/Tweak.h @@ -26,6 +26,7 @@ #include "index/Index.h" #include "support/Path.h" #include "clang/Tooling/Core/Replacement.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/Optional.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" @@ -35,6 +36,8 @@ namespace clang { namespace clangd { +class FeatureModuleSet; + /// An interface base for small context-sensitive refactoring actions. /// To implement a new tweak use the following pattern in a .cpp file: /// class MyTweak : public Tweak { @@ -128,13 +131,15 @@ class Tweak { /// can run on the selection. std::vector> prepareTweaks(const Tweak::Selection &S, - llvm::function_ref Filter); + llvm::function_ref Filter, + const FeatureModuleSet *Modules); // Calls prepare() on the tweak with a given ID. // If prepare() returns false, returns an error. // If prepare() returns true, returns the corresponding tweak. -llvm::Expected> prepareTweak(StringRef TweakID, - const Tweak::Selection &S); +llvm::Expected> +prepareTweak(StringRef ID, const Tweak::Selection &S, + const FeatureModuleSet *Modules); } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/test/initialize-params.test b/clang-tools-extra/clangd/test/initialize-params.test index 4b40b17b2d64..6cc6ac7272c5 100644 --- a/clang-tools-extra/clangd/test/initialize-params.test +++ b/clang-tools-extra/clangd/test/initialize-params.test @@ -7,6 +7,7 @@ # CHECK-NEXT: "capabilities": { # CHECK-NEXT: "astProvider": true, # CHECK-NEXT: "callHierarchyProvider": true, +# CHECK-NEXT: "clangdInlayHintsProvider": true, # CHECK-NEXT: "codeActionProvider": true, # CHECK-NEXT: "compilationDatabase": { # CHECK-NEXT: "automaticReload": true diff --git a/clang-tools-extra/clangd/tool/Check.cpp b/clang-tools-extra/clangd/tool/Check.cpp index 0138ae3eb13b..dc17530a2f8f 100644 --- a/clang-tools-extra/clangd/tool/Check.cpp +++ b/clang-tools-extra/clangd/tool/Check.cpp @@ -211,7 +211,8 @@ class Checker { auto Tree = SelectionTree::createRight(AST->getASTContext(), AST->getTokens(), Start, End); Tweak::Selection Selection(&Index, *AST, Start, End, std::move(Tree)); - for (const auto &T : prepareTweaks(Selection, Opts.TweakFilter)) { + for (const auto &T : + prepareTweaks(Selection, Opts.TweakFilter, Opts.FeatureModules)) { auto Result = T->apply(Selection); if (!Result) { elog(" tweak: {0} ==> FAIL: {1}", T->id(), Result.takeError()); diff --git a/clang-tools-extra/clangd/tool/ClangdMain.cpp b/clang-tools-extra/clangd/tool/ClangdMain.cpp index 6dd13a503887..8fe14231bfee 100644 --- a/clang-tools-extra/clangd/tool/ClangdMain.cpp +++ b/clang-tools-extra/clangd/tool/ClangdMain.cpp @@ -551,6 +551,8 @@ std::unique_ptr loadExternalIndex(const Config::ExternalIndexSpec &External, AsyncTaskRunner *Tasks) { switch (External.Kind) { + case Config::ExternalIndexSpec::None: + break; case Config::ExternalIndexSpec::Server: log("Associating {0} with remote index at {1}.", External.MountPoint, External.Location); @@ -853,8 +855,8 @@ clangd accepts flags on the commandline, and in the CLANGD_FLAGS environment var if (llvm::sys::path::user_config_directory(UserConfig)) { llvm::sys::path::append(UserConfig, "clangd", "config.yaml"); vlog("User config file is {0}", UserConfig); - ProviderStack.push_back( - config::Provider::fromYAMLFile(UserConfig, /*Directory=*/"", TFS)); + ProviderStack.push_back(config::Provider::fromYAMLFile( + UserConfig, /*Directory=*/"", TFS, /*Trusted=*/true)); } else { elog("Couldn't determine user config file, not loading"); } diff --git a/clang-tools-extra/clangd/unittests/CMakeLists.txt b/clang-tools-extra/clangd/unittests/CMakeLists.txt index b16a443b3da3..3a439b11e632 100644 --- a/clang-tools-extra/clangd/unittests/CMakeLists.txt +++ b/clang-tools-extra/clangd/unittests/CMakeLists.txt @@ -55,6 +55,7 @@ add_unittest(ClangdUnitTests ClangdTests DraftStoreTests.cpp DumpASTTests.cpp ExpectedTypeTest.cpp + FeatureModulesTests.cpp FileDistanceTests.cpp FileIndexTests.cpp FindSymbolsTests.cpp @@ -68,6 +69,7 @@ add_unittest(ClangdUnitTests ClangdTests HoverTests.cpp IndexActionTests.cpp IndexTests.cpp + InlayHintTests.cpp JSONTransportTests.cpp LoggerTests.cpp LSPBinderTests.cpp diff --git a/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp b/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp index f596f94bd6cd..6955fa0caa25 100644 --- a/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp +++ b/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp @@ -365,6 +365,27 @@ TEST_F(LSPTest, FeatureModulesThreadingTest) { // And immediately shut down. FeatureModule destructor verifies we blocked. } +TEST_F(LSPTest, DiagModuleTest) { + static constexpr llvm::StringLiteral DiagMsg = "DiagMsg"; + class DiagModule final : public FeatureModule { + struct DiagHooks : public ASTListener { + void sawDiagnostic(const clang::Diagnostic &, clangd::Diag &D) override { + D.Message = DiagMsg.str(); + } + }; + + public: + std::unique_ptr astListeners() override { + return std::make_unique(); + } + }; + FeatureModules.add(std::make_unique()); + + auto &Client = start(); + Client.didOpen("foo.cpp", "test;"); + EXPECT_THAT(Client.diagnostics("foo.cpp"), + llvm::ValueIs(testing::ElementsAre(DiagMessage(DiagMsg)))); +} } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp b/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp index 23347e2324fe..f999e0ec2c35 100644 --- a/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp +++ b/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp @@ -318,7 +318,21 @@ TEST_F(ConfigCompileTests, TidyBadChecks) { DiagKind(llvm::SourceMgr::DK_Warning)))); } +TEST_F(ConfigCompileTests, ExternalServerNeedsTrusted) { + Fragment::IndexBlock::ExternalBlock External; + External.Server.emplace("xxx"); + Frag.Index.External = std::move(External); + compileAndApply(); + EXPECT_THAT( + Diags.Diagnostics, + ElementsAre(DiagMessage( + "Remote index may not be specified by untrusted configuration. " + "Copy this into user config to use it."))); + EXPECT_FALSE(Conf.Index.External.hasValue()); +} + TEST_F(ConfigCompileTests, ExternalBlockWarnOnMultipleSource) { + Frag.Source.Trusted = true; Fragment::IndexBlock::ExternalBlock External; External.File.emplace(""); External.Server.emplace(""); diff --git a/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp b/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp index d5b4a08a4229..d5096cba7e74 100644 --- a/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp +++ b/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp @@ -9,6 +9,7 @@ #include "Annotations.h" #include "Config.h" #include "Diagnostics.h" +#include "FeatureModule.h" #include "ParsedAST.h" #include "Protocol.h" #include "SourceCode.h" @@ -26,6 +27,7 @@ #include "gmock/gmock.h" #include "gtest/gtest.h" #include +#include namespace clang { namespace clangd { @@ -1346,6 +1348,31 @@ TEST(ToLSPDiag, RangeIsInMain) { }); } +TEST(ParsedASTTest, ModuleSawDiag) { + static constexpr const llvm::StringLiteral KDiagMsg = "StampedDiag"; + struct DiagModifierModule final : public FeatureModule { + struct Listener : public FeatureModule::ASTListener { + void sawDiagnostic(const clang::Diagnostic &Info, + clangd::Diag &Diag) override { + Diag.Message = KDiagMsg.str(); + } + }; + std::unique_ptr astListeners() override { + return std::make_unique(); + }; + }; + FeatureModuleSet FMS; + FMS.add(std::make_unique()); + + Annotations Code("[[test]]; /* error-ok */"); + TestTU TU; + TU.Code = Code.code().str(); + TU.FeatureModules = &FMS; + + auto AST = TU.build(); + EXPECT_THAT(*AST.getDiagnostics(), + testing::Contains(Diag(Code.range(), KDiagMsg.str()))); +} } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/unittests/FeatureModulesTests.cpp b/clang-tools-extra/clangd/unittests/FeatureModulesTests.cpp new file mode 100644 index 000000000000..d73b805499f7 --- /dev/null +++ b/clang-tools-extra/clangd/unittests/FeatureModulesTests.cpp @@ -0,0 +1,55 @@ +//===--- FeatureModulesTests.cpp -------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "FeatureModule.h" +#include "Selection.h" +#include "TestTU.h" +#include "refactor/Tweak.h" +#include "support/Logger.h" +#include "llvm/Support/Error.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" +#include + +namespace clang { +namespace clangd { +namespace { + +TEST(FeatureModulesTest, ContributesTweak) { + static constexpr const char *TweakID = "ModuleTweak"; + struct TweakContributingModule final : public FeatureModule { + struct ModuleTweak final : public Tweak { + const char *id() const override { return TweakID; } + bool prepare(const Selection &Sel) override { return true; } + Expected apply(const Selection &Sel) override { + return error("not implemented"); + } + std::string title() const override { return id(); } + llvm::StringLiteral kind() const override { return ""; }; + }; + + void contributeTweaks(std::vector> &Out) override { + Out.emplace_back(new ModuleTweak); + } + }; + + FeatureModuleSet Set; + Set.add(std::make_unique()); + + auto AST = TestTU::withCode("").build(); + auto Tree = + SelectionTree::createRight(AST.getASTContext(), AST.getTokens(), 0, 0); + auto Actual = prepareTweak( + TweakID, Tweak::Selection(nullptr, AST, 0, 0, std::move(Tree)), &Set); + ASSERT_TRUE(bool(Actual)); + EXPECT_EQ(Actual->get()->id(), TweakID); +} + +} // namespace +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp new file mode 100644 index 000000000000..6a39dc9d923a --- /dev/null +++ b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp @@ -0,0 +1,327 @@ +//===-- InlayHintTests.cpp -------------------------------*- C++ -*-------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#include "Annotations.h" +#include "InlayHints.h" +#include "Protocol.h" +#include "TestTU.h" +#include "XRefs.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +namespace clang { +namespace clangd { +namespace { + +using ::testing::UnorderedElementsAre; + +std::vector parameterHints(ParsedAST &AST) { + std::vector Result; + for (auto &Hint : inlayHints(AST)) { + if (Hint.kind == InlayHintKind::ParameterHint) + Result.push_back(Hint); + } + return Result; +} + +struct ExpectedHint { + std::string Label; + std::string RangeName; +}; + +MATCHER_P2(HintMatcher, Expected, Code, "") { + return arg.label == Expected.Label && + arg.range == Code.range(Expected.RangeName); +} + +template +void assertParameterHints(llvm::StringRef AnnotatedSource, + ExpectedHints... Expected) { + Annotations Source(AnnotatedSource); + TestTU TU = TestTU::withCode(Source.code()); + TU.ExtraArgs.push_back("-std=c++11"); + auto AST = TU.build(); + + EXPECT_THAT(parameterHints(AST), + UnorderedElementsAre(HintMatcher(Expected, Source)...)); +} + +TEST(ParameterHints, Smoke) { + assertParameterHints(R"cpp( + void foo(int param); + void bar() { + foo($param[[42]]); + } + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, NoName) { + // No hint for anonymous parameter. + assertParameterHints(R"cpp( + void foo(int); + void bar() { + foo(42); + } + )cpp"); +} + +TEST(ParameterHints, NameInDefinition) { + // Parameter name picked up from definition if necessary. + assertParameterHints(R"cpp( + void foo(int); + void bar() { + foo($param[[42]]); + } + void foo(int param) {}; + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, NameMismatch) { + // Prefer name from declaration. + assertParameterHints(R"cpp( + void foo(int good); + void bar() { + foo($good[[42]]); + } + void foo(int bad) {}; + )cpp", + ExpectedHint{"good: ", "good"}); +} + +TEST(ParameterHints, Operator) { + // No hint for operator call with operator syntax. + assertParameterHints(R"cpp( + struct S {}; + void operator+(S lhs, S rhs); + void bar() { + S a, b; + a + b; + } + )cpp"); +} + +TEST(ParameterHints, Macros) { + // Handling of macros depends on where the call's argument list comes from. + + // If it comes from a macro definition, there's nothing to hint + // at the invocation site. + assertParameterHints(R"cpp( + void foo(int param); + #define ExpandsToCall() foo(42) + void bar() { + ExpandsToCall(); + } + )cpp"); + + // The argument expression being a macro invocation shouldn't interfere + // with hinting. + assertParameterHints(R"cpp( + #define PI 3.14 + void foo(double param); + void bar() { + foo($param[[PI]]); + } + )cpp", + ExpectedHint{"param: ", "param"}); + + // If the whole argument list comes from a macro parameter, hint it. + assertParameterHints(R"cpp( + void abort(); + #define ASSERT(expr) if (!expr) abort() + int foo(int param); + void bar() { + ASSERT(foo($param[[42]]) == 0); + } + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, ConstructorParens) { + assertParameterHints(R"cpp( + struct S { + S(int param); + }; + void bar() { + S obj($param[[42]]); + } + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, ConstructorBraces) { + assertParameterHints(R"cpp( + struct S { + S(int param); + }; + void bar() { + S obj{$param[[42]]}; + } + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, ConstructorStdInitList) { + // Do not show hints for std::initializer_list constructors. + assertParameterHints(R"cpp( + namespace std { + template class initializer_list {}; + } + struct S { + S(std::initializer_list param); + }; + void bar() { + S obj{42, 43}; + } + )cpp"); +} + +TEST(ParameterHints, MemberInit) { + assertParameterHints(R"cpp( + struct S { + S(int param); + }; + struct T { + S member; + T() : member($param[[42]]) {} + }; + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, ImplicitConstructor) { + assertParameterHints(R"cpp( + struct S { + S(int param); + }; + void bar(S); + S foo() { + // Do not show hint for implicit constructor call in argument. + bar(42); + // Do not show hint for implicit constructor call in return. + return 42; + } + )cpp"); +} + +TEST(ParameterHints, ArgMatchesParam) { + assertParameterHints(R"cpp( + void foo(int param); + struct S { + static const int param = 42; + }; + void bar() { + int param = 42; + // Do not show redundant "param: param". + foo(param); + // But show it if the argument is qualified. + foo($param[[S::param]]); + } + struct A { + int param; + void bar() { + // Do not show "param: param" for member-expr. + foo(param); + } + }; + )cpp", + ExpectedHint{"param: ", "param"}); +} + +TEST(ParameterHints, LeadingUnderscore) { + assertParameterHints(R"cpp( + void foo(int p1, int _p2, int __p3); + void bar() { + foo($p1[[41]], $p2[[42]], $p3[[43]]); + } + )cpp", + ExpectedHint{"p1: ", "p1"}, ExpectedHint{"p2: ", "p2"}, + ExpectedHint{"p3: ", "p3"}); +} + +TEST(ParameterHints, DependentCall) { + // FIXME: This doesn't currently produce a hint but should. + assertParameterHints(R"cpp( + template + void foo(T param); + + template + struct S { + void bar(T par) { + foo($param[[par]]); + } + }; + )cpp"); +} + +TEST(ParameterHints, VariadicFunction) { + assertParameterHints(R"cpp( + template + void foo(int fixed, T... variadic); + + void bar() { + foo($fixed[[41]], 42, 43); + } + )cpp", + ExpectedHint{"fixed: ", "fixed"}); +} + +TEST(ParameterHints, VarargsFunction) { + assertParameterHints(R"cpp( + void foo(int fixed, ...); + + void bar() { + foo($fixed[[41]], 42, 43); + } + )cpp", + ExpectedHint{"fixed: ", "fixed"}); +} + +TEST(ParameterHints, CopyOrMoveConstructor) { + // Do not show hint for parameter of copy or move constructor. + assertParameterHints(R"cpp( + struct S { + S(); + S(const S& other); + S(S&& other); + }; + void bar() { + S a; + S b(a); // copy + S c(S()); // move + } + )cpp"); +} + +TEST(ParameterHints, AggregateInit) { + // FIXME: This is not implemented yet, but it would be a natural + // extension to show member names as hints here. + assertParameterHints(R"cpp( + struct Point { + int x; + int y; + }; + void bar() { + Point p{41, 42}; + } + )cpp"); +} + +TEST(ParameterHints, UserDefinedLiteral) { + // Do not hint call to user-defined literal operator. + assertParameterHints(R"cpp( + long double operator"" _w(long double param); + void bar() { + 1.2_w; + } + )cpp"); +} + +} // namespace +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/unittests/TestTU.cpp b/clang-tools-extra/clangd/unittests/TestTU.cpp index 1c6e54774c03..b0c0d1b7c2a1 100644 --- a/clang-tools-extra/clangd/unittests/TestTU.cpp +++ b/clang-tools-extra/clangd/unittests/TestTU.cpp @@ -36,6 +36,7 @@ ParseInputs TestTU::inputs(MockFS &FS) const { FS.Files[ImportThunk] = ThunkContents; ParseInputs Inputs; + Inputs.FeatureModules = FeatureModules; auto &Argv = Inputs.CompileCommand.CommandLine; Argv = {"clang"}; // FIXME: this shouldn't need to be conditional, but it breaks a diff --git a/clang-tools-extra/clangd/unittests/TestTU.h b/clang-tools-extra/clangd/unittests/TestTU.h index 169cab045ea1..3e0c089dc5be 100644 --- a/clang-tools-extra/clangd/unittests/TestTU.h +++ b/clang-tools-extra/clangd/unittests/TestTU.h @@ -19,12 +19,14 @@ #include "../TidyProvider.h" #include "Compiler.h" +#include "FeatureModule.h" #include "ParsedAST.h" #include "TestFS.h" #include "index/Index.h" #include "support/Path.h" #include "llvm/ADT/StringMap.h" #include "gtest/gtest.h" +#include #include #include #include @@ -76,6 +78,8 @@ struct TestTU { // to eliminate this option some day. bool OverlayRealFileSystemForModules = false; + FeatureModuleSet *FeatureModules = nullptr; + // By default, build() will report Error diagnostics as GTest errors. // Suppress this behavior by adding an 'error-ok' comment to the code. // The result will always have getDiagnostics() populated. diff --git a/clang-tools-extra/clangd/unittests/tweaks/TweakTesting.cpp b/clang-tools-extra/clangd/unittests/tweaks/TweakTesting.cpp index 680280f83149..71bd09e34177 100644 --- a/clang-tools-extra/clangd/unittests/tweaks/TweakTesting.cpp +++ b/clang-tools-extra/clangd/unittests/tweaks/TweakTesting.cpp @@ -75,7 +75,7 @@ applyTweak(ParsedAST &AST, const Annotations &Input, StringRef TweakID, Range.second, [&](SelectionTree ST) { Tweak::Selection S(Index, AST, Range.first, Range.second, std::move(ST)); - if (auto T = prepareTweak(TweakID, S)) { + if (auto T = prepareTweak(TweakID, S, nullptr)) { Result = (*T)->apply(S); return true; } else { diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 61097d1fd624..a9c943795e94 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -84,6 +84,11 @@ Improvements to clang-tidy New checks ^^^^^^^^^^ +- New :doc:`bugprone-implicit-widening-of-multiplication-result + ` check. + + Diagnoses instances of an implicit widening of multiplication result. + - New :doc:`concurrency-thread-canceltype-asynchronous ` check. @@ -102,6 +107,11 @@ New checks Finds member initializations in the constructor body which can be placed into the initialization list instead. +- New :doc:`bugprone-unhandled-exception-at-new + ` check. + + Finds calls to ``new`` with missing exception handler for ``std::bad_alloc``. + New check aliases ^^^^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone-implicit-widening-of-multiplication-result.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone-implicit-widening-of-multiplication-result.rst new file mode 100644 index 000000000000..5386fdba9e7f --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone-implicit-widening-of-multiplication-result.rst @@ -0,0 +1,63 @@ +.. title:: clang-tidy - bugprone-implicit-widening-of-multiplication-result + +bugprone-implicit-widening-of-multiplication-result +=================================================== + +The check diagnoses instances where a result of a multiplication is implicitly +widened, and suggests (with fix-it) to either silence the code by making +widening explicit, or to perform the multiplication in a wider type, +to avoid the widening afterwards. + +This is mainly useful when operating on a very large buffers. +For example, consider: + +.. code-block:: c++ + + void zeroinit(char* base, unsigned width, unsigned height) { + for(unsigned row = 0; row != height; ++row) { + for(unsigned col = 0; col != width; ++col) { + char* ptr = base + row * width + col; + *ptr = 0; + } + } + } + +This is fine in general, but iff ``width * height`` overflows, +you end up wrapping back to the beginning of ``base`` +instead of processing the entire requested buffer. + +Indeed, this only matters for pretty large buffers (4GB+), +but that can happen very easily for example in image processing, +where for that to happen you "only" need a ~269MPix image. + + +Options +------- + +.. option:: UseCXXStaticCastsInCppSources + + When suggesting fix-its for C++ code, should C++-style ``static_cast<>()``'s + be suggested, or C-style casts. Defaults to ``true``. + +.. option:: UseCXXHeadersInCppSources + + When suggesting to include the appropriate header in C++ code, + should ```` header be suggested, or ````. + Defaults to ``true``. + + +Examples: + +.. code-block:: c++ + + long mul(int a, int b) { + return a * b; // warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + } + + char* ptr_add(char *base, int a, int b) { + return base + a * b; // warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ssize_t' + } + + char ptr_subscript(char *base, int a, int b) { + return base[a * b]; // warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ssize_t' + } diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone-unhandled-exception-at-new.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone-unhandled-exception-at-new.rst new file mode 100644 index 000000000000..01f59af49f81 --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone-unhandled-exception-at-new.rst @@ -0,0 +1,25 @@ +.. title:: clang-tidy - bugprone-unhandled-exception-at-new + +bugprone-unhandled-exception-at-new +=================================== + +Finds calls to ``new`` with missing exception handler for ``std::bad_alloc``. + +.. code-block:: c++ + + int *f() noexcept { + int *p = new int[1000]; + // ... + return p; + } + +Calls to ``new`` can throw exceptions of type ``std::bad_alloc`` that should +be handled by the code. Alternatively, the nonthrowing form of ``new`` can be +used. The check verifies that the exception is handled in the function +that calls ``new``, unless a nonthrowing version is used or the exception +is allowed to propagate out of the function (exception handler is checked for +types ``std::bad_alloc``, ``std::exception``, and catch-all handler). +The check assumes that any user-defined ``operator new`` is either +``noexcept`` or may throw an exception of type ``std::bad_alloc`` (or derived +from it). Other exception types or exceptions occuring in the objects's +constructor are not taken into account. diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index bdce63cd26b6..8889be098b6d 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -62,6 +62,7 @@ Clang-Tidy Checks `bugprone-fold-init-type `_, `bugprone-forward-declaration-namespace `_, `bugprone-forwarding-reference-overload `_, + `bugprone-implicit-widening-of-multiplication-result `_, "Yes" `bugprone-inaccurate-erase `_, "Yes" `bugprone-incorrect-roundings `_, `bugprone-infinite-loop `_, @@ -100,6 +101,7 @@ Clang-Tidy Checks `bugprone-too-small-loop-variable `_, `bugprone-undefined-memory-manipulation `_, `bugprone-undelegated-constructor `_, + `bugprone-unhandled-exception-at-new `_, `bugprone-unhandled-self-assignment `_, `bugprone-unused-raii `_, "Yes" `bugprone-unused-return-value `_, diff --git a/clang-tools-extra/docs/clang-tidy/checks/misc-uniqueptr-reset-release.rst b/clang-tools-extra/docs/clang-tidy/checks/misc-uniqueptr-reset-release.rst index 858fbe78fdfa..8d48fa192e69 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/misc-uniqueptr-reset-release.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/misc-uniqueptr-reset-release.rst @@ -14,3 +14,11 @@ Example: If ``y`` is already rvalue, ``std::move()`` is not added. ``x`` and ``y`` can also be ``std::unique_ptr*``. + +Options +------- + +.. option:: IncludeStyle + + A string specifying which include-style is used, `llvm` or `google`. Default + is `llvm`. diff --git a/clang-tools-extra/docs/clang-tidy/checks/modernize-use-nodiscard.rst b/clang-tools-extra/docs/clang-tidy/checks/modernize-use-nodiscard.rst index 3048db8682a0..1f5639cdb88b 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/modernize-use-nodiscard.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/modernize-use-nodiscard.rst @@ -41,8 +41,8 @@ transforms to: .. code-block:: c++ - [[nodiscard] bool empty() const; - [[nodiscard] bool empty(int i) const; + [[nodiscard]] bool empty() const; + [[nodiscard]] bool empty(int i) const; Options ------- diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-array-subscript-expression.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-array-subscript-expression.cpp new file mode 100644 index 000000000000..3cf6be194762 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-array-subscript-expression.cpp @@ -0,0 +1,90 @@ +// RUN: %check_clang_tidy -check-suffixes=ALL,C -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy -check-suffixes=ALL,CXX %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ + +// RUN: %check_clang_tidy -check-suffixes=ALL,C -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: bugprone-implicit-widening-of-multiplication-result.UseCXXStaticCastsInCppSources, value: 0} \ +// RUN: ]}' -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy -check-suffixes=ALL,C %s bugprone-implicit-widening-of-multiplication-result %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: bugprone-implicit-widening-of-multiplication-result.UseCXXStaticCastsInCppSources, value: 0} \ +// RUN: ]}' -- -target x86_64-unknown-unknown -x c++ + +char *t0(char *base, int a, int b) { + return &base[a * b]; + // CHECK-NOTES-ALL: :[[@LINE-1]]:11: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:16: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (ptrdiff_t)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:16: note: perform multiplication in a wider type + // CHECK-NOTES-C: (ptrdiff_t) + // CHECK-NOTES-CXX: static_cast() +} +void *t1(char *base, int a, int b) { + return &((a * b)[base]); + // CHECK-NOTES-ALL: :[[@LINE-1]]:12: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:13: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:13: note: perform multiplication in a wider type +} + +char *t2(char *base, unsigned int a, int b) { + return &base[a * b]; + // CHECK-NOTES-ALL: :[[@LINE-1]]:11: warning: result of multiplication in type 'unsigned int' is used as a pointer offset after an implicit widening conversion to type 'size_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:16: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (size_t) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:16: note: perform multiplication in a wider type + // CHECK-NOTES-C: (size_t) + // CHECK-NOTES-CXX: static_cast() +} + +char *t3(char *base, int a, unsigned int b) { + return &base[a * b]; + // CHECK-NOTES-ALL: :[[@LINE-1]]:11: warning: result of multiplication in type 'unsigned int' is used as a pointer offset after an implicit widening conversion to type 'size_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:16: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:16: note: perform multiplication in a wider type +} + +char *t4(char *base, unsigned int a, unsigned int b) { + return &base[a * b]; + // CHECK-NOTES-ALL: :[[@LINE-1]]:11: warning: result of multiplication in type 'unsigned int' is used as a pointer offset after an implicit widening conversion to type 'size_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:16: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:16: note: perform multiplication in a wider type +} + +char *n5(char *base, int a, int b, int c) { + return &base[a * b + c]; +} +char *n6(char *base, int a, int b, int c) { + return &base[a + b * c]; +} + +char *t7(char *base, int a, int b) { + return &base[(a * b)]; + // CHECK-NOTES-ALL: :[[@LINE-1]]:11: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:17: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:17: note: perform multiplication in a wider type +} +char *n8(char *base, int a, int b, int c) { + return &base[(a * b + c)]; +} +char *n9(char *base, int a, int b, int c) { + return &base[(a * b) + c]; +} + +char *n10(char *base, int a, int b) { + return &base[(long)(a * b)]; +} +char *n11(char *base, int a, int b) { + return &base[(unsigned long)(a * b)]; +} + +#ifdef __cplusplus +template +char *template_test(char *base, T a, T b) { + return &base[a * b]; +} +char *template_test_instantiation(char *base, int a, int b) { + return template_test(base, a, b); +} +#endif diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-char.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-char.cpp new file mode 100644 index 000000000000..7e0cb361cefb --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-char.cpp @@ -0,0 +1,99 @@ +// RUN: %check_clang_tidy -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ + +// RUN: %check_clang_tidy -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c -fsigned-char +// RUN: %check_clang_tidy %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ -fsigned-char + +// RUN: %check_clang_tidy -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c -funsigned-char +// RUN: %check_clang_tidy %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown-x c++ -funsigned-char + +long t0(char a, char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t1(char a, char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t2(unsigned char a, char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t3(unsigned char a, char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t4(char a, unsigned char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t5(char a, unsigned char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t6(unsigned char a, unsigned char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t7(unsigned char a, unsigned char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t8(signed char a, char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t9(signed char a, char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t10(char a, signed char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t11(char a, signed char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t12(signed char a, signed char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t13(signed char a, signed char b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-extint.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-extint.cpp new file mode 100644 index 000000000000..1da232e1902c --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-extint.cpp @@ -0,0 +1,21 @@ +// RUN: %check_clang_tidy -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ + +_ExtInt(64) t0(_ExtInt(32) a, _ExtInt(32) b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type '_ExtInt(64)' of a multiplication performed in type '_ExtInt(32)' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned _ExtInt(64) t1(_ExtInt(32) a, _ExtInt(32) b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned _ExtInt(64)' of a multiplication performed in type '_ExtInt(32)' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +_ExtInt(64) t2(unsigned _ExtInt(32) a, unsigned _ExtInt(32) b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type '_ExtInt(64)' of a multiplication performed in type 'unsigned _ExtInt(32)' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-int.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-int.cpp new file mode 100644 index 000000000000..e2184f7fcb5e --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-int.cpp @@ -0,0 +1,122 @@ +// RUN: %check_clang_tidy -check-suffixes=ALL,C -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy -check-suffixes=ALL,CXX %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ + +// RUN: %check_clang_tidy -check-suffixes=ALL,C -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: bugprone-implicit-widening-of-multiplication-result.UseCXXStaticCastsInCppSources, value: 0} \ +// RUN: ]}' -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy -check-suffixes=ALL,C %s bugprone-implicit-widening-of-multiplication-result %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: bugprone-implicit-widening-of-multiplication-result.UseCXXStaticCastsInCppSources, value: 0} \ +// RUN: ]}' -- -target x86_64-unknown-unknown -x c++ + +long t0(int a, int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (long)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:10: note: perform multiplication in a wider type + // CHECK-NOTES-C: (long) + // CHECK-NOTES-CXX: static_cast() +} +unsigned long t1(int a, int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (unsigned long)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:10: note: perform multiplication in a wider type + // CHECK-NOTES-C: (long) + // CHECK-NOTES-CXX: static_cast() +} + +long t2(unsigned int a, int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'unsigned int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (long)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:10: note: perform multiplication in a wider type + // CHECK-NOTES-C: (unsigned long) + // CHECK-NOTES-CXX: static_cast() +} +unsigned long t3(unsigned int a, int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'unsigned int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (unsigned long)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:10: note: perform multiplication in a wider type + // CHECK-NOTES-C: (unsigned long) + // CHECK-NOTES-CXX: static_cast() +} + +long t4(int a, unsigned int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'unsigned int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t5(int a, unsigned int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'unsigned int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t6(unsigned int a, unsigned int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'unsigned int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +unsigned long t7(unsigned int a, unsigned int b) { + return a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'unsigned long' of a multiplication performed in type 'unsigned int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +long t8(int a, int b) { + return (a * b); + // CHECK-NOTES-ALL: :[[@LINE-1]]:11: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:11: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:11: note: perform multiplication in a wider type +} +long t9(int a, int b) { + return (a)*b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +long n10(int a, int b) { + return (long)(a * b); +} +long n11(int a, int b) { + return (unsigned long)(a * b); +} + +long n12(long a, int b) { + return a * b; +} +long n13(int a, long b) { + return a * b; +} + +long n14(int a, int b, int c) { + return a + b * c; +} +long n15(int a, int b, int c) { + return a * b + c; +} + +#ifdef __cplusplus +template +T2 template_test(T1 a, T1 b) { + return a * b; +} +long template_test_instantiation(int a, int b) { + return template_test(a, b); +} +#endif diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-pointer-offset.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-pointer-offset.cpp new file mode 100644 index 000000000000..e5c526e96aeb --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-pointer-offset.cpp @@ -0,0 +1,99 @@ +// RUN: %check_clang_tidy -check-suffixes=ALL,C -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy -check-suffixes=ALL,CXX %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ + +// RUN: %check_clang_tidy -check-suffixes=ALL,C -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: bugprone-implicit-widening-of-multiplication-result.UseCXXStaticCastsInCppSources, value: 0} \ +// RUN: ]}' -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy -check-suffixes=ALL,C %s bugprone-implicit-widening-of-multiplication-result %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: bugprone-implicit-widening-of-multiplication-result.UseCXXStaticCastsInCppSources, value: 0} \ +// RUN: ]}' -- -target x86_64-unknown-unknown -x c++ + +char *t0(char *base, int a, int b) { + return base + a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:17: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (ptrdiff_t)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:17: note: perform multiplication in a wider type + // CHECK-NOTES-C: (ptrdiff_t) + // CHECK-NOTES-CXX: static_cast() +} +char *t1(char *base, int a, int b) { + return a * b + base; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} + +char *t2(char *base, unsigned int a, int b) { + return base + a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'unsigned int' is used as a pointer offset after an implicit widening conversion to type 'size_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:17: note: make conversion explicit to silence this warning + // CHECK-NOTES-C: (size_t)( ) + // CHECK-NOTES-CXX: static_cast( ) + // CHECK-NOTES-ALL: :[[@LINE-5]]:17: note: perform multiplication in a wider type + // CHECK-NOTES-C: (size_t) + // CHECK-NOTES-CXX: static_cast() +} + +char *t3(char *base, int a, unsigned int b) { + return base + a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'unsigned int' is used as a pointer offset after an implicit widening conversion to type 'size_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:17: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:17: note: perform multiplication in a wider type +} + +char *t4(char *base, unsigned int a, unsigned int b) { + return base + a * b; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'unsigned int' is used as a pointer offset after an implicit widening conversion to type 'size_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:17: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:17: note: perform multiplication in a wider type +} + +char *t5(char *base, int a, int b, int c) { + return base + a * b + c; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:17: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:17: note: perform multiplication in a wider type +} +char *t6(char *base, int a, int b, int c) { + return base + a + b * c; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:21: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:21: note: perform multiplication in a wider type +} + +char *n7(char *base, int a, int b) { + return base + (a * b); + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:18: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:18: note: perform multiplication in a wider type +} +char *n8(char *base, int a, int b, int c) { + return base + (a * b) + c; + // CHECK-NOTES-ALL: :[[@LINE-1]]:10: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' + // CHECK-NOTES-ALL: :[[@LINE-2]]:18: note: make conversion explicit to silence this warning + // CHECK-NOTES-ALL: :[[@LINE-3]]:18: note: perform multiplication in a wider type +} +char *n9(char *base, int a, int b, int c) { + return base + (a * b + c); +} + +char *n10(char *base, int a, int b) { + return base + (long)(a * b); +} +char *n11(char *base, int a, int b) { + return base + (unsigned long)(a * b); +} + +#ifdef __cplusplus +template +char *template_test(char *base, T a, T b) { + return base + a * b; +} +char *template_test_instantiation(char *base, int a, int b) { + return template_test(base, a, b); +} +#endif diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-short.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-short.cpp new file mode 100644 index 000000000000..d824ea3b818d --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-implicit-widening-of-multiplication-result-short.cpp @@ -0,0 +1,15 @@ +// RUN: %check_clang_tidy -std=c99 %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c +// RUN: %check_clang_tidy %s bugprone-implicit-widening-of-multiplication-result %t -- -- -target x86_64-unknown-unknown -x c++ + +long t0(short a, int b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} +long t1(short a, short b) { + return a * b; + // CHECK-NOTES: :[[@LINE-1]]:10: warning: performing an implicit widening conversion to type 'long' of a multiplication performed in type 'int' + // CHECK-NOTES: :[[@LINE-2]]:10: note: make conversion explicit to silence this warning + // CHECK-NOTES: :[[@LINE-3]]:10: note: perform multiplication in a wider type +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-unhandled-exception-at-new.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-unhandled-exception-at-new.cpp new file mode 100644 index 000000000000..6883463b0ae5 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-unhandled-exception-at-new.cpp @@ -0,0 +1,208 @@ +// RUN: %check_clang_tidy -std=c++14 %s bugprone-unhandled-exception-at-new %t -- -- -fexceptions + +namespace std { +typedef __typeof__(sizeof(0)) size_t; +enum class align_val_t : std::size_t {}; +class exception {}; +class bad_alloc : public exception {}; +class bad_array_new_length : public bad_alloc {}; +struct nothrow_t {}; +extern const nothrow_t nothrow; +} // namespace std + +void *operator new(std::size_t, const std::nothrow_t &) noexcept; +void *operator new(std::size_t, std::align_val_t, const std::nothrow_t &) noexcept; +void *operator new(std::size_t, void *) noexcept; + +class A {}; +typedef std::bad_alloc badalloc1; +using badalloc2 = std::bad_alloc; +using badalloc3 = std::bad_alloc &; + +void *operator new(std::size_t, int, int); +void *operator new(std::size_t, int, int, int) noexcept; + +struct ClassSpecificNew { + void *operator new(std::size_t); + void *operator new(std::size_t, std::align_val_t); + void *operator new(std::size_t, int, int) noexcept; + void *operator new(std::size_t, int, int, int); +}; + +void f1() noexcept { + int *I1 = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: missing exception handler for allocation failure at 'new' + try { + int *I2 = new int; + try { + int *I3 = new int; + } catch (A) { + } + } catch (std::bad_alloc) { + } + + try { + int *I = new int; + } catch (std::bad_alloc &) { + } + + try { + int *I = new int; + } catch (const std::bad_alloc &) { + } + + try { + int *I = new int; + } catch (badalloc1) { + } + + try { + int *I = new int; + } catch (badalloc1 &) { + } + + try { + int *I = new int; + } catch (const badalloc1 &) { + } + + try { + int *I = new int; + } catch (badalloc2) { + } + + try { + int *I = new int; + } catch (badalloc3) { + } + + try { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: missing exception handler for allocation failure at 'new' + } catch (std::bad_alloc *) { + } + + try { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: missing exception handler for allocation failure at 'new' + } catch (A) { + } +} + +void f2() noexcept { + try { + int *I = new int; + } catch (A) { + } catch (std::bad_alloc) { + } + + try { + int *I = new int; + } catch (...) { + } + + try { + int *I = new int; + } catch (const std::exception &) { + } + + try { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: missing exception handler for allocation failure at 'new' + } catch (const std::bad_array_new_length &) { + } +} + +void f_new_nothrow() noexcept { + int *I1 = new (std::nothrow) int; + int *I2 = new (static_cast(1), std::nothrow) int; +} + +void f_new_placement() noexcept { + char buf[100]; + int *I = new (buf) int; +} + +void f_new_user_defined() noexcept { + int *I1 = new (1, 2) int; + // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: missing exception handler for allocation failure at 'new' + int *I2 = new (1, 2, 3) int; +} + +void f_class_specific() noexcept { + ClassSpecificNew *N1 = new ClassSpecificNew; + // CHECK-MESSAGES: :[[@LINE-1]]:26: warning: missing exception handler for allocation failure at 'new' + ClassSpecificNew *N2 = new (static_cast(1)) ClassSpecificNew; + // CHECK-MESSAGES: :[[@LINE-1]]:26: warning: missing exception handler for allocation failure at 'new' + ClassSpecificNew *N3 = new (1, 2) ClassSpecificNew; + ClassSpecificNew *N4 = new (1, 2, 3) ClassSpecificNew; + // CHECK-MESSAGES: :[[@LINE-1]]:26: warning: missing exception handler for allocation failure at 'new' +} + +void f_est_none() { + int *I = new int; +} + +void f_est_noexcept_false() noexcept(false) { + int *I = new int; +} + +void f_est_noexcept_true() noexcept(true) { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: missing exception handler for allocation failure at 'new' +} + +void f_est_dynamic_none() throw() { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: missing exception handler for allocation failure at 'new' +} + +void f_est_dynamic_1() throw(std::bad_alloc) { + int *I = new int; +} + +void f_est_dynamic_2() throw(A) { + // the exception specification list is not checked + int *I = new int; +} + +void f_try() noexcept try { + int *I = new int; +} catch (const std::bad_alloc &) { +} + +void f_try_bad() noexcept try { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: missing exception handler for allocation failure at 'new' +} catch (const A &) { +} + +void f_embedded_try() noexcept { + try { + try { + int *I = new int; + } catch (const A &) { + } + } catch (const std::bad_alloc &) { + } +} + +template +void f_est_noexcept_dependent_unused() noexcept(P) { + int *I = new int; +} + +template +void f_est_noexcept_dependent_used() noexcept(P) { + int *I = new int; + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: missing exception handler for allocation failure at 'new' +} + +template +void f_dependent_new() { + T *X = new T; +} + +void f_1() { + f_est_noexcept_dependent_used(); +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc-uniqueptr-reset-release.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc-uniqueptr-reset-release.cpp index befd2a0576d2..629f55a96f3b 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/misc-uniqueptr-reset-release.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/misc-uniqueptr-reset-release.cpp @@ -1,5 +1,7 @@ // RUN: %check_clang_tidy %s misc-uniqueptr-reset-release %t +// CHECK-FIXES: #include + namespace std { template diff --git a/clang/cmake/caches/Apple-stage2.cmake b/clang/cmake/caches/Apple-stage2.cmake index d347ffcd0f4f..a2eb42efbaf6 100644 --- a/clang/cmake/caches/Apple-stage2.cmake +++ b/clang/cmake/caches/Apple-stage2.cmake @@ -56,6 +56,7 @@ set(LLVM_TOOLCHAIN_TOOLS llvm-objdump llvm-nm llvm-size + llvm-cxxfilt llvm-config CACHE STRING "") diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index bf28e0d86974..986963c8ce67 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -2128,6 +2128,56 @@ the configuration (without a prefix: ``Auto``). **DisableFormat** (``bool``) Disables formatting completely. +**EmptyLineAfterAccessModifier** (``EmptyLineAfterAccessModifierStyle``) + Defines when to put an empty line after access modifiers. + ``EmptyLineBeforeAccessModifier`` configuration handles the number of + empty lines between two access modifiers. + + Possible values: + + * ``ELAAMS_Never`` (in configuration: ``Never``) + Remove all empty lines after access modifiers. + + .. code-block:: c++ + + struct foo { + private: + int i; + protected: + int j; + /* comment */ + public: + foo() {} + private: + protected: + }; + + * ``ELAAMS_Leave`` (in configuration: ``Leave``) + Keep existing empty lines after access modifiers. + MaxEmptyLinesToKeep is applied instead. + + * ``ELAAMS_Always`` (in configuration: ``Always``) + Always add empty line after access modifiers if there are none. + MaxEmptyLinesToKeep is applied also. + + .. code-block:: c++ + + struct foo { + private: + + int i; + protected: + + int j; + /* comment */ + public: + + foo() {} + private: + + protected: + }; + **EmptyLineBeforeAccessModifier** (``EmptyLineBeforeAccessModifierStyle``) Defines in which cases to put empty line before access modifiers. @@ -2195,8 +2245,6 @@ the configuration (without a prefix: ``Auto``). protected: }; - - **ExperimentalAutoDetectBinPacking** (``bool``) If ``true``, clang-format detects whether function calls and definitions are formatted with one parameter per line. diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 73128b165700..d7ee7d4ad686 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -383,6 +383,18 @@ Builtin Macros Defined to a string that captures the Clang marketing version, including the Subversion tag or revision number, e.g., "``1.5 (trunk 102332)``". +``__clang_literal_encoding__`` + Defined to a narrow string literal that represents the current encoding of + narrow string literals, e.g., ``"hello"``. This macro typically expands to + "UTF-8" (but may change in the future if the + ``-fexec-charset="Encoding-Name"`` option is implemented.) + +``__clang_wide_literal_encoding__`` + Defined to a narrow string literal that represents the current encoding of + wide string literals, e.g., ``L"hello"``. This macro typically expands to + "UTF-16" or "UTF-32" (but may change in the future if the + ``-fwide-exec-charset="Encoding-Name"`` option is implemented.) + .. _langext-vectors: Vectors and Extended Vectors diff --git a/clang/docs/OpenCLSupport.rst b/clang/docs/OpenCLSupport.rst index 5b5ab2b1bec0..0d5774091fb6 100644 --- a/clang/docs/OpenCLSupport.rst +++ b/clang/docs/OpenCLSupport.rst @@ -380,7 +380,7 @@ implementation status. +------------------------------+--------------------------------------------------------------+----------------------+---------------------------------------------------------------------------+ | Feature optionality | Work group collective functions | :part:`worked on` | https://reviews.llvm.org/D92004 | +------------------------------+--------------------------------------------------------------+----------------------+---------------------------------------------------------------------------+ -| New functionality | RGBA vector components | :none:`unclaimed` | | +| New functionality | RGBA vector components | :good:`done` | https://reviews.llvm.org/D99969 | +------------------------------+--------------------------------------------------------------+----------------------+---------------------------------------------------------------------------+ | New functionality | Subgroup functions | :part:`worked on` | https://reviews.llvm.org/D92004 | +------------------------------+--------------------------------------------------------------+----------------------+---------------------------------------------------------------------------+ diff --git a/clang/docs/OpenMPSupport.rst b/clang/docs/OpenMPSupport.rst index 6a4cdf210131..3bd1a0c21148 100644 --- a/clang/docs/OpenMPSupport.rst +++ b/clang/docs/OpenMPSupport.rst @@ -193,7 +193,7 @@ implementation. +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | device extension | implicitly map 'this' (this[:1]) | :good:`done` | D55982 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ -| device extension | allow access to the reference count (omp_target_is_present) | :part:`done` | | +| device extension | allow access to the reference count (omp_target_is_present) | :good:`done` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | device extension | requires directive | :part:`partial` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ @@ -264,7 +264,9 @@ want to help with the implementation. +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ |Category | Feature | Status | Reviews | +==============================+==============================================================+==========================+=======================================================================+ -| atomic extension | 'compare' and 'fail' clauses on atomic construct | :none:`unclaimed` | | +| atomic extension | 'compare' clause on atomic construct | :good:`worked on` | | ++------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ +| atomic extension | 'fail' clause on atomic construct | :none:`unclaimed` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | base language | C++ attribute specifier syntax | :part:`worked on` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ @@ -338,7 +340,7 @@ want to help with the implementation. +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | misc extension | nothing directive | :none:`unclaimed` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ -| misc extension | masked construct and related combined constructs | :part:`worked on` | D99995 | +| misc extension | masked construct and related combined constructs | :part:`worked on` | D99995, D100514 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | misc extension | default(firstprivate) & default(private) | :part:`partial` | firstprivate done: D75591 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index d4c9f53b82c0..ad7ff71802dd 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -46,7 +46,13 @@ sections with improvements to Clang's support for those languages. Major New Features ------------------ -- ... +- Guaranteed tail calls are now supported with statement attributes + ``[[clang::musttail]]`` in C++ and ``__attribute__((musttail))`` in C. The + attribute is applied to a return statement (not a function declaration), + and an error is emitted if a tail call cannot be guaranteed, for example if + the function signatures of caller and callee are not compatible. Guaranteed + tail calls enable a class of algorithms that would otherwise use an + arbitrary amount of stack space. Improvements to Clang's diagnostics ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -216,6 +222,13 @@ clang-format - Support for Whitesmiths has been improved, with fixes for ``namespace`` blocks and ``case`` blocks and labels. +- Option ``EmptyLineAfterAccessModifier`` has been added to remove, force or keep + new lines after access modifiers. + +- Checks for newlines in option ``EmptyLineBeforeAccessModifier`` are now based + on the formatted new lines and not on the new lines in the file. (Fixes + https://llvm.org/PR41870.) + libclang -------- diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index 41ac4fa00029..caf2b7e6a7d0 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -2753,6 +2753,14 @@ class ASTContext : public RefCountedBase { // a given fixed point type. QualType getCorrespondingUnsignedType(QualType T) const; + // Per C99 6.2.5p6, for every signed integer type, there is a corresponding + // unsigned integer type. This method takes an unsigned type, and returns the + // corresponding signed integer type. + // With the introduction of fixed point types in ISO N1169, this method also + // accepts fixed point types and returns the corresponding signed type for + // a given fixed point type. + QualType getCorrespondingSignedType(QualType T) const; + // Per ISO N1169, this method accepts fixed point types and returns the // corresponding saturated type for a given fixed point type. QualType getCorrespondingSaturatedType(QualType Ty) const; diff --git a/clang/include/clang/AST/DeclCXX.h b/clang/include/clang/AST/DeclCXX.h index bb99ab1373ba..bbf7ecf6712a 100644 --- a/clang/include/clang/AST/DeclCXX.h +++ b/clang/include/clang/AST/DeclCXX.h @@ -2267,7 +2267,8 @@ class CXXCtorInitializer final { // For a pack expansion, returns the location of the ellipsis. SourceLocation getEllipsisLoc() const { - assert(isPackExpansion() && "Initializer is not a pack expansion"); + if (!isPackExpansion()) + return {}; return MemberOrEllipsisLocation; } diff --git a/clang/include/clang/AST/IgnoreExpr.h b/clang/include/clang/AST/IgnoreExpr.h index 1c2b538e5b63..a7e9b07bef6c 100644 --- a/clang/include/clang/AST/IgnoreExpr.h +++ b/clang/include/clang/AST/IgnoreExpr.h @@ -41,7 +41,7 @@ template Expr *IgnoreExprNodes(Expr *E, FnTys &&... Fns) { template const Expr *IgnoreExprNodes(const Expr *E, FnTys &&...Fns) { - return const_cast(IgnoreExprNodes(E, std::forward(Fns)...)); + return IgnoreExprNodes(const_cast(E), std::forward(Fns)...); } inline Expr *IgnoreImplicitCastsSingleStep(Expr *E) { @@ -121,6 +121,18 @@ inline Expr *IgnoreImplicitSingleStep(Expr *E) { return E; } +inline Expr *IgnoreElidableImplicitConstructorSingleStep(Expr *E) { + auto *CCE = dyn_cast(E); + if (CCE && CCE->isElidable() && !isa(CCE)) { + unsigned NumArgs = CCE->getNumArgs(); + if ((NumArgs == 1 || + (NumArgs > 1 && CCE->getArg(1)->isDefaultArgument())) && + !CCE->getArg(0)->isDefaultArgument() && !CCE->isListInitialization()) + return CCE->getArg(0); + } + return E; +} + inline Expr *IgnoreImplicitAsWrittenSingleStep(Expr *E) { if (auto *ICE = dyn_cast(E)) return ICE->getSubExprAsWritten(); diff --git a/clang/include/clang/AST/TemplateBase.h b/clang/include/clang/AST/TemplateBase.h index 1671637521e2..19f2cadc1f2b 100644 --- a/clang/include/clang/AST/TemplateBase.h +++ b/clang/include/clang/AST/TemplateBase.h @@ -512,7 +512,8 @@ class TemplateArgumentLoc { } TypeSourceInfo *getTypeSourceInfo() const { - assert(Argument.getKind() == TemplateArgument::Type); + if (Argument.getKind() != TemplateArgument::Type) + return nullptr; return LocInfo.getAsTypeSourceInfo(); } diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 66eb9a3fdb10..0cfd072825ab 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -1615,6 +1615,12 @@ def NoMerge : DeclOrStmtAttr { let SimpleHandler = 1; } +def MustTail : StmtAttr { + let Spellings = [Clang<"musttail">]; + let Documentation = [MustTailDocs]; + let Subjects = SubjectList<[ReturnStmt], ErrorDiag, "return statements">; +} + def FastCall : DeclOrTypeAttr { let Spellings = [GCC<"fastcall">, Keyword<"__fastcall">, Keyword<"_fastcall">]; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 73cd65eb7aa4..2a64d5822cba 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -467,6 +467,32 @@ calls. }]; } +def MustTailDocs : Documentation { + let Category = DocCatStmt; + let Content = [{ +If a ``return`` statement is marked ``musttail``, this indicates that the +compiler must generate a tail call for the program to be correct, even when +optimizations are disabled. This guarantees that the call will not cause +unbounded stack growth if it is part of a recursive cycle in the call graph. + +If the callee is a virtual function that is implemented by a thunk, there is +no guarantee in general that the thunk tail-calls the implementation of the +virtual function, so such a call in a recursive cycle can still result in +unbounded stack growth. + +``clang::musttail`` can only be applied to a ``return`` statement whose value +is the result of a function call (even functions returning void must use +``return``, although no value is returned). The target function must have the +same number of arguments as the caller. The types of the return value and all +arguments must be similar according to C++ rules (differing only in cv +qualifiers or array size), including the implicit "this" argument, if any. +Any variables in scope, including all arguments to the function and the +return value must be trivially destructible. The calling convention of the +caller and callee must match, and they must not be variadic functions or have +old style K&R C function declarations. + }]; +} + def AssertCapabilityDocs : Documentation { let Category = DocCatFunction; let Heading = "assert_capability, assert_shared_capability"; diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def index 3f8b050aabfd..bc0c37a11207 100644 --- a/clang/include/clang/Basic/BuiltinsWebAssembly.def +++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def @@ -191,13 +191,6 @@ TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16UcV8UsV8Us", "nc", "simd TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128") TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4UiV4Ui", "nc", "simd128") -TARGET_BUILTIN(__builtin_wasm_extend_low_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128") -TARGET_BUILTIN(__builtin_wasm_extend_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128") -TARGET_BUILTIN(__builtin_wasm_extend_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128") -TARGET_BUILTIN(__builtin_wasm_extend_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128") - -TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc", "simd128") -TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc", "simd128") TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128") TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128") TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc", "simd128") diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 81991931d174..6458d6632861 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -591,11 +591,13 @@ def SwiftNameAttribute : DiagGroup<"swift-name-attribute">; def IntInBoolContext : DiagGroup<"int-in-bool-context">; def TautologicalTypeLimitCompare : DiagGroup<"tautological-type-limit-compare">; def TautologicalUnsignedZeroCompare : DiagGroup<"tautological-unsigned-zero-compare">; +def TautologicalUnsignedCharZeroCompare : DiagGroup<"tautological-unsigned-char-zero-compare">; def TautologicalUnsignedEnumZeroCompare : DiagGroup<"tautological-unsigned-enum-zero-compare">; // For compatibility with GCC. Tautological comparison warnings for constants // that are an extremal value of the type. def TypeLimits : DiagGroup<"type-limits", [TautologicalTypeLimitCompare, TautologicalUnsignedZeroCompare, + TautologicalUnsignedCharZeroCompare, TautologicalUnsignedEnumZeroCompare]>; // Additional tautological comparison warnings based on the expression, not // only on its type. diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index b0f9b317a020..8b3da909dd11 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -684,8 +684,6 @@ def err_attribute_requires_arguments : Error< "parentheses must be omitted if %0 attribute's argument list is empty">; def err_cxx11_attribute_forbids_ellipsis : Error< "attribute %0 cannot be used as an attribute pack">; -def err_cxx11_attribute_repeated : Error< - "attribute %0 cannot appear multiple times in an attribute specifier">; def warn_cxx14_compat_using_attribute_ns : Warning< "default scope specifier for attributes is incompatible with C++ standards " "before C++17">, InGroup, DefaultIgnore; diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 20d9b7a3c287..9c460c0e6046 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -326,9 +326,10 @@ def err_anyx86_interrupt_attribute : Error< "a pointer as the first parameter|a %2 type as the second parameter}1">; def err_anyx86_interrupt_called : Error< "interrupt service routine cannot be called directly">; -def err_anyx86_interrupt_regsave : Error< - "interrupt service routine may only call a function" - " with attribute 'no_caller_saved_registers'">; +def warn_anyx86_interrupt_regsave : Warning< + "interrupt service routine should only call a function" + " with attribute 'no_caller_saved_registers'">, + InGroup>; def warn_arm_interrupt_calling_convention : Warning< "call to function without interrupt attribute could clobber interruptee's VFP registers">, InGroup; @@ -2856,6 +2857,53 @@ def warn_nomerge_attribute_ignored_in_stmt: Warning< "%0 attribute is ignored because there exists no call expression inside the " "statement">, InGroup; + +def err_musttail_needs_trivial_args : Error< + "tail call requires that the return value, all parameters, and any " + "temporaries created by the expression are trivially destructible">; +def err_musttail_needs_call : Error< + "%0 attribute requires that the return value is the result of a function call" + >; +def err_musttail_needs_prototype : Error< + "%0 attribute requires that both caller and callee functions have a " + "prototype">; +def note_musttail_fix_non_prototype : Note< + "add 'void' to the parameter list to turn an old-style K&R function " + "declaration into a prototype">; +def err_musttail_structors_forbidden : Error<"cannot perform a tail call " + "%select{from|to}0 a %select{constructor|destructor}1">; +def note_musttail_structors_forbidden : Note<"target " + "%select{constructor|destructor}0 is declared here">; +def err_musttail_forbidden_from_this_context : Error< + "%0 attribute cannot be used from " + "%select{a block|an Objective-C function|this context}1">; +def err_musttail_member_mismatch : Error< + "%select{non-member|static member|non-static member}0 " + "function cannot perform a tail call to " + "%select{non-member|static member|non-static member|pointer-to-member}1 " + "function%select{| %3}2">; +def note_musttail_callee_defined_here : Note<"%0 declared here">; +def note_tail_call_required : Note<"tail call required by %0 attribute here">; +def err_musttail_mismatch : Error< + "cannot perform a tail call to function%select{| %1}0 because its signature " + "is incompatible with the calling function">; +def note_musttail_mismatch : Note< + "target function " + "%select{is a member of different class%diff{ (expected $ but has $)|}1,2" + "|has different number of parameters (expected %1 but has %2)" + "|has type mismatch at %ordinal3 parameter" + "%diff{ (expected $ but has $)|}1,2" + "|has different return type%diff{ ($ expected but has $)|}1,2}0">; +def err_musttail_callconv_mismatch : Error< + "cannot perform a tail call to function%select{| %1}0 because it uses an " + "incompatible calling convention">; +def note_musttail_callconv_mismatch : Note< + "target function has calling convention %1 (expected %0)">; +def err_musttail_scope : Error< + "cannot perform a tail call from this return statement">; +def err_musttail_no_variadic : Error< + "%0 attribute may not be used with variadic functions">; + def err_nsobject_attribute : Error< "'NSObject' attribute is for pointer types only">; def err_attributes_are_not_compatible : Error< @@ -6826,6 +6874,10 @@ def warn_unsigned_always_true_comparison : Warning< "result of comparison of %select{%3|unsigned expression}0 %2 " "%select{unsigned expression|%3}0 is always %4">, InGroup, DefaultIgnore; +def warn_unsigned_char_always_true_comparison : Warning< + "result of comparison of %select{%3|char expression}0 %2 " + "%select{char expression|%3}0 is always %4, since char is interpreted as " + "unsigned">, InGroup, DefaultIgnore; def warn_unsigned_enum_always_true_comparison : Warning< "result of comparison of %select{%3|unsigned enum expression}0 %2 " "%select{unsigned enum expression|%3}0 is always %4">, diff --git a/clang/include/clang/Basic/OpenCLOptions.h b/clang/include/clang/Basic/OpenCLOptions.h index 9ad3a5681054..703b5ac48094 100644 --- a/clang/include/clang/Basic/OpenCLOptions.h +++ b/clang/include/clang/Basic/OpenCLOptions.h @@ -51,10 +51,10 @@ static inline OpenCLVersionID encodeOpenCLVersion(unsigned OpenCLVersion) { } } -// Simple helper to check if OpenCL C version is contained in a given encoded -// OpenCL C version mask -static inline bool isOpenCLVersionIsContainedInMask(const LangOptions &LO, - unsigned Mask) { +// Check if OpenCL C version is contained in a given encoded OpenCL C version +// mask. +static inline bool isOpenCLVersionContainedInMask(const LangOptions &LO, + unsigned Mask) { auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion; OpenCLVersionID Code = encodeOpenCLVersion(CLVer); return Mask & Code; @@ -101,12 +101,12 @@ class OpenCLOptions { // Is core option in OpenCL version \p LO. bool isCoreIn(const LangOptions &LO) const { - return isAvailableIn(LO) && isOpenCLVersionIsContainedInMask(LO, Core); + return isAvailableIn(LO) && isOpenCLVersionContainedInMask(LO, Core); } // Is optional core option in OpenCL version \p LO. bool isOptionalCoreIn(const LangOptions &LO) const { - return isAvailableIn(LO) && isOpenCLVersionIsContainedInMask(LO, Opt); + return isAvailableIn(LO) && isOpenCLVersionContainedInMask(LO, Opt); } }; diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 3ddb706dcf52..3bcaaceb63d8 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1130,6 +1130,15 @@ class TargetInfo : public virtual TransferrableTargetInfo, getTriple().isWindowsItaniumEnvironment() || getTriple().isPS4CPU(); } + // Does this target have PS4 specific dllimport/export handling? + virtual bool hasPS4DLLImportExport() const { + return getTriple().isPS4CPU() || + // Windows Itanium support allows for testing the SCEI flavour of + // dllimport/export handling on a Windows system. + (getTriple().isWindowsItaniumEnvironment() && + getTriple().getVendor() == llvm::Triple::SCEI); + } + /// An optional hook that targets can implement to perform semantic /// checking on attribute((section("foo"))) specifiers. /// diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index a073a8bab28e..5e9d1c96558b 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -2073,7 +2073,7 @@ def SVSM4E : SInst<"svsm4e[_{d}]", "ddd", "Ui", MergeNone, "aarch64_sve_sm def SVSM4EKEY : SInst<"svsm4ekey[_{d}]", "ddd", "Ui", MergeNone, "aarch64_sve_sm4ekey", [IsOverloadNone]>; } -let ArchGuard = "__ARM_FEATURE_SVE2_BITPERM" in { +let ArchGuard = "defined (__ARM_FEATURE_SVE2_BITPERM)" in { def SVBDEP : SInst<"svbdep[_{d}]", "ddd", "UcUsUiUl", MergeNone, "aarch64_sve_bdep_x">; def SVBDEP_N : SInst<"svbdep[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64_sve_bdep_x">; def SVBEXT : SInst<"svbext[_{d}]", "ddd", "UcUsUiUl", MergeNone, "aarch64_sve_bext_x">; diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index f684580190b6..2d94f111d8e3 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -92,6 +92,17 @@ // (SEW=16, LMUL=4) and Log2EEW is 3 (EEW=8), and then equivalent vector // type is __rvv_uint8m2_t (elmul=(8/16)*4 = 2). Ignore to define a new // builtins if its equivalent type has illegal lmul. +// (FixedSEW:Value): Given a vector type (SEW and LMUL), and computes another +// vector type which only changed SEW as given value. Ignore to define a new +// builtin if its equivalent type has illegal lmul or the SEW does not changed. +// (SFixedLog2LMUL:Value): Smaller Fixed Log2LMUL. Given a vector type (SEW +// and LMUL), and computes another vector type which only changed LMUL as +// given value. The new LMUL should be smaller than the old one. Ignore to +// define a new builtin if its equivalent type has illegal lmul. +// (LFixedLog2LMUL:Value): Larger Fixed Log2LMUL. Given a vector type (SEW +// and LMUL), and computes another vector type which only changed LMUL as +// given value. The new LMUL should be larger than the old one. Ignore to +// define a new builtin if its equivalent type has illegal lmul. // // Following with the example above, if t is "i", then "Ue" will yield unsigned // int and "Fv" will yield __rvv_float32m1_t (again assuming LMUL=1), Fw would @@ -246,6 +257,10 @@ multiclass RVVOutBuiltinSet> suffixes_prototypes> : RVVBuiltinSet; +multiclass RVVOp0BuiltinSet> suffixes_prototypes> + : RVVBuiltinSet; + // IntrinsicTypes is output, op1 [-1, 1] multiclass RVVOutOp1BuiltinSet> suffixes_prototypes> @@ -983,7 +998,18 @@ let HasMask = false, PermuteOperands = [2, 0, 1] in { } // 12.16. Vector Integer Move Instructions -// TODO +let HasMask = false in { + let MangledName = "vmv_v" in { + defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil", + [["v", "Uv", "UvUv"]]>; + defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd", + [["v", "v", "vv"]]>; + } + let HasNoMaskedOverloaded = false in + defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil", + [["x", "v", "ve"], + ["x", "Uv", "UvUe"]]>; +} // 13. Vector Fixed-Point Arithmetic Instructions // 13.1. Vector Single-Width Saturating Add and Subtract @@ -1091,7 +1117,9 @@ let HasMask = false, PermuteOperands = [2, 0, 1] in { } // 14.16. Vector Floating-Point Move Instruction -// TODO +let HasMask = false, HasNoMaskedOverloaded = false in + defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "fd", + [["f", "v", "ve"]]>; // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">; @@ -1194,10 +1222,27 @@ let HasNoMaskedOverloaded = false in { // 17. Vector Permutation Instructions // 17.1. Integer Scalar Move Instructions -// TODO +let HasMask = false in { + let HasVL = false, MangledName = "vmv_x" in + defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil", + [["s", "ve", "ev"], + ["s", "UvUe", "UeUv"]]>; + let MangledName = "vmv_s" in + defm vmv_s : RVVOutBuiltinSet<"vmv_s_x", "csil", + [["x", "v", "vve"], + ["x", "Uv", "UvUvUe"]]>; +} // 17.2. Floating-Point Scalar Move Instructions -// TODO +let HasMask = false in { + let HasVL = false, MangledName = "vfmv_f" in + defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "fd", + [["s", "ve", "ev"]]>; + let MangledName = "vfmv_s" in + defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "fd", + [["f", "v", "vve"], + ["x", "Uv", "UvUvUe"]]>; +} // 17.3. Vector Slide Instructions // 17.3.1. Vector Slideup Instructions @@ -1238,3 +1283,69 @@ let HasMask = false, PermuteOperands = [2, 0, 1] in { defm vcompress : RVVOutBuiltinSet<"vcompress", "csil", [["vm", "Uv", "UvUvUvm"]]>; } + +// Miscellaneous +let HasMask = false, HasVL = false, HasNoMaskedOverloaded = false, + IRName = "" in { + let Name = "vreinterpret_v", + ManualCodegen = [{ + return Builder.CreateBitCast(Ops[0], ResultType); + }] in { + // Reinterpret between different type under the same SEW and LMUL + def vreinterpret_i_u : RVVBuiltin<"Uvv", "vUv", "csil">; + def vreinterpret_i_f : RVVBuiltin<"Fvv", "vFv", "il">; + def vreinterpret_u_i : RVVBuiltin<"vUv", "Uvv", "csil">; + def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "il">; + def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "il">; + def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "il">; + + // Reinterpret between different SEW under the same LMUL + foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)", + "(FixedSEW:64)"] in { + def vreinterpret_i_ # dst_sew : RVVBuiltin<"v" # dst_sew # "v", dst_sew # "vv", "csil">; + def vreinterpret_u_ # dst_sew : RVVBuiltin<"Uv" # dst_sew # "Uv", dst_sew # "UvUv", "csil">; + } + } + + let Name = "vundefined", + ManualCodegen = [{ + return llvm::UndefValue::get(ResultType); + }] in { + def vundefined : RVVBuiltin<"v", "v", "csilfd">; + def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">; + } + + // LMUL truncation + // C/C++ Operand: VecTy, IR Operand: VecTy, Index + let Name = "vlmul_trunc_v", + ManualCodegen = [{ { + ID = Intrinsic::experimental_vector_extract; + IntrinsicTypes = {ResultType, Ops[0]->getType()}; + Ops.push_back(ConstantInt::get(Int64Ty, 0)); + return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); + } }] in { + foreach dst_lmul = ["(SFixedLog2LMUL:-3)", "(SFixedLog2LMUL:-2)", "(SFixedLog2LMUL:-1)", + "(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { + def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vv", "csilfd">; + def vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUv", "csil">; + } + } + + // LMUL extension + // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index + let Name = "vlmul_ext_v", + ManualCodegen = [{ + ID = Intrinsic::experimental_vector_insert; + IntrinsicTypes = {ResultType, Ops[0]->getType()}; + Ops.push_back(llvm::UndefValue::get(ResultType)); + std::swap(Ops[0], Ops[1]); + Ops.push_back(ConstantInt::get(Int64Ty, 0)); + return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); + }] in { + foreach dst_lmul = ["(LFixedLog2LMUL:-2)", "(LFixedLog2LMUL:-1)", "(LFixedLog2LMUL:-0)", + "(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { + def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vv", "csilfd">; + def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUv", "csil">; + } + } +} diff --git a/clang/include/clang/CodeGen/CGFunctionInfo.h b/clang/include/clang/CodeGen/CGFunctionInfo.h index 253ef946ce15..91d867e7f64a 100644 --- a/clang/include/clang/CodeGen/CGFunctionInfo.h +++ b/clang/include/clang/CodeGen/CGFunctionInfo.h @@ -94,12 +94,17 @@ class ABIArgInfo { llvm::Type *UnpaddedCoerceAndExpandType; // isCoerceAndExpand() }; union { - unsigned DirectOffset; // isDirect() || isExtend() - unsigned IndirectAlign; // isIndirect() + struct { + unsigned Offset; + unsigned Align; + } DirectAttr; // isDirect() || isExtend() + struct { + unsigned Align; + unsigned AddrSpace; + } IndirectAttr; // isIndirect() unsigned AllocaFieldIndex; // isInAlloca() }; Kind TheKind; - unsigned IndirectAddrSpace : 24; // isIndirect() bool PaddingInReg : 1; bool InAllocaSRet : 1; // isInAlloca() bool InAllocaIndirect : 1;// isInAlloca() @@ -126,19 +131,20 @@ class ABIArgInfo { public: ABIArgInfo(Kind K = Direct) - : TypeData(nullptr), PaddingType(nullptr), DirectOffset(0), TheKind(K), - IndirectAddrSpace(0), PaddingInReg(false), InAllocaSRet(false), + : TypeData(nullptr), PaddingType(nullptr), DirectAttr{0, 0}, TheKind(K), + PaddingInReg(false), InAllocaSRet(false), InAllocaIndirect(false), IndirectByVal(false), IndirectRealign(false), SRetAfterThis(false), InReg(false), CanBeFlattened(false), SignExt(false) {} static ABIArgInfo getDirect(llvm::Type *T = nullptr, unsigned Offset = 0, llvm::Type *Padding = nullptr, - bool CanBeFlattened = true) { + bool CanBeFlattened = true, unsigned Align = 0) { auto AI = ABIArgInfo(Direct); AI.setCoerceToType(T); AI.setPaddingType(Padding); AI.setDirectOffset(Offset); + AI.setDirectAlign(Align); AI.setCanBeFlattened(CanBeFlattened); return AI; } @@ -154,6 +160,7 @@ class ABIArgInfo { AI.setCoerceToType(T); AI.setPaddingType(nullptr); AI.setDirectOffset(0); + AI.setDirectAlign(0); AI.setSignExt(true); return AI; } @@ -164,6 +171,7 @@ class ABIArgInfo { AI.setCoerceToType(T); AI.setPaddingType(nullptr); AI.setDirectOffset(0); + AI.setDirectAlign(0); AI.setSignExt(false); return AI; } @@ -299,11 +307,20 @@ class ABIArgInfo { // Direct/Extend accessors unsigned getDirectOffset() const { assert((isDirect() || isExtend()) && "Not a direct or extend kind"); - return DirectOffset; + return DirectAttr.Offset; } void setDirectOffset(unsigned Offset) { assert((isDirect() || isExtend()) && "Not a direct or extend kind"); - DirectOffset = Offset; + DirectAttr.Offset = Offset; + } + + unsigned getDirectAlign() const { + assert((isDirect() || isExtend()) && "Not a direct or extend kind"); + return DirectAttr.Align; + } + void setDirectAlign(unsigned Align) { + assert((isDirect() || isExtend()) && "Not a direct or extend kind"); + DirectAttr.Align = Align; } bool isSignExt() const { @@ -369,11 +386,11 @@ class ABIArgInfo { // Indirect accessors CharUnits getIndirectAlign() const { assert((isIndirect() || isIndirectAliased()) && "Invalid kind!"); - return CharUnits::fromQuantity(IndirectAlign); + return CharUnits::fromQuantity(IndirectAttr.Align); } void setIndirectAlign(CharUnits IA) { assert((isIndirect() || isIndirectAliased()) && "Invalid kind!"); - IndirectAlign = IA.getQuantity(); + IndirectAttr.Align = IA.getQuantity(); } bool getIndirectByVal() const { @@ -387,12 +404,12 @@ class ABIArgInfo { unsigned getIndirectAddrSpace() const { assert(isIndirectAliased() && "Invalid kind!"); - return IndirectAddrSpace; + return IndirectAttr.AddrSpace; } void setIndirectAddrSpace(unsigned AddrSpace) { assert(isIndirectAliased() && "Invalid kind!"); - IndirectAddrSpace = AddrSpace; + IndirectAttr.AddrSpace = AddrSpace; } bool getIndirectRealign() const { diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 925d160ee841..816706931628 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5047,6 +5047,11 @@ def fdenormal_fp_math_f32_EQ : Joined<["-"], "fdenormal-fp-math-f32=">, def sys_header_deps : Flag<["-"], "sys-header-deps">, HelpText<"Include system headers in dependency output">, MarshallingInfoFlag>; +def show_skipped_includes : Flag<["-"], "show-skipped-includes">, + HelpText<"Show skipped includes in -H output.">, + DocBrief<[{#include files may be "skipped" due to include guard optimization + or #pragma once. This flag makes -H show also such includes.}]>, + MarshallingInfoFlag>; def module_file_deps : Flag<["-"], "module-file-deps">, HelpText<"Include module files in dependency output">, MarshallingInfoFlag>; diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index c560eff2afa2..104b9346cf52 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -1891,6 +1891,54 @@ struct FormatStyle { /// Disables formatting completely. bool DisableFormat; + /// Different styles for empty line after access modifiers. + /// ``EmptyLineBeforeAccessModifier`` configuration handles the number of + /// empty lines between two access modifiers. + enum EmptyLineAfterAccessModifierStyle : unsigned char { + /// Remove all empty lines after access modifiers. + /// \code + /// struct foo { + /// private: + /// int i; + /// protected: + /// int j; + /// /* comment */ + /// public: + /// foo() {} + /// private: + /// protected: + /// }; + /// \endcode + ELAAMS_Never, + /// Keep existing empty lines after access modifiers. + /// MaxEmptyLinesToKeep is applied instead. + ELAAMS_Leave, + /// Always add empty line after access modifiers if there are none. + /// MaxEmptyLinesToKeep is applied also. + /// \code + /// struct foo { + /// private: + // + /// int i; + /// protected: + // + /// int j; + /// /* comment */ + /// public: + // + /// foo() {} + /// private: + /// + /// protected: + // + /// }; + /// \endcode + ELAAMS_Always, + }; + + /// Defines in which cases to put empty line after access modifiers. + EmptyLineAfterAccessModifierStyle EmptyLineAfterAccessModifier; + /// Different styles for empty line before access modifiers. enum EmptyLineBeforeAccessModifierStyle : unsigned char { /// Remove all empty lines before access modifiers. @@ -3200,6 +3248,7 @@ struct FormatStyle { DeriveLineEnding == R.DeriveLineEnding && DerivePointerAlignment == R.DerivePointerAlignment && DisableFormat == R.DisableFormat && + EmptyLineAfterAccessModifier == R.EmptyLineAfterAccessModifier && EmptyLineBeforeAccessModifier == R.EmptyLineBeforeAccessModifier && ExperimentalAutoDetectBinPacking == R.ExperimentalAutoDetectBinPacking && diff --git a/clang/include/clang/Frontend/CompilerInvocation.h b/clang/include/clang/Frontend/CompilerInvocation.h index 05b7769f20ef..132a43a7def2 100644 --- a/clang/include/clang/Frontend/CompilerInvocation.h +++ b/clang/include/clang/Frontend/CompilerInvocation.h @@ -78,6 +78,9 @@ class CompilerInvocationBase { /// Options controlling the preprocessor (aside from \#include handling). std::shared_ptr PreprocessorOpts; + /// Options controlling the static analyzer. + AnalyzerOptionsRef AnalyzerOpts; + CompilerInvocationBase(); CompilerInvocationBase(const CompilerInvocationBase &X); CompilerInvocationBase &operator=(const CompilerInvocationBase &) = delete; @@ -110,6 +113,8 @@ class CompilerInvocationBase { const PreprocessorOptions &getPreprocessorOpts() const { return *PreprocessorOpts; } + + AnalyzerOptionsRef getAnalyzerOpts() const { return AnalyzerOpts; } }; /// Helper class for holding the data necessary to invoke the compiler. @@ -118,9 +123,6 @@ class CompilerInvocationBase { /// compiler, including data such as the include paths, the code generation /// options, the warning flags, and so on. class CompilerInvocation : public CompilerInvocationBase { - /// Options controlling the static analyzer. - AnalyzerOptionsRef AnalyzerOpts; - MigratorOptions MigratorOpts; /// Options controlling IRgen and the backend. @@ -139,8 +141,6 @@ class CompilerInvocation : public CompilerInvocationBase { PreprocessorOutputOptions PreprocessorOutputOpts; public: - CompilerInvocation() : AnalyzerOpts(new AnalyzerOptions()) {} - /// @name Utility Methods /// @{ @@ -203,8 +203,6 @@ class CompilerInvocation : public CompilerInvocationBase { /// @name Option Subgroups /// @{ - AnalyzerOptionsRef getAnalyzerOpts() const { return AnalyzerOpts; } - MigratorOptions &getMigratorOpts() { return MigratorOpts; } const MigratorOptions &getMigratorOpts() const { return MigratorOpts; } diff --git a/clang/include/clang/Frontend/DependencyOutputOptions.h b/clang/include/clang/Frontend/DependencyOutputOptions.h index 130b4a0230dd..fac18a458511 100644 --- a/clang/include/clang/Frontend/DependencyOutputOptions.h +++ b/clang/include/clang/Frontend/DependencyOutputOptions.h @@ -39,6 +39,10 @@ class DependencyOutputOptions { /// problems. unsigned AddMissingHeaderDeps : 1; ///< Add missing headers to dependency list unsigned IncludeModuleFiles : 1; ///< Include module file dependencies. + unsigned ShowSkippedHeaderIncludes : 1; ///< With ShowHeaderIncludes, show + /// also includes that were skipped + /// due to the "include guard + /// optimization" or #pragma once. /// Destination of cl.exe style /showIncludes info. ShowIncludesDestination ShowIncludesDest = ShowIncludesDestination::None; @@ -79,7 +83,8 @@ class DependencyOutputOptions { public: DependencyOutputOptions() : IncludeSystemHeaders(0), ShowHeaderIncludes(0), UsePhonyTargets(0), - AddMissingHeaderDeps(0), IncludeModuleFiles(0) {} + AddMissingHeaderDeps(0), IncludeModuleFiles(0), + ShowSkippedHeaderIncludes(0) {} }; } // end namespace clang diff --git a/clang/include/clang/Sema/ScopeInfo.h b/clang/include/clang/Sema/ScopeInfo.h index 8ec74cafeeca..98ed75acd9d2 100644 --- a/clang/include/clang/Sema/ScopeInfo.h +++ b/clang/include/clang/Sema/ScopeInfo.h @@ -118,6 +118,10 @@ class FunctionScopeInfo { /// Whether this function contains any indirect gotos. bool HasIndirectGoto : 1; + /// Whether this function contains any statement marked with + /// \c [[clang::musttail]]. + bool HasMustTail : 1; + /// Whether a statement was dropped because it was invalid. bool HasDroppedStmt : 1; @@ -370,14 +374,13 @@ class FunctionScopeInfo { public: FunctionScopeInfo(DiagnosticsEngine &Diag) : Kind(SK_Function), HasBranchProtectedScope(false), - HasBranchIntoScope(false), HasIndirectGoto(false), + HasBranchIntoScope(false), HasIndirectGoto(false), HasMustTail(false), HasDroppedStmt(false), HasOMPDeclareReductionCombiner(false), HasFallthroughStmt(false), UsesFPIntrin(false), - HasPotentialAvailabilityViolations(false), - ObjCShouldCallSuper(false), ObjCIsDesignatedInit(false), - ObjCWarnForNoDesignatedInitChain(false), ObjCIsSecondaryInit(false), - ObjCWarnForNoInitDelegation(false), NeedsCoroutineSuspends(true), - ErrorTrap(Diag) {} + HasPotentialAvailabilityViolations(false), ObjCShouldCallSuper(false), + ObjCIsDesignatedInit(false), ObjCWarnForNoDesignatedInitChain(false), + ObjCIsSecondaryInit(false), ObjCWarnForNoInitDelegation(false), + NeedsCoroutineSuspends(true), ErrorTrap(Diag) {} virtual ~FunctionScopeInfo(); @@ -423,6 +426,8 @@ class FunctionScopeInfo { HasIndirectGoto = true; } + void setHasMustTail() { HasMustTail = true; } + void setHasDroppedStmt() { HasDroppedStmt = true; } @@ -450,9 +455,8 @@ class FunctionScopeInfo { } bool NeedsScopeChecking() const { - return !HasDroppedStmt && - (HasIndirectGoto || - (HasBranchProtectedScope && HasBranchIntoScope)); + return !HasDroppedStmt && (HasIndirectGoto || HasMustTail || + (HasBranchProtectedScope && HasBranchIntoScope)); } // Add a block introduced in this function. diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index f1414c3af6e6..6f1712355cbb 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -2039,6 +2039,7 @@ class Sema final { void setFunctionHasBranchIntoScope(); void setFunctionHasBranchProtectedScope(); void setFunctionHasIndirectGoto(); + void setFunctionHasMustTail(); void PushCompoundScope(bool IsStmtExpr); void PopCompoundScope(); @@ -2791,6 +2792,9 @@ class Sema final { NamedDecl *HandleDeclarator(Scope *S, Declarator &D, MultiTemplateParamsArg TemplateParameterLists); + bool tryToFixVariablyModifiedVarType(TypeSourceInfo *&TInfo, + QualType &T, SourceLocation Loc, + unsigned FailedFoldDiagID); void RegisterLocallyScopedExternCDecl(NamedDecl *ND, Scope *S); bool DiagnoseClassNameShadow(DeclContext *DC, DeclarationNameInfo Info); bool diagnoseQualifiedDeclaration(CXXScopeSpec &SS, DeclContext *DC, @@ -11636,6 +11640,18 @@ class Sema final { /// function, issuing a diagnostic if not. void checkVariadicArgument(const Expr *E, VariadicCallType CT); + /// Check whether the given statement can have musttail applied to it, + /// issuing a diagnostic and returning false if not. In the success case, + /// the statement is rewritten to remove implicit nodes from the return + /// value. + bool checkAndRewriteMustTailAttr(Stmt *St, const Attr &MTA); + +private: + /// Check whether the given statement can have musttail applied to it, + /// issuing a diagnostic and returning false if not. + bool checkMustTailAttr(const Stmt *St, const Attr &MTA); + +public: /// Check to see if a given expression could have '.c_str()' called on it. bool hasCStrMethod(const Expr *E); diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h index 2358d2d66b30..99277e91ed06 100644 --- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h +++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h @@ -72,9 +72,6 @@ class SValBuilder { /// The width of the scalar type used for array indices. const unsigned ArrayIndexWidth; - virtual SVal evalCastFromNonLoc(NonLoc val, QualType castTy) = 0; - virtual SVal evalCastFromLoc(Loc val, QualType castTy) = 0; - SVal evalCastKind(UndefinedVal V, QualType CastTy, QualType OriginalTy); SVal evalCastKind(UnknownVal V, QualType CastTy, QualType OriginalTy); SVal evalCastKind(Loc V, QualType CastTy, QualType OriginalTy); @@ -97,11 +94,6 @@ class SValBuilder { SVal evalCastSubKind(nonloc::PointerToMember V, QualType CastTy, QualType OriginalTy); -public: - // FIXME: Make these protected again once RegionStoreManager correctly - // handles loads from different bound value types. - virtual SVal dispatchCast(SVal val, QualType castTy) = 0; - public: SValBuilder(llvm::BumpPtrAllocator &alloc, ASTContext &context, ProgramStateManager &stateMgr) diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h index c3b590e4784e..947913ae4eee 100644 --- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h +++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h @@ -280,12 +280,6 @@ class StoreManager { QualType pointeeTy, uint64_t index = 0); - /// CastRetrievedVal - Used by subclasses of StoreManager to implement - /// implicit casts that arise from loads from regions that are reinterpreted - /// as another region. - SVal CastRetrievedVal(SVal val, const TypedValueRegion *region, - QualType castTy); - private: SVal getLValueFieldOrIvar(const Decl *decl, SVal base); }; diff --git a/clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h b/clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h index b4fa27f531e3..09c385783c52 100644 --- a/clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h +++ b/clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h @@ -45,14 +45,14 @@ struct FullDependencies { /// appending to the original command line to pass to clang. std::vector AdditionalNonPathCommandLine; - /// Gets the full addtional command line suitable for appending to the - /// original command line to pass to clang. + /// Get additional arguments suitable for appending to the original Clang + /// command line. /// - /// \param LookupPCMPath this function is called to fill in `-fmodule-file=` + /// \param LookupPCMPath This function is called to fill in `-fmodule-file=` /// flags and for the `-o` flag. It needs to return a /// path for where the PCM for the given module is to /// be located. - /// \param LookupModuleDeps this fucntion is called to collect the full + /// \param LookupModuleDeps This function is called to collect the full /// transitive set of dependencies for this /// compilation. std::vector getAdditionalCommandLine( @@ -82,15 +82,14 @@ class DependencyScanningTool { getDependencyFile(const tooling::CompilationDatabase &Compilations, StringRef CWD); - /// Collect the full module depenedency graph for the input, ignoring any + /// Collect the full module dependency graph for the input, ignoring any /// modules which have already been seen. /// - /// \param AlreadySeen this is used to not report modules that have previously - /// been reported. Use the same `llvm::StringSet<>` for all - /// calls to `getFullDependencies` for a single - /// `DependencyScanningTool` for a single build. Use a - /// different one for different tools, and clear it between - /// builds. + /// \param AlreadySeen This stores modules which have previously been + /// reported. Use the same instance for all calls to this + /// function for a single \c DependencyScanningTool in a + /// single build. Use a different one for different tools, + /// and clear it between builds. /// /// \returns a \c StringError with the diagnostic output if clang errors /// occurred, \c FullDependencies otherwise. diff --git a/clang/include/clang/Tooling/NodeIntrospection.h b/clang/include/clang/Tooling/NodeIntrospection.h index 3b40e68df24e..5489a67efa22 100644 --- a/clang/include/clang/Tooling/NodeIntrospection.h +++ b/clang/include/clang/Tooling/NodeIntrospection.h @@ -15,62 +15,69 @@ #include "clang/AST/ASTTypeTraits.h" #include "clang/AST/DeclarationName.h" - -#include +#include "llvm/ADT/IntrusiveRefCntPtr.h" #include namespace clang { class Stmt; class Decl; +class CXXCtorInitializer; +class NestedNameSpecifierLoc; +class TemplateArgumentLoc; +class CXXBaseSpecifier; namespace tooling { -class LocationCall { +class LocationCall; +using SharedLocationCall = llvm::IntrusiveRefCntPtr; + +class LocationCall : public llvm::ThreadSafeRefCountedBase { public: enum LocationCallFlags { NoFlags, ReturnsPointer, IsCast }; - LocationCall(std::shared_ptr on, std::string name, - LocationCallFlags flags = NoFlags) - : m_on(on), m_name(name), m_flags(flags) {} - LocationCall(std::shared_ptr on, std::string name, - std::vector const &args, + LocationCall(SharedLocationCall on, std::string name, LocationCallFlags flags = NoFlags) - : m_on(on), m_name(name), m_flags(flags) {} + : m_flags(flags), m_on(std::move(on)), m_name(std::move(name)) {} + LocationCall(SharedLocationCall on, std::string name, + std::vector args, LocationCallFlags flags = NoFlags) + : m_flags(flags), m_on(std::move(on)), m_name(std::move(name)), + m_args(std::move(args)) {} LocationCall *on() const { return m_on.get(); } StringRef name() const { return m_name; } - std::vector const &args() const { return m_args; } + ArrayRef args() const { return m_args; } bool returnsPointer() const { return m_flags & ReturnsPointer; } bool isCast() const { return m_flags & IsCast; } private: - std::shared_ptr m_on; + LocationCallFlags m_flags; + SharedLocationCall m_on; std::string m_name; std::vector m_args; - LocationCallFlags m_flags; }; class LocationCallFormatterCpp { public: - static std::string format(LocationCall *Call); + static void print(const LocationCall &Call, llvm::raw_ostream &OS); + static std::string format(const LocationCall &Call); }; namespace internal { struct RangeLessThan { - bool operator()( - std::pair> const &LHS, - std::pair> const &RHS) const; + bool operator()(std::pair const &LHS, + std::pair const &RHS) const; + bool + operator()(std::pair const &LHS, + std::pair const &RHS) const; }; + } // namespace internal -template >> -using UniqueMultiMap = std::set, Comp>; +template +using UniqueMultiMap = std::set, internal::RangeLessThan>; -using SourceLocationMap = - UniqueMultiMap>; -using SourceRangeMap = - UniqueMultiMap, - internal::RangeLessThan>; +using SourceLocationMap = UniqueMultiMap; +using SourceRangeMap = UniqueMultiMap; struct NodeLocationAccessors { SourceLocationMap LocationAccessors; @@ -78,8 +85,13 @@ struct NodeLocationAccessors { }; namespace NodeIntrospection { +bool hasIntrospectionSupport(); NodeLocationAccessors GetLocations(clang::Stmt const *Object); NodeLocationAccessors GetLocations(clang::Decl const *Object); +NodeLocationAccessors GetLocations(clang::CXXCtorInitializer const *Object); +NodeLocationAccessors GetLocations(clang::NestedNameSpecifierLoc const *); +NodeLocationAccessors GetLocations(clang::TemplateArgumentLoc const *); +NodeLocationAccessors GetLocations(clang::CXXBaseSpecifier const *); NodeLocationAccessors GetLocations(clang::DynTypedNode const &Node); } // namespace NodeIntrospection } // namespace tooling diff --git a/clang/include/clang/Tooling/Refactoring/RecursiveSymbolVisitor.h b/clang/include/clang/Tooling/Refactoring/RecursiveSymbolVisitor.h index c0f995d85c14..63d46abc2034 100644 --- a/clang/include/clang/Tooling/Refactoring/RecursiveSymbolVisitor.h +++ b/clang/include/clang/Tooling/Refactoring/RecursiveSymbolVisitor.h @@ -122,6 +122,17 @@ class RecursiveSymbolVisitor return BaseType::TraverseNestedNameSpecifierLoc(NNS); } + bool VisitDesignatedInitExpr(const DesignatedInitExpr *E) { + for (const DesignatedInitExpr::Designator &D : E->designators()) { + if (D.isFieldDesignator() && D.getField()) { + const FieldDecl *Decl = D.getField(); + if (!visit(Decl, D.getFieldLoc(), D.getFieldLoc())) + return false; + } + } + return true; + } + private: const SourceManager &SM; const LangOptions &LangOpts; diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 708d1ffe6b67..008ffd672f1e 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -10120,7 +10120,12 @@ QualType ASTContext::getCorrespondingUnsignedType(QualType T) const { return getVectorType(getCorrespondingUnsignedType(VTy->getElementType()), VTy->getNumElements(), VTy->getVectorKind()); - // For enums, we return the unsigned version of the base type. + // For _ExtInt, return an unsigned _ExtInt with same width. + if (const auto *EITy = T->getAs()) + return getExtIntType(/*IsUnsigned=*/true, EITy->getNumBits()); + + // For enums, get the underlying integer type of the enum, and let the general + // integer type signchanging code handle it. if (const auto *ETy = T->getAs()) T = ETy->getDecl()->getIntegerType(); @@ -10173,6 +10178,74 @@ QualType ASTContext::getCorrespondingUnsignedType(QualType T) const { } } +QualType ASTContext::getCorrespondingSignedType(QualType T) const { + assert((T->hasUnsignedIntegerRepresentation() || + T->isUnsignedFixedPointType()) && + "Unexpected type"); + + // Turn <4 x unsigned int> -> <4 x signed int> + if (const auto *VTy = T->getAs()) + return getVectorType(getCorrespondingSignedType(VTy->getElementType()), + VTy->getNumElements(), VTy->getVectorKind()); + + // For _ExtInt, return a signed _ExtInt with same width. + if (const auto *EITy = T->getAs()) + return getExtIntType(/*IsUnsigned=*/false, EITy->getNumBits()); + + // For enums, get the underlying integer type of the enum, and let the general + // integer type signchanging code handle it. + if (const auto *ETy = T->getAs()) + T = ETy->getDecl()->getIntegerType(); + + switch (T->castAs()->getKind()) { + case BuiltinType::Char_U: + case BuiltinType::UChar: + return SignedCharTy; + case BuiltinType::UShort: + return ShortTy; + case BuiltinType::UInt: + return IntTy; + case BuiltinType::ULong: + return LongTy; + case BuiltinType::ULongLong: + return LongLongTy; + case BuiltinType::UInt128: + return Int128Ty; + // wchar_t is special. It is either unsigned or not, but when it's unsigned, + // there's no matching "signed wchar_t". Therefore we return the signed + // version of it's underlying type instead. + case BuiltinType::WChar_U: + return getSignedWCharType(); + + case BuiltinType::UShortAccum: + return ShortAccumTy; + case BuiltinType::UAccum: + return AccumTy; + case BuiltinType::ULongAccum: + return LongAccumTy; + case BuiltinType::SatUShortAccum: + return SatShortAccumTy; + case BuiltinType::SatUAccum: + return SatAccumTy; + case BuiltinType::SatULongAccum: + return SatLongAccumTy; + case BuiltinType::UShortFract: + return ShortFractTy; + case BuiltinType::UFract: + return FractTy; + case BuiltinType::ULongFract: + return LongFractTy; + case BuiltinType::SatUShortFract: + return SatShortFractTy; + case BuiltinType::SatUFract: + return SatFractTy; + case BuiltinType::SatULongFract: + return SatLongFractTy; + default: + llvm_unreachable("Unexpected unsigned integer or fixed point type"); + } +} + ASTMutationListener::~ASTMutationListener() = default; void ASTMutationListener::DeducedReturnType(const FunctionDecl *FD, diff --git a/clang/lib/AST/RecordLayoutBuilder.cpp b/clang/lib/AST/RecordLayoutBuilder.cpp index 561bb0e96a5a..cd56811b81b5 100644 --- a/clang/lib/AST/RecordLayoutBuilder.cpp +++ b/clang/lib/AST/RecordLayoutBuilder.cpp @@ -2293,7 +2293,8 @@ static const CXXMethodDecl *computeKeyFunction(ASTContext &Context, // If the key function is dllimport but the class isn't, then the class has // no key function. The DLL that exports the key function won't export the // vtable in this case. - if (MD->hasAttr() && !RD->hasAttr()) + if (MD->hasAttr() && !RD->hasAttr() && + !Context.getTargetInfo().hasPS4DLLImportExport()) return nullptr; // We found it. diff --git a/clang/lib/Basic/FileManager.cpp b/clang/lib/Basic/FileManager.cpp index 6e9d5d7fb422..d39d7ba22643 100644 --- a/clang/lib/Basic/FileManager.cpp +++ b/clang/lib/Basic/FileManager.cpp @@ -384,9 +384,12 @@ FileEntryRef FileManager::getVirtualFileRef(StringRef Filename, off_t Size, // Now that all ancestors of Filename are in the cache, the // following call is guaranteed to find the DirectoryEntry from the - // cache. - auto DirInfo = expectedToOptional( - getDirectoryFromFile(*this, Filename, /*CacheFailure=*/true)); + // cache. A virtual file can also have an empty filename, that could come + // from a source location preprocessor directive with an empty filename as + // an example, so we need to pretend it has a name to ensure a valid directory + // entry can be returned. + auto DirInfo = expectedToOptional(getDirectoryFromFile( + *this, Filename.empty() ? "." : Filename, /*CacheFailure=*/true)); assert(DirInfo && "The directory of a virtual file should already be in the cache."); diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp index e10fd77d2590..8e8a69f75c8b 100644 --- a/clang/lib/Basic/Targets/M68k.cpp +++ b/clang/lib/Basic/Targets/M68k.cpp @@ -159,9 +159,8 @@ const char *M68kTargetInfo::getClobbers() const { return ""; } -M68kTargetInfo::BuiltinVaListKind M68kTargetInfo::getBuiltinVaListKind() const { - // FIXME: implement - llvm_unreachable("Not implemented yet"); +TargetInfo::BuiltinVaListKind M68kTargetInfo::getBuiltinVaListKind() const { + return TargetInfo::VoidPtrBuiltinVaList; } } // namespace targets diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 694a8095e336..75d4aa77ab6e 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -467,6 +467,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_Cooperlake: case CK_Cannonlake: case CK_IcelakeClient: + case CK_Rocketlake: case CK_IcelakeServer: case CK_Tigerlake: case CK_SapphireRapids: @@ -1314,6 +1315,7 @@ Optional X86TargetInfo::getCPUCacheLineSize() const { case CK_Tigerlake: case CK_SapphireRapids: case CK_IcelakeClient: + case CK_Rocketlake: case CK_IcelakeServer: case CK_Alderlake: case CK_KNL: diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ccb36658d4db..d60aaf6db9c2 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -17142,19 +17142,19 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, switch (BuiltinID) { case WebAssembly::BI__builtin_wasm_ceil_f32x4: case WebAssembly::BI__builtin_wasm_ceil_f64x2: - IntNo = Intrinsic::wasm_ceil; + IntNo = Intrinsic::ceil; break; case WebAssembly::BI__builtin_wasm_floor_f32x4: case WebAssembly::BI__builtin_wasm_floor_f64x2: - IntNo = Intrinsic::wasm_floor; + IntNo = Intrinsic::floor; break; case WebAssembly::BI__builtin_wasm_trunc_f32x4: case WebAssembly::BI__builtin_wasm_trunc_f64x2: - IntNo = Intrinsic::wasm_trunc; + IntNo = Intrinsic::trunc; break; case WebAssembly::BI__builtin_wasm_nearest_f32x4: case WebAssembly::BI__builtin_wasm_nearest_f64x2: - IntNo = Intrinsic::wasm_nearest; + IntNo = Intrinsic::nearbyint; break; default: llvm_unreachable("unexpected builtin ID"); @@ -17481,48 +17481,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, CGM.getIntrinsic(IntNo, {ConvertType(E->getType()), Low->getType()}); return Builder.CreateCall(Callee, {Low, High}); } - case WebAssembly::BI__builtin_wasm_extend_low_s_i32x4_i64x2: - case WebAssembly::BI__builtin_wasm_extend_high_s_i32x4_i64x2: - case WebAssembly::BI__builtin_wasm_extend_low_u_i32x4_i64x2: - case WebAssembly::BI__builtin_wasm_extend_high_u_i32x4_i64x2: { - Value *Vec = EmitScalarExpr(E->getArg(0)); - unsigned IntNo; - switch (BuiltinID) { - case WebAssembly::BI__builtin_wasm_extend_low_s_i32x4_i64x2: - IntNo = Intrinsic::wasm_extend_low_signed; - break; - case WebAssembly::BI__builtin_wasm_extend_high_s_i32x4_i64x2: - IntNo = Intrinsic::wasm_extend_high_signed; - break; - case WebAssembly::BI__builtin_wasm_extend_low_u_i32x4_i64x2: - IntNo = Intrinsic::wasm_extend_low_unsigned; - break; - case WebAssembly::BI__builtin_wasm_extend_high_u_i32x4_i64x2: - IntNo = Intrinsic::wasm_extend_high_unsigned; - break; - default: - llvm_unreachable("unexpected builtin ID"); - } - Function *Callee = CGM.getIntrinsic(IntNo); - return Builder.CreateCall(Callee, Vec); - } - case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2: - case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: { - Value *Vec = EmitScalarExpr(E->getArg(0)); - unsigned IntNo; - switch (BuiltinID) { - case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2: - IntNo = Intrinsic::wasm_convert_low_signed; - break; - case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: - IntNo = Intrinsic::wasm_convert_low_unsigned; - break; - default: - llvm_unreachable("unexpected builtin ID"); - } - Function *Callee = CGM.getIntrinsic(IntNo); - return Builder.CreateCall(Callee, Vec); - } case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4: case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4: { Value *Vec = EmitScalarExpr(E->getArg(0)); diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 49562adffdd9..e33e601d3366 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -2369,6 +2369,7 @@ void CodeGenModule::ConstructAttributeList( Attrs.addAttribute(llvm::Attribute::Nest); else if (AI.getInReg()) Attrs.addAttribute(llvm::Attribute::InReg); + Attrs.addStackAlignmentAttr(llvm::MaybeAlign(AI.getDirectAlign())); break; case ABIArgInfo::Indirect: { @@ -4569,7 +4570,7 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, const CGCallee &Callee, ReturnValueSlot ReturnValue, const CallArgList &CallArgs, - llvm::CallBase **callOrInvoke, + llvm::CallBase **callOrInvoke, bool IsMustTail, SourceLocation Loc) { // FIXME: We no longer need the types from CallArgs; lift up and simplify. @@ -5267,10 +5268,12 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, if (CGM.getLangOpts().ObjCAutoRefCount) AddObjCARCExceptionMetadata(CI); - // Suppress tail calls if requested. + // Set tail call kind if necessary. if (llvm::CallInst *Call = dyn_cast(CI)) { if (TargetDecl && TargetDecl->hasAttr()) Call->setTailCallKind(llvm::CallInst::TCK_NoTail); + else if (IsMustTail) + Call->setTailCallKind(llvm::CallInst::TCK_MustTail); } // Add metadata for calls to MSAllocator functions @@ -5333,6 +5336,24 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, return GetUndefRValue(RetTy); } + // If this is a musttail call, return immediately. We do not branch to the + // epilogue in this case. + if (IsMustTail) { + for (auto it = EHStack.find(CurrentCleanupScopeDepth); it != EHStack.end(); + ++it) { + EHCleanupScope *Cleanup = dyn_cast(&*it); + if (!(Cleanup && Cleanup->getCleanup()->isRedundantBeforeReturn())) + CGM.ErrorUnsupported(MustTailCall, "tail call skipping over cleanups"); + } + if (CI->getType()->isVoidTy()) + Builder.CreateRetVoid(); + else + Builder.CreateRet(CI); + Builder.ClearInsertionPoint(); + EnsureInsertPoint(); + return GetUndefRValue(RetTy); + } + // Perform the swifterror writeback. if (swiftErrorTemp.isValid()) { llvm::Value *errorResult = Builder.CreateLoad(swiftErrorTemp); diff --git a/clang/lib/CodeGen/CGClass.cpp b/clang/lib/CodeGen/CGClass.cpp index 7fcc84bc7a09..50681da6608d 100644 --- a/clang/lib/CodeGen/CGClass.cpp +++ b/clang/lib/CodeGen/CGClass.cpp @@ -2182,7 +2182,7 @@ void CodeGenFunction::EmitCXXConstructorCall(const CXXConstructorDecl *D, const CGFunctionInfo &Info = CGM.getTypes().arrangeCXXConstructorCall( Args, D, Type, ExtraArgs.Prefix, ExtraArgs.Suffix, PassPrototypeArgs); CGCallee Callee = CGCallee::forDirect(CalleePtr, GlobalDecl(D, Type)); - EmitCall(Info, Callee, ReturnValueSlot(), Args, nullptr, Loc); + EmitCall(Info, Callee, ReturnValueSlot(), Args, nullptr, false, Loc); // Generate vtable assumptions if we're constructing a complete object // with a vtable. We don't do this for base subobjects for two reasons: diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index e313cb4120ca..9e648c04722e 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -577,6 +577,7 @@ namespace { struct CallStackRestore final : EHScopeStack::Cleanup { Address Stack; CallStackRestore(Address Stack) : Stack(Stack) {} + bool isRedundantBeforeReturn() override { return true; } void Emit(CodeGenFunction &CGF, Flags flags) override { llvm::Value *V = CGF.Builder.CreateLoad(Stack); llvm::Function *F = CGF.CGM.getIntrinsic(llvm::Intrinsic::stackrestore); diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 6cc04523cbae..1a7cb27b3110 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -39,6 +39,7 @@ #include "llvm/Support/ConvertUTF.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Path.h" +#include "llvm/Support/SaveAndRestore.h" #include "llvm/Transforms/Utils/SanitizerStats.h" #include @@ -5323,7 +5324,7 @@ RValue CodeGenFunction::EmitCall(QualType CalleeType, const CGCallee &OrigCallee } llvm::CallBase *CallOrInvoke = nullptr; RValue Call = EmitCall(FnInfo, Callee, ReturnValue, Args, &CallOrInvoke, - E->getExprLoc()); + E == MustTailCall, E->getExprLoc()); // Generate function declaration DISuprogram in order to be used // in debug info about call sites. diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index b8608911edb2..96cf977ca290 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -87,6 +87,7 @@ RValue CodeGenFunction::EmitCXXMemberOrOperatorCall( auto &FnInfo = CGM.getTypes().arrangeCXXMethodCall( Args, FPT, CallInfo.ReqArgs, CallInfo.PrefixSize); return EmitCall(FnInfo, Callee, ReturnValue, Args, nullptr, + CE && CE == MustTailCall, CE ? CE->getExprLoc() : SourceLocation()); } @@ -112,7 +113,7 @@ RValue CodeGenFunction::EmitCXXDestructorCall( commonEmitCXXMemberOrOperatorCall(*this, DtorDecl, This, ImplicitParam, ImplicitParamTy, CE, Args, nullptr); return EmitCall(CGM.getTypes().arrangeCXXStructorDeclaration(Dtor), Callee, - ReturnValueSlot(), Args, nullptr, + ReturnValueSlot(), Args, nullptr, CE && CE == MustTailCall, CE ? CE->getExprLoc() : SourceLocation{}); } @@ -472,7 +473,8 @@ CodeGenFunction::EmitCXXMemberPointerCallExpr(const CXXMemberCallExpr *E, EmitCallArgs(Args, FPT, E->arguments()); return EmitCall(CGM.getTypes().arrangeCXXMethodCall(Args, FPT, required, /*PrefixSize=*/0), - Callee, ReturnValue, Args, nullptr, E->getExprLoc()); + Callee, ReturnValue, Args, nullptr, E == MustTailCall, + E->getExprLoc()); } RValue diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 37146989e252..18ad5066fbba 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -2279,6 +2279,35 @@ void CGOpenMPRuntime::emitMasterRegion(CodeGenFunction &CGF, Action.Done(CGF); } +void CGOpenMPRuntime::emitMaskedRegion(CodeGenFunction &CGF, + const RegionCodeGenTy &MaskedOpGen, + SourceLocation Loc, const Expr *Filter) { + if (!CGF.HaveInsertPoint()) + return; + // if(__kmpc_masked(ident_t *, gtid, filter)) { + // MaskedOpGen(); + // __kmpc_end_masked(iden_t *, gtid); + // } + // Prepare arguments and build a call to __kmpc_masked + llvm::Value *FilterVal = Filter + ? CGF.EmitScalarExpr(Filter, CGF.Int32Ty) + : llvm::ConstantInt::get(CGM.Int32Ty, /*V=*/0); + llvm::Value *Args[] = {emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc), + FilterVal}; + llvm::Value *ArgsEnd[] = {emitUpdateLocation(CGF, Loc), + getThreadID(CGF, Loc)}; + CommonActionTy Action(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_masked), + Args, + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_end_masked), + ArgsEnd, + /*Conditional=*/true); + MaskedOpGen.setAction(Action); + emitInlinedDirective(CGF, OMPD_masked, MaskedOpGen); + Action.Done(CGF); +} + void CGOpenMPRuntime::emitTaskyieldCall(CodeGenFunction &CGF, SourceLocation Loc) { if (!CGF.HaveInsertPoint()) @@ -6232,7 +6261,8 @@ void CGOpenMPRuntime::emitInlinedDirective(CodeGenFunction &CGF, return; InlinedOpenMPRegionRAII Region(CGF, CodeGen, InnerKind, HasCancel, InnerKind != OMPD_critical && - InnerKind != OMPD_master); + InnerKind != OMPD_master && + InnerKind != OMPD_masked); CGF.CapturedStmtInfo->EmitBody(CGF, /*S=*/nullptr); } @@ -12596,6 +12626,13 @@ void CGOpenMPSIMDRuntime::emitMasterRegion(CodeGenFunction &CGF, llvm_unreachable("Not supported in SIMD-only mode"); } +void CGOpenMPSIMDRuntime::emitMaskedRegion(CodeGenFunction &CGF, + const RegionCodeGenTy &MasterOpGen, + SourceLocation Loc, + const Expr *Filter) { + llvm_unreachable("Not supported in SIMD-only mode"); +} + void CGOpenMPSIMDRuntime::emitTaskyieldCall(CodeGenFunction &CGF, SourceLocation Loc) { llvm_unreachable("Not supported in SIMD-only mode"); diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h index 541904aa3988..c35202a51371 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -1012,6 +1012,14 @@ class CGOpenMPRuntime { const RegionCodeGenTy &MasterOpGen, SourceLocation Loc); + /// Emits a masked region. + /// \param MaskedOpGen Generator for the statement associated with the given + /// masked region. + virtual void emitMaskedRegion(CodeGenFunction &CGF, + const RegionCodeGenTy &MaskedOpGen, + SourceLocation Loc, + const Expr *Filter = nullptr); + /// Emits code for a taskyield directive. virtual void emitTaskyieldCall(CodeGenFunction &CGF, SourceLocation Loc); @@ -1984,6 +1992,17 @@ class CGOpenMPSIMDRuntime final : public CGOpenMPRuntime { const RegionCodeGenTy &MasterOpGen, SourceLocation Loc) override; + /// Emits a masked region. + /// \param MaskedOpGen Generator for the statement associated with the given + /// masked region. + void emitMaskedRegion(CodeGenFunction &CGF, + const RegionCodeGenTy &MaskedOpGen, SourceLocation Loc, + const Expr *Filter = nullptr) override; + + /// Emits a masked region. + /// \param MaskedOpGen Generator for the statement associated with the given + /// masked region. + /// Emits code for a taskyield directive. void emitTaskyieldCall(CodeGenFunction &CGF, SourceLocation Loc) override; diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp index daecb44abbd8..b6f4f98fbd2e 100644 --- a/clang/lib/CodeGen/CGStmt.cpp +++ b/clang/lib/CodeGen/CGStmt.cpp @@ -16,6 +16,8 @@ #include "CodeGenModule.h" #include "TargetInfo.h" #include "clang/AST/Attr.h" +#include "clang/AST/Expr.h" +#include "clang/AST/Stmt.h" #include "clang/AST/StmtVisitor.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/DiagnosticSema.h" @@ -382,7 +384,7 @@ void CodeGenFunction::EmitStmt(const Stmt *S, ArrayRef Attrs) { llvm_unreachable("Dispatch directive not supported yet."); break; case Stmt::OMPMaskedDirectiveClass: - llvm_unreachable("Masked directive not supported yet."); + EmitOMPMaskedDirective(cast(*S)); break; } } @@ -649,12 +651,20 @@ void CodeGenFunction::EmitLabelStmt(const LabelStmt &S) { void CodeGenFunction::EmitAttributedStmt(const AttributedStmt &S) { bool nomerge = false; - for (const auto *A : S.getAttrs()) + const CallExpr *musttail = nullptr; + + for (const auto *A : S.getAttrs()) { if (A->getKind() == attr::NoMerge) { nomerge = true; - break; } + if (A->getKind() == attr::MustTail) { + const Stmt *Sub = S.getSubStmt(); + const ReturnStmt *R = cast(Sub); + musttail = cast(R->getRetValue()->IgnoreParens()); + } + } SaveAndRestore save_nomerge(InNoMergeAttributedStmt, nomerge); + SaveAndRestore save_musttail(MustTailCall, musttail); EmitStmt(S.getSubStmt(), S.getAttrs()); } diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index 4b93fddab523..7d8744651a4e 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -241,11 +241,22 @@ class OMPSimdLexicalScope : public CodeGenFunction::LexicalScope { if (const Expr *E = TG->getReductionRef()) CGF.EmitVarDecl(*cast(cast(E)->getDecl())); } + // Temp copy arrays for inscan reductions should not be emitted as they are + // not used in simd only mode. + llvm::DenseSet> CopyArrayTemps; + for (const auto *C : S.getClausesOfKind()) { + if (C->getModifier() != OMPC_REDUCTION_inscan) + continue; + for (const Expr *E : C->copy_array_temps()) + CopyArrayTemps.insert(cast(E)->getDecl()); + } const auto *CS = cast_or_null(S.getAssociatedStmt()); while (CS) { for (auto &C : CS->captures()) { if (C.capturesVariable() || C.capturesVariableByCopy()) { auto *VD = C.getCapturedVar(); + if (CopyArrayTemps.contains(VD)) + continue; assert(VD == VD->getCanonicalDecl() && "Canonical decl must be captured."); DeclRefExpr DRE(CGF.getContext(), const_cast(VD), @@ -3295,53 +3306,30 @@ emitDispatchForLoopBounds(CodeGenFunction &CGF, const OMPExecutableDirective &S, return {LBVal, UBVal}; } -/// Emits the code for the directive with inscan reductions. +/// Emits internal temp array declarations for the directive with inscan +/// reductions. /// The code is the following: /// \code /// size num_iters = ; /// buffer[num_iters]; -/// #pragma omp ... -/// for (i: 0..) { -/// ; -/// buffer[i] = red; -/// } -/// for (int k = 0; k != ceil(log2(num_iters)); ++k) -/// for (size cnt = last_iter; cnt >= pow(2, k); --k) -/// buffer[i] op= buffer[i-pow(2,k)]; -/// #pragma omp ... -/// for (0..) { -/// red = InclusiveScan ? buffer[i] : buffer[i-1]; -/// ; -/// } /// \endcode -static void emitScanBasedDirective( +static void emitScanBasedDirectiveDecls( CodeGenFunction &CGF, const OMPLoopDirective &S, - llvm::function_ref NumIteratorsGen, - llvm::function_ref FirstGen, - llvm::function_ref SecondGen) { + llvm::function_ref NumIteratorsGen) { llvm::Value *OMPScanNumIterations = CGF.Builder.CreateIntCast( NumIteratorsGen(CGF), CGF.SizeTy, /*isSigned=*/false); SmallVector Shareds; SmallVector Privates; SmallVector ReductionOps; - SmallVector LHSs; - SmallVector RHSs; - SmallVector CopyOps; SmallVector CopyArrayTemps; - SmallVector CopyArrayElems; for (const auto *C : S.getClausesOfKind()) { assert(C->getModifier() == OMPC_REDUCTION_inscan && "Only inscan reductions are expected."); Shareds.append(C->varlist_begin(), C->varlist_end()); Privates.append(C->privates().begin(), C->privates().end()); ReductionOps.append(C->reduction_ops().begin(), C->reduction_ops().end()); - LHSs.append(C->lhs_exprs().begin(), C->lhs_exprs().end()); - RHSs.append(C->rhs_exprs().begin(), C->rhs_exprs().end()); - CopyOps.append(C->copy_ops().begin(), C->copy_ops().end()); CopyArrayTemps.append(C->copy_array_temps().begin(), C->copy_array_temps().end()); - CopyArrayElems.append(C->copy_array_elems().begin(), - C->copy_array_elems().end()); } { // Emit buffers for each reduction variables. @@ -3370,6 +3358,49 @@ static void emitScanBasedDirective( ++Count; } } +} + +/// Emits the code for the directive with inscan reductions. +/// The code is the following: +/// \code +/// #pragma omp ... +/// for (i: 0..) { +/// ; +/// buffer[i] = red; +/// } +/// #pragma omp master // in parallel region +/// for (int k = 0; k != ceil(log2(num_iters)); ++k) +/// for (size cnt = last_iter; cnt >= pow(2, k); --k) +/// buffer[i] op= buffer[i-pow(2,k)]; +/// #pragma omp barrier // in parallel region +/// #pragma omp ... +/// for (0..) { +/// red = InclusiveScan ? buffer[i] : buffer[i-1]; +/// ; +/// } +/// \endcode +static void emitScanBasedDirective( + CodeGenFunction &CGF, const OMPLoopDirective &S, + llvm::function_ref NumIteratorsGen, + llvm::function_ref FirstGen, + llvm::function_ref SecondGen) { + llvm::Value *OMPScanNumIterations = CGF.Builder.CreateIntCast( + NumIteratorsGen(CGF), CGF.SizeTy, /*isSigned=*/false); + SmallVector Privates; + SmallVector ReductionOps; + SmallVector LHSs; + SmallVector RHSs; + SmallVector CopyArrayElems; + for (const auto *C : S.getClausesOfKind()) { + assert(C->getModifier() == OMPC_REDUCTION_inscan && + "Only inscan reductions are expected."); + Privates.append(C->privates().begin(), C->privates().end()); + ReductionOps.append(C->reduction_ops().begin(), C->reduction_ops().end()); + LHSs.append(C->lhs_exprs().begin(), C->lhs_exprs().end()); + RHSs.append(C->rhs_exprs().begin(), C->rhs_exprs().end()); + CopyArrayElems.append(C->copy_array_elems().begin(), + C->copy_array_elems().end()); + } CodeGenFunction::ParentLoopDirectiveForScanRegion ScanRegion(CGF, S); { // Emit loop with input phase: @@ -3382,90 +3413,108 @@ static void emitScanBasedDirective( CodeGenFunction::OMPLocalDeclMapRAII Scope(CGF); FirstGen(CGF); } - // Emit prefix reduction: - // for (int k = 0; k <= ceil(log2(n)); ++k) - llvm::BasicBlock *InputBB = CGF.Builder.GetInsertBlock(); - llvm::BasicBlock *LoopBB = CGF.createBasicBlock("omp.outer.log.scan.body"); - llvm::BasicBlock *ExitBB = CGF.createBasicBlock("omp.outer.log.scan.exit"); - llvm::Function *F = CGF.CGM.getIntrinsic(llvm::Intrinsic::log2, CGF.DoubleTy); - llvm::Value *Arg = - CGF.Builder.CreateUIToFP(OMPScanNumIterations, CGF.DoubleTy); - llvm::Value *LogVal = CGF.EmitNounwindRuntimeCall(F, Arg); - F = CGF.CGM.getIntrinsic(llvm::Intrinsic::ceil, CGF.DoubleTy); - LogVal = CGF.EmitNounwindRuntimeCall(F, LogVal); - LogVal = CGF.Builder.CreateFPToUI(LogVal, CGF.IntTy); - llvm::Value *NMin1 = CGF.Builder.CreateNUWSub( - OMPScanNumIterations, llvm::ConstantInt::get(CGF.SizeTy, 1)); - auto DL = ApplyDebugLocation::CreateDefaultArtificial(CGF, S.getBeginLoc()); - CGF.EmitBlock(LoopBB); - auto *Counter = CGF.Builder.CreatePHI(CGF.IntTy, 2); - // size pow2k = 1; - auto *Pow2K = CGF.Builder.CreatePHI(CGF.SizeTy, 2); - Counter->addIncoming(llvm::ConstantInt::get(CGF.IntTy, 0), InputBB); - Pow2K->addIncoming(llvm::ConstantInt::get(CGF.SizeTy, 1), InputBB); - // for (size i = n - 1; i >= 2 ^ k; --i) - // tmp[i] op= tmp[i-pow2k]; - llvm::BasicBlock *InnerLoopBB = - CGF.createBasicBlock("omp.inner.log.scan.body"); - llvm::BasicBlock *InnerExitBB = - CGF.createBasicBlock("omp.inner.log.scan.exit"); - llvm::Value *CmpI = CGF.Builder.CreateICmpUGE(NMin1, Pow2K); - CGF.Builder.CreateCondBr(CmpI, InnerLoopBB, InnerExitBB); - CGF.EmitBlock(InnerLoopBB); - auto *IVal = CGF.Builder.CreatePHI(CGF.SizeTy, 2); - IVal->addIncoming(NMin1, LoopBB); - { - CodeGenFunction::OMPPrivateScope PrivScope(CGF); - auto *ILHS = LHSs.begin(); - auto *IRHS = RHSs.begin(); - for (const Expr *CopyArrayElem : CopyArrayElems) { - const auto *LHSVD = cast(cast(*ILHS)->getDecl()); - const auto *RHSVD = cast(cast(*IRHS)->getDecl()); - Address LHSAddr = Address::invalid(); - { - CodeGenFunction::OpaqueValueMapping IdxMapping( - CGF, - cast( - cast(CopyArrayElem)->getIdx()), - RValue::get(IVal)); - LHSAddr = CGF.EmitLValue(CopyArrayElem).getAddress(CGF); - } - PrivScope.addPrivate(LHSVD, [LHSAddr]() { return LHSAddr; }); - Address RHSAddr = Address::invalid(); - { - llvm::Value *OffsetIVal = CGF.Builder.CreateNUWSub(IVal, Pow2K); - CodeGenFunction::OpaqueValueMapping IdxMapping( - CGF, - cast( - cast(CopyArrayElem)->getIdx()), - RValue::get(OffsetIVal)); - RHSAddr = CGF.EmitLValue(CopyArrayElem).getAddress(CGF); + // #pragma omp barrier // in parallel region + auto &&CodeGen = [&S, OMPScanNumIterations, &LHSs, &RHSs, &CopyArrayElems, + &ReductionOps, + &Privates](CodeGenFunction &CGF, PrePostActionTy &Action) { + Action.Enter(CGF); + // Emit prefix reduction: + // #pragma omp master // in parallel region + // for (int k = 0; k <= ceil(log2(n)); ++k) + llvm::BasicBlock *InputBB = CGF.Builder.GetInsertBlock(); + llvm::BasicBlock *LoopBB = CGF.createBasicBlock("omp.outer.log.scan.body"); + llvm::BasicBlock *ExitBB = CGF.createBasicBlock("omp.outer.log.scan.exit"); + llvm::Function *F = + CGF.CGM.getIntrinsic(llvm::Intrinsic::log2, CGF.DoubleTy); + llvm::Value *Arg = + CGF.Builder.CreateUIToFP(OMPScanNumIterations, CGF.DoubleTy); + llvm::Value *LogVal = CGF.EmitNounwindRuntimeCall(F, Arg); + F = CGF.CGM.getIntrinsic(llvm::Intrinsic::ceil, CGF.DoubleTy); + LogVal = CGF.EmitNounwindRuntimeCall(F, LogVal); + LogVal = CGF.Builder.CreateFPToUI(LogVal, CGF.IntTy); + llvm::Value *NMin1 = CGF.Builder.CreateNUWSub( + OMPScanNumIterations, llvm::ConstantInt::get(CGF.SizeTy, 1)); + auto DL = ApplyDebugLocation::CreateDefaultArtificial(CGF, S.getBeginLoc()); + CGF.EmitBlock(LoopBB); + auto *Counter = CGF.Builder.CreatePHI(CGF.IntTy, 2); + // size pow2k = 1; + auto *Pow2K = CGF.Builder.CreatePHI(CGF.SizeTy, 2); + Counter->addIncoming(llvm::ConstantInt::get(CGF.IntTy, 0), InputBB); + Pow2K->addIncoming(llvm::ConstantInt::get(CGF.SizeTy, 1), InputBB); + // for (size i = n - 1; i >= 2 ^ k; --i) + // tmp[i] op= tmp[i-pow2k]; + llvm::BasicBlock *InnerLoopBB = + CGF.createBasicBlock("omp.inner.log.scan.body"); + llvm::BasicBlock *InnerExitBB = + CGF.createBasicBlock("omp.inner.log.scan.exit"); + llvm::Value *CmpI = CGF.Builder.CreateICmpUGE(NMin1, Pow2K); + CGF.Builder.CreateCondBr(CmpI, InnerLoopBB, InnerExitBB); + CGF.EmitBlock(InnerLoopBB); + auto *IVal = CGF.Builder.CreatePHI(CGF.SizeTy, 2); + IVal->addIncoming(NMin1, LoopBB); + { + CodeGenFunction::OMPPrivateScope PrivScope(CGF); + auto *ILHS = LHSs.begin(); + auto *IRHS = RHSs.begin(); + for (const Expr *CopyArrayElem : CopyArrayElems) { + const auto *LHSVD = cast(cast(*ILHS)->getDecl()); + const auto *RHSVD = cast(cast(*IRHS)->getDecl()); + Address LHSAddr = Address::invalid(); + { + CodeGenFunction::OpaqueValueMapping IdxMapping( + CGF, + cast( + cast(CopyArrayElem)->getIdx()), + RValue::get(IVal)); + LHSAddr = CGF.EmitLValue(CopyArrayElem).getAddress(CGF); + } + PrivScope.addPrivate(LHSVD, [LHSAddr]() { return LHSAddr; }); + Address RHSAddr = Address::invalid(); + { + llvm::Value *OffsetIVal = CGF.Builder.CreateNUWSub(IVal, Pow2K); + CodeGenFunction::OpaqueValueMapping IdxMapping( + CGF, + cast( + cast(CopyArrayElem)->getIdx()), + RValue::get(OffsetIVal)); + RHSAddr = CGF.EmitLValue(CopyArrayElem).getAddress(CGF); + } + PrivScope.addPrivate(RHSVD, [RHSAddr]() { return RHSAddr; }); + ++ILHS; + ++IRHS; } - PrivScope.addPrivate(RHSVD, [RHSAddr]() { return RHSAddr; }); - ++ILHS; - ++IRHS; + PrivScope.Privatize(); + CGF.CGM.getOpenMPRuntime().emitReduction( + CGF, S.getEndLoc(), Privates, LHSs, RHSs, ReductionOps, + {/*WithNowait=*/true, /*SimpleReduction=*/true, OMPD_unknown}); } - PrivScope.Privatize(); - CGF.CGM.getOpenMPRuntime().emitReduction( - CGF, S.getEndLoc(), Privates, LHSs, RHSs, ReductionOps, - {/*WithNowait=*/true, /*SimpleReduction=*/true, OMPD_unknown}); - } - llvm::Value *NextIVal = - CGF.Builder.CreateNUWSub(IVal, llvm::ConstantInt::get(CGF.SizeTy, 1)); - IVal->addIncoming(NextIVal, CGF.Builder.GetInsertBlock()); - CmpI = CGF.Builder.CreateICmpUGE(NextIVal, Pow2K); - CGF.Builder.CreateCondBr(CmpI, InnerLoopBB, InnerExitBB); - CGF.EmitBlock(InnerExitBB); - llvm::Value *Next = - CGF.Builder.CreateNUWAdd(Counter, llvm::ConstantInt::get(CGF.IntTy, 1)); - Counter->addIncoming(Next, CGF.Builder.GetInsertBlock()); - // pow2k <<= 1; - llvm::Value *NextPow2K = CGF.Builder.CreateShl(Pow2K, 1, "", /*HasNUW=*/true); - Pow2K->addIncoming(NextPow2K, CGF.Builder.GetInsertBlock()); - llvm::Value *Cmp = CGF.Builder.CreateICmpNE(Next, LogVal); - CGF.Builder.CreateCondBr(Cmp, LoopBB, ExitBB); - auto DL1 = ApplyDebugLocation::CreateDefaultArtificial(CGF, S.getEndLoc()); - CGF.EmitBlock(ExitBB); + llvm::Value *NextIVal = + CGF.Builder.CreateNUWSub(IVal, llvm::ConstantInt::get(CGF.SizeTy, 1)); + IVal->addIncoming(NextIVal, CGF.Builder.GetInsertBlock()); + CmpI = CGF.Builder.CreateICmpUGE(NextIVal, Pow2K); + CGF.Builder.CreateCondBr(CmpI, InnerLoopBB, InnerExitBB); + CGF.EmitBlock(InnerExitBB); + llvm::Value *Next = + CGF.Builder.CreateNUWAdd(Counter, llvm::ConstantInt::get(CGF.IntTy, 1)); + Counter->addIncoming(Next, CGF.Builder.GetInsertBlock()); + // pow2k <<= 1; + llvm::Value *NextPow2K = + CGF.Builder.CreateShl(Pow2K, 1, "", /*HasNUW=*/true); + Pow2K->addIncoming(NextPow2K, CGF.Builder.GetInsertBlock()); + llvm::Value *Cmp = CGF.Builder.CreateICmpNE(Next, LogVal); + CGF.Builder.CreateCondBr(Cmp, LoopBB, ExitBB); + auto DL1 = ApplyDebugLocation::CreateDefaultArtificial(CGF, S.getEndLoc()); + CGF.EmitBlock(ExitBB); + }; + if (isOpenMPParallelDirective(S.getDirectiveKind())) { + CGF.CGM.getOpenMPRuntime().emitMasterRegion(CGF, CodeGen, S.getBeginLoc()); + CGF.CGM.getOpenMPRuntime().emitBarrierCall( + CGF, S.getBeginLoc(), OMPD_unknown, /*EmitChecks=*/false, + /*ForceSimpleCall=*/true); + } else { + RegionCodeGenTy RCG(CodeGen); + RCG(CGF); + } CGF.OMPFirstScanLoop = false; SecondGen(CGF); @@ -3502,6 +3551,8 @@ static bool emitWorksharingDirective(CodeGenFunction &CGF, emitForLoopBounds, emitDispatchForLoopBounds); }; + if (!isOpenMPParallelDirective(S.getDirectiveKind())) + emitScanBasedDirectiveDecls(CGF, S, NumIteratorsGen); emitScanBasedDirective(CGF, S, NumIteratorsGen, FirstGen, SecondGen); } else { CodeGenFunction::OMPCancelStackRAII CancelRegion(CGF, S.getDirectiveKind(), @@ -3844,6 +3895,55 @@ void CodeGenFunction::EmitOMPMasterDirective(const OMPMasterDirective &S) { emitMaster(*this, S); } +static void emitMasked(CodeGenFunction &CGF, const OMPExecutableDirective &S) { + auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { + Action.Enter(CGF); + CGF.EmitStmt(S.getRawStmt()); + }; + Expr *Filter = nullptr; + if (const auto *FilterClause = S.getSingleClause()) + Filter = FilterClause->getThreadID(); + CGF.CGM.getOpenMPRuntime().emitMaskedRegion(CGF, CodeGen, S.getBeginLoc(), + Filter); +} + +void CodeGenFunction::EmitOMPMaskedDirective(const OMPMaskedDirective &S) { + if (CGM.getLangOpts().OpenMPIRBuilder) { + llvm::OpenMPIRBuilder &OMPBuilder = CGM.getOpenMPRuntime().getOMPBuilder(); + using InsertPointTy = llvm::OpenMPIRBuilder::InsertPointTy; + + const Stmt *MaskedRegionBodyStmt = S.getAssociatedStmt(); + const Expr *Filter = nullptr; + if (const auto *FilterClause = S.getSingleClause()) + Filter = FilterClause->getThreadID(); + llvm::Value *FilterVal = Filter + ? EmitScalarExpr(Filter, CGM.Int32Ty) + : llvm::ConstantInt::get(CGM.Int32Ty, /*V=*/0); + + auto FiniCB = [this](InsertPointTy IP) { + OMPBuilderCBHelpers::FinalizeOMPRegion(*this, IP); + }; + + auto BodyGenCB = [MaskedRegionBodyStmt, this](InsertPointTy AllocaIP, + InsertPointTy CodeGenIP, + llvm::BasicBlock &FiniBB) { + OMPBuilderCBHelpers::InlinedRegionBodyRAII IRB(*this, AllocaIP, FiniBB); + OMPBuilderCBHelpers::EmitOMPRegionBody(*this, MaskedRegionBodyStmt, + CodeGenIP, FiniBB); + }; + + LexicalScope Scope(*this, S.getSourceRange()); + EmitStopPoint(&S); + Builder.restoreIP( + OMPBuilder.createMasked(Builder, BodyGenCB, FiniCB, FilterVal)); + + return; + } + LexicalScope Scope(*this, S.getSourceRange()); + EmitStopPoint(&S); + emitMasked(*this, S); +} + void CodeGenFunction::EmitOMPCriticalDirective(const OMPCriticalDirective &S) { if (CGM.getLangOpts().OpenMPIRBuilder) { llvm::OpenMPIRBuilder &OMPBuilder = CGM.getOpenMPRuntime().getOMPBuilder(); @@ -3906,6 +4006,19 @@ void CodeGenFunction::EmitOMPParallelForDirective( (void)emitWorksharingDirective(CGF, S, S.hasCancel()); }; { + if (llvm::any_of(S.getClausesOfKind(), + [](const OMPReductionClause *C) { + return C->getModifier() == OMPC_REDUCTION_inscan; + })) { + const auto &&NumIteratorsGen = [&S](CodeGenFunction &CGF) { + CodeGenFunction::OMPLocalDeclMapRAII Scope(CGF); + CGCapturedStmtInfo CGSI(CR_OpenMP); + CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGSI); + OMPLoopScope LoopScope(CGF, S); + return CGF.EmitScalarExpr(S.getNumIterations()); + }; + emitScanBasedDirectiveDecls(*this, S, NumIteratorsGen); + } auto LPCRegion = CGOpenMPRuntime::LastprivateConditionalRAII::disable(*this, S); emitCommonOMPParallelDirective(*this, S, OMPD_for, CodeGen, @@ -3924,6 +4037,19 @@ void CodeGenFunction::EmitOMPParallelForSimdDirective( (void)emitWorksharingDirective(CGF, S, /*HasCancel=*/false); }; { + if (llvm::any_of(S.getClausesOfKind(), + [](const OMPReductionClause *C) { + return C->getModifier() == OMPC_REDUCTION_inscan; + })) { + const auto &&NumIteratorsGen = [&S](CodeGenFunction &CGF) { + CodeGenFunction::OMPLocalDeclMapRAII Scope(CGF); + CGCapturedStmtInfo CGSI(CR_OpenMP); + CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGSI); + OMPLoopScope LoopScope(CGF, S); + return CGF.EmitScalarExpr(S.getNumIterations()); + }; + emitScanBasedDirectiveDecls(*this, S, NumIteratorsGen); + } auto LPCRegion = CGOpenMPRuntime::LastprivateConditionalRAII::disable(*this, S); emitCommonOMPParallelDirective(*this, S, OMPD_for_simd, CodeGen, @@ -6930,7 +7056,8 @@ void CodeGenFunction::EmitSimpleOMPExecutableDirective( if (D.getDirectiveKind() == OMPD_atomic || D.getDirectiveKind() == OMPD_critical || D.getDirectiveKind() == OMPD_section || - D.getDirectiveKind() == OMPD_master) { + D.getDirectiveKind() == OMPD_master || + D.getDirectiveKind() == OMPD_masked) { EmitStmt(D.getAssociatedStmt()); } else { auto LPCRegion = diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 0483db3811ba..7f687fb09d5b 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -520,6 +520,10 @@ class CodeGenFunction : public CodeGenTypeCache { /// True if the current statement has nomerge attribute. bool InNoMergeAttributedStmt = false; + // The CallExpr within the current statement that the musttail attribute + // applies to. nullptr if there is no 'musttail' on the current statement. + const CallExpr *MustTailCall = nullptr; + /// True if the current function should be marked mustprogress. bool FnIsMustProgress = false; @@ -568,6 +572,8 @@ class CodeGenFunction : public CodeGenTypeCache { llvm::Instruction *CurrentFuncletPad = nullptr; class CallLifetimeEnd final : public EHScopeStack::Cleanup { + bool isRedundantBeforeReturn() override { return true; } + llvm::Value *Addr; llvm::Value *Size; @@ -3421,6 +3427,7 @@ class CodeGenFunction : public CodeGenTypeCache { void EmitOMPSectionDirective(const OMPSectionDirective &S); void EmitOMPSingleDirective(const OMPSingleDirective &S); void EmitOMPMasterDirective(const OMPMasterDirective &S); + void EmitOMPMaskedDirective(const OMPMaskedDirective &S); void EmitOMPCriticalDirective(const OMPCriticalDirective &S); void EmitOMPParallelForDirective(const OMPParallelForDirective &S); void EmitOMPParallelForSimdDirective(const OMPParallelForSimdDirective &S); @@ -3912,12 +3919,14 @@ class CodeGenFunction : public CodeGenTypeCache { /// LLVM arguments and the types they were derived from. RValue EmitCall(const CGFunctionInfo &CallInfo, const CGCallee &Callee, ReturnValueSlot ReturnValue, const CallArgList &Args, - llvm::CallBase **callOrInvoke, SourceLocation Loc); + llvm::CallBase **callOrInvoke, bool IsMustTail, + SourceLocation Loc); RValue EmitCall(const CGFunctionInfo &CallInfo, const CGCallee &Callee, ReturnValueSlot ReturnValue, const CallArgList &Args, - llvm::CallBase **callOrInvoke = nullptr) { + llvm::CallBase **callOrInvoke = nullptr, + bool IsMustTail = false) { return EmitCall(CallInfo, Callee, ReturnValue, Args, callOrInvoke, - SourceLocation()); + IsMustTail, SourceLocation()); } RValue EmitCall(QualType FnType, const CGCallee &Callee, const CallExpr *E, ReturnValueSlot ReturnValue, llvm::Value *Chain = nullptr); diff --git a/clang/lib/CodeGen/EHScopeStack.h b/clang/lib/CodeGen/EHScopeStack.h index 3a640d6117d6..994d3db555aa 100644 --- a/clang/lib/CodeGen/EHScopeStack.h +++ b/clang/lib/CodeGen/EHScopeStack.h @@ -150,6 +150,8 @@ class EHScopeStack { Cleanup(Cleanup &&) {} Cleanup() = default; + virtual bool isRedundantBeforeReturn() { return false; } + /// Generation flags. class Flags { enum { diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp index 727bc679de78..4afb609a2e50 100644 --- a/clang/lib/CodeGen/ItaniumCXXABI.cpp +++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp @@ -1835,6 +1835,29 @@ ItaniumCXXABI::getVTableAddressPoint(BaseSubobject Base, /*InRangeIndex=*/1); } +// Check whether all the non-inline virtual methods for the class have the +// specified attribute. +template +static bool CXXRecordAllNonInlineVirtualsHaveAttr(const CXXRecordDecl *RD) { + bool FoundNonInlineVirtualMethodWithAttr = false; + for (const auto *D : RD->noload_decls()) { + if (const auto *FD = dyn_cast(D)) { + if (!FD->isVirtualAsWritten() || FD->isInlineSpecified() || + FD->doesThisDeclarationHaveABody()) + continue; + if (!D->hasAttr()) + return false; + FoundNonInlineVirtualMethodWithAttr = true; + } + } + + // We didn't find any non-inline virtual methods missing the attribute. We + // will return true when we found at least one non-inline virtual with the + // attribute. (This lets our caller know that the attribute needs to be + // propagated up to the vtable.) + return FoundNonInlineVirtualMethodWithAttr; +} + llvm::Value *ItaniumCXXABI::getVTableAddressPointInStructorWithVTT( CodeGenFunction &CGF, const CXXRecordDecl *VTableClass, BaseSubobject Base, const CXXRecordDecl *NearestVBase) { @@ -1891,6 +1914,24 @@ llvm::GlobalVariable *ItaniumCXXABI::getAddrOfVTable(const CXXRecordDecl *RD, getContext().toCharUnitsFromBits(PAlign).getQuantity()); VTable->setUnnamedAddr(llvm::GlobalValue::UnnamedAddr::Global); + // In MS C++ if you have a class with virtual functions in which you are using + // selective member import/export, then all virtual functions must be exported + // unless they are inline, otherwise a link error will result. To match this + // behavior, for such classes, we dllimport the vtable if it is defined + // externally and all the non-inline virtual methods are marked dllimport, and + // we dllexport the vtable if it is defined in this TU and all the non-inline + // virtual methods are marked dllexport. + if (CGM.getTarget().hasPS4DLLImportExport()) { + if ((!RD->hasAttr()) && (!RD->hasAttr())) { + if (CGM.getVTables().isVTableExternal(RD)) { + if (CXXRecordAllNonInlineVirtualsHaveAttr(RD)) + VTable->setDLLStorageClass(llvm::GlobalValue::DLLImportStorageClass); + } else { + if (CXXRecordAllNonInlineVirtualsHaveAttr(RD)) + VTable->setDLLStorageClass(llvm::GlobalValue::DLLExportStorageClass); + } + } + } CGM.setGVProperties(VTable, RD); return VTable; @@ -3139,6 +3180,14 @@ ItaniumRTTIBuilder::GetAddrOfExternalRTTIDescriptor(QualType Ty) { Name); const CXXRecordDecl *RD = Ty->getAsCXXRecordDecl(); CGM.setGVProperties(GV, RD); + // Import the typeinfo symbol when all non-inline virtual methods are + // imported. + if (CGM.getTarget().hasPS4DLLImportExport()) { + if (RD && CXXRecordAllNonInlineVirtualsHaveAttr(RD)) { + GV->setDLLStorageClass(llvm::GlobalVariable::DLLImportStorageClass); + CGM.setDSOLocal(GV); + } + } } return llvm::ConstantExpr::getBitCast(GV, CGM.Int8PtrTy); @@ -3320,11 +3369,14 @@ static bool ShouldUseExternalRTTIDescriptor(CodeGenModule &CGM, if (CGM.getTriple().isWindowsGNUEnvironment()) return false; - if (CGM.getVTables().isVTableExternal(RD)) + if (CGM.getVTables().isVTableExternal(RD)) { + if (CGM.getTarget().hasPS4DLLImportExport()) + return true; + return IsDLLImport && !CGM.getTriple().isWindowsItaniumEnvironment() ? false : true; - + } if (IsDLLImport) return true; } @@ -3776,6 +3828,18 @@ llvm::Constant *ItaniumRTTIBuilder::BuildTypeInfo( new llvm::GlobalVariable(M, Init->getType(), /*isConstant=*/true, Linkage, Init, Name); + // Export the typeinfo in the same circumstances as the vtable is exported. + auto GVDLLStorageClass = DLLStorageClass; + if (CGM.getTarget().hasPS4DLLImportExport()) { + if (const RecordType *RecordTy = dyn_cast(Ty)) { + const CXXRecordDecl *RD = cast(RecordTy->getDecl()); + if (RD->hasAttr() || + CXXRecordAllNonInlineVirtualsHaveAttr(RD)) { + GVDLLStorageClass = llvm::GlobalVariable::DLLExportStorageClass; + } + } + } + // If there's already an old global variable, replace it with the new one. if (OldGV) { GV->takeName(OldGV); @@ -3814,7 +3878,9 @@ llvm::Constant *ItaniumRTTIBuilder::BuildTypeInfo( CGM.setDSOLocal(GV); TypeName->setDLLStorageClass(DLLStorageClass); - GV->setDLLStorageClass(DLLStorageClass); + GV->setDLLStorageClass(CGM.getTarget().hasPS4DLLImportExport() + ? GVDLLStorageClass + : DLLStorageClass); TypeName->setPartition(CGM.getCodeGenOpts().SymbolPartition); GV->setPartition(CGM.getCodeGenOpts().SymbolPartition); diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 1ceafa1a842a..7bb6eaa81900 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -1105,6 +1105,7 @@ class X86_32ABIInfo : public SwiftABIInfo { bool IsWin32StructABI; bool IsSoftFloatABI; bool IsMCUABI; + bool IsLinuxABI; unsigned DefaultNumRegisterParameters; static bool isRegisterSize(unsigned Size) { @@ -1167,9 +1168,9 @@ class X86_32ABIInfo : public SwiftABIInfo { unsigned NumRegisterParameters, bool SoftFloatABI) : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI), IsRetSmallStructInRegABI(RetSmallStructInRegABI), - IsWin32StructABI(Win32StructABI), - IsSoftFloatABI(SoftFloatABI), + IsWin32StructABI(Win32StructABI), IsSoftFloatABI(SoftFloatABI), IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()), + IsLinuxABI(CGT.getTarget().getTriple().isOSLinux()), DefaultNumRegisterParameters(NumRegisterParameters) {} bool shouldPassIndirectlyForSwift(ArrayRef scalars, @@ -1594,6 +1595,14 @@ unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, if (Align <= MinABIStackAlignInBytes) return 0; // Use default alignment. + if (IsLinuxABI) { + // Exclude other System V OS (e.g Darwin, PS4 and FreeBSD) since we don't + // want to spend any effort dealing with the ramifications of ABI breaks. + // + // If the vector type is __m128/__m256/__m512, return the default alignment. + if (Ty->isVectorType() && (Align == 16 || Align == 32 || Align == 64)) + return Align; + } // On non-Darwin, the stack type alignment is always 4. if (!IsDarwinVectorABI) { // Set explicit alignment, since we may need to realign the top. @@ -5409,7 +5418,8 @@ class AArch64ABIInfo : public SwiftABIInfo { bool isDarwinPCS() const { return Kind == DarwinPCS; } ABIArgInfo classifyReturnType(QualType RetTy, bool IsVariadic) const; - ABIArgInfo classifyArgumentType(QualType RetTy) const; + ABIArgInfo classifyArgumentType(QualType RetTy, bool IsVariadic, + unsigned CallingConvention) const; ABIArgInfo coerceIllegalVector(QualType Ty) const; bool isHomogeneousAggregateBaseType(QualType Ty) const override; bool isHomogeneousAggregateSmallEnough(const Type *Ty, @@ -5423,7 +5433,8 @@ class AArch64ABIInfo : public SwiftABIInfo { classifyReturnType(FI.getReturnType(), FI.isVariadic()); for (auto &it : FI.arguments()) - it.info = classifyArgumentType(it.type); + it.info = classifyArgumentType(it.type, FI.isVariadic(), + FI.getCallingConvention()); } Address EmitDarwinVAArg(Address VAListAddr, QualType Ty, @@ -5626,7 +5637,9 @@ ABIArgInfo AArch64ABIInfo::coerceIllegalVector(QualType Ty) const { return getNaturalAlignIndirect(Ty, /*ByVal=*/false); } -ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const { +ABIArgInfo +AArch64ABIInfo::classifyArgumentType(QualType Ty, bool IsVariadic, + unsigned CallingConvention) const { Ty = useFirstFieldIfTransparentUnion(Ty); // Handle illegal vector types here. @@ -5672,9 +5685,24 @@ ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const { // Homogeneous Floating-point Aggregates (HFAs) need to be expanded. const Type *Base = nullptr; uint64_t Members = 0; - if (isHomogeneousAggregate(Ty, Base, Members)) { + bool IsWin64 = Kind == Win64 || CallingConvention == llvm::CallingConv::Win64; + bool IsWinVariadic = IsWin64 && IsVariadic; + // In variadic functions on Windows, all composite types are treated alike, + // no special handling of HFAs/HVAs. + if (!IsWinVariadic && isHomogeneousAggregate(Ty, Base, Members)) { + if (Kind != AArch64ABIInfo::AAPCS) + return ABIArgInfo::getDirect( + llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members)); + + // For alignment adjusted HFAs, cap the argument alignment to 16, leave it + // default otherwise. + unsigned Align = + getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity(); + unsigned BaseAlign = getContext().getTypeAlignInChars(Base).getQuantity(); + Align = (Align > BaseAlign && Align >= 16) ? 16 : 0; return ABIArgInfo::getDirect( - llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members)); + llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members), 0, + nullptr, true, Align); } // Aggregates <= 16 bytes are passed directly in registers or on the stack. @@ -5829,10 +5857,10 @@ bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base, return Members <= 4; } -Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, - QualType Ty, - CodeGenFunction &CGF) const { - ABIArgInfo AI = classifyArgumentType(Ty); +Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty, + CodeGenFunction &CGF) const { + ABIArgInfo AI = classifyArgumentType(Ty, /*IsVariadic=*/true, + CGF.CurFnInfo->getCallingConvention()); bool IsIndirect = AI.isIndirect(); llvm::Type *BaseTy = CGF.ConvertType(Ty); @@ -6112,7 +6140,13 @@ Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty, Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty) const { - return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false, + bool IsIndirect = false; + + // Composites larger than 16 bytes are passed by reference. + if (isAggregateTypeForABI(Ty) && getContext().getTypeSize(Ty) > 128) + IsIndirect = true; + + return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, CGF.getContext().getTypeInfoInChars(Ty), CharUnits::fromQuantity(8), /*allowHigherAlign*/ false); diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index a608f073eae1..2a3ad71e29eb 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -4219,7 +4219,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, // of the module. // All other jobs are expected to have exactly one input. bool IsCuda = JA.isOffloading(Action::OFK_Cuda); + bool IsCudaDevice = JA.isDeviceOffloading(Action::OFK_Cuda); bool IsHIP = JA.isOffloading(Action::OFK_HIP); + bool IsHIPDevice = JA.isDeviceOffloading(Action::OFK_HIP); bool IsOpenMPDevice = JA.isDeviceOffloading(Action::OFK_OpenMP); bool IsSYCLOffloadDevice = JA.isDeviceOffloading(Action::OFK_SYCL); bool IsSYCL = JA.isOffloading(Action::OFK_SYCL); @@ -5186,9 +5188,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, // Prepare `-aux-target-cpu` and `-aux-target-feature` unless // `--gpu-use-aux-triple-only` is specified. if (!Args.getLastArg(options::OPT_gpu_use_aux_triple_only) && - ((IsCuda && JA.isDeviceOffloading(Action::OFK_Cuda)) || - (IsSYCL && IsSYCLOffloadDevice) || - (IsHIP && JA.isDeviceOffloading(Action::OFK_HIP)))) { + (IsCudaDevice || (IsSYCL && IsSYCLOffloadDevice) || IsHIPDevice)) { const ArgList &HostArgs = C.getArgsForToolChain(nullptr, StringRef(), Action::OFK_None); std::string HostCPU = @@ -6036,29 +6036,32 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.MakeArgString(Twine("-fcf-protection=") + A->getValue())); } - // Forward -f options with positive and negative forms; we translate - // these by hand. - if (Arg *A = getLastProfileSampleUseArg(Args)) { - auto *PGOArg = Args.getLastArg( - options::OPT_fprofile_generate, options::OPT_fprofile_generate_EQ, - options::OPT_fcs_profile_generate, options::OPT_fcs_profile_generate_EQ, - options::OPT_fprofile_use, options::OPT_fprofile_use_EQ); - if (PGOArg) - D.Diag(diag::err_drv_argument_not_allowed_with) - << "SampleUse with PGO options"; + // Forward -f options with positive and negative forms; we translate these by + // hand. Do not propagate PGO options to the GPU-side compilations as the + // profile info is for the host-side compilation only. + if (!(IsCudaDevice || IsHIPDevice)) { + if (Arg *A = getLastProfileSampleUseArg(Args)) { + auto *PGOArg = Args.getLastArg( + options::OPT_fprofile_generate, options::OPT_fprofile_generate_EQ, + options::OPT_fcs_profile_generate, + options::OPT_fcs_profile_generate_EQ, options::OPT_fprofile_use, + options::OPT_fprofile_use_EQ); + if (PGOArg) + D.Diag(diag::err_drv_argument_not_allowed_with) + << "SampleUse with PGO options"; + + StringRef fname = A->getValue(); + if (!llvm::sys::fs::exists(fname)) + D.Diag(diag::err_drv_no_such_file) << fname; + else + A->render(Args, CmdArgs); + } + Args.AddLastArg(CmdArgs, options::OPT_fprofile_remapping_file_EQ); - StringRef fname = A->getValue(); - if (!llvm::sys::fs::exists(fname)) - D.Diag(diag::err_drv_no_such_file) << fname; - else - A->render(Args, CmdArgs); + if (Args.hasFlag(options::OPT_fpseudo_probe_for_profiling, + options::OPT_fno_pseudo_probe_for_profiling, false)) + CmdArgs.push_back("-fpseudo-probe-for-profiling"); } - Args.AddLastArg(CmdArgs, options::OPT_fprofile_remapping_file_EQ); - - if (Args.hasFlag(options::OPT_fpseudo_probe_for_profiling, - options::OPT_fno_pseudo_probe_for_profiling, false)) - CmdArgs.push_back("-fpseudo-probe-for-profiling"); - RenderBuiltinOptions(TC, RawTriple, Args, CmdArgs); if (!Args.hasFlag(options::OPT_fassume_sane_operator_new, diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index 76bd0363bc85..b37ac80dfc73 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -745,13 +745,12 @@ void CudaToolChain::addClangTargetOptions( if (DriverArgs.hasArg(options::OPT_nogpulib)) return; - std::string LibDeviceFile = CudaInstallation.getLibDeviceFile(GpuArch); + if (DeviceOffloadingKind == Action::OFK_OpenMP && + DriverArgs.hasArg(options::OPT_S)) + return; + std::string LibDeviceFile = CudaInstallation.getLibDeviceFile(GpuArch); if (LibDeviceFile.empty()) { - if (DeviceOffloadingKind == Action::OFK_OpenMP && - DriverArgs.hasArg(options::OPT_S)) - return; - getDriver().Diag(diag::err_drv_no_cuda_libdevice) << GpuArch; return; } diff --git a/clang/lib/Driver/ToolChains/FreeBSD.cpp b/clang/lib/Driver/ToolChains/FreeBSD.cpp index c508af655ac2..f8c6a81bf3bc 100644 --- a/clang/lib/Driver/ToolChains/FreeBSD.cpp +++ b/clang/lib/Driver/ToolChains/FreeBSD.cpp @@ -467,6 +467,7 @@ bool FreeBSD::IsUnwindTablesDefault(const ArgList &Args) const { return true; } bool FreeBSD::isPIEDefault() const { return getSanitizerArgs().requiresPIE(); } SanitizerMask FreeBSD::getSupportedSanitizers() const { + const bool IsAArch64 = getTriple().getArch() == llvm::Triple::aarch64; const bool IsX86 = getTriple().getArch() == llvm::Triple::x86; const bool IsX86_64 = getTriple().getArch() == llvm::Triple::x86_64; const bool IsMIPS64 = getTriple().isMIPS64(); @@ -485,8 +486,13 @@ SanitizerMask FreeBSD::getSupportedSanitizers() const { Res |= SanitizerKind::Fuzzer; Res |= SanitizerKind::FuzzerNoLink; } - if (IsX86_64) + if (IsAArch64 || IsX86_64) { + Res |= SanitizerKind::KernelAddress; + Res |= SanitizerKind::KernelMemory; + } + if (IsX86_64) { Res |= SanitizerKind::Memory; + } return Res; } diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 120202caa3cd..00849107c894 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -241,6 +241,16 @@ struct ScalarEnumerationTraits { } }; +template <> +struct ScalarEnumerationTraits { + static void + enumeration(IO &IO, FormatStyle::EmptyLineAfterAccessModifierStyle &Value) { + IO.enumCase(Value, "Never", FormatStyle::ELAAMS_Never); + IO.enumCase(Value, "Leave", FormatStyle::ELAAMS_Leave); + IO.enumCase(Value, "Always", FormatStyle::ELAAMS_Always); + } +}; + template <> struct ScalarEnumerationTraits< FormatStyle::EmptyLineBeforeAccessModifierStyle> { @@ -584,6 +594,8 @@ template <> struct MappingTraits { IO.mapOptional("DeriveLineEnding", Style.DeriveLineEnding); IO.mapOptional("DerivePointerAlignment", Style.DerivePointerAlignment); IO.mapOptional("DisableFormat", Style.DisableFormat); + IO.mapOptional("EmptyLineAfterAccessModifier", + Style.EmptyLineAfterAccessModifier); IO.mapOptional("EmptyLineBeforeAccessModifier", Style.EmptyLineBeforeAccessModifier); IO.mapOptional("ExperimentalAutoDetectBinPacking", @@ -974,6 +986,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { LLVMStyle.Cpp11BracedListStyle = true; LLVMStyle.DeriveLineEnding = true; LLVMStyle.DerivePointerAlignment = false; + LLVMStyle.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Never; LLVMStyle.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_LogicalBlock; LLVMStyle.ExperimentalAutoDetectBinPacking = false; LLVMStyle.FixNamespaceComments = true; diff --git a/clang/lib/Format/SortJavaScriptImports.cpp b/clang/lib/Format/SortJavaScriptImports.cpp index db2b65b08898..b7df1a5f1b53 100644 --- a/clang/lib/Format/SortJavaScriptImports.cpp +++ b/clang/lib/Format/SortJavaScriptImports.cpp @@ -83,8 +83,16 @@ struct JsModuleReference { // Prefix from "import * as prefix". Empty for symbol imports and `export *`. // Implies an empty names list. StringRef Prefix; + // Default import from "import DefaultName from '...';". + StringRef DefaultImport; // Symbols from `import {SymbolA, SymbolB, ...} from ...;`. SmallVector Symbols; + // Whether some symbols were merged into this one. Controls if the module + // reference needs re-formatting. + bool SymbolsMerged = false; + // The source location just after { and just before } in the import. + // Extracted eagerly to allow modification of Symbols later on. + SourceLocation SymbolsStart, SymbolsEnd; // Textual position of the import/export, including preceding and trailing // comments. SourceRange Range; @@ -146,6 +154,8 @@ class JavaScriptImportSorter : public TokenAnalyzer { }); bool ReferencesInOrder = llvm::is_sorted(Indices); + mergeModuleReferences(References, Indices); + std::string ReferencesText; bool SymbolsInOrder = true; for (unsigned i = 0, e = Indices.size(); i != e; ++i) { @@ -163,7 +173,6 @@ class JavaScriptImportSorter : public TokenAnalyzer { ReferencesText += "\n"; } } - if (ReferencesInOrder && SymbolsInOrder) return {Result, 0}; @@ -239,6 +248,45 @@ class JavaScriptImportSorter : public TokenAnalyzer { SM.getFileOffset(End) - SM.getFileOffset(Begin)); } + // Merge module references. + // After sorting, find all references that import named symbols from the + // same URL and merge their names. E.g. + // import {X} from 'a'; + // import {Y} from 'a'; + // should be rewritten to: + // import {X, Y} from 'a'; + // Note: this modifies the passed in ``Indices`` vector (by removing no longer + // needed references), but not ``References``. + // ``JsModuleReference``s that get merged have the ``SymbolsMerged`` flag + // flipped to true. + void mergeModuleReferences(SmallVector &References, + SmallVector &Indices) { + JsModuleReference *PreviousReference = &References[Indices[0]]; + auto *It = std::next(Indices.begin()); + while (It != std::end(Indices)) { + JsModuleReference *Reference = &References[*It]; + // Skip: + // import 'foo'; + // import * as foo from 'foo'; on either previous or this. + // import Default from 'foo'; on either previous or this. + // mismatching + if (Reference->Category == JsModuleReference::SIDE_EFFECT || + !PreviousReference->Prefix.empty() || !Reference->Prefix.empty() || + !PreviousReference->DefaultImport.empty() || + !Reference->DefaultImport.empty() || Reference->Symbols.empty() || + PreviousReference->URL != Reference->URL) { + PreviousReference = Reference; + ++It; + continue; + } + // Merge symbols from identical imports. + PreviousReference->Symbols.append(Reference->Symbols); + PreviousReference->SymbolsMerged = true; + // Remove the merged import. + It = Indices.erase(It); + } + } + // Appends ``Reference`` to ``Buffer``, returning true if text within the // ``Reference`` changed (e.g. symbol order). bool appendReference(std::string &Buffer, JsModuleReference &Reference) { @@ -249,16 +297,14 @@ class JavaScriptImportSorter : public TokenAnalyzer { Symbols, [&](const JsImportedSymbol &LHS, const JsImportedSymbol &RHS) { return LHS.Symbol.compare_lower(RHS.Symbol) < 0; }); - if (Symbols == Reference.Symbols) { - // No change in symbol order. + if (!Reference.SymbolsMerged && Symbols == Reference.Symbols) { + // Symbols didn't change, just emit the entire module reference. StringRef ReferenceStmt = getSourceText(Reference.Range); Buffer += ReferenceStmt; return false; } // Stitch together the module reference start... - SourceLocation SymbolsStart = Reference.Symbols.front().Range.getBegin(); - SourceLocation SymbolsEnd = Reference.Symbols.back().Range.getEnd(); - Buffer += getSourceText(Reference.Range.getBegin(), SymbolsStart); + Buffer += getSourceText(Reference.Range.getBegin(), Reference.SymbolsStart); // ... then the references in order ... for (auto I = Symbols.begin(), E = Symbols.end(); I != E; ++I) { if (I != Symbols.begin()) @@ -266,7 +312,7 @@ class JavaScriptImportSorter : public TokenAnalyzer { Buffer += getSourceText(I->Range); } // ... followed by the module reference end. - Buffer += getSourceText(SymbolsEnd, Reference.Range.getEnd()); + Buffer += getSourceText(Reference.SymbolsEnd, Reference.Range.getEnd()); return true; } @@ -280,7 +326,7 @@ class JavaScriptImportSorter : public TokenAnalyzer { SourceLocation Start; AnnotatedLine *FirstNonImportLine = nullptr; bool AnyImportAffected = false; - for (auto Line : AnnotatedLines) { + for (auto *Line : AnnotatedLines) { Current = Line->First; LineEnd = Line->Last; skipComments(); @@ -393,7 +439,9 @@ class JavaScriptImportSorter : public TokenAnalyzer { bool parseNamedBindings(const AdditionalKeywords &Keywords, JsModuleReference &Reference) { + // eat a potential "import X, " prefix. if (Current->is(tok::identifier)) { + Reference.DefaultImport = Current->TokenText; nextToken(); if (Current->is(Keywords.kw_from)) return true; @@ -405,6 +453,7 @@ class JavaScriptImportSorter : public TokenAnalyzer { return false; // {sym as alias, sym2 as ...} from '...'; + Reference.SymbolsStart = Current->Tok.getEndLoc(); while (Current->isNot(tok::r_brace)) { nextToken(); if (Current->is(tok::r_brace)) @@ -432,6 +481,11 @@ class JavaScriptImportSorter : public TokenAnalyzer { if (!Current->isOneOf(tok::r_brace, tok::comma)) return false; } + Reference.SymbolsEnd = Current->Tok.getLocation(); + // For named imports with a trailing comma ("import {X,}"), consider the + // comma to be the end of the import list, so that it doesn't get removed. + if (Current->Previous->is(tok::comma)) + Reference.SymbolsEnd = Current->Previous->Tok.getLocation(); nextToken(); // consume r_brace return true; } diff --git a/clang/lib/Format/UnwrappedLineFormatter.cpp b/clang/lib/Format/UnwrappedLineFormatter.cpp index ea18e660785e..e38d90d58362 100644 --- a/clang/lib/Format/UnwrappedLineFormatter.cpp +++ b/clang/lib/Format/UnwrappedLineFormatter.cpp @@ -1254,16 +1254,17 @@ void UnwrappedLineFormatter::formatFirstToken( if (PreviousLine && RootToken.isAccessSpecifier()) { switch (Style.EmptyLineBeforeAccessModifier) { case FormatStyle::ELBAMS_Never: - if (RootToken.NewlinesBefore > 1) + if (Newlines > 1) Newlines = 1; break; case FormatStyle::ELBAMS_Leave: Newlines = std::max(RootToken.NewlinesBefore, 1u); break; case FormatStyle::ELBAMS_LogicalBlock: - if (PreviousLine->Last->isOneOf(tok::semi, tok::r_brace) && - RootToken.NewlinesBefore <= 1) + if (PreviousLine->Last->isOneOf(tok::semi, tok::r_brace) && Newlines <= 1) Newlines = 2; + if (PreviousLine->First->isAccessSpecifier()) + Newlines = 1; // Previous is an access modifier remove all new lines. break; case FormatStyle::ELBAMS_Always: { const FormatToken *previousToken; @@ -1271,17 +1272,34 @@ void UnwrappedLineFormatter::formatFirstToken( previousToken = PreviousLine->Last->getPreviousNonComment(); else previousToken = PreviousLine->Last; - if ((!previousToken || !previousToken->is(tok::l_brace)) && - RootToken.NewlinesBefore <= 1) + if ((!previousToken || !previousToken->is(tok::l_brace)) && Newlines <= 1) Newlines = 2; } break; } } - // Remove empty lines after access specifiers. + // Insert or remove empty line after access specifiers. if (PreviousLine && PreviousLine->First->isAccessSpecifier() && - (!PreviousLine->InPPDirective || !RootToken.HasUnescapedNewline)) - Newlines = std::min(1u, Newlines); + (!PreviousLine->InPPDirective || !RootToken.HasUnescapedNewline)) { + // EmptyLineBeforeAccessModifier is handling the case when two access + // modifiers follow each other. + if (!RootToken.isAccessSpecifier()) { + switch (Style.EmptyLineAfterAccessModifier) { + case FormatStyle::ELAAMS_Never: + Newlines = 1; + break; + case FormatStyle::ELAAMS_Leave: + Newlines = std::max(Newlines, 1u); + break; + case FormatStyle::ELAAMS_Always: + if (RootToken.is(tok::r_brace)) // Do not add at end of class. + Newlines = 1u; + else + Newlines = std::max(Newlines, 2u); + break; + } + } + } if (Newlines) Indent = NewlineIndent; diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index e6b74741c713..de075af61ba3 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -113,14 +113,16 @@ CompilerInvocationBase::CompilerInvocationBase() : LangOpts(new LangOptions()), TargetOpts(new TargetOptions()), DiagnosticOpts(new DiagnosticOptions()), HeaderSearchOpts(new HeaderSearchOptions()), - PreprocessorOpts(new PreprocessorOptions()) {} + PreprocessorOpts(new PreprocessorOptions()), + AnalyzerOpts(new AnalyzerOptions()) {} CompilerInvocationBase::CompilerInvocationBase(const CompilerInvocationBase &X) : LangOpts(new LangOptions(*X.getLangOpts())), TargetOpts(new TargetOptions(X.getTargetOpts())), DiagnosticOpts(new DiagnosticOptions(X.getDiagnosticOpts())), HeaderSearchOpts(new HeaderSearchOptions(X.getHeaderSearchOpts())), - PreprocessorOpts(new PreprocessorOptions(X.getPreprocessorOpts())) {} + PreprocessorOpts(new PreprocessorOptions(X.getPreprocessorOpts())), + AnalyzerOpts(new AnalyzerOptions(*X.getAnalyzerOpts())) {} CompilerInvocationBase::~CompilerInvocationBase() = default; diff --git a/clang/lib/Frontend/HeaderIncludeGen.cpp b/clang/lib/Frontend/HeaderIncludeGen.cpp index df3f5345775a..1ee47d8d2480 100644 --- a/clang/lib/Frontend/HeaderIncludeGen.cpp +++ b/clang/lib/Frontend/HeaderIncludeGen.cpp @@ -45,6 +45,9 @@ class HeaderIncludesCallback : public PPCallbacks { void FileChanged(SourceLocation Loc, FileChangeReason Reason, SrcMgr::CharacteristicKind FileType, FileID PrevFID) override; + + void FileSkipped(const FileEntryRef &SkippedFile, const Token &FilenameTok, + SrcMgr::CharacteristicKind FileType) override; }; } @@ -181,3 +184,16 @@ void HeaderIncludesCallback::FileChanged(SourceLocation Loc, MSStyle); } } + +void HeaderIncludesCallback::FileSkipped(const FileEntryRef &SkippedFile, const + Token &FilenameTok, + SrcMgr::CharacteristicKind FileType) { + if (!DepOpts.ShowSkippedHeaderIncludes) + return; + + if (!DepOpts.IncludeSystemHeaders && isSystem(FileType)) + return; + + PrintHeaderInfo(OutputFile, SkippedFile.getName(), ShowDepth, + CurrentIncludeDepth + 1, MSStyle); +} diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index b83436bc4e26..fff38ed036d9 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -789,6 +789,21 @@ static void InitializePredefinedMacros(const TargetInfo &TI, } } + // Macros to help identify the narrow and wide character sets + // FIXME: clang currently ignores -fexec-charset=. If this changes, + // then this may need to be updated. + Builder.defineMacro("__clang_literal_encoding__", "\"UTF-8\""); + if (TI.getTypeWidth(TI.getWCharType()) >= 32) { + // FIXME: 32-bit wchar_t signals UTF-32. This may change + // if -fwide-exec-charset= is ever supported. + Builder.defineMacro("__clang_wide_literal_encoding__", "\"UTF-32\""); + } else { + // FIXME: Less-than 32-bit wchar_t generally means UTF-16 + // (e.g., Windows, 32-bit IBM). This may need to be + // updated if -fwide-exec-charset= is ever supported. + Builder.defineMacro("__clang_wide_literal_encoding__", "\"UTF-16\""); + } + if (LangOpts.Optimize) Builder.defineMacro("__OPTIMIZE__"); if (LangOpts.OptimizeSize) diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index 498036368c19..af3d0df53e91 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -4213,10 +4213,21 @@ void Parser::ParseCXX11AttributeSpecifier(ParsedAttributes &attrs, llvm::SmallDenseMap SeenAttrs; - while (Tok.isNot(tok::r_square)) { - // attribute not present - if (TryConsumeToken(tok::comma)) - continue; + bool AttrParsed = false; + while (!Tok.isOneOf(tok::r_square, tok::semi)) { + if (AttrParsed) { + // If we parsed an attribute, a comma is required before parsing any + // additional attributes. + if (ExpectAndConsume(tok::comma)) { + SkipUntil(tok::r_square, StopAtSemi | StopBeforeMatch); + continue; + } + AttrParsed = false; + } + + // Eat all remaining superfluous commas before parsing the next attribute. + while (TryConsumeToken(tok::comma)) + ; SourceLocation ScopeLoc, AttrLoc; IdentifierInfo *ScopeName = nullptr, *AttrName = nullptr; @@ -4249,31 +4260,32 @@ void Parser::ParseCXX11AttributeSpecifier(ParsedAttributes &attrs, } } - bool StandardAttr = IsBuiltInOrStandardCXX11Attribute(AttrName, ScopeName); - bool AttrParsed = false; - - if (StandardAttr && - !SeenAttrs.insert(std::make_pair(AttrName, AttrLoc)).second) - Diag(AttrLoc, diag::err_cxx11_attribute_repeated) - << AttrName << SourceRange(SeenAttrs[AttrName]); - // Parse attribute arguments if (Tok.is(tok::l_paren)) AttrParsed = ParseCXX11AttributeArgs(AttrName, AttrLoc, attrs, endLoc, ScopeName, ScopeLoc); - if (!AttrParsed) + if (!AttrParsed) { attrs.addNew( AttrName, SourceRange(ScopeLoc.isValid() ? ScopeLoc : AttrLoc, AttrLoc), ScopeName, ScopeLoc, nullptr, 0, getLangOpts().CPlusPlus ? ParsedAttr::AS_CXX11 : ParsedAttr::AS_C2x); + AttrParsed = true; + } if (TryConsumeToken(tok::ellipsis)) Diag(Tok, diag::err_cxx11_attribute_forbids_ellipsis) << AttrName; } + // If we hit an error and recovered by parsing up to a semicolon, eat the + // semicolon and don't issue further diagnostics about missing brackets. + if (Tok.is(tok::semi)) { + ConsumeToken(); + return; + } + SourceLocation CloseLoc = Tok.getLocation(); if (ExpectAndConsume(tok::r_square)) SkipUntil(tok::r_square); diff --git a/clang/lib/Sema/JumpDiagnostics.cpp b/clang/lib/Sema/JumpDiagnostics.cpp index d33b14a79dc1..9d73881d66d7 100644 --- a/clang/lib/Sema/JumpDiagnostics.cpp +++ b/clang/lib/Sema/JumpDiagnostics.cpp @@ -11,13 +11,14 @@ // //===----------------------------------------------------------------------===// -#include "clang/Sema/SemaInternal.h" #include "clang/AST/DeclCXX.h" #include "clang/AST/Expr.h" #include "clang/AST/ExprCXX.h" #include "clang/AST/StmtCXX.h" #include "clang/AST/StmtObjC.h" #include "clang/AST/StmtOpenMP.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Sema/SemaInternal.h" #include "llvm/ADT/BitVector.h" using namespace clang; @@ -29,6 +30,10 @@ namespace { /// int a[n]; /// L: /// +/// We also detect jumps out of protected scopes when it's not possible to do +/// cleanups properly. Indirect jumps and ASM jumps can't do cleanups because +/// the target is unknown. Return statements with \c [[clang::musttail]] cannot +/// handle any cleanups due to the nature of a tail call. class JumpScopeChecker { Sema &S; @@ -68,6 +73,7 @@ class JumpScopeChecker { SmallVector IndirectJumps; SmallVector AsmJumps; + SmallVector MustTailStmts; SmallVector IndirectJumpTargets; SmallVector AsmJumpTargets; public: @@ -81,6 +87,7 @@ class JumpScopeChecker { void VerifyJumps(); void VerifyIndirectOrAsmJumps(bool IsAsmGoto); + void VerifyMustTailStmts(); void NoteJumpIntoScopes(ArrayRef ToScopes); void DiagnoseIndirectOrAsmJump(Stmt *IG, unsigned IGScope, LabelDecl *Target, unsigned TargetScope); @@ -88,6 +95,7 @@ class JumpScopeChecker { unsigned JumpDiag, unsigned JumpDiagWarning, unsigned JumpDiagCXX98Compat); void CheckGotoStmt(GotoStmt *GS); + const Attr *GetMustTailAttr(AttributedStmt *AS); unsigned GetDeepestCommonScope(unsigned A, unsigned B); }; @@ -109,6 +117,7 @@ JumpScopeChecker::JumpScopeChecker(Stmt *Body, Sema &s) VerifyJumps(); VerifyIndirectOrAsmJumps(false); VerifyIndirectOrAsmJumps(true); + VerifyMustTailStmts(); } /// GetDeepestCommonScope - Finds the innermost scope enclosing the @@ -580,6 +589,15 @@ void JumpScopeChecker::BuildScopeInformation(Stmt *S, LabelAndGotoScopes[S] = ParentScope; break; + case Stmt::AttributedStmtClass: { + AttributedStmt *AS = cast(S); + if (GetMustTailAttr(AS)) { + LabelAndGotoScopes[AS] = ParentScope; + MustTailStmts.push_back(AS); + } + break; + } + default: if (auto *ED = dyn_cast(S)) { if (!ED->isStandaloneDirective()) { @@ -971,6 +989,24 @@ void JumpScopeChecker::CheckGotoStmt(GotoStmt *GS) { } } +void JumpScopeChecker::VerifyMustTailStmts() { + for (AttributedStmt *AS : MustTailStmts) { + for (unsigned I = LabelAndGotoScopes[AS]; I; I = Scopes[I].ParentScope) { + if (Scopes[I].OutDiag) { + S.Diag(AS->getBeginLoc(), diag::err_musttail_scope); + S.Diag(Scopes[I].Loc, Scopes[I].OutDiag); + } + } + } +} + +const Attr *JumpScopeChecker::GetMustTailAttr(AttributedStmt *AS) { + ArrayRef Attrs = AS->getAttrs(); + const auto *Iter = + llvm::find_if(Attrs, [](const Attr *A) { return isa(A); }); + return Iter != Attrs.end() ? *Iter : nullptr; +} + void Sema::DiagnoseInvalidJumps(Stmt *Body) { (void)JumpScopeChecker(Body, *this); } diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 8d0a95a4ec9c..b388fe142865 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -2146,6 +2146,11 @@ void Sema::setFunctionHasIndirectGoto() { FunctionScopes.back()->setHasIndirectGoto(); } +void Sema::setFunctionHasMustTail() { + if (!FunctionScopes.empty()) + FunctionScopes.back()->setHasMustTail(); +} + BlockScopeInfo *Sema::getCurBlock() { if (FunctionScopes.empty()) return nullptr; diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 86e41e58e2ec..2a3d6270f1ae 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -11585,11 +11585,14 @@ static bool CheckTautologicalComparison(Sema &S, BinaryOperator *E, << OtherIsBooleanDespiteType << *Result << E->getLHS()->getSourceRange() << E->getRHS()->getSourceRange()); } else { - unsigned Diag = (isKnownToHaveUnsignedValue(OriginalOther) && Value == 0) - ? (HasEnumType(OriginalOther) - ? diag::warn_unsigned_enum_always_true_comparison - : diag::warn_unsigned_always_true_comparison) - : diag::warn_tautological_constant_compare; + bool IsCharTy = OtherT.withoutLocalFastQualifiers() == S.Context.CharTy; + unsigned Diag = + (isKnownToHaveUnsignedValue(OriginalOther) && Value == 0) + ? (HasEnumType(OriginalOther) + ? diag::warn_unsigned_enum_always_true_comparison + : IsCharTy ? diag::warn_unsigned_char_always_true_comparison + : diag::warn_unsigned_always_true_comparison) + : diag::warn_tautological_constant_compare; S.Diag(E->getOperatorLoc(), Diag) << RhsConstant << OtherT << E->getOpcodeStr() << OS.str() << *Result diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index fd832859189f..78e5634b9886 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -6088,26 +6088,26 @@ TryToFixInvalidVariablyModifiedTypeSourceInfo(TypeSourceInfo *TInfo, /// Attempt to fold a variable-sized type to a constant-sized type, returning /// true if we were successful. -static bool tryToFixVariablyModifiedVarType(Sema &S, TypeSourceInfo *&TInfo, - QualType &T, SourceLocation Loc, - unsigned FailedFoldDiagID) { +bool Sema::tryToFixVariablyModifiedVarType(TypeSourceInfo *&TInfo, + QualType &T, SourceLocation Loc, + unsigned FailedFoldDiagID) { bool SizeIsNegative; llvm::APSInt Oversized; TypeSourceInfo *FixedTInfo = TryToFixInvalidVariablyModifiedTypeSourceInfo( - TInfo, S.Context, SizeIsNegative, Oversized); + TInfo, Context, SizeIsNegative, Oversized); if (FixedTInfo) { - S.Diag(Loc, diag::ext_vla_folded_to_constant); + Diag(Loc, diag::ext_vla_folded_to_constant); TInfo = FixedTInfo; T = FixedTInfo->getType(); return true; } if (SizeIsNegative) - S.Diag(Loc, diag::err_typecheck_negative_array_size); + Diag(Loc, diag::err_typecheck_negative_array_size); else if (Oversized.getBoolValue()) - S.Diag(Loc, diag::err_array_too_large) << Oversized.toString(10); + Diag(Loc, diag::err_array_too_large) << Oversized.toString(10); else if (FailedFoldDiagID) - S.Diag(Loc, FailedFoldDiagID); + Diag(Loc, FailedFoldDiagID); return false; } @@ -6955,10 +6955,10 @@ NamedDecl *Sema::ActOnVariableDeclarator( } } - // If this variable has a variable-modified type and an initializer, try to + // If this variable has a VLA type and an initializer, try to // fold to a constant-sized type. This is otherwise invalid. - if (D.hasInitializer() && R->isVariablyModifiedType()) - tryToFixVariablyModifiedVarType(*this, TInfo, R, D.getIdentifierLoc(), + if (D.hasInitializer() && R->isVariableArrayType()) + tryToFixVariablyModifiedVarType(TInfo, R, D.getIdentifierLoc(), /*DiagID=*/0); bool IsMemberSpecialization = false; @@ -9746,6 +9746,10 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC, (D.getCXXScopeSpec().getScopeRep()->isDependent() || (!Previous.empty() && CurContext->isDependentContext()))) { // ignore these + } else if (NewFD->isCPUDispatchMultiVersion() || + NewFD->isCPUSpecificMultiVersion()) { + // ignore this, we allow the redeclaration behavior here to create new + // versions of the function. } else { // The user tried to provide an out-of-line definition for a // function that is a member of a class or namespace, but there @@ -16840,7 +16844,7 @@ FieldDecl *Sema::CheckFieldDecl(DeclarationName Name, QualType T, // than a variably modified type. if (!InvalidDecl && T->isVariablyModifiedType()) { if (!tryToFixVariablyModifiedVarType( - *this, TInfo, T, Loc, diag::err_typecheck_field_variable_size)) + TInfo, T, Loc, diag::err_typecheck_field_variable_size)) InvalidDecl = true; } @@ -17068,7 +17072,7 @@ Decl *Sema::ActOnIvar(Scope *S, // than a variably modified type. else if (T->isVariablyModifiedType()) { if (!tryToFixVariablyModifiedVarType( - *this, TInfo, T, Loc, diag::err_typecheck_ivar_variable_size)) + TInfo, T, Loc, diag::err_typecheck_ivar_variable_size)) D.setInvalidType(); } diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index a3ca0f3c0994..ea9bc91d3501 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -6707,7 +6707,7 @@ ExprResult Sema::BuildResolvedCallExpr(Expr *Fn, NamedDecl *NDecl, } if (Caller->hasAttr() && ((!FDecl || !FDecl->hasAttr()))) { - Diag(Fn->getExprLoc(), diag::err_anyx86_interrupt_regsave); + Diag(Fn->getExprLoc(), diag::warn_anyx86_interrupt_regsave); if (FDecl) Diag(FDecl->getLocation(), diag::note_callee_decl) << FDecl; } @@ -6974,9 +6974,12 @@ Sema::BuildCompoundLiteralExpr(SourceLocation LParenLoc, TypeSourceInfo *TInfo, diag::err_array_incomplete_or_sizeless_type, SourceRange(LParenLoc, LiteralExpr->getSourceRange().getEnd()))) return ExprError(); - if (literalType->isVariableArrayType()) - return ExprError(Diag(LParenLoc, diag::err_variable_object_no_init) - << SourceRange(LParenLoc, LiteralExpr->getSourceRange().getEnd())); + if (literalType->isVariableArrayType()) { + if (!tryToFixVariablyModifiedVarType(TInfo, literalType, LParenLoc, + diag::err_variable_object_no_init)) { + return ExprError(); + } + } } else if (!literalType->isDependentType() && RequireCompleteType(LParenLoc, literalType, diag::err_typecheck_decl_incomplete_type, diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 3d169ab02b78..b2c14d39144e 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -1007,21 +1007,33 @@ static bool isIdiomaticBraceElisionEntity(const InitializedEntity &Entity) { // // (where std::array is an aggregate struct containing a single array field. - // FIXME: Should aggregate initialization of a struct with a single - // base class and no members also suppress the warning? - if (Entity.getKind() != InitializedEntity::EK_Member || !Entity.getParent()) + if (!Entity.getParent()) return false; - auto *ParentRD = - Entity.getParent()->getType()->castAs()->getDecl(); - if (CXXRecordDecl *CXXRD = dyn_cast(ParentRD)) - if (CXXRD->getNumBases()) - return false; + // Allows elide brace initialization for aggregates with empty base. + if (Entity.getKind() == InitializedEntity::EK_Base) { + auto *ParentRD = + Entity.getParent()->getType()->castAs()->getDecl(); + CXXRecordDecl *CXXRD = cast(ParentRD); + return CXXRD->getNumBases() == 1 && CXXRD->field_empty(); + } + + // Allow brace elision if the only subobject is a field. + if (Entity.getKind() == InitializedEntity::EK_Member) { + auto *ParentRD = + Entity.getParent()->getType()->castAs()->getDecl(); + if (CXXRecordDecl *CXXRD = dyn_cast(ParentRD)) { + if (CXXRD->getNumBases()) { + return false; + } + } + auto FieldIt = ParentRD->field_begin(); + assert(FieldIt != ParentRD->field_end() && + "no fields but have initializer for member?"); + return ++FieldIt == ParentRD->field_end(); + } - auto FieldIt = ParentRD->field_begin(); - assert(FieldIt != ParentRD->field_end() && - "no fields but have initializer for member?"); - return ++FieldIt == ParentRD->field_end(); + return false; } /// Check whether the range of the initializer \p ParentIList from element diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 4e0181ed72d2..177022d64812 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -4598,6 +4598,17 @@ StmtResult Sema::ActOnOpenMPRegionEnd(StmtResult S, } } } + if (ThisCaptureRegion == OMPD_parallel) { + // Capture temp arrays for inscan reductions. + for (OMPClause *C : Clauses) { + if (auto *RC = dyn_cast(C)) { + if (RC->getModifier() != OMPC_REDUCTION_inscan) + continue; + for (Expr *E : RC->copy_array_temps()) + MarkDeclarationsReferencedInExpr(E); + } + } + } if (++CompletedRegions == CaptureRegions.size()) DSAStack->setBodyComplete(); SR = ActOnCapturedRegionEnd(SR.get()); diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp index a258b2b3f98f..6c06bdb7ab8c 100644 --- a/clang/lib/Sema/SemaStmt.cpp +++ b/clang/lib/Sema/SemaStmt.cpp @@ -10,17 +10,16 @@ // //===----------------------------------------------------------------------===// -#include "clang/Sema/Ownership.h" -#include "clang/Sema/SemaInternal.h" #include "clang/AST/ASTContext.h" #include "clang/AST/ASTDiagnostic.h" #include "clang/AST/ASTLambda.h" -#include "clang/AST/CharUnits.h" #include "clang/AST/CXXInheritance.h" +#include "clang/AST/CharUnits.h" #include "clang/AST/DeclObjC.h" #include "clang/AST/EvaluatedExprVisitor.h" #include "clang/AST/ExprCXX.h" #include "clang/AST/ExprObjC.h" +#include "clang/AST/IgnoreExpr.h" #include "clang/AST/RecursiveASTVisitor.h" #include "clang/AST/StmtCXX.h" #include "clang/AST/StmtObjC.h" @@ -30,8 +29,10 @@ #include "clang/Lex/Preprocessor.h" #include "clang/Sema/Initialization.h" #include "clang/Sema/Lookup.h" +#include "clang/Sema/Ownership.h" #include "clang/Sema/Scope.h" #include "clang/Sema/ScopeInfo.h" +#include "clang/Sema/SemaInternal.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" @@ -558,6 +559,17 @@ Sema::ActOnLabelStmt(SourceLocation IdentLoc, LabelDecl *TheDecl, StmtResult Sema::BuildAttributedStmt(SourceLocation AttrsLoc, ArrayRef Attrs, Stmt *SubStmt) { + // FIXME: this code should move when a planned refactoring around statement + // attributes lands. + for (const auto *A : Attrs) { + if (A->getKind() == attr::MustTail) { + if (!checkAndRewriteMustTailAttr(SubStmt, *A)) { + return SubStmt; + } + setFunctionHasMustTail(); + } + } + return AttributedStmt::Create(Context, AttrsLoc, Attrs, SubStmt); } @@ -573,6 +585,259 @@ StmtResult Sema::ActOnAttributedStmt(const ParsedAttributesWithRange &Attrs, return SubStmt; } +bool Sema::checkAndRewriteMustTailAttr(Stmt *St, const Attr &MTA) { + ReturnStmt *R = cast(St); + Expr *E = R->getRetValue(); + + if (CurContext->isDependentContext() || (E && E->isInstantiationDependent())) + // We have to suspend our check until template instantiation time. + return true; + + if (!checkMustTailAttr(St, MTA)) + return false; + + // FIXME: Replace Expr::IgnoreImplicitAsWritten() with this function. + // Currently it does not skip implicit constructors in an initialization + // context. + auto IgnoreImplicitAsWritten = [](Expr *E) -> Expr * { + return IgnoreExprNodes(E, IgnoreImplicitAsWrittenSingleStep, + IgnoreElidableImplicitConstructorSingleStep); + }; + + // Now that we have verified that 'musttail' is valid here, rewrite the + // return value to remove all implicit nodes, but retain parentheses. + R->setRetValue(IgnoreImplicitAsWritten(E)); + return true; +} + +bool Sema::checkMustTailAttr(const Stmt *St, const Attr &MTA) { + assert(!CurContext->isDependentContext() && + "musttail cannot be checked from a dependent context"); + + // FIXME: Add Expr::IgnoreParenImplicitAsWritten() with this definition. + auto IgnoreParenImplicitAsWritten = [](const Expr *E) -> const Expr * { + return IgnoreExprNodes(const_cast(E), IgnoreParensSingleStep, + IgnoreImplicitAsWrittenSingleStep, + IgnoreElidableImplicitConstructorSingleStep); + }; + + const Expr *E = cast(St)->getRetValue(); + const auto *CE = dyn_cast_or_null(IgnoreParenImplicitAsWritten(E)); + + if (!CE) { + Diag(St->getBeginLoc(), diag::err_musttail_needs_call) << &MTA; + return false; + } + + if (const auto *EWC = dyn_cast(E)) { + if (EWC->cleanupsHaveSideEffects()) { + Diag(St->getBeginLoc(), diag::err_musttail_needs_trivial_args) << &MTA; + return false; + } + } + + // We need to determine the full function type (including "this" type, if any) + // for both caller and callee. + struct FuncType { + enum { + ft_non_member, + ft_static_member, + ft_non_static_member, + ft_pointer_to_member, + } MemberType = ft_non_member; + + QualType This; + const FunctionProtoType *Func; + const CXXMethodDecl *Method = nullptr; + } CallerType, CalleeType; + + auto GetMethodType = [this, St, MTA](const CXXMethodDecl *CMD, FuncType &Type, + bool IsCallee) -> bool { + if (isa(CMD)) { + Diag(St->getBeginLoc(), diag::err_musttail_structors_forbidden) + << IsCallee << isa(CMD); + if (IsCallee) + Diag(CMD->getBeginLoc(), diag::note_musttail_structors_forbidden) + << isa(CMD); + Diag(MTA.getLocation(), diag::note_tail_call_required) << &MTA; + return false; + } + if (CMD->isStatic()) + Type.MemberType = FuncType::ft_static_member; + else { + Type.This = CMD->getThisType()->getPointeeType(); + Type.MemberType = FuncType::ft_non_static_member; + } + Type.Func = CMD->getType()->castAs(); + return true; + }; + + const auto *CallerDecl = dyn_cast(CurContext); + + // Find caller function signature. + if (!CallerDecl) { + int ContextType; + if (isa(CurContext)) + ContextType = 0; + else if (isa(CurContext)) + ContextType = 1; + else + ContextType = 2; + Diag(St->getBeginLoc(), diag::err_musttail_forbidden_from_this_context) + << &MTA << ContextType; + return false; + } else if (const auto *CMD = dyn_cast(CurContext)) { + // Caller is a class/struct method. + if (!GetMethodType(CMD, CallerType, false)) + return false; + } else { + // Caller is a non-method function. + CallerType.Func = CallerDecl->getType()->getAs(); + } + + const Expr *CalleeExpr = CE->getCallee()->IgnoreParens(); + const auto *CalleeBinOp = dyn_cast(CalleeExpr); + SourceLocation CalleeLoc = CE->getCalleeDecl() + ? CE->getCalleeDecl()->getBeginLoc() + : St->getBeginLoc(); + + // Find callee function signature. + if (const CXXMethodDecl *CMD = + dyn_cast_or_null(CE->getCalleeDecl())) { + // Call is: obj.method(), obj->method(), functor(), etc. + if (!GetMethodType(CMD, CalleeType, true)) + return false; + } else if (CalleeBinOp && CalleeBinOp->isPtrMemOp()) { + // Call is: obj->*method_ptr or obj.*method_ptr + const auto *MPT = + CalleeBinOp->getRHS()->getType()->castAs(); + CalleeType.This = QualType(MPT->getClass(), 0); + CalleeType.Func = MPT->getPointeeType()->castAs(); + CalleeType.MemberType = FuncType::ft_pointer_to_member; + } else if (isa(CalleeExpr)) { + Diag(St->getBeginLoc(), diag::err_musttail_structors_forbidden) + << /* IsCallee = */ 1 << /* IsDestructor = */ 1; + Diag(MTA.getLocation(), diag::note_tail_call_required) << &MTA; + return false; + } else { + // Non-method function. + CalleeType.Func = + CalleeExpr->getType()->getPointeeType()->getAs(); + } + + // Both caller and callee must have a prototype (no K&R declarations). + if (!CalleeType.Func || !CallerType.Func) { + Diag(St->getBeginLoc(), diag::err_musttail_needs_prototype) << &MTA; + if (!CalleeType.Func && CE->getDirectCallee()) { + Diag(CE->getDirectCallee()->getBeginLoc(), + diag::note_musttail_fix_non_prototype); + } + if (!CallerType.Func) + Diag(CallerDecl->getBeginLoc(), diag::note_musttail_fix_non_prototype); + return false; + } + + // Caller and callee must have matching calling conventions. + // + // Some calling conventions are physically capable of supporting tail calls + // even if the function types don't perfectly match. LLVM is currently too + // strict to allow this, but if LLVM added support for this in the future, we + // could exit early here and skip the remaining checks if the functions are + // using such a calling convention. + if (CallerType.Func->getCallConv() != CalleeType.Func->getCallConv()) { + if (const auto *ND = dyn_cast_or_null(CE->getCalleeDecl())) + Diag(St->getBeginLoc(), diag::err_musttail_callconv_mismatch) + << true << ND->getDeclName(); + else + Diag(St->getBeginLoc(), diag::err_musttail_callconv_mismatch) << false; + Diag(CalleeLoc, diag::note_musttail_callconv_mismatch) + << FunctionType::getNameForCallConv(CallerType.Func->getCallConv()) + << FunctionType::getNameForCallConv(CalleeType.Func->getCallConv()); + Diag(MTA.getLocation(), diag::note_tail_call_required) << &MTA; + return false; + } + + if (CalleeType.Func->isVariadic() || CallerType.Func->isVariadic()) { + Diag(St->getBeginLoc(), diag::err_musttail_no_variadic) << &MTA; + return false; + } + + // Caller and callee must match in whether they have a "this" parameter. + if (CallerType.This.isNull() != CalleeType.This.isNull()) { + if (const auto *ND = dyn_cast_or_null(CE->getCalleeDecl())) { + Diag(St->getBeginLoc(), diag::err_musttail_member_mismatch) + << CallerType.MemberType << CalleeType.MemberType << true + << ND->getDeclName(); + Diag(CalleeLoc, diag::note_musttail_callee_defined_here) + << ND->getDeclName(); + } else + Diag(St->getBeginLoc(), diag::err_musttail_member_mismatch) + << CallerType.MemberType << CalleeType.MemberType << false; + Diag(MTA.getLocation(), diag::note_tail_call_required) << &MTA; + return false; + } + + auto CheckTypesMatch = [this](FuncType CallerType, FuncType CalleeType, + PartialDiagnostic &PD) -> bool { + enum { + ft_different_class, + ft_parameter_arity, + ft_parameter_mismatch, + ft_return_type, + }; + + auto DoTypesMatch = [this, &PD](QualType A, QualType B, + unsigned Select) -> bool { + if (!Context.hasSimilarType(A, B)) { + PD << Select << A.getUnqualifiedType() << B.getUnqualifiedType(); + return false; + } + return true; + }; + + if (!CallerType.This.isNull() && + !DoTypesMatch(CallerType.This, CalleeType.This, ft_different_class)) + return false; + + if (!DoTypesMatch(CallerType.Func->getReturnType(), + CalleeType.Func->getReturnType(), ft_return_type)) + return false; + + if (CallerType.Func->getNumParams() != CalleeType.Func->getNumParams()) { + PD << ft_parameter_arity << CallerType.Func->getNumParams() + << CalleeType.Func->getNumParams(); + return false; + } + + ArrayRef CalleeParams = CalleeType.Func->getParamTypes(); + ArrayRef CallerParams = CallerType.Func->getParamTypes(); + size_t N = CallerType.Func->getNumParams(); + for (size_t I = 0; I < N; I++) { + if (!DoTypesMatch(CalleeParams[I], CallerParams[I], + ft_parameter_mismatch)) { + PD << static_cast(I) + 1; + return false; + } + } + + return true; + }; + + PartialDiagnostic PD = PDiag(diag::note_musttail_mismatch); + if (!CheckTypesMatch(CallerType, CalleeType, PD)) { + if (const auto *ND = dyn_cast_or_null(CE->getCalleeDecl())) + Diag(St->getBeginLoc(), diag::err_musttail_mismatch) + << true << ND->getDeclName(); + else + Diag(St->getBeginLoc(), diag::err_musttail_mismatch) << false; + Diag(CalleeLoc, PD); + Diag(MTA.getLocation(), diag::note_tail_call_required) << &MTA; + return false; + } + + return true; +} + namespace { class CommaVisitor : public EvaluatedExprVisitor { typedef EvaluatedExprVisitor Inherited; diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp index 32c6edc77168..56264f4e94b5 100644 --- a/clang/lib/Sema/SemaStmtAttr.cpp +++ b/clang/lib/Sema/SemaStmtAttr.cpp @@ -389,6 +389,12 @@ static Attr *handleNoMergeAttr(Sema &S, Stmt *St, const ParsedAttr &A, return ::new (S.Context) NoMergeAttr(S.Context, A); } +static Attr *handleMustTailAttr(Sema &S, Stmt *St, const ParsedAttr &A, + SourceRange Range) { + // Validation is in Sema::ActOnAttributedStmt(). + return ::new (S.Context) MustTailAttr(S.Context, A); +} + static Attr *handleLikely(Sema &S, Stmt *St, const ParsedAttr &A, SourceRange Range) { @@ -694,6 +700,8 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A, return handleSuppressAttr(S, St, A, Range); case ParsedAttr::AT_NoMerge: return handleNoMergeAttr(S, St, A, Range); + case ParsedAttr::AT_MustTail: + return handleMustTailAttr(S, St, A, Range); case ParsedAttr::AT_Likely: return handleLikely(S, St, A, Range); case ParsedAttr::AT_Unlikely: diff --git a/clang/lib/StaticAnalyzer/Core/RegionStore.cpp b/clang/lib/StaticAnalyzer/Core/RegionStore.cpp index 5acc51674e9a..4ffa1aacb41f 100644 --- a/clang/lib/StaticAnalyzer/Core/RegionStore.cpp +++ b/clang/lib/StaticAnalyzer/Core/RegionStore.cpp @@ -1478,7 +1478,7 @@ SVal RegionStoreManager::getBinding(RegionBindingsConstRef B, Loc L, QualType T) return UnknownVal(); if (const FieldRegion* FR = dyn_cast(R)) - return CastRetrievedVal(getBindingForField(B, FR), FR, T); + return svalBuilder.evalCast(getBindingForField(B, FR), T, QualType{}); if (const ElementRegion* ER = dyn_cast(R)) { // FIXME: Here we actually perform an implicit conversion from the loaded @@ -1486,7 +1486,7 @@ SVal RegionStoreManager::getBinding(RegionBindingsConstRef B, Loc L, QualType T) // more intelligently. For example, an 'element' can encompass multiple // bound regions (e.g., several bound bytes), or could be a subset of // a larger value. - return CastRetrievedVal(getBindingForElement(B, ER), ER, T); + return svalBuilder.evalCast(getBindingForElement(B, ER), T, QualType{}); } if (const ObjCIvarRegion *IVR = dyn_cast(R)) { @@ -1496,7 +1496,7 @@ SVal RegionStoreManager::getBinding(RegionBindingsConstRef B, Loc L, QualType T) // reinterpretted, it is possible we stored a different value that could // fit within the ivar. Either we need to cast these when storing them // or reinterpret them lazily (as we do here). - return CastRetrievedVal(getBindingForObjCIvar(B, IVR), IVR, T); + return svalBuilder.evalCast(getBindingForObjCIvar(B, IVR), T, QualType{}); } if (const VarRegion *VR = dyn_cast(R)) { @@ -1506,7 +1506,7 @@ SVal RegionStoreManager::getBinding(RegionBindingsConstRef B, Loc L, QualType T) // variable is reinterpretted, it is possible we stored a different value // that could fit within the variable. Either we need to cast these when // storing them or reinterpret them lazily (as we do here). - return CastRetrievedVal(getBindingForVar(B, VR), VR, T); + return svalBuilder.evalCast(getBindingForVar(B, VR), T, QualType{}); } const SVal *V = B.lookup(R, BindingKey::Direct); diff --git a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp index 9942b7e1423c..a49099384d2a 100644 --- a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp +++ b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp @@ -107,7 +107,7 @@ SVal SValBuilder::convertToArrayIndex(SVal val) { return val; } - return evalCastFromNonLoc(val.castAs(), ArrayIndexTy); + return evalCast(val, ArrayIndexTy, QualType{}); } nonloc::ConcreteInt SValBuilder::makeBoolVal(const CXXBoolLiteralExpr *boolean){ @@ -544,20 +544,39 @@ SVal SValBuilder::evalIntegralCast(ProgramStateRef state, SVal val, // `evalCastKind` and `evalCastSubKind` are helpers //===----------------------------------------------------------------------===// +/// Cast a given SVal to another SVal using given QualType's. +/// \param V -- SVal that should be casted. +/// \param CastTy -- QualType that V should be casted according to. +/// \param OriginalTy -- QualType which is associated to V. It provides +/// additional information about what type the cast performs from. +/// \returns the most appropriate casted SVal. +/// Note: Many cases don't use an exact OriginalTy. It can be extracted +/// from SVal or the cast can performs unconditionaly. Always pass OriginalTy! +/// It can be crucial in certain cases and generates different results. +/// FIXME: If `OriginalTy.isNull()` is true, then cast performs based on CastTy +/// only. This behavior is uncertain and should be improved. SVal SValBuilder::evalCast(SVal V, QualType CastTy, QualType OriginalTy) { - CastTy = Context.getCanonicalType(CastTy); - OriginalTy = Context.getCanonicalType(OriginalTy); - if (CastTy == OriginalTy) + if (CastTy.isNull()) return V; - // FIXME: Move this check to the most appropriate evalCastKind/evalCastSubKind - // function. - // For const casts, casts to void, just propagate the value. - if (!CastTy->isVariableArrayType() && !OriginalTy->isVariableArrayType()) - if (shouldBeModeledWithNoOp(Context, Context.getPointerType(CastTy), - Context.getPointerType(OriginalTy))) + CastTy = Context.getCanonicalType(CastTy); + + const bool IsUnknownOriginalType = OriginalTy.isNull(); + if (!IsUnknownOriginalType) { + OriginalTy = Context.getCanonicalType(OriginalTy); + + if (CastTy == OriginalTy) return V; + // FIXME: Move this check to the most appropriate + // evalCastKind/evalCastSubKind function. For const casts, casts to void, + // just propagate the value. + if (!CastTy->isVariableArrayType() && !OriginalTy->isVariableArrayType()) + if (shouldBeModeledWithNoOp(Context, Context.getPointerType(CastTy), + Context.getPointerType(OriginalTy))) + return V; + } + // Cast SVal according to kinds. switch (V.getBaseKind()) { case SVal::UndefinedValKind: @@ -591,9 +610,9 @@ SVal SValBuilder::evalCastKind(Loc V, QualType CastTy, QualType OriginalTy) { return evalCastSubKind(V.castAs(), CastTy, OriginalTy); case loc::MemRegionValKind: return evalCastSubKind(V.castAs(), CastTy, OriginalTy); - default: - llvm_unreachable("Unknown SVal kind"); } + + llvm_unreachable("Unknown SVal kind"); } SVal SValBuilder::evalCastKind(NonLoc V, QualType CastTy, QualType OriginalTy) { @@ -613,9 +632,9 @@ SVal SValBuilder::evalCastKind(NonLoc V, QualType CastTy, QualType OriginalTy) { case nonloc::PointerToMemberKind: return evalCastSubKind(V.castAs(), CastTy, OriginalTy); - default: - llvm_unreachable("Unknown SVal kind"); } + + llvm_unreachable("Unknown SVal kind"); } SVal SValBuilder::evalCastSubKind(loc::ConcreteInt V, QualType CastTy, @@ -652,10 +671,13 @@ SVal SValBuilder::evalCastSubKind(loc::GotoLabel V, QualType CastTy, return makeLocAsInteger(V, BitWidth); } - // Array to pointer. - if (isa(OriginalTy)) - if (CastTy->isPointerType() || CastTy->isReferenceType()) - return UnknownVal(); + const bool IsUnknownOriginalType = OriginalTy.isNull(); + if (!IsUnknownOriginalType) { + // Array to pointer. + if (isa(OriginalTy)) + if (CastTy->isPointerType() || CastTy->isReferenceType()) + return UnknownVal(); + } // Pointer to any pointer. if (Loc::isLocType(CastTy)) @@ -665,6 +687,11 @@ SVal SValBuilder::evalCastSubKind(loc::GotoLabel V, QualType CastTy, return UnknownVal(); } +static bool hasSameUnqualifiedPointeeType(QualType ty1, QualType ty2) { + return ty1->getPointeeType().getCanonicalType().getTypePtr() == + ty2->getPointeeType().getCanonicalType().getTypePtr(); +} + SVal SValBuilder::evalCastSubKind(loc::MemRegionVal V, QualType CastTy, QualType OriginalTy) { // Pointer to bool. @@ -685,8 +712,12 @@ SVal SValBuilder::evalCastSubKind(loc::MemRegionVal V, QualType CastTy, return makeTruthVal(true, CastTy); } + const bool IsUnknownOriginalType = OriginalTy.isNull(); // Try to cast to array - const auto *ArrayTy = dyn_cast(OriginalTy.getCanonicalType()); + const auto *ArrayTy = + IsUnknownOriginalType + ? nullptr + : dyn_cast(OriginalTy.getCanonicalType()); // Pointer to integer. if (CastTy->isIntegralOrEnumerationType()) { @@ -707,6 +738,29 @@ SVal SValBuilder::evalCastSubKind(loc::MemRegionVal V, QualType CastTy, // Pointer to pointer. if (Loc::isLocType(CastTy)) { + + if (IsUnknownOriginalType) { + // When retrieving symbolic pointer and expecting a non-void pointer, + // wrap them into element regions of the expected type if necessary. + // It is necessary to make sure that the retrieved value makes sense, + // because there's no other cast in the AST that would tell us to cast + // it to the correct pointer type. We might need to do that for non-void + // pointers as well. + // FIXME: We really need a single good function to perform casts for us + // correctly every time we need it. + if (CastTy->isPointerType() && !CastTy->isVoidPointerType()) { + const MemRegion *R = V.getRegion(); + if (const auto *SR = dyn_cast(R)) { + QualType SRTy = SR->getSymbol()->getType(); + if (!hasSameUnqualifiedPointeeType(SRTy, CastTy)) { + R = StateMgr.getStoreManager().castRegion(SR, CastTy); + return loc::MemRegionVal(R); + } + } + } + return V; + } + if (OriginalTy->isIntegralOrEnumerationType() || OriginalTy->isBlockPointerType() || OriginalTy->isFunctionPointerType()) return V; @@ -807,7 +861,10 @@ SVal SValBuilder::evalCastSubKind(nonloc::LocAsInteger V, QualType CastTy, // Pass to Loc function. return evalCastKind(L, CastTy, OriginalTy); - if (Loc::isLocType(CastTy) && OriginalTy->isIntegralOrEnumerationType()) { + const bool IsUnknownOriginalType = OriginalTy.isNull(); + // Pointer as integer to pointer. + if (!IsUnknownOriginalType && Loc::isLocType(CastTy) && + OriginalTy->isIntegralOrEnumerationType()) { if (const MemRegion *R = L.getAsRegion()) if ((R = StateMgr.getStoreManager().castRegion(R, CastTy))) return loc::MemRegionVal(R); @@ -815,9 +872,9 @@ SVal SValBuilder::evalCastSubKind(nonloc::LocAsInteger V, QualType CastTy, } // Pointer as integer with region to integer/pointer. - if (const MemRegion *R = L.getAsRegion()) { + const MemRegion *R = L.getAsRegion(); + if (!IsUnknownOriginalType && R) { if (CastTy->isIntegralOrEnumerationType()) - // Pass to MemRegion function. return evalCastSubKind(loc::MemRegionVal(R), CastTy, OriginalTy); if (Loc::isLocType(CastTy)) { @@ -830,15 +887,28 @@ SVal SValBuilder::evalCastSubKind(nonloc::LocAsInteger V, QualType CastTy, return loc::MemRegionVal(R); } } else { - if (Loc::isLocType(CastTy)) + if (Loc::isLocType(CastTy)) { + if (IsUnknownOriginalType) + return evalCastSubKind(loc::MemRegionVal(R), CastTy, OriginalTy); return L; + } - // FIXME: Correctly support promotions/truncations. - const unsigned CastSize = Context.getIntWidth(CastTy); - if (CastSize == V.getNumBits()) - return V; + SymbolRef SE = nullptr; + if (R) { + if (const SymbolicRegion *SR = + dyn_cast(R->StripCasts())) { + SE = SR->getSymbol(); + } + } - return makeLocAsInteger(L, CastSize); + if (!CastTy->isFloatingType() || !SE || SE->getType()->isFloatingType()) { + // FIXME: Correctly support promotions/truncations. + const unsigned CastSize = Context.getIntWidth(CastTy); + if (CastSize == V.getNumBits()) + return V; + + return makeLocAsInteger(L, CastSize); + } } // Pointer as integer to whatever else. @@ -849,13 +919,13 @@ SVal SValBuilder::evalCastSubKind(nonloc::SymbolVal V, QualType CastTy, QualType OriginalTy) { SymbolRef SE = V.getSymbol(); + const bool IsUnknownOriginalType = OriginalTy.isNull(); // Symbol to bool. - if (CastTy->isBooleanType()) { + if (!IsUnknownOriginalType && CastTy->isBooleanType()) { // Non-float to bool. if (Loc::isLocType(OriginalTy) || OriginalTy->isIntegralOrEnumerationType() || OriginalTy->isMemberPointerType()) { - SymbolRef SE = V.getSymbol(); BasicValueFactory &BVF = getBasicValueFactory(); return makeNonLoc(SE, BO_NE, BVF.getValue(0, SE->getType()), CastTy); } @@ -872,7 +942,9 @@ SVal SValBuilder::evalCastSubKind(nonloc::SymbolVal V, QualType CastTy, if (haveSameType(T, CastTy)) return V; if (!Loc::isLocType(CastTy)) - return makeNonLoc(SE, T, CastTy); + if (!IsUnknownOriginalType || !CastTy->isFloatingType() || + T->isFloatingType()) + return makeNonLoc(SE, T, CastTy); } // Symbol to pointer and whatever else. diff --git a/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp b/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp index 872616fedb4e..e57d92fbcebb 100644 --- a/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp +++ b/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp @@ -22,11 +22,6 @@ using namespace ento; namespace { class SimpleSValBuilder : public SValBuilder { -protected: - SVal dispatchCast(SVal val, QualType castTy) override; - SVal evalCastFromNonLoc(NonLoc val, QualType castTy) override; - SVal evalCastFromLoc(Loc val, QualType castTy) override; - public: SimpleSValBuilder(llvm::BumpPtrAllocator &alloc, ASTContext &context, ProgramStateManager &stateMgr) @@ -61,133 +56,6 @@ SValBuilder *ento::createSimpleSValBuilder(llvm::BumpPtrAllocator &alloc, return new SimpleSValBuilder(alloc, context, stateMgr); } -//===----------------------------------------------------------------------===// -// Transfer function for Casts. -//===----------------------------------------------------------------------===// - -SVal SimpleSValBuilder::dispatchCast(SVal Val, QualType CastTy) { - assert(Val.getAs() || Val.getAs()); - return Val.getAs() ? evalCastFromLoc(Val.castAs(), CastTy) - : evalCastFromNonLoc(Val.castAs(), CastTy); -} - -SVal SimpleSValBuilder::evalCastFromNonLoc(NonLoc val, QualType castTy) { - bool isLocType = Loc::isLocType(castTy); - if (val.getAs()) - return val; - - if (Optional LI = val.getAs()) { - if (isLocType) - return LI->getLoc(); - // FIXME: Correctly support promotions/truncations. - unsigned castSize = Context.getIntWidth(castTy); - if (castSize == LI->getNumBits()) - return val; - return makeLocAsInteger(LI->getLoc(), castSize); - } - - if (SymbolRef se = val.getAsSymbol()) { - QualType T = Context.getCanonicalType(se->getType()); - // If types are the same or both are integers, ignore the cast. - // FIXME: Remove this hack when we support symbolic truncation/extension. - // HACK: If both castTy and T are integers, ignore the cast. This is - // not a permanent solution. Eventually we want to precisely handle - // extension/truncation of symbolic integers. This prevents us from losing - // precision when we assign 'x = y' and 'y' is symbolic and x and y are - // different integer types. - if (haveSameType(T, castTy)) - return val; - - if (!isLocType) - return makeNonLoc(se, T, castTy); - return UnknownVal(); - } - - // If value is a non-integer constant, produce unknown. - if (!val.getAs()) - return UnknownVal(); - - // Handle casts to a boolean type. - if (castTy->isBooleanType()) { - bool b = val.castAs().getValue().getBoolValue(); - return makeTruthVal(b, castTy); - } - - // Only handle casts from integers to integers - if val is an integer constant - // being cast to a non-integer type, produce unknown. - if (!isLocType && !castTy->isIntegralOrEnumerationType()) - return UnknownVal(); - - llvm::APSInt i = val.castAs().getValue(); - BasicVals.getAPSIntType(castTy).apply(i); - - if (isLocType) - return makeIntLocVal(i); - else - return makeIntVal(i); -} - -SVal SimpleSValBuilder::evalCastFromLoc(Loc val, QualType castTy) { - - // Casts from pointers -> pointers, just return the lval. - // - // Casts from pointers -> references, just return the lval. These - // can be introduced by the frontend for corner cases, e.g - // casting from va_list* to __builtin_va_list&. - // - if (Loc::isLocType(castTy) || castTy->isReferenceType()) - return val; - - // FIXME: Handle transparent unions where a value can be "transparently" - // lifted into a union type. - if (castTy->isUnionType()) - return UnknownVal(); - - // Casting a Loc to a bool will almost always be true, - // unless this is a weak function or a symbolic region. - if (castTy->isBooleanType()) { - switch (val.getSubKind()) { - case loc::MemRegionValKind: { - const MemRegion *R = val.castAs().getRegion(); - if (const FunctionCodeRegion *FTR = dyn_cast(R)) - if (const FunctionDecl *FD = dyn_cast(FTR->getDecl())) - if (FD->isWeak()) - // FIXME: Currently we are using an extent symbol here, - // because there are no generic region address metadata - // symbols to use, only content metadata. - return nonloc::SymbolVal(SymMgr.getExtentSymbol(FTR)); - - if (const SymbolicRegion *SymR = R->getSymbolicBase()) - return makeNonLoc(SymR->getSymbol(), BO_NE, - BasicVals.getZeroWithPtrWidth(), castTy); - - // FALL-THROUGH - LLVM_FALLTHROUGH; - } - - case loc::GotoLabelKind: - // Labels and non-symbolic memory regions are always true. - return makeTruthVal(true, castTy); - } - } - - if (castTy->isIntegralOrEnumerationType()) { - unsigned BitWidth = Context.getIntWidth(castTy); - - if (!val.getAs()) - return makeLocAsInteger(val, BitWidth); - - llvm::APSInt i = val.castAs().getValue(); - BasicVals.getAPSIntType(castTy).apply(i); - return makeIntVal(i); - } - - // All other cases: return 'UnknownVal'. This includes casting pointers - // to floats, which is probably badness it itself, but this is a good - // intermediate solution until we do something better. - return UnknownVal(); -} - //===----------------------------------------------------------------------===// // Transfer function for unary operators. //===----------------------------------------------------------------------===// @@ -276,10 +144,10 @@ SVal SimpleSValBuilder::MakeSymIntVal(const SymExpr *LHS, } // Idempotent ops (like a*1) can still change the type of an expression. - // Wrap the LHS up in a NonLoc again and let evalCastFromNonLoc do the + // Wrap the LHS up in a NonLoc again and let evalCast do the // dirty work. if (isIdempotent) - return evalCastFromNonLoc(nonloc::SymbolVal(LHS), resultTy); + return evalCast(nonloc::SymbolVal(LHS), resultTy, QualType{}); // If we reach this point, the expression cannot be simplified. // Make a SymbolVal for the entire expression, after converting the RHS. @@ -525,10 +393,11 @@ SVal SimpleSValBuilder::evalBinOpNN(ProgramStateRef state, case BO_Sub: if (resultTy->isIntegralOrEnumerationType()) return makeIntVal(0, resultTy); - return evalCastFromNonLoc(makeIntVal(0, /*isUnsigned=*/false), resultTy); + return evalCast(makeIntVal(0, /*isUnsigned=*/false), resultTy, + QualType{}); case BO_Or: case BO_And: - return evalCastFromNonLoc(lhs, resultTy); + return evalCast(lhs, resultTy, QualType{}); } while (1) { @@ -645,12 +514,12 @@ SVal SimpleSValBuilder::evalBinOpNN(ProgramStateRef state, case BO_Shr: // (~0)>>a if (LHSValue.isAllOnesValue() && LHSValue.isSigned()) - return evalCastFromNonLoc(lhs, resultTy); + return evalCast(lhs, resultTy, QualType{}); LLVM_FALLTHROUGH; case BO_Shl: // 0<>a if (LHSValue == 0) - return evalCastFromNonLoc(lhs, resultTy); + return evalCast(lhs, resultTy, QualType{}); return makeSymExprValNN(op, InputLHS, InputRHS, resultTy); case BO_Div: // 0 / x == 0 @@ -867,7 +736,7 @@ SVal SimpleSValBuilder::evalBinOpLL(ProgramStateRef state, default: break; case BO_Sub: - return evalCastFromLoc(lhs, resultTy); + return evalCast(lhs, resultTy, QualType{}); case BO_EQ: case BO_LE: case BO_LT: @@ -904,7 +773,7 @@ SVal SimpleSValBuilder::evalBinOpLL(ProgramStateRef state, SVal ResultVal = lhs.castAs().evalBinOp(BasicVals, op, *rInt); if (Optional Result = ResultVal.getAs()) - return evalCastFromNonLoc(*Result, resultTy); + return evalCast(*Result, resultTy, QualType{}); assert(!ResultVal.getAs() && "Loc-Loc ops should not produce Locs"); return UnknownVal(); @@ -949,11 +818,11 @@ SVal SimpleSValBuilder::evalBinOpLL(ProgramStateRef state, // to be non-NULL. if (rInt->isZeroConstant()) { if (op == BO_Sub) - return evalCastFromLoc(lhs, resultTy); + return evalCast(lhs, resultTy, QualType{}); if (BinaryOperator::isComparisonOp(op)) { QualType boolType = getContext().BoolTy; - NonLoc l = evalCastFromLoc(lhs, boolType).castAs(); + NonLoc l = evalCast(lhs, boolType, QualType{}).castAs(); NonLoc r = makeTruthVal(false, boolType).castAs(); return evalBinOpNN(state, op, l, r, resultTy); } @@ -1035,7 +904,7 @@ SVal SimpleSValBuilder::evalBinOpLL(ProgramStateRef state, Optional LeftIndex = LeftIndexVal.getAs(); if (!LeftIndex) return UnknownVal(); - LeftIndexVal = evalCastFromNonLoc(*LeftIndex, ArrayIndexTy); + LeftIndexVal = evalCast(*LeftIndex, ArrayIndexTy, QualType{}); LeftIndex = LeftIndexVal.getAs(); if (!LeftIndex) return UnknownVal(); @@ -1045,7 +914,7 @@ SVal SimpleSValBuilder::evalBinOpLL(ProgramStateRef state, Optional RightIndex = RightIndexVal.getAs(); if (!RightIndex) return UnknownVal(); - RightIndexVal = evalCastFromNonLoc(*RightIndex, ArrayIndexTy); + RightIndexVal = evalCast(*RightIndex, ArrayIndexTy, QualType{}); RightIndex = RightIndexVal.getAs(); if (!RightIndex) return UnknownVal(); diff --git a/clang/lib/StaticAnalyzer/Core/Store.cpp b/clang/lib/StaticAnalyzer/Core/Store.cpp index ea617bbeeba1..c563b44efc13 100644 --- a/clang/lib/StaticAnalyzer/Core/Store.cpp +++ b/clang/lib/StaticAnalyzer/Core/Store.cpp @@ -394,48 +394,6 @@ SVal StoreManager::attemptDownCast(SVal Base, QualType TargetType, return UnknownVal(); } -static bool hasSameUnqualifiedPointeeType(QualType ty1, QualType ty2) { - return ty1->getPointeeType().getCanonicalType().getTypePtr() == - ty2->getPointeeType().getCanonicalType().getTypePtr(); -} - -/// CastRetrievedVal - Used by subclasses of StoreManager to implement -/// implicit casts that arise from loads from regions that are reinterpreted -/// as another region. -SVal StoreManager::CastRetrievedVal(SVal V, const TypedValueRegion *R, - QualType castTy) { - if (castTy.isNull() || V.isUnknownOrUndef()) - return V; - - // The dispatchCast() call below would convert the int into a float. - // What we want, however, is a bit-by-bit reinterpretation of the int - // as a float, which usually yields nothing garbage. For now skip casts - // from ints to floats. - // TODO: What other combinations of types are affected? - if (castTy->isFloatingType()) { - SymbolRef Sym = V.getAsSymbol(); - if (Sym && !Sym->getType()->isFloatingType()) - return UnknownVal(); - } - - // When retrieving symbolic pointer and expecting a non-void pointer, - // wrap them into element regions of the expected type if necessary. - // SValBuilder::dispatchCast() doesn't do that, but it is necessary to - // make sure that the retrieved value makes sense, because there's no other - // cast in the AST that would tell us to cast it to the correct pointer type. - // We might need to do that for non-void pointers as well. - // FIXME: We really need a single good function to perform casts for us - // correctly every time we need it. - if (castTy->isPointerType() && !castTy->isVoidPointerType()) - if (const auto *SR = dyn_cast_or_null(V.getAsRegion())) { - QualType sr = SR->getSymbol()->getType(); - if (!hasSameUnqualifiedPointeeType(sr, castTy)) - return loc::MemRegionVal(castRegion(SR, castTy)); - } - - return svalBuilder.dispatchCast(V, castTy); -} - SVal StoreManager::getLValueFieldOrIvar(const Decl *D, SVal Base) { if (Base.isUnknownOrUndef()) return Base; diff --git a/clang/lib/Tooling/CMakeLists.txt b/clang/lib/Tooling/CMakeLists.txt index ce7936a53671..0da3dbd0b927 100644 --- a/clang/lib/Tooling/CMakeLists.txt +++ b/clang/lib/Tooling/CMakeLists.txt @@ -35,12 +35,30 @@ if (NOT Python3_EXECUTABLE namespace clang { namespace tooling { +bool NodeIntrospection::hasIntrospectionSupport() { return false; } + NodeLocationAccessors NodeIntrospection::GetLocations(clang::Stmt const *) { return {}; } NodeLocationAccessors NodeIntrospection::GetLocations(clang::Decl const *) { return {}; } +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::CXXCtorInitializer const *) { + return {}; +} +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::NestedNameSpecifierLoc const*) { + return {}; +} +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::TemplateArgumentLoc const*) { + return {}; +} +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::CXXBaseSpecifier const*) { + return {}; +} NodeLocationAccessors NodeIntrospection::GetLocations(clang::DynTypedNode const &) { return {}; @@ -62,11 +80,6 @@ else() set(skip_expensive_processing $,$>>) - file(GENERATE OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/ASTTU.cpp - CONTENT " -#include -") - set(implicitDirs) foreach(implicitDir ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) list(APPEND implicitDirs -I ${implicitDir}) @@ -75,12 +88,11 @@ else() add_custom_command( COMMENT Generate ASTNodeAPI.json OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/ASTNodeAPI.json - DEPENDS clang-ast-dump clang-resource-headers ${CMAKE_CURRENT_BINARY_DIR}/ASTTU.cpp + DEPENDS clang-ast-dump clang-resource-headers COMMAND $ # Skip this in debug mode because parsing AST.h is too slow --skip-processing=${skip_expensive_processing} - --astheader=${CMAKE_CURRENT_BINARY_DIR}/ASTTU.cpp -I ${CMAKE_BINARY_DIR}/lib/clang/${CLANG_VERSION}/include -I ${CMAKE_SOURCE_DIR}/../clang/include -I ${CMAKE_BINARY_DIR}/tools/clang/include diff --git a/clang/lib/Tooling/DumpTool/ASTSrcLocProcessor.cpp b/clang/lib/Tooling/DumpTool/ASTSrcLocProcessor.cpp index d611261dd1a7..a19114a06064 100644 --- a/clang/lib/Tooling/DumpTool/ASTSrcLocProcessor.cpp +++ b/clang/lib/Tooling/DumpTool/ASTSrcLocProcessor.cpp @@ -26,7 +26,11 @@ ASTSrcLocProcessor::ASTSrcLocProcessor(StringRef JsonPath) isDefinition(), isSameOrDerivedFrom( // TODO: Extend this with other clades - namedDecl(hasAnyName("clang::Stmt", "clang::Decl")) + namedDecl(hasAnyName("clang::Stmt", "clang::Decl", + "clang::CXXCtorInitializer", + "clang::NestedNameSpecifierLoc", + "clang::TemplateArgumentLoc", + "clang::CXXBaseSpecifier")) .bind("nodeClade")), optionally(isDerivedFrom(cxxRecordDecl().bind("derivedFrom")))) .bind("className"), @@ -116,22 +120,30 @@ CaptureMethods(std::string TypeString, const clang::CXXRecordDecl *ASTClass, InnerMatcher...); }; - auto BoundNodesVec = - match(findAll(publicAccessor(ofClass(equalsNode(ASTClass)), - returns(asString(TypeString))) - .bind("classMethod")), - *ASTClass, *Result.Context); + auto BoundNodesVec = match( + findAll( + publicAccessor( + ofClass(cxxRecordDecl( + equalsNode(ASTClass), + optionally(isDerivedFrom( + cxxRecordDecl(hasAnyName("clang::Stmt", "clang::Decl")) + .bind("stmtOrDeclBase"))))), + returns(asString(TypeString))) + .bind("classMethod")), + *ASTClass, *Result.Context); std::vector Methods; for (const auto &BN : BoundNodesVec) { + const auto *StmtOrDeclBase = + BN.getNodeAs("stmtOrDeclBase"); if (const auto *Node = BN.getNodeAs("classMethod")) { // Only record the getBeginLoc etc on Stmt etc, because it will call // more-derived implementations pseudo-virtually. - if ((ASTClass->getName() != "Stmt" && ASTClass->getName() != "Decl") && + if (StmtOrDeclBase && (Node->getName() == "getBeginLoc" || Node->getName() == "getEndLoc" || - Node->getName() == "getSourceRange")) { + Node->getName() == "getSourceRange")) continue; - } + // Only record the getExprLoc on Expr, because it will call // more-derived implementations pseudo-virtually. if (ASTClass->getName() != "Expr" && Node->getName() == "getExprLoc") { @@ -145,29 +157,28 @@ CaptureMethods(std::string TypeString, const clang::CXXRecordDecl *ASTClass, void ASTSrcLocProcessor::run(const MatchFinder::MatchResult &Result) { - if (const auto *ASTClass = - Result.Nodes.getNodeAs("className")) { + const auto *ASTClass = + Result.Nodes.getNodeAs("className"); - StringRef ClassName = ASTClass->getName(); + StringRef ClassName = ASTClass->getName(); - ClassData CD; + ClassData CD; - const auto *NodeClade = - Result.Nodes.getNodeAs("nodeClade"); - StringRef CladeName = NodeClade->getName(); + const auto *NodeClade = + Result.Nodes.getNodeAs("nodeClade"); + StringRef CladeName = NodeClade->getName(); - if (const auto *DerivedFrom = - Result.Nodes.getNodeAs("derivedFrom")) - ClassInheritance[ClassName] = DerivedFrom->getName(); + if (const auto *DerivedFrom = + Result.Nodes.getNodeAs("derivedFrom")) + ClassInheritance[ClassName] = DerivedFrom->getName(); - CD.ASTClassLocations = - CaptureMethods("class clang::SourceLocation", ASTClass, Result); - CD.ASTClassRanges = - CaptureMethods("class clang::SourceRange", ASTClass, Result); + CD.ASTClassLocations = + CaptureMethods("class clang::SourceLocation", ASTClass, Result); + CD.ASTClassRanges = + CaptureMethods("class clang::SourceRange", ASTClass, Result); - if (!CD.isEmpty()) { - ClassEntries[ClassName] = CD; - ClassesInClade[CladeName].push_back(ClassName); - } + if (!CD.isEmpty()) { + ClassEntries[ClassName] = CD; + ClassesInClade[CladeName].push_back(ClassName); } } diff --git a/clang/lib/Tooling/DumpTool/ClangSrcLocDump.cpp b/clang/lib/Tooling/DumpTool/ClangSrcLocDump.cpp index 8328977178cc..436d388a99f4 100644 --- a/clang/lib/Tooling/DumpTool/ClangSrcLocDump.cpp +++ b/clang/lib/Tooling/DumpTool/ClangSrcLocDump.cpp @@ -14,6 +14,7 @@ #include "clang/Driver/Tool.h" #include "clang/Frontend/CompilerInstance.h" #include "clang/Frontend/TextDiagnosticPrinter.h" +#include "clang/Lex/PreprocessorOptions.h" #include "clang/Tooling/Tooling.h" #include "llvm/Option/ArgList.h" #include "llvm/Support/CommandLine.h" @@ -30,10 +31,6 @@ static cl::list IncludeDirectories( "I", cl::desc("Include directories to use while compiling"), cl::value_desc("directory"), cl::Required, cl::OneOrMore, cl::Prefix); -static cl::opt - AstHeaderFile("astheader", cl::desc("AST header to parse API from"), - cl::Required, cl::value_desc("AST header file")); - static cl::opt SkipProcessing("skip-processing", cl::desc("Avoid processing the AST header file"), @@ -66,6 +63,8 @@ class ASTSrcLocGenerationAction : public clang::ASTFrontendAction { ASTSrcLocProcessor Processor; }; +static const char Filename[] = "ASTTU.cpp"; + int main(int argc, const char **argv) { cl::ParseCommandLineOptions(argc, argv); @@ -86,7 +85,7 @@ int main(int argc, const char **argv) { [](const std::string &IncDir) { return "-I" + IncDir; }); Args.push_back("-fsyntax-only"); - Args.push_back(AstHeaderFile); + Args.push_back(Filename); std::vector Argv(Args.size(), nullptr); llvm::transform(Args, Argv.begin(), @@ -102,18 +101,23 @@ int main(int argc, const char **argv) { // Don't output diagnostics, because common scenarios such as // cross-compiling fail with diagnostics. This is not fatal, but // just causes attempts to use the introspection API to return no data. - std::string Str; - llvm::raw_string_ostream OS(Str); - TextDiagnosticPrinter DiagnosticPrinter(OS, &*DiagOpts); + TextDiagnosticPrinter DiagnosticPrinter(llvm::nulls(), &*DiagOpts); DiagnosticsEngine Diagnostics( IntrusiveRefCntPtr(new DiagnosticIDs()), &*DiagOpts, &DiagnosticPrinter, false); - FileManager Files(FileSystemOptions(), vfs::getRealFileSystem()); + auto *OFS = new llvm::vfs::OverlayFileSystem(vfs::getRealFileSystem()); + + auto *MemFS = new llvm::vfs::InMemoryFileSystem(); + OFS->pushOverlay(MemFS); + MemFS->addFile(Filename, 0, + MemoryBuffer::getMemBuffer("#include \"clang/AST/AST.h\"\n")); + + auto Files = llvm::makeIntrusiveRefCnt(FileSystemOptions(), OFS); auto Driver = std::make_unique( "clang", llvm::sys::getDefaultTargetTriple(), Diagnostics, - "ast-api-dump-tool", &Files.getVirtualFileSystem()); + "ast-api-dump-tool", OFS); std::unique_ptr Comp( Driver->BuildCompilation(llvm::makeArrayRef(Argv))); @@ -143,12 +147,13 @@ int main(int argc, const char **argv) { // Suppress "2 errors generated" or similar messages Compiler.getDiagnosticOpts().ShowCarets = false; - Compiler.createSourceManager(Files); + Compiler.createSourceManager(*Files); + Compiler.setFileManager(Files.get()); ASTSrcLocGenerationAction ScopedToolAction; Compiler.ExecuteAction(ScopedToolAction); - Files.clearStatCache(); + Files->clearStatCache(); return 0; } diff --git a/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py b/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py index 15a373e52480..b0953df19203 100755 --- a/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py +++ b/clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py @@ -28,12 +28,14 @@ def GeneratePrologue(self): using LocationAndString = SourceLocationMap::value_type; using RangeAndString = SourceRangeMap::value_type; + +bool NodeIntrospection::hasIntrospectionSupport() { return true; } """ def GenerateBaseGetLocationsDeclaration(self, CladeName): self.implementationContent += \ """ -void GetLocationsImpl(std::shared_ptr const& Prefix, +void GetLocationsImpl(SharedLocationCall const& Prefix, clang::{0} const *Object, SourceLocationMap &Locs, SourceRangeMap &Rngs); """.format(CladeName) @@ -42,7 +44,7 @@ def GenerateSrcLocMethod(self, ClassName, ClassData): self.implementationContent += \ """ -static void GetLocations{0}(std::shared_ptr const& Prefix, +static void GetLocations{0}(SharedLocationCall const& Prefix, clang::{0} const &Object, SourceLocationMap &Locs, SourceRangeMap &Rngs) {{ @@ -53,7 +55,7 @@ def GenerateSrcLocMethod(self, ClassName, ClassData): self.implementationContent += \ """ Locs.insert(LocationAndString(Object.{0}(), - std::make_shared(Prefix, "{0}"))); + llvm::makeIntrusiveRefCnt(Prefix, "{0}"))); """.format(locName) self.implementationContent += '\n' @@ -63,7 +65,7 @@ def GenerateSrcLocMethod(self, ClassName, ClassData): self.implementationContent += \ """ Rngs.insert(RangeAndString(Object.{0}(), - std::make_shared(Prefix, "{0}"))); + llvm::makeIntrusiveRefCnt(Prefix, "{0}"))); """.format(rngName) self.implementationContent += '\n' @@ -83,7 +85,7 @@ def GenerateBaseGetLocationsFunction(self, ASTClassNames, CladeName): 'GetLocations(clang::{0} const *Object)'.format(CladeName) ImplSignature = \ """ -GetLocationsImpl(std::shared_ptr const& Prefix, +GetLocationsImpl(SharedLocationCall const& Prefix, clang::{0} const *Object, SourceLocationMap &Locs, SourceRangeMap &Rngs) """.format(CladeName) @@ -108,7 +110,7 @@ def GenerateBaseGetLocationsFunction(self, ASTClassNames, CladeName): """ {0} NodeIntrospection::{1} {{ NodeLocationAccessors Result; - std::shared_ptr Prefix; + SharedLocationCall Prefix; GetLocationsImpl(Prefix, Object, Result.LocationAccessors, Result.RangeAccessors); @@ -174,12 +176,30 @@ def main(): namespace clang { namespace tooling { +bool NodeIntrospection::hasIntrospectionSupport() { return false; } + NodeLocationAccessors NodeIntrospection::GetLocations(clang::Stmt const *) { return {}; } NodeLocationAccessors NodeIntrospection::GetLocations(clang::Decl const *) { return {}; } +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::CXXCtorInitializer const *) { + return {}; +} +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::NestedNameSpecifierLoc const*) { + return {}; +} +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::TemplateArgumentLoc const*) { + return {}; +} +NodeLocationAccessors NodeIntrospection::GetLocations( + clang::CXXBaseSpecifier const*) { + return {}; +} NodeLocationAccessors NodeIntrospection::GetLocations(clang::DynTypedNode const &) { return {}; diff --git a/clang/lib/Tooling/NodeIntrospection.cpp b/clang/lib/Tooling/NodeIntrospection.cpp index 89e8c19c6ba8..0e3ef3c6a01e 100644 --- a/clang/lib/Tooling/NodeIntrospection.cpp +++ b/clang/lib/Tooling/NodeIntrospection.cpp @@ -13,31 +13,46 @@ #include "clang/Tooling/NodeIntrospection.h" #include "clang/AST/AST.h" +#include "llvm/Support/raw_ostream.h" namespace clang { namespace tooling { -std::string LocationCallFormatterCpp::format(LocationCall *Call) { - SmallVector vec; - while (Call) { - vec.push_back(Call); - Call = Call->on(); +void LocationCallFormatterCpp::print(const LocationCall &Call, + llvm::raw_ostream &OS) { + if (const LocationCall *On = Call.on()) { + print(*On, OS); + if (On->returnsPointer()) + OS << "->"; + else + OS << '.'; } - std::string result; - for (auto *VecCall : llvm::reverse(llvm::makeArrayRef(vec).drop_front())) { - result += - (VecCall->name() + "()" + (VecCall->returnsPointer() ? "->" : ".")) - .str(); + + OS << Call.name(); + if (Call.args().empty()) { + OS << "()"; + return; + } + OS << '(' << Call.args().front(); + for (const std::string &Arg : Call.args().drop_front()) { + OS << ", " << Arg; } - result += (vec.back()->name() + "()").str(); - return result; + OS << ')'; +} + +std::string LocationCallFormatterCpp::format(const LocationCall &Call) { + std::string Result; + llvm::raw_string_ostream OS(Result); + print(Call, OS); + OS.flush(); + return Result; } namespace internal { bool RangeLessThan::operator()( - std::pair> const &LHS, - std::pair> const &RHS) const { + std::pair const &LHS, + std::pair const &RHS) const { if (!LHS.first.isValid() || !RHS.first.isValid()) return false; @@ -51,7 +66,16 @@ bool RangeLessThan::operator()( else if (LHS.first.getEnd() != RHS.first.getEnd()) return false; - return LHS.second->name() < RHS.second->name(); + return LocationCallFormatterCpp::format(*LHS.second) < + LocationCallFormatterCpp::format(*RHS.second); +} +bool RangeLessThan::operator()( + std::pair const &LHS, + std::pair const &RHS) const { + if (LHS.first == RHS.first) + return LocationCallFormatterCpp::format(*LHS.second) < + LocationCallFormatterCpp::format(*RHS.second); + return LHS.first < RHS.first; } } // namespace internal diff --git a/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp b/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp index 6a08c7fd5247..aecfffcbef1f 100644 --- a/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp +++ b/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp @@ -226,6 +226,24 @@ class RenameLocFinder : public RecursiveASTVisitor { return true; } + bool VisitDesignatedInitExpr(const DesignatedInitExpr *E) { + for (const DesignatedInitExpr::Designator &D : E->designators()) { + if (D.isFieldDesignator() && D.getField()) { + const FieldDecl *Decl = D.getField(); + if (isInUSRSet(Decl)) { + auto StartLoc = D.getFieldLoc(); + auto EndLoc = D.getFieldLoc(); + RenameInfos.push_back({StartLoc, EndLoc, + /*FromDecl=*/nullptr, + /*Context=*/nullptr, + /*Specifier=*/nullptr, + /*IgnorePrefixQualifiers=*/true}); + } + } + } + return true; + } + bool VisitCXXConstructorDecl(const CXXConstructorDecl *CD) { // Fix the constructor initializer when renaming class members. for (const auto *Initializer : CD->inits()) { diff --git a/clang/lib/Tooling/Transformer/Stencil.cpp b/clang/lib/Tooling/Transformer/Stencil.cpp index d46087e4b04b..235473b69187 100644 --- a/clang/lib/Tooling/Transformer/Stencil.cpp +++ b/clang/lib/Tooling/Transformer/Stencil.cpp @@ -323,10 +323,23 @@ Error evalData(const AccessData &Data, const MatchFinder::MatchResult &Match, return llvm::make_error(errc::invalid_argument, "Id not bound: " + Data.BaseId); if (!E->isImplicitCXXThis()) { - if (llvm::Optional S = - E->getType()->isAnyPointerType() - ? tooling::buildArrow(*E, *Match.Context) - : tooling::buildDot(*E, *Match.Context)) + llvm::Optional S; + if (E->getType()->isAnyPointerType() || + isSmartPointerType(E->getType(), *Match.Context)) { + // Strip off any operator->. This can only occur inside an actual arrow + // member access, so we treat it as equivalent to an actual object + // expression. + if (const auto *OpCall = dyn_cast(E)) { + if (OpCall->getOperator() == clang::OO_Arrow && + OpCall->getNumArgs() == 1) { + E = OpCall->getArg(0); + } + } + S = tooling::buildArrow(*E, *Match.Context); + } else { + S = tooling::buildDot(*E, *Match.Context); + } + if (S.hasValue()) *Result += *S; else return llvm::make_error( diff --git a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.depend/p1.cpp b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.depend/p1.cpp index 6cf27af3230b..424b159667c3 100644 --- a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.depend/p1.cpp +++ b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.depend/p1.cpp @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -verify -std=c++11 %s -[[carries_dependency, carries_dependency]] int m1(); // expected-error {{attribute 'carries_dependency' cannot appear multiple times in an attribute specifier}} +[[carries_dependency, carries_dependency]] int m1(); // ok [[carries_dependency]] [[carries_dependency]] int m2(); // ok [[carries_dependency()]] int m3(); // expected-error {{attribute 'carries_dependency' cannot have an argument list}} diff --git a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.fallthrough/p1.cpp b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.fallthrough/p1.cpp index 22815bbde9db..675ab3e089b8 100644 --- a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.fallthrough/p1.cpp +++ b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.fallthrough/p1.cpp @@ -61,7 +61,7 @@ void g() { return; case 0: - [[fallthrough, fallthrough]]; // expected-error {{multiple times}} + [[fallthrough, fallthrough]]; // ok case 1: [[fallthrough(0)]]; // expected-error {{argument list}} case 2: diff --git a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p1.cpp b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p1.cpp index 45911958af74..142d4d6f369f 100644 --- a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p1.cpp +++ b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p1.cpp @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -fsyntax-only -std=c++2a -verify %s struct [[nodiscard]] S1 {}; // ok -struct [[nodiscard nodiscard]] S2 {}; // expected-error {{attribute 'nodiscard' cannot appear multiple times in an attribute specifier}} +struct [[nodiscard, nodiscard]] S2 {}; // ok struct [[nodiscard("Wrong")]] S3 {}; [[nodiscard]] int f(); diff --git a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.noreturn/p1.cpp b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.noreturn/p1.cpp index d92356c1ec0b..49c1106b51a5 100644 --- a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.noreturn/p1.cpp +++ b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.noreturn/p1.cpp @@ -14,7 +14,7 @@ template void a4 [[noreturn]] () { return; } // expected-warning {{ // expected-warning@-1 {{function 'a4' declared 'noreturn' should not return}} void a4_test() { a4(); } // expected-note {{in instantiation of function template specialization 'a4' requested here}} -[[noreturn, noreturn]] void b() { throw 0; } // expected-error {{attribute 'noreturn' cannot appear multiple times in an attribute specifier}} +[[noreturn, noreturn]] void b() { throw 0; } // ok [[noreturn]] [[noreturn]] void b2() { throw 0; } // ok [[noreturn()]] void c(); // expected-error {{attribute 'noreturn' cannot have an argument list}} diff --git a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.unused/p1.cpp b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.unused/p1.cpp index 8da2ca7d6d86..2cee3cbcdf8a 100644 --- a/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.unused/p1.cpp +++ b/clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.unused/p1.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fsyntax-only -Wunused -std=c++1z -verify %s struct [[maybe_unused]] S1 {}; // ok -struct [[maybe_unused maybe_unused]] S2 {}; // expected-error {{attribute 'maybe_unused' cannot appear multiple times in an attribute specifier}} +struct [[maybe_unused, maybe_unused]] S2 {}; // ok struct [[maybe_unused("Wrong")]] S3 {}; // expected-error {{'maybe_unused' cannot have an argument list}} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c index 179028804e07..bfed7a1b4b79 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vaadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c index 8e6c592a2595..f684ce213dae 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vadc_vvm_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c index fc783e7bdac7..28348741446e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c @@ -4,10 +4,7 @@ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c index 1a3d0a060c01..12ade5d8b62e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vand_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c index ac623811db8a..fc09310605f3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vasub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c index 3a412c0257c4..a090359b13ae 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vdiv_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c index 25fc2fe4e101..a51128d81ed8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c @@ -4,10 +4,7 @@ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfadd_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c index 77e9feed037b..1357980060c6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfclass_v_u32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c index 640eebf31e5c..46d6844b48bc 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfcvt_x_f_v_i32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c index c38fdbea7cbb..ca2e4a45df61 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfdiv_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c index 4cfa5df5e08f..3e620ec75847 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfirst_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c index 130f599defe1..e4c75c4f6acf 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmacc_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c index fbc3a421e62b..c480b2e3def6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmadd_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c index a77883f52892..7811ac399ee9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmax_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c index d1c5a308fdfe..89bec794912a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c index c471c8451b1e..2d0c24cf17c6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmin_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c index ad19ae848f6a..d99603ef69eb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmsac_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c index 91c393d46f63..ac2698ba262f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmsub_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c index 245231157a36..7918ddd9eca8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmul_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c new file mode 100644 index 000000000000..d0fac7ab80a6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c @@ -0,0 +1,242 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32mf2_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32( [[SRC:%.*]]) [[ATTR6:#.*]] +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32( [[SRC:%.*]]) [[ATTR6:#.*]] +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32mf2_f32(vfloat32mf2_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vfmv_s_f_f32mf2(vfloat32mf2_t dst, float src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m1_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m1_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m1_f32(vfloat32m1_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfmv_s_f_f32m1(vfloat32m1_t dst, float src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m2_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m2_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m2_f32(vfloat32m2_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfmv_s_f_f32m2(vfloat32m2_t dst, float src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m4_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m4_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m4_f32(vfloat32m4_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfmv_s_f_f32m4(vfloat32m4_t dst, float src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m8_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m8_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m8_f32(vfloat32m8_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv16f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv16f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfmv_s_f_f32m8(vfloat32m8_t dst, float src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m1_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m1_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m1_f64(vfloat64m1_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfmv_s_f_f64m1(vfloat64m1_t dst, double src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m2_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m2_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m2_f64(vfloat64m2_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfmv_s_f_f64m2(vfloat64m2_t dst, double src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m4_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m4_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m4_f64(vfloat64m4_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfmv_s_f_f64m4(vfloat64m4_t dst, double src, size_t vl) { + return vfmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m8_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m8_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64( [[SRC:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m8_f64(vfloat64m8_t src) { return vfmv_f(src); } + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR6]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfmv_s_f_f64m8(vfloat64m8_t dst, double src, size_t vl) { + return vfmv_s(dst, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c index af9394f63980..b2d0780b828b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfncvt_x_f_w_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c index 816d4aff50a1..3a854a381843 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmacc_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c index 7bddabb00c2a..1d314fcaf65c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmadd_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c index dbffecdc2cc3..c9865da1a124 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmsac_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c index ae28fcdf4bcf..80dfbffc2509 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmsub_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c index 46432daf711a..56bbde126c81 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrdiv_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c index 48340499961c..41566950679b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrec7_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c index c852f998b8ab..f9ff3a64548e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfredmax_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c index daf7cd77a4b4..87206f81b3f6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfredmin_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c index 5d032716bc29..2d931ef87579 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfredsum_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c index d24dbd6e0a87..1543518b962b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrsqrt7_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c index 9a69688bd937..6105e2dbad6e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrsub_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c index 296d97f3f703..5686f4a87f6c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfsgnj_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c index 60847f48ff93..65687a3366d9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c index 81e8d33d9780..aa462de6a38a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c index 6d330b43d333..e6ec7dc67777 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfsqrt_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c index 591e260a8d11..78eeca237a99 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfsub_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c index e62526b45acc..002a922dd8c3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwadd_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c index 95ee8107fe6a..9c4f599d2125 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c index 15e79f5cf249..eca89a545ff6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwmacc_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c index e2148c975281..ccb70d8e3c86 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwmsac_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c index c10067c1f46f..f625969be03e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwmul_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c index aa13e27a6abf..1a4d9e4579ea 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwnmacc_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c index 539f7d60eddd..cdffa9fef669 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwnmsac_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c index e1339bf25124..87c5092b0beb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwredsum_vs_f32mf2_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c index d86264a73225..b4422bcca4fa 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwsub_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c index 043924d35c1e..3f8dd05d5d38 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vid_v_u8mf8_m( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c index 653c8ac4dbe5..7ed891aa7a8c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_viota_m_u8mf8_m( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c index 0b313a0f5c30..dd4f7932210b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vle8_v_i8mf8_m( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c index 5652eda62b25..5229f2fab404 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vloxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c index 75bb6bd792e1..7f7075c78509 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vlse8_v_i8mf8_m( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c index 15fa817c9e90..67f80842422c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vluxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c index d8c9549ecf1c..cd6e4365d54c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmacc_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c index 41ac0b350325..d34d31bc121b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmadc_vvm_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c index aea689906706..2c1721589070 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c index 1d762565fa7b..e15ffbe8b011 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmand_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c index 388fa93a85bc..27bda47bab6d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmax_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c index e2c78736e3ae..4dd57773647e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmerge_vvm_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c index ed73e9a55598..44b949db77bf 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfeq_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c index 5d90b5e72160..b211fa01e389 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfge_vf_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c index 8a3d1da6fc2e..1601d6b1650f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfgt_vf_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c index d0ea18094d42..70785fef4bdd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfle_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c index 4825bbbd664c..56e85013ee5e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmflt_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c index 4093ca0d11d0..4fbff2b1ad51 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfne_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c index 6dd3e7ad4e67..8ed1b4494ed6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmin_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c index 7e0792efcc67..419c5dee6b78 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmnand_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c index 7eed0c6caed1..c5420030bcf5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmnor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c index 9883130869a2..c7f95fe7fda8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c index cc941bffe6d8..7302ed70d94f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsbc_vvm_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c index 03be5a611345..baa09cffe4d7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsbf_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c index c0729e5eb08b..78b2ee179c8a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmseq_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c index d98664edba9f..46acc5481cf2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsgt_vx_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c index 0e6b39d63b1b..1beb5b50cce3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsif_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c index dcfce37e9e43..ed32bc3bde6d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsle_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c index 742d189eec00..e5ae791ea804 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmslt_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c index 12d6e21ba5ca..e6ee3c574b02 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsne_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c index f816cbceea4a..d17e8da37254 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsof_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c index 0a370c7a2b89..16727980db83 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmul_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c new file mode 100644 index 000000000000..41e4be0ac6e3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c @@ -0,0 +1,1886 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8:#.*]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8:#.*]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) { return vmv_v(src, vl); } + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) { return vmv_v(src, vl); } + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) { return vmv_v(src, vl); } + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) { return vmv_v(src, vl); } + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) { + return vmv_v(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8mf8_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf8_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8mf8_i8(vint8mf8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vmv_s_x_i8mf8(vint8mf8_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8mf4_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf4_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8mf4_i8(vint8mf4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vmv_s_x_i8mf4(vint8mf4_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8mf2_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf2_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8mf2_i8(vint8mf2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vmv_s_x_i8mf2(vint8mf2_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m1_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m1_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m1_i8(vint8m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vmv_s_x_i8m1(vint8m1_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m2_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m2_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m2_i8(vint8m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vmv_s_x_i8m2(vint8m2_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m4_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m4_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m4_i8(vint8m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vmv_s_x_i8m4(vint8m4_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m8_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m8_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m8_i8(vint8m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vmv_s_x_i8m8(vint8m8_t dst, int8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16mf4_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16mf4_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16mf4_i16(vint16mf4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vmv_s_x_i16mf4(vint16mf4_t dst, int16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16mf2_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16mf2_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16mf2_i16(vint16mf2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vmv_s_x_i16mf2(vint16mf2_t dst, int16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m1_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m1_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m1_i16(vint16m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vmv_s_x_i16m1(vint16m1_t dst, int16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m2_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m2_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m2_i16(vint16m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vmv_s_x_i16m2(vint16m2_t dst, int16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m4_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m4_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m4_i16(vint16m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vmv_s_x_i16m4(vint16m4_t dst, int16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m8_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m8_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m8_i16(vint16m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vmv_s_x_i16m8(vint16m8_t dst, int16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32mf2_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32mf2_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32mf2_i32(vint32mf2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vmv_s_x_i32mf2(vint32mf2_t dst, int32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m1_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m1_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m1_i32(vint32m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vmv_s_x_i32m1(vint32m1_t dst, int32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m2_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m2_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m2_i32(vint32m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vmv_s_x_i32m2(vint32m2_t dst, int32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m4_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m4_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m4_i32(vint32m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vmv_s_x_i32m4(vint32m4_t dst, int32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m8_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m8_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m8_i32(vint32m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vmv_s_x_i32m8(vint32m8_t dst, int32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m1_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m1_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m1_i64(vint64m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vmv_s_x_i64m1(vint64m1_t dst, int64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m2_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m2_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m2_i64(vint64m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vmv_s_x_i64m2(vint64m2_t dst, int64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m4_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m4_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m4_i64(vint64m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vmv_s_x_i64m4(vint64m4_t dst, int64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m8_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m8_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m8_i64(vint64m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vmv_s_x_i64m8(vint64m8_t dst, int64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8mf8_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8mf8_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8mf8_u8(vuint8mf8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vmv_s_x_u8mf8(vuint8mf8_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8mf4_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8mf4_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8mf4_u8(vuint8mf4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vmv_s_x_u8mf4(vuint8mf4_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8mf2_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8mf2_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8mf2_u8(vuint8mf2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vmv_s_x_u8mf2(vuint8mf2_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m1_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m1_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m1_u8(vuint8m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vmv_s_x_u8m1(vuint8m1_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m2_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m2_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m2_u8(vuint8m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vmv_s_x_u8m2(vuint8m2_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m4_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m4_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m4_u8(vuint8m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vmv_s_x_u8m4(vuint8m4_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m8_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m8_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m8_u8(vuint8m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vmv_s_x_u8m8(vuint8m8_t dst, uint8_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16mf4_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16mf4_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16mf4_u16(vuint16mf4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vmv_s_x_u16mf4(vuint16mf4_t dst, uint16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16mf2_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16mf2_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16mf2_u16(vuint16mf2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vmv_s_x_u16mf2(vuint16mf2_t dst, uint16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m1_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m1_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m1_u16(vuint16m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vmv_s_x_u16m1(vuint16m1_t dst, uint16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m2_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m2_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m2_u16(vuint16m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vmv_s_x_u16m2(vuint16m2_t dst, uint16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m4_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m4_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m4_u16(vuint16m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vmv_s_x_u16m4(vuint16m4_t dst, uint16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m8_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m8_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m8_u16(vuint16m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vmv_s_x_u16m8(vuint16m8_t dst, uint16_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32mf2_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32mf2_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32mf2_u32(vuint32mf2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vmv_s_x_u32mf2(vuint32mf2_t dst, uint32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m1_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m1_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m1_u32(vuint32m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vmv_s_x_u32m1(vuint32m1_t dst, uint32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m2_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m2_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m2_u32(vuint32m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vmv_s_x_u32m2(vuint32m2_t dst, uint32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m4_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m4_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m4_u32(vuint32m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vmv_s_x_u32m4(vuint32m4_t dst, uint32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m8_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m8_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m8_u32(vuint32m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vmv_s_x_u32m8(vuint32m8_t dst, uint32_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m1_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m1_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m1_u64(vuint64m1_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vmv_s_x_u64m1(vuint64m1_t dst, uint64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m2_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m2_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m2_u64(vuint64m2_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vmv_s_x_u64m2(vuint64m2_t dst, uint64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m4_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m4_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m4_u64(vuint64m4_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vmv_s_x_u64m4(vuint64m4_t dst, uint64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m8_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m8_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m8_u64(vuint64m8_t src) { return vmv_x(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) [[ATTR8]] +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vmv_s_x_u64m8(vuint64m8_t dst, uint64_t src, size_t vl) { + return vmv_s(dst, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c index ca5799c6f6f7..abc44ea3e8c8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmxnor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c index 809b4d80cd07..3825212cf694 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmxor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c index 450bd33a8d99..34b570aeb4c1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnclip_wv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c index 6771870536b4..2867cde94068 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnmsac_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c index f71f384135d0..4538f16a4ccc 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnmsub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c index 1000376024a7..d685ceeee982 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnsra_wv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c index 9d17cfc47118..8506b89289b5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnsrl_wv_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c index 168a6f9ee88e..dfbc8a32ae79 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vor_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c index 52f58beab4c3..6d9454622efd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vpopc_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c index 17b893e694b9..898fea1e226f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredand_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c index e6b215d5c31f..80037b200942 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredmax_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c index cefff41a13b6..c3e87dc5c069 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredmin_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c index 034b7ef3eb4c..66b8214d5ef5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredor_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c index 6fdadc8c78f0..2152b924eb37 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredsum_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c index 3c9729ab3994..523bb8c5f5f4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredxor_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c index ff6e320a7574..4a995e0e02ca 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vrem_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c index 1e68480efc71..9468041b1be4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c index 486232ce6ff4..e91ae30b0367 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vrsub_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c index 2e1d8e8a148e..64dc720091b2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c index e9f3b6844a25..2ba1d42b863f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsbc_vvm_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c index b957f296e175..496cba2f7bce 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vse8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c index 026fdbdf5e40..41201fb88fbd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsext_vf2_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c index 744a45f08af6..df3937f318ab 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c index 93c6ec673dfd..97b15e741db9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c index 6cb1239c64c1..3dbb7c2d9018 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c index 907cb04407d7..1b667e291cec 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c index e3fde37a24d8..88313c9fd22e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsll_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c index ca0e02e5ed53..c13bd7505611 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsmul_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c index 08c94ac686ed..8e49b4cd86e1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsoxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c index 9b8a93ee26b5..e67201d46a15 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsra_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c index 46ad59cd5b83..55f0817b4641 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsrl_vv_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c index b787820e6391..da1a35821f73 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsse8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c index c5031598d25e..e747232b40b2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vssra_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c index 35cec9517b2a..d8682a4a190a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vssrl_vv_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c index 9e485c4f8b4b..2cc75be70ddb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vssub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c index 31e047dbe709..88915c72be1c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c index edcddfe1919c..3177e8907a97 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsuxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c index 744ea4d7709d..5d6c2317af6a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwadd_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c index c2a99cb088c7..d872bfce4f26 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwmacc_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c index ea2e12fef8cf..5bc425099401 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwmul_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c index ef6d793ade34..2f047820c22e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwredsum_vs_i8mf8_i16m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c index 9c483f42c82b..07798793be0a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwsub_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c index 42ba2e276a8b..d4b7d06e4ca2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vxor_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c index 2dc9d3d7824d..310fb572254c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vzext_vf2_u16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c index b7a9ee6bcdf5..840cc2c9a525 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vaadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c index 01a4a6f303e9..7499400b7170 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vadc_vvm_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c index 902f5e0bf2ed..567c7abbc463 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c @@ -4,10 +4,7 @@ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c index 33f2836b5cda..a2f895d0c9e1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vand_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c index c7e376be4d80..6bcf1a13a2e7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vasub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c index 3f2138a44fce..162581924cd3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vdiv_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c index 43be374794d4..5e9400abcd8a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c @@ -4,10 +4,7 @@ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfadd_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c index 8068a02b0c39..374e4537095c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfclass_v_u32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c index 87f0a972be38..b9bb920f5563 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfcvt_x_f_v_i32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c index bca8b4c63ed8..cb1ec6f96723 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfdiv_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c index e1201f2c8a19..61af88f9d0b0 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfirst_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c index e0f83ffc9cb6..e72571df4318 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmacc_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c index 01ab8439e639..a4d41219ff91 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmadd_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c index ee4cdb03d1c6..959f901c30df 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmax_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c index be96573d9c55..0abe61e8901d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c index 2230af151f28..48d6552dcaf1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmin_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c index dcbab0cf914d..50962a8ddd31 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmsac_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c index 2c0e35c495df..84cac4d7b665 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmsub_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c index 709f3e776a63..0432ac2f204b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfmul_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c new file mode 100644 index 000000000000..de59e7c4bea9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c @@ -0,0 +1,386 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv1f32.i32(float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv1f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vfmv_v_f_f32mf2(float src, size_t vl) { + return vfmv_v_f_f32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv2f32.i32(float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv2f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfmv_v_f_f32m1(float src, size_t vl) { + return vfmv_v_f_f32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv4f32.i32(float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv4f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfmv_v_f_f32m2(float src, size_t vl) { + return vfmv_v_f_f32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv8f32.i32(float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv8f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfmv_v_f_f32m4(float src, size_t vl) { + return vfmv_v_f_f32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv16f32.i32(float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv16f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfmv_v_f_f32m8(float src, size_t vl) { + return vfmv_v_f_f32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv1f64.i32(double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv1f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfmv_v_f_f64m1(double src, size_t vl) { + return vfmv_v_f_f64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv2f64.i32(double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv2f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfmv_v_f_f64m2(double src, size_t vl) { + return vfmv_v_f_f64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv4f64.i32(double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv4f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfmv_v_f_f64m4(double src, size_t vl) { + return vfmv_v_f_f64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_v_f_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv8f64.i32(double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.v.f.nxv8f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfmv_v_f_f64m8(double src, size_t vl) { + return vfmv_v_f_f64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32mf2_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32mf2_f32(vfloat32mf2_t src) { + return vfmv_f_s_f32mf2_f32(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vfmv_s_f_f32mf2(vfloat32mf2_t dst, float src, size_t vl) { + return vfmv_s_f_f32mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m1_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m1_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m1_f32(vfloat32m1_t src) { + return vfmv_f_s_f32m1_f32(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfmv_s_f_f32m1(vfloat32m1_t dst, float src, size_t vl) { + return vfmv_s_f_f32m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m2_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m2_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m2_f32(vfloat32m2_t src) { + return vfmv_f_s_f32m2_f32(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfmv_s_f_f32m2(vfloat32m2_t dst, float src, size_t vl) { + return vfmv_s_f_f32m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m4_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m4_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m4_f32(vfloat32m4_t src) { + return vfmv_f_s_f32m4_f32(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfmv_s_f_f32m4(vfloat32m4_t dst, float src, size_t vl) { + return vfmv_s_f_f32m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f32m8_f32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret float [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m8_f32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret float [[TMP0]] +// +float test_vfmv_f_s_f32m8_f32(vfloat32m8_t src) { + return vfmv_f_s_f32m8_f32(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv16f32.i32( [[DST:%.*]], float [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv16f32.i64( [[DST:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfmv_s_f_f32m8(vfloat32m8_t dst, float src, size_t vl) { + return vfmv_s_f_f32m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m1_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m1_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m1_f64(vfloat64m1_t src) { + return vfmv_f_s_f64m1_f64(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv1f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfmv_s_f_f64m1(vfloat64m1_t dst, double src, size_t vl) { + return vfmv_s_f_f64m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m2_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m2_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m2_f64(vfloat64m2_t src) { + return vfmv_f_s_f64m2_f64(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv2f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfmv_s_f_f64m2(vfloat64m2_t dst, double src, size_t vl) { + return vfmv_s_f_f64m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m4_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m4_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m4_f64(vfloat64m4_t src) { + return vfmv_f_s_f64m4_f64(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv4f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfmv_s_f_f64m4(vfloat64m4_t dst, double src, size_t vl) { + return vfmv_s_f_f64m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfmv_f_s_f64m8_f64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret double [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m8_f64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret double [[TMP0]] +// +double test_vfmv_f_s_f64m8_f64(vfloat64m8_t src) { + return vfmv_f_s_f64m8_f64(src); +} + +// CHECK-RV32-LABEL: @test_vfmv_s_f_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f64.i32( [[DST:%.*]], double [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfmv_s_f_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfmv.s.f.nxv8f64.i64( [[DST:%.*]], double [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfmv_s_f_f64m8(vfloat64m8_t dst, double src, size_t vl) { + return vfmv_s_f_f64m8(dst, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c index 3f89ca551ddd..2341c3007c69 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfncvt_x_f_w_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c index 30407445af67..dfb2ec8b45ee 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmacc_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c index 79cd39d9c1d3..7143376d2d68 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmadd_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c index 259e60f48052..2d11aef38487 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmsac_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c index a77ee037e8bd..546cb78f95ec 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfnmsub_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c index e47ff2d52edf..c8e643b6f267 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrdiv_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c index a46874f05ca8..28bfb476b14d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrec7_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c index 13ab0a1588cd..303d1663dc8c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfredmax_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c index 6e4b0b114946..8f3c7e42c1e0 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfredmin_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c index 190a6e31c8d0..a2948db87957 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfredsum_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c index 486627504b69..2c32137bff18 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrsqrt7_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c index d2a29ceab1a4..6f78c4c9d0bc 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfrsub_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c index a135be3af2d0..c021a383425e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfsgnj_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c index d7a857fcf715..229ff9428a92 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c index 34d7cf31b74a..ca9e707e850a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c index f87c1e9a2536..63dbdf8819e3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfsqrt_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c index dc8b198db79a..074202d8eaa1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfsub_vv_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c index 4f5ec65bd37d..c70e2a79e89b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwadd_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c index ae01b1e7f34b..72c98cde3414 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32mf2( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c index 0693c164e3f1..bebb0a6de93f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwmacc_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c index cec278eb5ee9..25b73b2079fe 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwmsac_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c index b40af3e22f45..5e5c7822f850 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwmul_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c index 4d15978b6d12..3bd472aa14e5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwnmacc_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c index 44bd012b1726..3de9cbbab7ce 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwnmsac_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c index c010bcf608a8..36dd4b9d71fc 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwredosum_vs_f32mf2_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c index 023ecd72ccf4..5431a2d6f58a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwredsum_vs_f32mf2_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c index 9d75dc9425f8..b386d8d06f22 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vfwsub_vv_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c index 314abf18476b..e85658703398 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vid_v_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c index dd7c7cd17b50..9046eec23f10 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_viota_m_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c index ebbd552b8a7f..3784ec5df40b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vle8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c index 58ab525b03fd..a23dc284c1b1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c @@ -6,12 +6,7 @@ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s \ // RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f \ -// RUN: -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -S -o - %s >/dev/null 2>%t -// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vle8ff_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c new file mode 100644 index 000000000000..6d1e055624b1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c @@ -0,0 +1,3368 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) { + return vlmul_ext_v_i8mf8_i8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf8_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) { + return vlmul_ext_v_i8mf8_i8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf8_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) { + return vlmul_ext_v_i8mf8_i8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf8_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) { + return vlmul_ext_v_i8mf8_i8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf8_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) { + return vlmul_ext_v_i8mf8_i8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf8_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) { + return vlmul_ext_v_i8mf8_i8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf4_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) { + return vlmul_ext_v_i8mf4_i8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf4_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) { + return vlmul_ext_v_i8mf4_i8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf4_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) { + return vlmul_ext_v_i8mf4_i8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf4_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) { + return vlmul_ext_v_i8mf4_i8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf4_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) { + return vlmul_ext_v_i8mf4_i8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf2_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) { + return vlmul_ext_v_i8mf2_i8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf2_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) { + return vlmul_ext_v_i8mf2_i8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf2_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) { + return vlmul_ext_v_i8mf2_i8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8mf2_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) { + return vlmul_ext_v_i8mf2_i8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8m1_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) { + return vlmul_ext_v_i8m1_i8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8m1_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) { + return vlmul_ext_v_i8m1_i8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8m1_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) { + return vlmul_ext_v_i8m1_i8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8m2_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) { + return vlmul_ext_v_i8m2_i8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8m2_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) { + return vlmul_ext_v_i8m2_i8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i8m4_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv32i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m4_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv32i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) { + return vlmul_ext_v_i8m4_i8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf4_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) { + return vlmul_ext_v_i16mf4_i16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf4_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) { + return vlmul_ext_v_i16mf4_i16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf4_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) { + return vlmul_ext_v_i16mf4_i16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf4_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) { + return vlmul_ext_v_i16mf4_i16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf4_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { + return vlmul_ext_v_i16mf4_i16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf2_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) { + return vlmul_ext_v_i16mf2_i16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf2_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) { + return vlmul_ext_v_i16mf2_i16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf2_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) { + return vlmul_ext_v_i16mf2_i16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16mf2_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) { + return vlmul_ext_v_i16mf2_i16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16m1_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) { + return vlmul_ext_v_i16m1_i16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16m1_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) { + return vlmul_ext_v_i16m1_i16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16m1_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) { + return vlmul_ext_v_i16m1_i16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16m2_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) { + return vlmul_ext_v_i16m2_i16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16m2_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) { + return vlmul_ext_v_i16m2_i16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i16m4_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv16i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m4_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv16i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) { + return vlmul_ext_v_i16m4_i16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32mf2_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) { + return vlmul_ext_v_i32mf2_i32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32mf2_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) { + return vlmul_ext_v_i32mf2_i32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32mf2_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) { + return vlmul_ext_v_i32mf2_i32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32mf2_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) { + return vlmul_ext_v_i32mf2_i32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32m1_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) { + return vlmul_ext_v_i32m1_i32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32m1_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) { + return vlmul_ext_v_i32m1_i32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32m1_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) { + return vlmul_ext_v_i32m1_i32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32m2_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) { + return vlmul_ext_v_i32m2_i32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32m2_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) { + return vlmul_ext_v_i32m2_i32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i32m4_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv8i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m4_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv8i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) { + return vlmul_ext_v_i32m4_i32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i64m1_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) { + return vlmul_ext_v_i64m1_i64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i64m1_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) { + return vlmul_ext_v_i64m1_i64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i64m1_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) { + return vlmul_ext_v_i64m1_i64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i64m2_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) { + return vlmul_ext_v_i64m2_i64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i64m2_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { + return vlmul_ext_v_i64m2_i64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_i64m4_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv4i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m4_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv4i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) { + return vlmul_ext_v_i64m4_i64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf8_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) { + return vlmul_ext_v_u8mf8_u8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf8_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) { + return vlmul_ext_v_u8mf8_u8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf8_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) { + return vlmul_ext_v_u8mf8_u8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf8_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) { + return vlmul_ext_v_u8mf8_u8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf8_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) { + return vlmul_ext_v_u8mf8_u8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf8_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv1i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) { + return vlmul_ext_v_u8mf8_u8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf4_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) { + return vlmul_ext_v_u8mf4_u8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf4_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) { + return vlmul_ext_v_u8mf4_u8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf4_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) { + return vlmul_ext_v_u8mf4_u8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf4_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) { + return vlmul_ext_v_u8mf4_u8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf4_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv2i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) { + return vlmul_ext_v_u8mf4_u8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf2_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) { + return vlmul_ext_v_u8mf2_u8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf2_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) { + return vlmul_ext_v_u8mf2_u8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf2_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) { + return vlmul_ext_v_u8mf2_u8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8mf2_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv4i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) { + return vlmul_ext_v_u8mf2_u8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8m1_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) { + return vlmul_ext_v_u8m1_u8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8m1_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) { + return vlmul_ext_v_u8m1_u8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8m1_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv8i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) { + return vlmul_ext_v_u8m1_u8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8m2_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) { + return vlmul_ext_v_u8m2_u8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8m2_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv16i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) { + return vlmul_ext_v_u8m2_u8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u8m4_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv32i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m4_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv64i8.nxv32i8( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) { + return vlmul_ext_v_u8m4_u8m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf4_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) { + return vlmul_ext_v_u16mf4_u16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf4_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) { + return vlmul_ext_v_u16mf4_u16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf4_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) { + return vlmul_ext_v_u16mf4_u16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf4_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) { + return vlmul_ext_v_u16mf4_u16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf4_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv1i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) { + return vlmul_ext_v_u16mf4_u16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf2_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) { + return vlmul_ext_v_u16mf2_u16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf2_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) { + return vlmul_ext_v_u16mf2_u16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf2_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) { + return vlmul_ext_v_u16mf2_u16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16mf2_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv2i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) { + return vlmul_ext_v_u16mf2_u16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16m1_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) { + return vlmul_ext_v_u16m1_u16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16m1_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) { + return vlmul_ext_v_u16m1_u16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16m1_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv4i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) { + return vlmul_ext_v_u16m1_u16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16m2_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) { + return vlmul_ext_v_u16m2_u16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16m2_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv8i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) { + return vlmul_ext_v_u16m2_u16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u16m4_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv16i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m4_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv32i16.nxv16i16( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) { + return vlmul_ext_v_u16m4_u16m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32mf2_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) { + return vlmul_ext_v_u32mf2_u32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32mf2_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) { + return vlmul_ext_v_u32mf2_u32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32mf2_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) { + return vlmul_ext_v_u32mf2_u32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32mf2_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv1i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) { + return vlmul_ext_v_u32mf2_u32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32m1_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) { + return vlmul_ext_v_u32m1_u32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32m1_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) { + return vlmul_ext_v_u32m1_u32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32m1_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv2i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) { + return vlmul_ext_v_u32m1_u32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32m2_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) { + return vlmul_ext_v_u32m2_u32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32m2_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv4i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) { + return vlmul_ext_v_u32m2_u32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u32m4_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv8i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m4_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16i32.nxv8i32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) { + return vlmul_ext_v_u32m4_u32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u64m1_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) { + return vlmul_ext_v_u64m1_u64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u64m1_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) { + return vlmul_ext_v_u64m1_u64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u64m1_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv1i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) { + return vlmul_ext_v_u64m1_u64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u64m2_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) { + return vlmul_ext_v_u64m2_u64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u64m2_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv2i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) { + return vlmul_ext_v_u64m2_u64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_u64m4_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv4i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m4_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8i64.nxv4i64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) { + return vlmul_ext_v_u64m4_u64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32mf2_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) { + return vlmul_ext_v_f32mf2_f32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32mf2_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) { + return vlmul_ext_v_f32mf2_f32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32mf2_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) { + return vlmul_ext_v_f32mf2_f32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32mf2_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv1f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) { + return vlmul_ext_v_f32mf2_f32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32m1_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f32.nxv2f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f32.nxv2f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) { + return vlmul_ext_v_f32m1_f32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32m1_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f32.nxv2f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f32.nxv2f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) { + return vlmul_ext_v_f32m1_f32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32m1_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv2f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv2f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) { + return vlmul_ext_v_f32m1_f32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32m2_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f32.nxv4f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f32.nxv4f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) { + return vlmul_ext_v_f32m2_f32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32m2_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv4f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv4f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) { + return vlmul_ext_v_f32m2_f32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f32m4_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv8f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m4_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv16f32.nxv8f32( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) { + return vlmul_ext_v_f32m4_f32m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f64m1_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2f64.nxv1f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv2f64.nxv1f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) { + return vlmul_ext_v_f64m1_f64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f64m1_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f64.nxv1f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f64.nxv1f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) { + return vlmul_ext_v_f64m1_f64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f64m1_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f64.nxv1f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f64.nxv1f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) { + return vlmul_ext_v_f64m1_f64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f64m2_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f64.nxv2f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv4f64.nxv2f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) { + return vlmul_ext_v_f64m2_f64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f64m2_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f64.nxv2f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f64.nxv2f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) { + return vlmul_ext_v_f64m2_f64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_ext_v_f64m4_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f64.nxv4f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m4_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.insert.nxv8f64.nxv4f64( undef, [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) { + return vlmul_ext_v_f64m4_f64m8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8mf4_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv2i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf4_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv2i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1) { + return vlmul_trunc_v_i8mf4_i8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1) { + return vlmul_trunc_v_i8mf2_i8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1) { + return vlmul_trunc_v_i8mf2_i8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m1_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1) { + return vlmul_trunc_v_i8m1_i8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m1_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1) { + return vlmul_trunc_v_i8m1_i8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m1_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1) { + return vlmul_trunc_v_i8m1_i8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m2_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1) { + return vlmul_trunc_v_i8m2_i8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m2_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1) { + return vlmul_trunc_v_i8m2_i8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m2_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1) { + return vlmul_trunc_v_i8m2_i8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m2_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1) { + return vlmul_trunc_v_i8m2_i8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m4_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1) { + return vlmul_trunc_v_i8m4_i8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m4_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1) { + return vlmul_trunc_v_i8m4_i8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m4_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1) { + return vlmul_trunc_v_i8m4_i8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m4_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1) { + return vlmul_trunc_v_i8m4_i8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m4_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1) { + return vlmul_trunc_v_i8m4_i8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m8_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1) { + return vlmul_trunc_v_i8m8_i8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m8_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1) { + return vlmul_trunc_v_i8m8_i8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m8_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1) { + return vlmul_trunc_v_i8m8_i8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m8_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1) { + return vlmul_trunc_v_i8m8_i8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m8_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1) { + return vlmul_trunc_v_i8m8_i8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i8m8_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv32i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv32i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1) { + return vlmul_trunc_v_i8m8_i8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16mf2_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv2i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16mf2_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv2i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1) { + return vlmul_trunc_v_i16mf2_i16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m1_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1) { + return vlmul_trunc_v_i16m1_i16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m1_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1) { + return vlmul_trunc_v_i16m1_i16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m2_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1) { + return vlmul_trunc_v_i16m2_i16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m2_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1) { + return vlmul_trunc_v_i16m2_i16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m2_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1) { + return vlmul_trunc_v_i16m2_i16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m4_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1) { + return vlmul_trunc_v_i16m4_i16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m4_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1) { + return vlmul_trunc_v_i16m4_i16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m4_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1) { + return vlmul_trunc_v_i16m4_i16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m4_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1) { + return vlmul_trunc_v_i16m4_i16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m8_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1) { + return vlmul_trunc_v_i16m8_i16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m8_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1) { + return vlmul_trunc_v_i16m8_i16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m8_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1) { + return vlmul_trunc_v_i16m8_i16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m8_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1) { + return vlmul_trunc_v_i16m8_i16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i16m8_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1) { + return vlmul_trunc_v_i16m8_i16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m1_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv2i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m1_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv2i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1) { + return vlmul_trunc_v_i32m1_i32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m2_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1) { + return vlmul_trunc_v_i32m2_i32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m2_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1) { + return vlmul_trunc_v_i32m2_i32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m4_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1) { + return vlmul_trunc_v_i32m4_i32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m4_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1) { + return vlmul_trunc_v_i32m4_i32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m4_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1) { + return vlmul_trunc_v_i32m4_i32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m8_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1) { + return vlmul_trunc_v_i32m8_i32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m8_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1) { + return vlmul_trunc_v_i32m8_i32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m8_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1) { + return vlmul_trunc_v_i32m8_i32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i32m8_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1) { + return vlmul_trunc_v_i32m8_i32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i64m2_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv2i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m2_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv2i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1) { + return vlmul_trunc_v_i64m2_i64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i64m4_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1) { + return vlmul_trunc_v_i64m4_i64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i64m4_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1) { + return vlmul_trunc_v_i64m4_i64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i64m8_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1) { + return vlmul_trunc_v_i64m8_i64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i64m8_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1) { + return vlmul_trunc_v_i64m8_i64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_i64m8_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1) { + return vlmul_trunc_v_i64m8_i64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8mf4_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv2i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf4_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv2i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1) { + return vlmul_trunc_v_u8mf4_u8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1) { + return vlmul_trunc_v_u8mf2_u8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv4i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1) { + return vlmul_trunc_v_u8mf2_u8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m1_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1) { + return vlmul_trunc_v_u8m1_u8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m1_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1) { + return vlmul_trunc_v_u8m1_u8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m1_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv8i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1) { + return vlmul_trunc_v_u8m1_u8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m2_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1) { + return vlmul_trunc_v_u8m2_u8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m2_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1) { + return vlmul_trunc_v_u8m2_u8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m2_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1) { + return vlmul_trunc_v_u8m2_u8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m2_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv16i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1) { + return vlmul_trunc_v_u8m2_u8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m4_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1) { + return vlmul_trunc_v_u8m4_u8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m4_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1) { + return vlmul_trunc_v_u8m4_u8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m4_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1) { + return vlmul_trunc_v_u8m4_u8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m4_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1) { + return vlmul_trunc_v_u8m4_u8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m4_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv32i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1) { + return vlmul_trunc_v_u8m4_u8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m8_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1) { + return vlmul_trunc_v_u8m8_u8mf8(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m8_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1) { + return vlmul_trunc_v_u8m8_u8mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m8_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1) { + return vlmul_trunc_v_u8m8_u8mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m8_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1) { + return vlmul_trunc_v_u8m8_u8m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m8_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1) { + return vlmul_trunc_v_u8m8_u8m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u8m8_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv32i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv32i8.nxv64i8( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1) { + return vlmul_trunc_v_u8m8_u8m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16mf2_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv2i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16mf2_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv2i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1) { + return vlmul_trunc_v_u16mf2_u16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m1_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1) { + return vlmul_trunc_v_u16m1_u16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m1_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv4i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1) { + return vlmul_trunc_v_u16m1_u16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m2_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1) { + return vlmul_trunc_v_u16m2_u16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m2_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1) { + return vlmul_trunc_v_u16m2_u16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m2_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv8i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1) { + return vlmul_trunc_v_u16m2_u16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m4_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1) { + return vlmul_trunc_v_u16m4_u16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m4_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1) { + return vlmul_trunc_v_u16m4_u16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m4_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1) { + return vlmul_trunc_v_u16m4_u16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m4_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv16i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1) { + return vlmul_trunc_v_u16m4_u16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m8_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1) { + return vlmul_trunc_v_u16m8_u16mf4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m8_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1) { + return vlmul_trunc_v_u16m8_u16mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m8_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1) { + return vlmul_trunc_v_u16m8_u16m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m8_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1) { + return vlmul_trunc_v_u16m8_u16m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u16m8_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv16i16.nxv32i16( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1) { + return vlmul_trunc_v_u16m8_u16m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m1_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv2i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m1_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv2i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1) { + return vlmul_trunc_v_u32m1_u32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m2_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1) { + return vlmul_trunc_v_u32m2_u32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m2_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv4i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1) { + return vlmul_trunc_v_u32m2_u32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m4_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1) { + return vlmul_trunc_v_u32m4_u32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m4_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1) { + return vlmul_trunc_v_u32m4_u32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m4_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv8i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1) { + return vlmul_trunc_v_u32m4_u32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m8_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1) { + return vlmul_trunc_v_u32m8_u32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m8_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1) { + return vlmul_trunc_v_u32m8_u32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m8_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1) { + return vlmul_trunc_v_u32m8_u32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u32m8_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8i32.nxv16i32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1) { + return vlmul_trunc_v_u32m8_u32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u64m2_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv2i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m2_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv2i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1) { + return vlmul_trunc_v_u64m2_u64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u64m4_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1) { + return vlmul_trunc_v_u64m4_u64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u64m4_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv4i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1) { + return vlmul_trunc_v_u64m4_u64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u64m8_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1) { + return vlmul_trunc_v_u64m8_u64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u64m8_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1) { + return vlmul_trunc_v_u64m8_u64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_u64m8_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4i64.nxv8i64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1) { + return vlmul_trunc_v_u64m8_u64m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m1_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv2f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m1_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv2f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1) { + return vlmul_trunc_v_f32m1_f32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m2_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv4f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv4f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1) { + return vlmul_trunc_v_f32m2_f32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m2_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f32.nxv4f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f32.nxv4f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1) { + return vlmul_trunc_v_f32m2_f32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m4_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv8f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv8f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1) { + return vlmul_trunc_v_f32m4_f32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m4_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f32.nxv8f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f32.nxv8f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1) { + return vlmul_trunc_v_f32m4_f32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m4_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4f32.nxv8f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4f32.nxv8f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1) { + return vlmul_trunc_v_f32m4_f32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m8_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1) { + return vlmul_trunc_v_f32m8_f32mf2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m8_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1) { + return vlmul_trunc_v_f32m8_f32m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m8_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1) { + return vlmul_trunc_v_f32m8_f32m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f32m8_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv8f32.nxv16f32( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1) { + return vlmul_trunc_v_f32m8_f32m4(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f64m2_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f64.nxv2f64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m2_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f64.nxv2f64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1) { + return vlmul_trunc_v_f64m2_f64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f64m4_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f64.nxv4f64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f64.nxv4f64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1) { + return vlmul_trunc_v_f64m4_f64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f64m4_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f64.nxv4f64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f64.nxv4f64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1) { + return vlmul_trunc_v_f64m4_f64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f64m8_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f64.nxv8f64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv1f64.nxv8f64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1) { + return vlmul_trunc_v_f64m8_f64m1(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f64m8_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f64.nxv8f64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv2f64.nxv8f64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1) { + return vlmul_trunc_v_f64m8_f64m2(op1); +} + +// CHECK-RV32-LABEL: @test_vlmul_trunc_v_f64m8_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4f64.nxv8f64( [[OP1:%.*]], i64 0) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.experimental.vector.extract.nxv4f64.nxv8f64( [[OP1:%.*]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1) { + return vlmul_trunc_v_f64m8_f64m4(op1); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c index 21ca49ded56b..ebb69f1e89c1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S > /dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @testuxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c index f4d108df25f0..1cea88c4eec2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vlse8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c index ae34fbe1909a..0955f8c51513 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S > /dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @testuxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c index 44915ecd355f..241df9f7da99 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmacc_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c index 620421658141..b9aedb391d97 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmadc_vvm_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c index 8980828fb045..c9e04781b85f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c index f89808de7ff8..6bece91ae1cb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmand_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c index 11332ec8b118..ee00964e15ba 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmax_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c index 70424925ba02..772bd92e0afb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmclr_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c index 72dbfa7e58e1..7240d443b895 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmerge_vvm_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c index 455cdb325136..a87a08b79bb7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfeq_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c index d25258997b52..dfe7b61dc54b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfge_vf_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c index 12b39553d4fe..840a317f13d8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfgt_vf_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c index 8ae45a4accf1..f04553e6a010 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfle_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c index 7b87bd985902..d1b83ba86657 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmflt_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c index bbfe91c5c80f..92eb43ef279a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmfne_vv_f32mf2_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c index 7af09cd98de6..85f18840ec16 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmin_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c index c7fd8f589f92..05af7e9585da 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmnand_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c index 2641e55e04c6..996d1ed2b7d2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmnor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c index c6c6e7a5ba93..f423c7292639 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c index 774de45dabf7..797ce31f6e41 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsbc_vvm_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c index df0afc96309f..28301ae4306c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsbf_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c index dd581dc4aa6b..b3235ab9d51c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmseq_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c index bb61dfe7c8fa..595700659398 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmset_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c index 4fcac2adb94b..fc8e61ed60c6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsgt_vx_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c index f3ad1de79f2c..c145dd60db2c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsif_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c index 1959f490357a..bd4b03e6f141 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsle_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c index c872d30dabd9..c55b9ef60f80 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmslt_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c index 432c80994608..b24b91175607 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsne_vv_i8mf8_b64( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c index ccc66d48bdf5..617631d320b8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmsof_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c index 165bd1a12c1d..ee5caa87e48b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmul_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c new file mode 100644 index 000000000000..c6f4237b2e59 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c @@ -0,0 +1,2570 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) { + return vmv_v_v_i8mf8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vmv_v_x_i8mf8(int8_t src, size_t vl) { + return vmv_v_x_i8mf8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) { + return vmv_v_v_i8mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vmv_v_x_i8mf4(int8_t src, size_t vl) { + return vmv_v_x_i8mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) { + return vmv_v_v_i8mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vmv_v_x_i8mf2(int8_t src, size_t vl) { + return vmv_v_x_i8mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) { + return vmv_v_v_i8m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vmv_v_x_i8m1(int8_t src, size_t vl) { + return vmv_v_x_i8m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) { + return vmv_v_v_i8m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vmv_v_x_i8m2(int8_t src, size_t vl) { + return vmv_v_x_i8m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) { + return vmv_v_v_i8m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vmv_v_x_i8m4(int8_t src, size_t vl) { + return vmv_v_x_i8m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) { + return vmv_v_v_i8m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv64i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv64i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vmv_v_x_i8m8(int8_t src, size_t vl) { + return vmv_v_x_i8m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) { + return vmv_v_v_i16mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vmv_v_x_i16mf4(int16_t src, size_t vl) { + return vmv_v_x_i16mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) { + return vmv_v_v_i16mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vmv_v_x_i16mf2(int16_t src, size_t vl) { + return vmv_v_x_i16mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) { + return vmv_v_v_i16m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vmv_v_x_i16m1(int16_t src, size_t vl) { + return vmv_v_x_i16m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) { + return vmv_v_v_i16m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vmv_v_x_i16m2(int16_t src, size_t vl) { + return vmv_v_x_i16m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) { + return vmv_v_v_i16m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vmv_v_x_i16m4(int16_t src, size_t vl) { + return vmv_v_x_i16m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) { + return vmv_v_v_i16m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vmv_v_x_i16m8(int16_t src, size_t vl) { + return vmv_v_x_i16m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) { + return vmv_v_v_i32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vmv_v_x_i32mf2(int32_t src, size_t vl) { + return vmv_v_x_i32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) { + return vmv_v_v_i32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vmv_v_x_i32m1(int32_t src, size_t vl) { + return vmv_v_x_i32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) { + return vmv_v_v_i32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vmv_v_x_i32m2(int32_t src, size_t vl) { + return vmv_v_x_i32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) { + return vmv_v_v_i32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vmv_v_x_i32m4(int32_t src, size_t vl) { + return vmv_v_x_i32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) { + return vmv_v_v_i32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vmv_v_x_i32m8(int32_t src, size_t vl) { + return vmv_v_x_i32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) { + return vmv_v_v_i64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vmv_v_x_i64m1(int64_t src, size_t vl) { + return vmv_v_x_i64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) { + return vmv_v_v_i64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vmv_v_x_i64m2(int64_t src, size_t vl) { + return vmv_v_x_i64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) { + return vmv_v_v_i64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vmv_v_x_i64m4(int64_t src, size_t vl) { + return vmv_v_x_i64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) { + return vmv_v_v_i64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vmv_v_x_i64m8(int64_t src, size_t vl) { + return vmv_v_x_i64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) { + return vmv_v_v_u8mf8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vmv_v_x_u8mf8(uint8_t src, size_t vl) { + return vmv_v_x_u8mf8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) { + return vmv_v_v_u8mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vmv_v_x_u8mf4(uint8_t src, size_t vl) { + return vmv_v_x_u8mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) { + return vmv_v_v_u8mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vmv_v_x_u8mf2(uint8_t src, size_t vl) { + return vmv_v_x_u8mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) { + return vmv_v_v_u8m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vmv_v_x_u8m1(uint8_t src, size_t vl) { + return vmv_v_x_u8m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) { + return vmv_v_v_u8m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vmv_v_x_u8m2(uint8_t src, size_t vl) { + return vmv_v_x_u8m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) { + return vmv_v_v_u8m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vmv_v_x_u8m4(uint8_t src, size_t vl) { + return vmv_v_x_u8m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv64i8.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) { + return vmv_v_v_u8m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv64i8.i32(i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv64i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vmv_v_x_u8m8(uint8_t src, size_t vl) { + return vmv_v_x_u8m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) { + return vmv_v_v_u16mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vmv_v_x_u16mf4(uint16_t src, size_t vl) { + return vmv_v_x_u16mf4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) { + return vmv_v_v_u16mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vmv_v_x_u16mf2(uint16_t src, size_t vl) { + return vmv_v_x_u16mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) { + return vmv_v_v_u16m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vmv_v_x_u16m1(uint16_t src, size_t vl) { + return vmv_v_x_u16m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) { + return vmv_v_v_u16m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vmv_v_x_u16m2(uint16_t src, size_t vl) { + return vmv_v_x_u16m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) { + return vmv_v_v_u16m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vmv_v_x_u16m4(uint16_t src, size_t vl) { + return vmv_v_x_u16m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv32i16.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) { + return vmv_v_v_u16m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i16.i32(i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv32i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vmv_v_x_u16m8(uint16_t src, size_t vl) { + return vmv_v_x_u16m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) { + return vmv_v_v_u32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vmv_v_x_u32mf2(uint32_t src, size_t vl) { + return vmv_v_x_u32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) { + return vmv_v_v_u32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vmv_v_x_u32m1(uint32_t src, size_t vl) { + return vmv_v_x_u32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) { + return vmv_v_v_u32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vmv_v_x_u32m2(uint32_t src, size_t vl) { + return vmv_v_x_u32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) { + return vmv_v_v_u32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vmv_v_x_u32m4(uint32_t src, size_t vl) { + return vmv_v_x_u32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16i32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) { + return vmv_v_v_u32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i32.i32(i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv16i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vmv_v_x_u32m8(uint32_t src, size_t vl) { + return vmv_v_x_u32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) { + return vmv_v_v_u64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv1i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vmv_v_x_u64m1(uint64_t src, size_t vl) { + return vmv_v_x_u64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) { + return vmv_v_v_u64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv2i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vmv_v_x_u64m2(uint64_t src, size_t vl) { + return vmv_v_x_u64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) { + return vmv_v_v_u64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv4i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vmv_v_x_u64m4(uint64_t src, size_t vl) { + return vmv_v_x_u64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8i64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) { + return vmv_v_v_u64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_x_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i64.i32(i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_x_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.x.nxv8i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vmv_v_x_u64m8(uint64_t src, size_t vl) { + return vmv_v_x_u64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) { + return vmv_v_v_f32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) { + return vmv_v_v_f32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) { + return vmv_v_v_f32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) { + return vmv_v_v_f32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16f32.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv16f32.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) { + return vmv_v_v_f32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv1f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) { + return vmv_v_v_f64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv2f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) { + return vmv_v_v_f64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv4f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) { + return vmv_v_v_f64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_v_v_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f64.i32( [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_v_v_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.v.v.nxv8f64.i64( [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) { + return vmv_v_v_f64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8mf8_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf8_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8mf8_i8(vint8mf8_t src) { return vmv_x_s_i8mf8_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vmv_s_x_i8mf8(vint8mf8_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8mf8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8mf4_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf4_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8mf4_i8(vint8mf4_t src) { return vmv_x_s_i8mf4_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vmv_s_x_i8mf4(vint8mf4_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8mf4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8mf2_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf2_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8mf2_i8(vint8mf2_t src) { return vmv_x_s_i8mf2_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vmv_s_x_i8mf2(vint8mf2_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m1_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m1_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m1_i8(vint8m1_t src) { return vmv_x_s_i8m1_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vmv_s_x_i8m1(vint8m1_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m2_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m2_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m2_i8(vint8m2_t src) { return vmv_x_s_i8m2_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vmv_s_x_i8m2(vint8m2_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m4_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m4_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m4_i8(vint8m4_t src) { return vmv_x_s_i8m4_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vmv_s_x_i8m4(vint8m4_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i8m8_i8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i8m8_i8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +int8_t test_vmv_x_s_i8m8_i8(vint8m8_t src) { return vmv_x_s_i8m8_i8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vmv_s_x_i8m8(vint8m8_t dst, int8_t src, size_t vl) { + return vmv_s_x_i8m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16mf4_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16mf4_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16mf4_i16(vint16mf4_t src) { + return vmv_x_s_i16mf4_i16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vmv_s_x_i16mf4(vint16mf4_t dst, int16_t src, size_t vl) { + return vmv_s_x_i16mf4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16mf2_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16mf2_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16mf2_i16(vint16mf2_t src) { + return vmv_x_s_i16mf2_i16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vmv_s_x_i16mf2(vint16mf2_t dst, int16_t src, size_t vl) { + return vmv_s_x_i16mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m1_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m1_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m1_i16(vint16m1_t src) { + return vmv_x_s_i16m1_i16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vmv_s_x_i16m1(vint16m1_t dst, int16_t src, size_t vl) { + return vmv_s_x_i16m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m2_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m2_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m2_i16(vint16m2_t src) { + return vmv_x_s_i16m2_i16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vmv_s_x_i16m2(vint16m2_t dst, int16_t src, size_t vl) { + return vmv_s_x_i16m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m4_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m4_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m4_i16(vint16m4_t src) { + return vmv_x_s_i16m4_i16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vmv_s_x_i16m4(vint16m4_t dst, int16_t src, size_t vl) { + return vmv_s_x_i16m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i16m8_i16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i16m8_i16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +int16_t test_vmv_x_s_i16m8_i16(vint16m8_t src) { + return vmv_x_s_i16m8_i16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vmv_s_x_i16m8(vint16m8_t dst, int16_t src, size_t vl) { + return vmv_s_x_i16m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32mf2_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32mf2_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32mf2_i32(vint32mf2_t src) { + return vmv_x_s_i32mf2_i32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vmv_s_x_i32mf2(vint32mf2_t dst, int32_t src, size_t vl) { + return vmv_s_x_i32mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m1_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m1_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m1_i32(vint32m1_t src) { + return vmv_x_s_i32m1_i32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vmv_s_x_i32m1(vint32m1_t dst, int32_t src, size_t vl) { + return vmv_s_x_i32m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m2_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m2_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m2_i32(vint32m2_t src) { + return vmv_x_s_i32m2_i32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vmv_s_x_i32m2(vint32m2_t dst, int32_t src, size_t vl) { + return vmv_s_x_i32m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m4_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m4_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m4_i32(vint32m4_t src) { + return vmv_x_s_i32m4_i32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vmv_s_x_i32m4(vint32m4_t dst, int32_t src, size_t vl) { + return vmv_s_x_i32m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i32m8_i32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i32m8_i32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +int32_t test_vmv_x_s_i32m8_i32(vint32m8_t src) { + return vmv_x_s_i32m8_i32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vmv_s_x_i32m8(vint32m8_t dst, int32_t src, size_t vl) { + return vmv_s_x_i32m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m1_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m1_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m1_i64(vint64m1_t src) { + return vmv_x_s_i64m1_i64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vmv_s_x_i64m1(vint64m1_t dst, int64_t src, size_t vl) { + return vmv_s_x_i64m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m2_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m2_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m2_i64(vint64m2_t src) { + return vmv_x_s_i64m2_i64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vmv_s_x_i64m2(vint64m2_t dst, int64_t src, size_t vl) { + return vmv_s_x_i64m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m4_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m4_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m4_i64(vint64m4_t src) { + return vmv_x_s_i64m4_i64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vmv_s_x_i64m4(vint64m4_t dst, int64_t src, size_t vl) { + return vmv_s_x_i64m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_i64m8_i64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_i64m8_i64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +int64_t test_vmv_x_s_i64m8_i64(vint64m8_t src) { + return vmv_x_s_i64m8_i64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vmv_s_x_i64m8(vint64m8_t dst, int64_t src, size_t vl) { + return vmv_s_x_i64m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8mf8_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8mf8_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8mf8_u8(vuint8mf8_t src) { return vmv_x_s_u8mf8_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vmv_s_x_u8mf8(vuint8mf8_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8mf8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8mf4_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8mf4_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8mf4_u8(vuint8mf4_t src) { return vmv_x_s_u8mf4_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vmv_s_x_u8mf4(vuint8mf4_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8mf4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8mf2_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8mf2_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8mf2_u8(vuint8mf2_t src) { return vmv_x_s_u8mf2_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vmv_s_x_u8mf2(vuint8mf2_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m1_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m1_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m1_u8(vuint8m1_t src) { return vmv_x_s_u8m1_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vmv_s_x_u8m1(vuint8m1_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m2_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m2_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m2_u8(vuint8m2_t src) { return vmv_x_s_u8m2_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vmv_s_x_u8m2(vuint8m2_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m4_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m4_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m4_u8(vuint8m4_t src) { return vmv_x_s_u8m4_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vmv_s_x_u8m4(vuint8m4_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u8m8_u8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i8 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u8m8_u8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i8 [[TMP0]] +// +uint8_t test_vmv_x_s_u8m8_u8(vuint8m8_t src) { return vmv_x_s_u8m8_u8(src); } + +// CHECK-RV32-LABEL: @test_vmv_s_x_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i32( [[DST:%.*]], i8 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv64i8.i64( [[DST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vmv_s_x_u8m8(vuint8m8_t dst, uint8_t src, size_t vl) { + return vmv_s_x_u8m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16mf4_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16mf4_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16mf4_u16(vuint16mf4_t src) { + return vmv_x_s_u16mf4_u16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vmv_s_x_u16mf4(vuint16mf4_t dst, uint16_t src, size_t vl) { + return vmv_s_x_u16mf4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16mf2_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16mf2_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16mf2_u16(vuint16mf2_t src) { + return vmv_x_s_u16mf2_u16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vmv_s_x_u16mf2(vuint16mf2_t dst, uint16_t src, size_t vl) { + return vmv_s_x_u16mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m1_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m1_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m1_u16(vuint16m1_t src) { + return vmv_x_s_u16m1_u16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vmv_s_x_u16m1(vuint16m1_t dst, uint16_t src, size_t vl) { + return vmv_s_x_u16m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m2_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m2_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m2_u16(vuint16m2_t src) { + return vmv_x_s_u16m2_u16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vmv_s_x_u16m2(vuint16m2_t dst, uint16_t src, size_t vl) { + return vmv_s_x_u16m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m4_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m4_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m4_u16(vuint16m4_t src) { + return vmv_x_s_u16m4_u16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vmv_s_x_u16m4(vuint16m4_t dst, uint16_t src, size_t vl) { + return vmv_s_x_u16m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u16m8_u16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i16 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u16m8_u16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i16 [[TMP0]] +// +uint16_t test_vmv_x_s_u16m8_u16(vuint16m8_t src) { + return vmv_x_s_u16m8_u16(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i32( [[DST:%.*]], i16 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv32i16.i64( [[DST:%.*]], i16 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vmv_s_x_u16m8(vuint16m8_t dst, uint16_t src, size_t vl) { + return vmv_s_x_u16m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32mf2_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32mf2_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32mf2_u32(vuint32mf2_t src) { + return vmv_x_s_u32mf2_u32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vmv_s_x_u32mf2(vuint32mf2_t dst, uint32_t src, size_t vl) { + return vmv_s_x_u32mf2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m1_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m1_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m1_u32(vuint32m1_t src) { + return vmv_x_s_u32m1_u32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vmv_s_x_u32m1(vuint32m1_t dst, uint32_t src, size_t vl) { + return vmv_s_x_u32m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m2_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m2_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m2_u32(vuint32m2_t src) { + return vmv_x_s_u32m2_u32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vmv_s_x_u32m2(vuint32m2_t dst, uint32_t src, size_t vl) { + return vmv_s_x_u32m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m4_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m4_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m4_u32(vuint32m4_t src) { + return vmv_x_s_u32m4_u32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vmv_s_x_u32m4(vuint32m4_t dst, uint32_t src, size_t vl) { + return vmv_s_x_u32m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u32m8_u32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i32 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u32m8_u32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i32 [[TMP0]] +// +uint32_t test_vmv_x_s_u32m8_u32(vuint32m8_t src) { + return vmv_x_s_u32m8_u32(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i32( [[DST:%.*]], i32 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv16i32.i64( [[DST:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vmv_s_x_u32m8(vuint32m8_t dst, uint32_t src, size_t vl) { + return vmv_s_x_u32m8(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m1_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m1_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m1_u64(vuint64m1_t src) { + return vmv_x_s_u64m1_u64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv1i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vmv_s_x_u64m1(vuint64m1_t dst, uint64_t src, size_t vl) { + return vmv_s_x_u64m1(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m2_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m2_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m2_u64(vuint64m2_t src) { + return vmv_x_s_u64m2_u64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv2i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vmv_s_x_u64m2(vuint64m2_t dst, uint64_t src, size_t vl) { + return vmv_s_x_u64m2(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m4_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m4_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m4_u64(vuint64m4_t src) { + return vmv_x_s_u64m4_u64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv4i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vmv_s_x_u64m4(vuint64m4_t dst, uint64_t src, size_t vl) { + return vmv_s_x_u64m4(dst, src, vl); +} + +// CHECK-RV32-LABEL: @test_vmv_x_s_u64m8_u64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) +// CHECK-RV32-NEXT: ret i64 [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_x_s_u64m8_u64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64( [[SRC:%.*]]) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +uint64_t test_vmv_x_s_u64m8_u64(vuint64m8_t src) { + return vmv_x_s_u64m8_u64(src); +} + +// CHECK-RV32-LABEL: @test_vmv_s_x_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i32( [[DST:%.*]], i64 [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmv_s_x_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vmv.s.x.nxv8i64.i64( [[DST:%.*]], i64 [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vmv_s_x_u64m8(vuint64m8_t dst, uint64_t src, size_t vl) { + return vmv_s_x_u64m8(dst, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c index 5f06b751718b..f3ba466fc983 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmxnor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c index 9c843877a83f..644a8b1ad88c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vmxor_mm_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c index 5c3c0cbb0c81..b71b5b1b2345 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnclip_wv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c index f3f2ee6a9905..e8168dc715d3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnmsac_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c index 4cc83f48c1a1..81062689c135 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnmsub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c index 5783d5ef363c..ff2aad906dd2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnsra_wv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c index 38e4f109546a..a1ee09a127b8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vnsrl_wv_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c index 544b52467304..b5e8f7f89017 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vor_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c index a94aa34d1f9f..74e7ae3e6f62 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vpopc_m_b1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c index 268f2e4cd9f0..f2d50d6f131c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredand_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c index 490121430daa..89a7e31bcf0f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredmax_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c index e9e8cac3a5a4..55952709796a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredmin_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c index c933e4a0f73a..f4ba6d6e8df1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredor_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c index e574243d0f2d..09d1936572d9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredsum_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c index 04de6d0e1e6b..61aa929fcbe0 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vredxor_vs_i8mf8_i8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c new file mode 100644 index 000000000000..e3142ab8fe8b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c @@ -0,0 +1,2608 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8mf8_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8mf8_t test_vreinterpret_v_i8mf8_u8mf8(vint8mf8_t src) { + return vreinterpret_v_i8mf8_u8mf8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8mf4_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf4_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8mf4_t test_vreinterpret_v_i8mf4_u8mf4(vint8mf4_t src) { + return vreinterpret_v_i8mf4_u8mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8mf2_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8mf2_t test_vreinterpret_v_i8mf2_u8mf2(vint8mf2_t src) { + return vreinterpret_v_i8mf2_u8mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m1_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src) { + return vreinterpret_v_i8m1_u8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m2_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src) { + return vreinterpret_v_i8m2_u8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m4_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src) { + return vreinterpret_v_i8m4_u8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m8_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src) { + return vreinterpret_v_i8m8_u8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8mf8_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf8_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8mf8_t test_vreinterpret_v_u8mf8_i8mf8(vuint8mf8_t src) { + return vreinterpret_v_u8mf8_i8mf8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8mf4_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf4_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8mf4_t test_vreinterpret_v_u8mf4_i8mf4(vuint8mf4_t src) { + return vreinterpret_v_u8mf4_i8mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8mf2_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8mf2_t test_vreinterpret_v_u8mf2_i8mf2(vuint8mf2_t src) { + return vreinterpret_v_u8mf2_i8mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m1_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src) { + return vreinterpret_v_u8m1_i8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m2_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src) { + return vreinterpret_v_u8m2_i8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m4_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src) { + return vreinterpret_v_u8m4_i8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m8_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src) { + return vreinterpret_v_u8m8_i8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16mf4_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint16mf4_t test_vreinterpret_v_i16mf4_u16mf4(vint16mf4_t src) { + return vreinterpret_v_i16mf4_u16mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16mf2_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint16mf2_t test_vreinterpret_v_i16mf2_u16mf2(vint16mf2_t src) { + return vreinterpret_v_i16mf2_u16mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m1_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src) { + return vreinterpret_v_i16m1_u16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m2_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src) { + return vreinterpret_v_i16m2_u16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m4_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src) { + return vreinterpret_v_i16m4_u16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m8_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src) { + return vreinterpret_v_i16m8_u16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16mf4_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint16mf4_t test_vreinterpret_v_u16mf4_i16mf4(vuint16mf4_t src) { + return vreinterpret_v_u16mf4_i16mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16mf2_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint16mf2_t test_vreinterpret_v_u16mf2_i16mf2(vuint16mf2_t src) { + return vreinterpret_v_u16mf2_i16mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m1_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src) { + return vreinterpret_v_u16m1_i16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m2_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src) { + return vreinterpret_v_u16m2_i16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m4_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src) { + return vreinterpret_v_u16m4_i16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m8_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src) { + return vreinterpret_v_u16m8_i16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32mf2_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint32mf2_t test_vreinterpret_v_i32mf2_u32mf2(vint32mf2_t src) { + return vreinterpret_v_i32mf2_u32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m1_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src) { + return vreinterpret_v_i32m1_u32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m2_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src) { + return vreinterpret_v_i32m2_u32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m4_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src) { + return vreinterpret_v_i32m4_u32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m8_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src) { + return vreinterpret_v_i32m8_u32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32mf2_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint32mf2_t test_vreinterpret_v_u32mf2_i32mf2(vuint32mf2_t src) { + return vreinterpret_v_u32mf2_i32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m1_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src) { + return vreinterpret_v_u32m1_i32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m2_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src) { + return vreinterpret_v_u32m2_i32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m4_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src) { + return vreinterpret_v_u32m4_i32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m8_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src) { + return vreinterpret_v_u32m8_i32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32mf2_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32mf2_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vreinterpret_v_f32mf2_i32mf2(vfloat32mf2_t src) { + return vreinterpret_v_f32mf2_i32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m1_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m1_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src) { + return vreinterpret_v_f32m1_i32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m2_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m2_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src) { + return vreinterpret_v_f32m2_i32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m4_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m4_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src) { + return vreinterpret_v_f32m4_i32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m8_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m8_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src) { + return vreinterpret_v_f32m8_i32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32mf2_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32mf2_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vreinterpret_v_f32mf2_u32mf2(vfloat32mf2_t src) { + return vreinterpret_v_f32mf2_u32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m1_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m1_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src) { + return vreinterpret_v_f32m1_u32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m2_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m2_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src) { + return vreinterpret_v_f32m2_u32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m4_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m4_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src) { + return vreinterpret_v_f32m4_u32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f32m8_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m8_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src) { + return vreinterpret_v_f32m8_u32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32mf2_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vreinterpret_v_i32mf2_f32mf2(vint32mf2_t src) { + return vreinterpret_v_i32mf2_f32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m1_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src) { + return vreinterpret_v_i32m1_f32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m2_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src) { + return vreinterpret_v_i32m2_f32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m4_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src) { + return vreinterpret_v_i32m4_f32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m8_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src) { + return vreinterpret_v_i32m8_f32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32mf2_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vreinterpret_v_u32mf2_f32mf2(vuint32mf2_t src) { + return vreinterpret_v_u32mf2_f32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m1_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src) { + return vreinterpret_v_u32m1_f32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m2_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src) { + return vreinterpret_v_u32m2_f32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m4_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src) { + return vreinterpret_v_u32m4_f32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m8_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src) { + return vreinterpret_v_u32m8_f32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m1_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src) { + return vreinterpret_v_i64m1_u64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m2_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src) { + return vreinterpret_v_i64m2_u64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m4_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src) { + return vreinterpret_v_i64m4_u64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m8_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src) { + return vreinterpret_v_i64m8_u64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m1_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src) { + return vreinterpret_v_u64m1_i64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m2_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src) { + return vreinterpret_v_u64m2_i64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m4_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src) { + return vreinterpret_v_u64m4_i64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m8_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret [[SRC:%.*]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret [[SRC:%.*]] +// +vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src) { + return vreinterpret_v_u64m8_i64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m1_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m1_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src) { + return vreinterpret_v_f64m1_i64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m2_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m2_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src) { + return vreinterpret_v_f64m2_i64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m4_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m4_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src) { + return vreinterpret_v_f64m4_i64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m8_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m8_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src) { + return vreinterpret_v_f64m8_i64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m1_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m1_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src) { + return vreinterpret_v_f64m1_u64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m2_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m2_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src) { + return vreinterpret_v_f64m2_u64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m4_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m4_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src) { + return vreinterpret_v_f64m4_u64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_f64m8_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m8_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vreinterpret_v_f64m8_u64m8(vfloat64m8_t src) { + return vreinterpret_v_f64m8_u64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m1_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src) { + return vreinterpret_v_i64m1_f64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m2_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src) { + return vreinterpret_v_i64m2_f64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m4_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src) { + return vreinterpret_v_i64m4_f64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m8_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src) { + return vreinterpret_v_i64m8_f64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m1_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src) { + return vreinterpret_v_u64m1_f64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m2_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src) { + return vreinterpret_v_u64m2_f64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m4_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src) { + return vreinterpret_v_u64m4_f64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m8_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src) { + return vreinterpret_v_u64m8_f64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8mf4_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf4_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vreinterpret_v_i8mf4_i16mf4(vint8mf4_t src) { + return vreinterpret_v_i8mf4_i16mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8mf2_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vreinterpret_v_i8mf2_i16mf2(vint8mf2_t src) { + return vreinterpret_v_i8mf2_i16mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m1_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src) { + return vreinterpret_v_i8m1_i16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m2_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src) { + return vreinterpret_v_i8m2_i16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m4_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src) { + return vreinterpret_v_i8m4_i16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m8_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src) { + return vreinterpret_v_i8m8_i16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8mf4_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf4_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vreinterpret_v_u8mf4_u16mf4(vuint8mf4_t src) { + return vreinterpret_v_u8mf4_u16mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8mf2_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vreinterpret_v_u8mf2_u16mf2(vuint8mf2_t src) { + return vreinterpret_v_u8mf2_u16mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m1_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src) { + return vreinterpret_v_u8m1_u16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m2_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src) { + return vreinterpret_v_u8m2_u16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m4_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src) { + return vreinterpret_v_u8m4_u16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m8_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src) { + return vreinterpret_v_u8m8_u16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8mf2_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vreinterpret_v_i8mf2_i32mf2(vint8mf2_t src) { + return vreinterpret_v_i8mf2_i32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m1_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src) { + return vreinterpret_v_i8m1_i32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m2_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src) { + return vreinterpret_v_i8m2_i32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m4_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src) { + return vreinterpret_v_i8m4_i32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m8_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src) { + return vreinterpret_v_i8m8_i32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8mf2_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vreinterpret_v_u8mf2_u32mf2(vuint8mf2_t src) { + return vreinterpret_v_u8mf2_u32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m1_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src) { + return vreinterpret_v_u8m1_u32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m2_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src) { + return vreinterpret_v_u8m2_u32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m4_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src) { + return vreinterpret_v_u8m4_u32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m8_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src) { + return vreinterpret_v_u8m8_u32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m1_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src) { + return vreinterpret_v_i8m1_i64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m2_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src) { + return vreinterpret_v_i8m2_i64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m4_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src) { + return vreinterpret_v_i8m4_i64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i8m8_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src) { + return vreinterpret_v_i8m8_i64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m1_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src) { + return vreinterpret_v_u8m1_u64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m2_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src) { + return vreinterpret_v_u8m2_u64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m4_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src) { + return vreinterpret_v_u8m4_u64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u8m8_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src) { + return vreinterpret_v_u8m8_u64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16mf4_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vreinterpret_v_i16mf4_i8mf4(vint16mf4_t src) { + return vreinterpret_v_i16mf4_i8mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16mf2_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vreinterpret_v_i16mf2_i8mf2(vint16mf2_t src) { + return vreinterpret_v_i16mf2_i8mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m1_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src) { + return vreinterpret_v_i16m1_i8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m2_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src) { + return vreinterpret_v_i16m2_i8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m4_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src) { + return vreinterpret_v_i16m4_i8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m8_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src) { + return vreinterpret_v_i16m8_i8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16mf4_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vreinterpret_v_u16mf4_u8mf4(vuint16mf4_t src) { + return vreinterpret_v_u16mf4_u8mf4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16mf2_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vreinterpret_v_u16mf2_u8mf2(vuint16mf2_t src) { + return vreinterpret_v_u16mf2_u8mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m1_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src) { + return vreinterpret_v_u16m1_u8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m2_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src) { + return vreinterpret_v_u16m2_u8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m4_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src) { + return vreinterpret_v_u16m4_u8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m8_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src) { + return vreinterpret_v_u16m8_u8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16mf2_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vreinterpret_v_i16mf2_i32mf2(vint16mf2_t src) { + return vreinterpret_v_i16mf2_i32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m1_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src) { + return vreinterpret_v_i16m1_i32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m2_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src) { + return vreinterpret_v_i16m2_i32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m4_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src) { + return vreinterpret_v_i16m4_i32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m8_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src) { + return vreinterpret_v_i16m8_i32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16mf2_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vreinterpret_v_u16mf2_u32mf2(vuint16mf2_t src) { + return vreinterpret_v_u16mf2_u32mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m1_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src) { + return vreinterpret_v_u16m1_u32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m2_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src) { + return vreinterpret_v_u16m2_u32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m4_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src) { + return vreinterpret_v_u16m4_u32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m8_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src) { + return vreinterpret_v_u16m8_u32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m1_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src) { + return vreinterpret_v_i16m1_i64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m2_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src) { + return vreinterpret_v_i16m2_i64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m4_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src) { + return vreinterpret_v_i16m4_i64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i16m8_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src) { + return vreinterpret_v_i16m8_i64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m1_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src) { + return vreinterpret_v_u16m1_u64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m2_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src) { + return vreinterpret_v_u16m2_u64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m4_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src) { + return vreinterpret_v_u16m4_u64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u16m8_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src) { + return vreinterpret_v_u16m8_u64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32mf2_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vreinterpret_v_i32mf2_i8mf2(vint32mf2_t src) { + return vreinterpret_v_i32mf2_i8mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m1_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src) { + return vreinterpret_v_i32m1_i8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m2_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src) { + return vreinterpret_v_i32m2_i8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m4_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src) { + return vreinterpret_v_i32m4_i8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m8_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src) { + return vreinterpret_v_i32m8_i8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32mf2_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vreinterpret_v_u32mf2_u8mf2(vuint32mf2_t src) { + return vreinterpret_v_u32mf2_u8mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m1_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src) { + return vreinterpret_v_u32m1_u8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m2_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src) { + return vreinterpret_v_u32m2_u8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m4_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src) { + return vreinterpret_v_u32m4_u8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m8_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src) { + return vreinterpret_v_u32m8_u8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32mf2_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vreinterpret_v_i32mf2_i16mf2(vint32mf2_t src) { + return vreinterpret_v_i32mf2_i16mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m1_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src) { + return vreinterpret_v_i32m1_i16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m2_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src) { + return vreinterpret_v_i32m2_i16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m4_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src) { + return vreinterpret_v_i32m4_i16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m8_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src) { + return vreinterpret_v_i32m8_i16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32mf2_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vreinterpret_v_u32mf2_u16mf2(vuint32mf2_t src) { + return vreinterpret_v_u32mf2_u16mf2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m1_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src) { + return vreinterpret_v_u32m1_u16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m2_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src) { + return vreinterpret_v_u32m2_u16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m4_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src) { + return vreinterpret_v_u32m4_u16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m8_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src) { + return vreinterpret_v_u32m8_u16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m1_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src) { + return vreinterpret_v_i32m1_i64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m2_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src) { + return vreinterpret_v_i32m2_i64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m4_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src) { + return vreinterpret_v_i32m4_i64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i32m8_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src) { + return vreinterpret_v_i32m8_i64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m1_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src) { + return vreinterpret_v_u32m1_u64m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m2_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src) { + return vreinterpret_v_u32m2_u64m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m4_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src) { + return vreinterpret_v_u32m4_u64m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u32m8_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src) { + return vreinterpret_v_u32m8_u64m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m1_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src) { + return vreinterpret_v_i64m1_i8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m2_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src) { + return vreinterpret_v_i64m2_i8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m4_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src) { + return vreinterpret_v_i64m4_i8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m8_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src) { + return vreinterpret_v_i64m8_i8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m1_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src) { + return vreinterpret_v_u64m1_u8m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m2_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src) { + return vreinterpret_v_u64m2_u8m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m4_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src) { + return vreinterpret_v_u64m4_u8m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m8_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src) { + return vreinterpret_v_u64m8_u8m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m1_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src) { + return vreinterpret_v_i64m1_i16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m2_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src) { + return vreinterpret_v_i64m2_i16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m4_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src) { + return vreinterpret_v_i64m4_i16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m8_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src) { + return vreinterpret_v_i64m8_i16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m1_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src) { + return vreinterpret_v_u64m1_u16m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m2_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src) { + return vreinterpret_v_u64m2_u16m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m4_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src) { + return vreinterpret_v_u64m4_u16m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m8_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src) { + return vreinterpret_v_u64m8_u16m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m1_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src) { + return vreinterpret_v_i64m1_i32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m2_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src) { + return vreinterpret_v_i64m2_i32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m4_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src) { + return vreinterpret_v_i64m4_i32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_i64m8_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src) { + return vreinterpret_v_i64m8_i32m8(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m1_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src) { + return vreinterpret_v_u64m1_u32m1(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m2_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src) { + return vreinterpret_v_u64m2_u32m2(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m4_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src) { + return vreinterpret_v_u64m4_u32m4(src); +} + +// CHECK-RV32-LABEL: @test_vreinterpret_v_u64m8_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC:%.*]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src) { + return vreinterpret_v_u64m8_u32m8(src); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c index 06e0e8a2749f..0ea20941fdff 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vrem_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c index 0268c4baab9e..d4b8a043f2d6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c index 51f905001e57..bf42d5929996 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vrsub_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c index f81ebc026902..6696cfda36e9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsadd_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c index b8f051b86517..aba0bb212048 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsbc_vvm_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c index facd1aa8c480..69d4e81a8c69 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vse8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c index 5d68209d88a7..5b2b2e47a4b2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c @@ -4,10 +4,7 @@ // RUN: | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \ // RUN: | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsetvl_e8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c index 447ca0595f0b..c4903a4b1023 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c @@ -4,10 +4,7 @@ // RUN: | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \ // RUN: | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsetvlmax_e8m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c index c2634603e65f..99a762f4013a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsext_vf2_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c index c35a3ffa35a8..1f8dfaf1a0d2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c index b1334da4ca1f..540a023a4b28 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c index 46d739ec3401..c4880656b0d6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c index 8c6b99e8617c..13a3d559b116 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c index be5add398e65..88249fe1dab2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsll_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c index e5d709adc3c1..58dea088811c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsmul_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c index b9af7ca76eab..95182217cad7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsoxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c index 4ad0bcae1e2b..a3fe854b308f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsra_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c index 9c5df425af96..4b0f6c32a11f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsrl_vv_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c index 851ba6fed9cc..96d96f21baf8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsse8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c index 717070e4b6b8..70d7f2416004 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vssra_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c index 11b918bad79a..f9a755d0e4bd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vssrl_vv_u8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c index de2ae7a9e91b..18781430ca77 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vssub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c index 4ac644ebbbfd..f348e9a6e9ea 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsub_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c index 593cccb25d2a..a78799fa0233 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c @@ -4,10 +4,7 @@ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ -// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vsuxei8_v_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c new file mode 100644 index 000000000000..a322b74d760c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c @@ -0,0 +1,538 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV32-LABEL: @test_vundefined_i8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8mf8_t test_vundefined_i8mf8() { return vundefined_i8mf8(); } + +// CHECK-RV32-LABEL: @test_vundefined_i8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8mf4_t test_vundefined_i8mf4() { return vundefined_i8mf4(); } + +// CHECK-RV32-LABEL: @test_vundefined_i8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8mf2_t test_vundefined_i8mf2() { return vundefined_i8mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8m1_t test_vundefined_i8m1() { return vundefined_i8m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_i8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8m2_t test_vundefined_i8m2() { return vundefined_i8m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8m4_t test_vundefined_i8m4() { return vundefined_i8m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_i8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint8m8_t test_vundefined_i8m8() { return vundefined_i8m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_i16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint16mf4_t test_vundefined_i16mf4() { return vundefined_i16mf4(); } + +// CHECK-RV32-LABEL: @test_vundefined_i16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint16mf2_t test_vundefined_i16mf2() { return vundefined_i16mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint16m1_t test_vundefined_i16m1() { return vundefined_i16m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_i16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint16m2_t test_vundefined_i16m2() { return vundefined_i16m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint16m4_t test_vundefined_i16m4() { return vundefined_i16m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_i16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint16m8_t test_vundefined_i16m8() { return vundefined_i16m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_i32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint32mf2_t test_vundefined_i32mf2() { return vundefined_i32mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint32m1_t test_vundefined_i32m1() { return vundefined_i32m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_i32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint32m2_t test_vundefined_i32m2() { return vundefined_i32m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint32m4_t test_vundefined_i32m4() { return vundefined_i32m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_i32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint32m8_t test_vundefined_i32m8() { return vundefined_i32m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint64m1_t test_vundefined_i64m1() { return vundefined_i64m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint64m2_t test_vundefined_i64m2() { return vundefined_i64m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint64m4_t test_vundefined_i64m4() { return vundefined_i64m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vint64m8_t test_vundefined_i64m8() { return vundefined_i64m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8mf8_t test_vundefined_u8mf8() { return vundefined_u8mf8(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8mf4_t test_vundefined_u8mf4() { return vundefined_u8mf4(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8mf2_t test_vundefined_u8mf2() { return vundefined_u8mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8m1_t test_vundefined_u8m1() { return vundefined_u8m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8m2_t test_vundefined_u8m2() { return vundefined_u8m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8m4_t test_vundefined_u8m4() { return vundefined_u8m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint8m8_t test_vundefined_u8m8() { return vundefined_u8m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint16mf4_t test_vundefined_u16mf4() { return vundefined_u16mf4(); } + +// CHECK-RV32-LABEL: @test_vundefined_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint16mf2_t test_vundefined_u16mf2() { return vundefined_u16mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint16m1_t test_vundefined_u16m1() { return vundefined_u16m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint16m2_t test_vundefined_u16m2() { return vundefined_u16m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint16m4_t test_vundefined_u16m4() { return vundefined_u16m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint16m8_t test_vundefined_u16m8() { return vundefined_u16m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint32mf2_t test_vundefined_u32mf2() { return vundefined_u32mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint32m1_t test_vundefined_u32m1() { return vundefined_u32m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint32m2_t test_vundefined_u32m2() { return vundefined_u32m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint32m4_t test_vundefined_u32m4() { return vundefined_u32m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint32m8_t test_vundefined_u32m8() { return vundefined_u32m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint64m1_t test_vundefined_u64m1() { return vundefined_u64m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint64m2_t test_vundefined_u64m2() { return vundefined_u64m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint64m4_t test_vundefined_u64m4() { return vundefined_u64m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vuint64m8_t test_vundefined_u64m8() { return vundefined_u64m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat32mf2_t test_vundefined_f32mf2() { return vundefined_f32mf2(); } + +// CHECK-RV32-LABEL: @test_vundefined_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat32m1_t test_vundefined_f32m1() { return vundefined_f32m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat32m2_t test_vundefined_f32m2() { return vundefined_f32m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat32m4_t test_vundefined_f32m4() { return vundefined_f32m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat32m8_t test_vundefined_f32m8() { return vundefined_f32m8(); } + +// CHECK-RV32-LABEL: @test_vundefined_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat64m1_t test_vundefined_f64m1() { return vundefined_f64m1(); } + +// CHECK-RV32-LABEL: @test_vundefined_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat64m2_t test_vundefined_f64m2() { return vundefined_f64m2(); } + +// CHECK-RV32-LABEL: @test_vundefined_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat64m4_t test_vundefined_f64m4() { return vundefined_f64m4(); } + +// CHECK-RV32-LABEL: @test_vundefined_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: ret undef +// +// CHECK-RV64-LABEL: @test_vundefined_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret undef +// +vfloat64m8_t test_vundefined_f64m8() { return vundefined_f64m8(); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c index 34071a7af902..d8f9d4daf4cb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwadd_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c index caffdf75e923..45783f2b736e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwmacc_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c index 7d4a02f22583..b327c8efc1b1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwmul_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c index 3ccba3e5949e..c767d82467c9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwredsum_vs_i8mf8_i16m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c index dd29f7262775..ed6ca5e8b34b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vwsub_vv_i16mf4( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c index 2351c55bd7f5..f256cbfedd7d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vxor_vv_i8mf8( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c index 5fd4609715f9..d9ed4606e907 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c @@ -2,9 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s -// ASM-NOT: warning #include // CHECK-RV32-LABEL: @test_vzext_vf2_u16mf4( diff --git a/clang/test/CodeGen/aarch64-args-hfa.c b/clang/test/CodeGen/aarch64-args-hfa.c new file mode 100644 index 000000000000..4abdc426a5ed --- /dev/null +++ b/clang/test/CodeGen/aarch64-args-hfa.c @@ -0,0 +1,69 @@ +// RUN: %clang_cc1 -triple aarch64-none-eabi -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS +// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-abi darwinpcs -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DARWIN +// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - -x c %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS + +typedef struct { + float v[2]; +} S0; + +// CHECK: define{{.*}} float @f0([2 x float] %h.coerce) +float f0(S0 h) { + return h.v[0]; +} + +// CHECK: define{{.*}} float @f0_call() +// CHECK: %call = call float @f0([2 x float] %1) +float f0_call() { + S0 h = {1.0f, 2.0f}; + return f0(h); +} +typedef struct { + double v[2]; +} S1; + +// CHECK: define{{.*}} double @f1([2 x double] %h.coerce) +double f1(S1 h) { + return h.v[0]; +} + +// CHECK: define{{.*}} double @f1_call() +// CHECK: %call = call double @f1([2 x double] %1 +double f1_call() { + S1 h = {1.0, 2.0}; + return f1(h); +} +typedef struct { + __attribute__((__aligned__(16))) double v[2]; +} S2; + +// CHECK-AAPCS: define{{.*}} double @f2([2 x double] alignstack(16) %h.coerce) +// CHECK-DARWIN: define{{.*}} double @f2([2 x double] %h.coerce) +double f2(S2 h) { + return h.v[0]; +} + +// CHECK: define{{.*}} double @f2_call() +// CHECK-AAPCS: %call = call double @f2([2 x double] alignstack(16) %1) +// CHECK-DARWIN: %call = call double @f2([2 x double] %1 +double f2_call() { + S2 h = {1.0, 2.0}; + return f2(h); +} + +typedef struct { + __attribute__((__aligned__(32))) double v[4]; +} S3; + +// CHECK-AAPCS: define{{.*}} double @f3([4 x double] alignstack(16) %h.coerce) +// CHECK-DARWIN: define{{.*}} double @f3([4 x double] %h.coerce) +double f3(S3 h) { + return h.v[0]; +} + +// CHECK: define{{.*}} double @f3_call() +// CHECK-AAPCS: %call = call double @f3([4 x double] alignstack(16) %1) +// CHECK-DARWIN: %call = call double @f3([4 x double] %1 +double f3_call() { + S3 h = {1.0, 2.0}; + return f3(h); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c index 412734b08d79..f632be7b8598 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c @@ -1,6 +1,8 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - %s >/dev/null #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c index c38195388d56..50337643b757 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c @@ -1,6 +1,8 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - %s >/dev/null #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfb.c index e8815a05c3a5..641bbff06aa5 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfb.c @@ -10,7 +10,7 @@ void test_svprfb(svbool_t pg, const void *base) void test_svprfb_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfb(pg, base, -1); } @@ -22,6 +22,12 @@ void test_svprfb_vnum(svbool_t pg, const void *base) void test_svprfb_vnum_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfb_vnum(pg, base, 0, -1); } + +void test_svprfb_svpattern(svbool_t pg, const void *base) +{ + // expected-warning@+1 {{implicit conversion from enumeration type 'enum svpattern' to different enumeration type 'enum svprfop'}} + return svprfb(pg, base, SV_VL1); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfd.c index cd15ac58d961..e1ad02d812ad 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfd.c @@ -10,7 +10,7 @@ void test_svprfd(svbool_t pg, const void *base) void test_svprfd_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfd(pg, base, -1); } @@ -22,6 +22,6 @@ void test_svprfd_vnum(svbool_t pg, const void *base) void test_svprfd_vnum_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfd_vnum(pg, base, 0, -1); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfh.c index c18b66f06529..7ffff9b08e4a 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfh.c @@ -10,7 +10,7 @@ void test_svprfh(svbool_t pg, const void *base) void test_svprfh_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfh(pg, base, -1); } @@ -22,6 +22,6 @@ void test_svprfh_vnum(svbool_t pg, const void *base) void test_svprfh_vnum_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfh_vnum(pg, base, 0, -1); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfw.c index 6e3c27a48859..8ce509784ccd 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_prfw.c @@ -10,7 +10,7 @@ void test_svprfw(svbool_t pg, const void *base) void test_svprfw_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfw(pg, base, -1); } @@ -22,6 +22,6 @@ void test_svprfw_vnum(svbool_t pg, const void *base) void test_svprfw_vnum_1(svbool_t pg, const void *base) { - // expected-error@+1 {{argument value -1 is outside the valid range [0, 13]}} + // expected-error-re@+1 {{argument value {{.*}} is outside the valid range [0, 13]}} return svprfw_vnum(pg, base, 0, -1); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdecb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdecb.c index 2878a6fa35b6..e07094c5ed52 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdecb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdecb.c @@ -105,3 +105,9 @@ uint64_t test_svqdecb_pat_n_u64_1(uint64_t op) // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 16]}} return SVE_ACLE_FUNC(svqdecb_pat,_n_u64,,)(op, SV_VL7, 17); } + +uint64_t test_svqdecb_svprfop(uint64_t op) +{ + // expected-warning@+1 {{implicit conversion from enumeration type 'enum svprfop' to different enumeration type 'enum svpattern'}} + return SVE_ACLE_FUNC(svqdecb_pat,_n_u64,,)(op, SV_PLDL1KEEP, 1); +} diff --git a/clang/test/CodeGen/attr-target-mv.c b/clang/test/CodeGen/attr-target-mv.c index ef966cf2efec..54fa1b8a09ab 100644 --- a/clang/test/CodeGen/attr-target-mv.c +++ b/clang/test/CodeGen/attr-target-mv.c @@ -13,6 +13,7 @@ int __attribute__((target("arch=cooperlake"))) foo(void) {return 8;} int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;} int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;} int __attribute__((target("arch=alderlake"))) foo(void) {return 11;} +int __attribute__((target("arch=rocketlake"))) foo(void) {return 12;} int __attribute__((target("default"))) foo(void) { return 2; } int bar() { @@ -97,6 +98,8 @@ __attribute__((target("avx,sse4.2"), used)) inline void foo_used2(int i, double // LINUX: ret i32 10 // LINUX: define{{.*}} i32 @foo.arch_alderlake() // LINUX: ret i32 11 +// LINUX: define{{.*}} i32 @foo.arch_rocketlake() +// LINUX: ret i32 12 // LINUX: define{{.*}} i32 @foo() // LINUX: ret i32 2 // LINUX: define{{.*}} i32 @bar() diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c index c27be6d909c0..1a986f03dc49 100644 --- a/clang/test/CodeGen/builtins-wasm.c +++ b/clang/test/CodeGen/builtins-wasm.c @@ -792,49 +792,49 @@ f64x2 pmax_f64x2(f64x2 x, f64x2 y) { f32x4 ceil_f32x4(f32x4 x) { return __builtin_wasm_ceil_f32x4(x); - // WEBASSEMBLY: call <4 x float> @llvm.wasm.ceil.v4f32(<4 x float> %x) + // WEBASSEMBLY: call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) // WEBASSEMBLY: ret } f32x4 floor_f32x4(f32x4 x) { return __builtin_wasm_floor_f32x4(x); - // WEBASSEMBLY: call <4 x float> @llvm.wasm.floor.v4f32(<4 x float> %x) + // WEBASSEMBLY: call <4 x float> @llvm.floor.v4f32(<4 x float> %x) // WEBASSEMBLY: ret } f32x4 trunc_f32x4(f32x4 x) { return __builtin_wasm_trunc_f32x4(x); - // WEBASSEMBLY: call <4 x float> @llvm.wasm.trunc.v4f32(<4 x float> %x) + // WEBASSEMBLY: call <4 x float> @llvm.trunc.v4f32(<4 x float> %x) // WEBASSEMBLY: ret } f32x4 nearest_f32x4(f32x4 x) { return __builtin_wasm_nearest_f32x4(x); - // WEBASSEMBLY: call <4 x float> @llvm.wasm.nearest.v4f32(<4 x float> %x) + // WEBASSEMBLY: call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %x) // WEBASSEMBLY: ret } f64x2 ceil_f64x2(f64x2 x) { return __builtin_wasm_ceil_f64x2(x); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.ceil.v2f64(<2 x double> %x) + // WEBASSEMBLY: call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) // WEBASSEMBLY: ret } f64x2 floor_f64x2(f64x2 x) { return __builtin_wasm_floor_f64x2(x); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.floor.v2f64(<2 x double> %x) + // WEBASSEMBLY: call <2 x double> @llvm.floor.v2f64(<2 x double> %x) // WEBASSEMBLY: ret } f64x2 trunc_f64x2(f64x2 x) { return __builtin_wasm_trunc_f64x2(x); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.trunc.v2f64(<2 x double> %x) + // WEBASSEMBLY: call <2 x double> @llvm.trunc.v2f64(<2 x double> %x) // WEBASSEMBLY: ret } f64x2 nearest_f64x2(f64x2 x) { return __builtin_wasm_nearest_f64x2(x); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.nearest.v2f64(<2 x double> %x) + // WEBASSEMBLY: call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %x) // WEBASSEMBLY: ret } @@ -890,42 +890,6 @@ u16x8 narrow_u_i16x8_i32x4(u32x4 low, u32x4 high) { // WEBASSEMBLY: ret } -i64x2 extend_low_s_i32x4_i64x2(i32x4 x) { - return __builtin_wasm_extend_low_s_i32x4_i64x2(x); - // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32> %x) - // WEBASSEMBLY: ret -} - -i64x2 extend_high_s_i32x4_i64x2(i32x4 x) { - return __builtin_wasm_extend_high_s_i32x4_i64x2(x); - // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32> %x) - // WEBASSEMBLY: ret -} - -u64x2 extend_low_u_i32x4_i64x2(u32x4 x) { - return __builtin_wasm_extend_low_u_i32x4_i64x2(x); - // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32> %x) - // WEBASSEMBLY: ret -} - -u64x2 extend_high_u_i32x4_i64x2(u32x4 x) { - return __builtin_wasm_extend_high_u_i32x4_i64x2(x); - // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32> %x) - // WEBASSEMBLY: ret -} - -f64x2 convert_low_s_i32x4_f64x2(i32x4 x) { - return __builtin_wasm_convert_low_s_i32x4_f64x2(x); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x) - // WEBASSEMBLY: ret -} - -f64x2 convert_low_u_i32x4_f64x2(u32x4 x) { - return __builtin_wasm_convert_low_u_i32x4_f64x2(x); - // WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %x) - // WEBASSEMBLY: ret -} - i32x4 trunc_sat_zero_s_f64x2_i32x4(f64x2 x) { return __builtin_wasm_trunc_sat_zero_s_f64x2_i32x4(x); // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double> %x) diff --git a/clang/test/CodeGen/ms_abi_aarch64.c b/clang/test/CodeGen/ms_abi_aarch64.c index bbb4be94d7dc..cf244420296d 100644 --- a/clang/test/CodeGen/ms_abi_aarch64.c +++ b/clang/test/CodeGen/ms_abi_aarch64.c @@ -1,5 +1,13 @@ -// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm < %s | FileCheck -check-prefix=LINUX %s -// RUN: %clang_cc1 -triple aarch64-pc-win32 -emit-llvm < %s | FileCheck -check-prefix=WIN64 %s +// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm < %s | FileCheck -check-prefixes=LINUX,COMMON %s +// RUN: %clang_cc1 -triple aarch64-pc-win32 -emit-llvm < %s | FileCheck -check-prefixes=WIN64,COMMON %s + +struct small_odd { + char a, b, c; +}; + +struct larger { + int a, b, c, d, e; +}; void __attribute__((ms_abi)) f1(void); void f2(void); @@ -10,8 +18,7 @@ void f3(void) { // LINUX: call win64cc void @f1() // WIN64: call void @f1() f2(); - // LINUX: call void @f2() - // WIN64: call void @f2() + // COMMON: call void @f2() } // LINUX: declare win64cc void @f1() // LINUX: declare void @f2() @@ -24,28 +31,39 @@ void __attribute__((ms_abi)) f4(int a, ...) { // WIN64-LABEL: define dso_local void @f4 __builtin_ms_va_list ap; __builtin_ms_va_start(ap, a); - // LINUX: %[[AP:.*]] = alloca i8* - // LINUX: call void @llvm.va_start - // WIN64: %[[AP:.*]] = alloca i8* - // WIN64: call void @llvm.va_start + // COMMON: %[[AP:.*]] = alloca i8* + // COMMON: call void @llvm.va_start int b = __builtin_va_arg(ap, int); - // LINUX: %[[AP_CUR:.*]] = load i8*, i8** %[[AP]] - // LINUX-NEXT: %[[AP_NEXT:.*]] = getelementptr inbounds i8, i8* %[[AP_CUR]], i64 8 - // LINUX-NEXT: store i8* %[[AP_NEXT]], i8** %[[AP]] - // LINUX-NEXT: bitcast i8* %[[AP_CUR]] to i32* - // WIN64: %[[AP_CUR:.*]] = load i8*, i8** %[[AP]] - // WIN64-NEXT: %[[AP_NEXT:.*]] = getelementptr inbounds i8, i8* %[[AP_CUR]], i64 8 - // WIN64-NEXT: store i8* %[[AP_NEXT]], i8** %[[AP]] - // WIN64-NEXT: bitcast i8* %[[AP_CUR]] to i32* + // COMMON: %[[AP_CUR:.*]] = load i8*, i8** %[[AP]] + // COMMON-NEXT: %[[AP_NEXT:.*]] = getelementptr inbounds i8, i8* %[[AP_CUR]], i64 8 + // COMMON-NEXT: store i8* %[[AP_NEXT]], i8** %[[AP]] + // COMMON-NEXT: bitcast i8* %[[AP_CUR]] to i32* __builtin_ms_va_list ap2; __builtin_ms_va_copy(ap2, ap); - // LINUX: %[[AP_VAL:.*]] = load i8*, i8** %[[AP]] - // LINUX-NEXT: store i8* %[[AP_VAL]], i8** %[[AP2:.*]] - // WIN64: %[[AP_VAL:.*]] = load i8*, i8** %[[AP]] - // WIN64-NEXT: store i8* %[[AP_VAL]], i8** %[[AP2:.*]] + // COMMON: %[[AP_VAL:.*]] = load i8*, i8** %[[AP]] + // COMMON-NEXT: store i8* %[[AP_VAL]], i8** %[[AP2:.*]] + __builtin_ms_va_end(ap); + // COMMON: call void @llvm.va_end +} + +void __attribute__((ms_abi)) f4_2(int a, ...) { + // LINUX-LABEL: define{{.*}} win64cc void @f4_2 + // WIN64-LABEL: define dso_local void @f4_2 + __builtin_ms_va_list ap; + __builtin_ms_va_start(ap, a); + // COMMON: %[[AP:.*]] = alloca i8* + // COMMON: call void @llvm.va_start + struct small_odd s1 = __builtin_va_arg(ap, struct small_odd); + // COMMON: %[[AP_CUR:.*]] = load i8*, i8** %[[AP]] + // COMMON-NEXT: %[[AP_NEXT:.*]] = getelementptr inbounds i8, i8* %[[AP_CUR]], i64 8 + // COMMON-NEXT: store i8* %[[AP_NEXT]], i8** %[[AP]] + // COMMON-NEXT: bitcast i8* %[[AP_CUR]] to %struct.small_odd* + struct larger s2 = __builtin_va_arg(ap, struct larger); + // COMMON: %[[AP_CUR2:.*]] = load i8*, i8** %[[AP]] + // COMMON-NEXT: %[[AP_NEXT3:.*]] = getelementptr inbounds i8, i8* %[[AP_CUR2]], i64 8 + // COMMON-NEXT: store i8* %[[AP_NEXT3]], i8** %[[AP]] + // COMMON-NEXT: bitcast i8* %[[AP_CUR2]] to %struct.larger** __builtin_ms_va_end(ap); - // LINUX: call void @llvm.va_end - // WIN64: call void @llvm.va_end } // Let's verify that normal va_lists work right on Win64, too. @@ -66,3 +84,39 @@ void f5(int a, ...) { __builtin_va_end(ap); // WIN64: call void @llvm.va_end } + +struct HFA { + float a, b, c; +}; + +__attribute__((ms_abi)) void msabi_hfa(struct HFA a); +__attribute__((ms_abi)) void msabi_hfa_vararg(struct HFA a, int b, ...); + +void call_msabi_hfa(void) { + // COMMON-LABEL: define{{.*}} void @call_msabi_hfa() + // WIN64: call void @msabi_hfa([3 x float] {{.*}}) + // LINUX: call win64cc void @msabi_hfa([3 x float] {{.*}}) + msabi_hfa((struct HFA){1.0f, 2.0f, 3.0f}); +} + +void call_msabi_hfa_vararg(void) { + // COMMON-LABEL: define{{.*}} void @call_msabi_hfa_vararg() + // WIN64: call void ([2 x i64], i32, ...) @msabi_hfa_vararg([2 x i64] {{.*}}, i32 4, [2 x i64] {{.*}}) + // LINUX: call win64cc void ([2 x i64], i32, ...) @msabi_hfa_vararg([2 x i64] {{.*}}, i32 4, [2 x i64] {{.*}}) + msabi_hfa_vararg((struct HFA){1.0f, 2.0f, 3.0f}, 4, + (struct HFA){5.0f, 6.0f, 7.0f}); +} + +__attribute__((ms_abi)) void get_msabi_hfa_vararg(int a, ...) { + // COMMON-LABEL: define{{.*}} void @get_msabi_hfa_vararg + __builtin_ms_va_list ap; + __builtin_ms_va_start(ap, a); + // COMMON: %[[AP:.*]] = alloca i8* + // COMMON: call void @llvm.va_start + struct HFA b = __builtin_va_arg(ap, struct HFA); + // COMMON: %[[AP_CUR:.*]] = load i8*, i8** %[[AP]] + // COMMON-NEXT: %[[AP_NEXT:.*]] = getelementptr inbounds i8, i8* %[[AP_CUR]], i64 16 + // COMMON-NEXT: store i8* %[[AP_NEXT]], i8** %[[AP]] + // COMMON-NEXT: bitcast i8* %[[AP_CUR]] to %struct.HFA* + __builtin_ms_va_end(ap); +} diff --git a/clang/test/CodeGen/sanitizer-module-constructor.c b/clang/test/CodeGen/sanitizer-module-constructor.c index 3e29a923a9f1..108cdcb892a6 100644 --- a/clang/test/CodeGen/sanitizer-module-constructor.c +++ b/clang/test/CodeGen/sanitizer-module-constructor.c @@ -16,6 +16,6 @@ static void f(b g) { } void h() { f(e); } -// CHECK: Running pass: {{.*}}SanitizerPass on {{.*}}sanitizer-module-constructor.c +// CHECK: Running pass: {{.*}}SanitizerPass // CHECK-NOT: Running pass: LoopSimplifyPass on {{.*}}san.module_ctor // CHECK: Running analysis: DominatorTreeAnalysis on {{.*}}san.module_ctor diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c index 808f3a03431b..12d23aedbe53 100644 --- a/clang/test/CodeGen/target-builtin-noerror.c +++ b/clang/test/CodeGen/target-builtin-noerror.c @@ -116,6 +116,7 @@ void verifycpustrings() { (void)__builtin_cpu_is("knl"); (void)__builtin_cpu_is("knm"); (void)__builtin_cpu_is("nehalem"); + (void)__builtin_cpu_is("rocketlake"); (void)__builtin_cpu_is("sandybridge"); (void)__builtin_cpu_is("shanghai"); (void)__builtin_cpu_is("silvermont"); diff --git a/clang/test/CodeGen/thinlto-distributed-newpm.ll b/clang/test/CodeGen/thinlto-distributed-newpm.ll index 1e9d5d4d2629..398b65116bbd 100644 --- a/clang/test/CodeGen/thinlto-distributed-newpm.ll +++ b/clang/test/CodeGen/thinlto-distributed-newpm.ll @@ -31,6 +31,7 @@ ; CHECK-O: Running analysis: OptimizationRemarkEmitterAnalysis on main ; CHECK-O: Running pass: InferFunctionAttrsPass ; CHECK-O: Starting {{.*}}Function pass manager run. +; CHECK-O: Running pass: LowerExpectIntrinsicPass on main ; CHECK-O: Running pass: SimplifyCFGPass on main ; CHECK-O: Running analysis: TargetIRAnalysis on main ; CHECK-O: Running analysis: AssumptionAnalysis on main @@ -38,7 +39,6 @@ ; CHECK-O: Running analysis: DominatorTreeAnalysis on main ; CHECK-O: Running pass: EarlyCSEPass on main ; CHECK-O: Running analysis: TargetLibraryAnalysis on main -; CHECK-O: Running pass: LowerExpectIntrinsicPass on main ; CHECK-O3: Running pass: CallSiteSplittingPass on main ; CHECK-O: Finished {{.*}}Function pass manager run. ; CHECK-O: Running pass: LowerTypeTestsPass diff --git a/clang/test/CodeGen/x86_32-align-linux.c b/clang/test/CodeGen/x86_32-align-linux.c new file mode 100644 index 000000000000..6e6ddd757b6f --- /dev/null +++ b/clang/test/CodeGen/x86_32-align-linux.c @@ -0,0 +1,60 @@ +// RUN: %clang_cc1 -w -fblocks -ffreestanding -triple i386-pc-linux-gnu -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -w -fblocks -ffreestanding -triple i386-pc-linux-gnu -target-feature +avx -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -w -fblocks -ffreestanding -triple i386-pc-linux-gnu -target-feature +avx512f -emit-llvm -o - %s | FileCheck %s + +#include + +// CHECK-LABEL: define dso_local void @testm128 +// CHECK-LABEL: %argp.cur = load i8*, i8** %args, align 4 +// CHECK-NEXT: %0 = ptrtoint i8* %argp.cur to i32 +// CHECK-NEXT: %1 = add i32 %0, 15 +// CHECK-NEXT: %2 = and i32 %1, -16 +// CHECK-NEXT: %argp.cur.aligned = inttoptr i32 %2 to i8* +void testm128(int argCount, ...) { + __m128 res; + __builtin_va_list args; + __builtin_va_start(args, argCount); + res = __builtin_va_arg(args, __m128); + __builtin_va_end(args); +} + +// CHECK-LABEL: define dso_local void @testm256 +// CHECK-LABEL: %argp.cur = load i8*, i8** %args, align 4 +// CHECK-NEXT: %0 = ptrtoint i8* %argp.cur to i32 +// CHECK-NEXT: %1 = add i32 %0, 31 +// CHECK-NEXT: %2 = and i32 %1, -32 +// CHECK-NEXT: %argp.cur.aligned = inttoptr i32 %2 to i8* +void testm256(int argCount, ...) { + __m256 res; + __builtin_va_list args; + __builtin_va_start(args, argCount); + res = __builtin_va_arg(args, __m256); + __builtin_va_end(args); +} + +// CHECK-LABEL: define dso_local void @testm512 +// CHECK-LABEL: %argp.cur = load i8*, i8** %args, align 4 +// CHECK-NEXT: %0 = ptrtoint i8* %argp.cur to i32 +// CHECK-NEXT: %1 = add i32 %0, 63 +// CHECK-NEXT: %2 = and i32 %1, -64 +// CHECK-NEXT: %argp.cur.aligned = inttoptr i32 %2 to i8* +void testm512(int argCount, ...) { + __m512 res; + __builtin_va_list args; + __builtin_va_start(args, argCount); + res = __builtin_va_arg(args, __m512); + __builtin_va_end(args); +} + +// CHECK-LABEL: define dso_local void @testPastArguments +// CHECK: call void (i32, ...) @testm128(i32 1, <4 x float> %0) +// CHECK: call void (i32, ...) @testm256(i32 1, <8 x float> %1) +// CHECK: call void (i32, ...) @testm512(i32 1, <16 x float> %2) +void testPastArguments(void) { + __m128 a; + __m256 b; + __m512 c; + testm128(1, a); + testm256(1, b); + testm512(1, c); +} diff --git a/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp b/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp new file mode 100644 index 000000000000..a34a0b88e281 --- /dev/null +++ b/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp @@ -0,0 +1,97 @@ +// RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=LINUX +// RUN: %clang_cc1 -triple x86_64-windows-pc -fms-compatibility -emit-llvm -o - %s | FileCheck %s --check-prefix=WINDOWS + +struct OutOfLineDefs { + int foo(int); + int foo(int, int); + __attribute__((cpu_specific(atom))) int foo(int, int, int) { return 1; } +}; + +int __attribute__((cpu_specific(atom))) OutOfLineDefs::foo(int) { + return 1; +} +int __attribute__((cpu_specific(ivybridge))) OutOfLineDefs::foo(int) { + return 2; +} +int __attribute__((cpu_dispatch(ivybridge, atom))) OutOfLineDefs::foo(int) { +} + +int __attribute__((cpu_specific(atom))) OutOfLineDefs::foo(int, int) { + return 1; +} +int __attribute__((cpu_specific(ivybridge))) OutOfLineDefs::foo(int, int) { + return 2; +} +int __attribute__((cpu_dispatch(ivybridge, atom))) +OutOfLineDefs::foo(int, int) { +} + +int __attribute__((cpu_specific(ivybridge))) OutOfLineDefs::foo(int, int, int) { + return 2; +} +int __attribute__((cpu_specific(sandybridge))) +OutOfLineDefs::foo(int, int, int) { + return 3; +} +int __attribute__((cpu_dispatch(sandybridge, ivybridge, atom))) +OutOfLineDefs::foo(int, int, int) { +} + +// IFunc definitions, Linux only. +// LINUX: @_ZN13OutOfLineDefs3fooEi = weak_odr alias i32 (%struct.OutOfLineDefs*, i32), i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.ifunc +// LINUX: @_ZN13OutOfLineDefs3fooEii = weak_odr alias i32 (%struct.OutOfLineDefs*, i32, i32), i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.ifunc +// LINUX: @_ZN13OutOfLineDefs3fooEiii = weak_odr alias i32 (%struct.OutOfLineDefs*, i32, i32, i32), i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.ifunc + +// LINUX: @_ZN13OutOfLineDefs3fooEi.ifunc = weak_odr ifunc i32 (%struct.OutOfLineDefs*, i32), i32 (%struct.OutOfLineDefs*, i32)* ()* @_ZN13OutOfLineDefs3fooEi.resolver +// LINUX: @_ZN13OutOfLineDefs3fooEii.ifunc = weak_odr ifunc i32 (%struct.OutOfLineDefs*, i32, i32), i32 (%struct.OutOfLineDefs*, i32, i32)* ()* @_ZN13OutOfLineDefs3fooEii.resolver +// LINUX: @_ZN13OutOfLineDefs3fooEiii.ifunc = weak_odr ifunc i32 (%struct.OutOfLineDefs*, i32, i32, i32), i32 (%struct.OutOfLineDefs*, i32, i32, i32)* ()* @_ZN13OutOfLineDefs3fooEiii.resolver + +// Arity 1 version: +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEi.O +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEi.S +// LINUX: define weak_odr i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.resolver() +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.S +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.O +// LINUX: call void @llvm.trap + +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.O" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.S" +// WINDOWS: define weak_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHH@Z"(%struct.OutOfLineDefs* %0, i32 %1) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.S"(%struct.OutOfLineDefs* %0, i32 %1) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.O"(%struct.OutOfLineDefs* %0, i32 %1) +// WINDOWS: call void @llvm.trap + +// Arity 2 version: +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEii.O +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEii.S +// LINUX: define weak_odr i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.resolver() +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.S +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.O +// LINUX: call void @llvm.trap + +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.O" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.S" +// WINDOWS: define weak_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.S"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.O"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2) +// WINDOWS: call void @llvm.trap + +// Arity 3 version: +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEiii.S +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEiii.R +// LINUX: define weak_odr i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.resolver() +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.R +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.S +// LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.O +// LINUX: call void @llvm.trap +// LINUX: define linkonce_odr i32 @_ZN13OutOfLineDefs3fooEiii.O + +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.S" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.R" +// WINDOWS: define weak_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.R"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.S"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) +// WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.O"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) +// WINDOWS: call void @llvm.trap +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.O" + diff --git a/clang/test/CodeGenCXX/attr-musttail.cpp b/clang/test/CodeGenCXX/attr-musttail.cpp new file mode 100644 index 000000000000..1d02d03ec578 --- /dev/null +++ b/clang/test/CodeGenCXX/attr-musttail.cpp @@ -0,0 +1,228 @@ +// RUN: %clang_cc1 -fno-elide-constructors -S -emit-llvm %s -triple x86_64-unknown-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -fno-elide-constructors -S -emit-llvm %s -triple x86_64-unknown-linux-gnu -o - | opt -verify +// FIXME: remove the call to "opt" once the tests are running the Clang verifier automatically again. + +int Bar(int); +int Baz(int); + +int Func1(int x) { + if (x) { + // CHECK: %call = musttail call i32 @_Z3Bari(i32 %1) + // CHECK-NEXT: ret i32 %call + [[clang::musttail]] return Bar(x); + } else { + [[clang::musttail]] return Baz(x); // CHECK: %call1 = musttail call i32 @_Z3Bazi(i32 %3) + } +} + +int Func2(int x) { + { + [[clang::musttail]] return Bar(Bar(x)); + } +} + +// CHECK: %call1 = musttail call i32 @_Z3Bari(i32 %call) + +class Foo { +public: + static int StaticMethod(int x); + int MemberFunction(int x); + int TailFrom(int x); + int TailFrom2(int x); + int TailFrom3(int x); +}; + +int Foo::TailFrom(int x) { + [[clang::musttail]] return MemberFunction(x); +} + +// CHECK: %call = musttail call i32 @_ZN3Foo14MemberFunctionEi(%class.Foo* nonnull dereferenceable(1) %this1, i32 %0) + +int Func3(int x) { + [[clang::musttail]] return Foo::StaticMethod(x); +} + +// CHECK: %call = musttail call i32 @_ZN3Foo12StaticMethodEi(i32 %0) + +int Func4(int x) { + Foo foo; // Object with trivial destructor. + [[clang::musttail]] return foo.StaticMethod(x); +} + +// CHECK: %call = musttail call i32 @_ZN3Foo12StaticMethodEi(i32 %0) + +int (Foo::*pmf)(int); + +int Foo::TailFrom2(int x) { + [[clang::musttail]] return ((*this).*pmf)(x); +} + +// CHECK: %call = musttail call i32 %8(%class.Foo* nonnull dereferenceable(1) %this.adjusted, i32 %9) + +int Foo::TailFrom3(int x) { + [[clang::musttail]] return (this->*pmf)(x); +} + +// CHECK: %call = musttail call i32 %8(%class.Foo* nonnull dereferenceable(1) %this.adjusted, i32 %9) + +void ReturnsVoid(); + +void Func5() { + [[clang::musttail]] return ReturnsVoid(); +} + +// CHECK: musttail call void @_Z11ReturnsVoidv() + +class HasTrivialDestructor {}; + +int ReturnsInt(int x); + +int Func6(int x) { + HasTrivialDestructor foo; + [[clang::musttail]] return ReturnsInt(x); +} + +// CHECK: %call = musttail call i32 @_Z10ReturnsInti(i32 %0) + +struct Data { + int (*fptr)(Data *); +}; + +int Func7(Data *data) { + [[clang::musttail]] return data->fptr(data); +} + +// CHECK: %call = musttail call i32 %1(%struct.Data* %2) + +template +T TemplateFunc(T) { + return 5; +} + +int Func9(int x) { + [[clang::musttail]] return TemplateFunc(x); +} + +// CHECK: %call = musttail call i32 @_Z12TemplateFuncIiET_S0_(i32 %0) + +template +int Func10(int x) { + T t; + [[clang::musttail]] return Bar(x); +} + +int Func11(int x) { + return Func10(x); +} + +// CHECK: %call = musttail call i32 @_Z3Bari(i32 %0) + +template +T Func12(T x) { + [[clang::musttail]] return ::Bar(x); +} + +int Func13(int x) { + return Func12(x); +} + +// CHECK: %call = musttail call i32 @_Z3Bari(i32 %0) + +int Func14(int x) { + int vla[x]; + [[clang::musttail]] return Bar(x); +} + +// CHECK: %call = musttail call i32 @_Z3Bari(i32 %3) + +void TrivialDestructorParam(HasTrivialDestructor obj); + +void Func14(HasTrivialDestructor obj) { + [[clang::musttail]] return TrivialDestructorParam(obj); +} + +// CHECK: musttail call void @_Z22TrivialDestructorParam20HasTrivialDestructor() + +struct Struct3 { + void ConstMemberFunction(const int *) const; + void NonConstMemberFunction(int *i); +}; +void Struct3::NonConstMemberFunction(int *i) { + // The parameters are not identical, but they are compatible. + [[clang::musttail]] return ConstMemberFunction(i); +} + +// CHECK: musttail call void @_ZNK7Struct319ConstMemberFunctionEPKi(%struct.Struct3* nonnull dereferenceable(1) %this1, i32* %0) + +struct HasNonTrivialCopyConstructor { + HasNonTrivialCopyConstructor(const HasNonTrivialCopyConstructor &); +}; +HasNonTrivialCopyConstructor ReturnsClassByValue(); +HasNonTrivialCopyConstructor TestNonElidableCopyConstructor() { + [[clang::musttail]] return (((ReturnsClassByValue()))); +} + +// CHECK: musttail call void @_Z19ReturnsClassByValuev(%struct.HasNonTrivialCopyConstructor* sret(%struct.HasNonTrivialCopyConstructor) align 1 %agg.result) + +struct HasNonTrivialCopyConstructor2 { + // Copy constructor works even if it has extra default params. + HasNonTrivialCopyConstructor2(const HasNonTrivialCopyConstructor &, int DefaultParam = 5); +}; +HasNonTrivialCopyConstructor2 ReturnsClassByValue2(); +HasNonTrivialCopyConstructor2 TestNonElidableCopyConstructor2() { + [[clang::musttail]] return (((ReturnsClassByValue2()))); +} + +// CHECK: musttail call void @_Z20ReturnsClassByValue2v() + +void TestFunctionPointer(int x) { + void (*p)(int) = nullptr; + [[clang::musttail]] return p(x); +} + +// CHECK: musttail call void %0(i32 %1) + +struct LargeWithCopyConstructor { + LargeWithCopyConstructor(const LargeWithCopyConstructor &); + char data[32]; +}; +LargeWithCopyConstructor ReturnsLarge(); +LargeWithCopyConstructor TestLargeWithCopyConstructor() { + [[clang::musttail]] return ReturnsLarge(); +} + +// CHECK: define dso_local void @_Z28TestLargeWithCopyConstructorv(%struct.LargeWithCopyConstructor* noalias sret(%struct.LargeWithCopyConstructor) align 1 %agg.result) +// CHECK: musttail call void @_Z12ReturnsLargev(%struct.LargeWithCopyConstructor* sret(%struct.LargeWithCopyConstructor) align 1 %agg.result) + +using IntFunctionType = int(); +IntFunctionType *ReturnsIntFunction(); +int TestRValueFunctionPointer() { + [[clang::musttail]] return ReturnsIntFunction()(); +} + +// CHECK: musttail call i32 %call() + +void(FuncWithParens)() { + [[clang::musttail]] return FuncWithParens(); +} + +// CHECK: musttail call void @_Z14FuncWithParensv() + +int TestNonCapturingLambda() { + auto lambda = []() { return 12; }; + [[clang::musttail]] return (+lambda)(); +} + +// CHECK: %call = call i32 ()* @"_ZZ22TestNonCapturingLambdavENK3$_0cvPFivEEv"(%class.anon* nonnull dereferenceable(1) %lambda) +// CHECK: musttail call i32 %call() + +class TestVirtual { + virtual void TailTo(); + virtual void TailFrom(); +}; + +void TestVirtual::TailFrom() { + [[clang::musttail]] return TailTo(); +} + +// CHECK: musttail call void %1(%class.TestVirtual* nonnull dereferenceable(8) %this1) diff --git a/clang/test/CodeGenCXX/ps4-dllstorage-vtable-rtti.cpp b/clang/test/CodeGenCXX/ps4-dllstorage-vtable-rtti.cpp new file mode 100644 index 000000000000..d334291b51b7 --- /dev/null +++ b/clang/test/CodeGenCXX/ps4-dllstorage-vtable-rtti.cpp @@ -0,0 +1,210 @@ +// For a class that has a vtable (and hence, also has a typeinfo symbol for +// RTTI), if a user marks either: +// +// (a) the entire class as dllexport (dllimport), or +// (b) all non-inline virtual methods of the class as dllexport (dllimport) +// +// then Clang must export the vtable and typeinfo symbol from the TU where they +// are defined (the TU containing the definition of the Itanium C++ ABI "key +// function"), and must import them in other modules where they are referenced. +// +// Conversely to point (b), if some (but not all) of the non-inline virtual +// methods of a class are marked as dllexport (dllimport), then the vtable and +// typeinfo symbols must not be exported (imported). This will result in a +// link-time failure when linking the importing module. This link-time failure +// is the desired behavior, because the Microsoft toolchain also gets a +// link-time failure in these cases (and since __declspec(dllexport) +// (__declspec(dllimport)) is a Microsoft extension, our intention is to mimic +// that Microsoft behavior). +// +// Side note: It is within the bodies of constructors (and in some cases, +// destructors) that the vtable is explicitly referenced. In case (a) above, +// where the entire class is exported (imported), then all constructors (among +// other things) are exported (imported). So for that situation, an importing +// module for a well-formed program will not actually reference the vtable, +// since constructor calls will all be to functions external to that module +// (and imported into it, from the exporting module). I.e., all vtable +// references will be in that module where the constructor and destructor +// bodies are, therefore, there will not be a need to import the vtable in +// that case. +// +// This test contains 6 test classes: +// 2 for point (a), +// 2 for point (b), +// and 2 negative tests for the converse of point (b). +// +// The two tests for each of these points are one for importing, and one for +// exporting. + +// RUN: %clang_cc1 -I%S -fdeclspec -triple x86_64-unknown-windows-itanium -emit-llvm -o - %s -fhalf-no-semantic-interposition | FileCheck %s -check-prefix=WI +// RUN: %clang_cc1 -I%S -fdeclspec -triple x86_64-scei-windows-itanium -emit-llvm -o - %s -fhalf-no-semantic-interposition | FileCheck %s --check-prefixes=PS4,SCEI_WI +// RUN: %clang_cc1 -I%S -fdeclspec -triple x86_64-scei-ps4 -emit-llvm -o - %s -fhalf-no-semantic-interposition | FileCheck %s --check-prefixes=PS4,SCEI_PS4 + +#include + +// Case (a) -- Import Aspect +// The entire class is imported. The typeinfo symbol must also be imported, +// but the vtable will not be referenced, and so does not need to be imported +// (as described in the "Side note", above). +// +// PS4-DAG: @_ZTI10FullImport = {{.*}}dllimport +// WI-DAG: @_ZTI10FullImport = external dllimport constant i8* +struct __declspec(dllimport) FullImport +{ + virtual void getId() {} + virtual void Bump(); + virtual void Decrement(); +}; + +// 'FullImport::Bump()' is the key function, so the vtable and typeinfo symbol +// of 'FullImport' will be defined in the TU that contains the definition of +// 'Bump()' (and they must be exported from there). +void FullImportTest() +{ + typeid(FullImport).name(); +} + +/////////////////////////////////////////////////////////////////// + +// Case (a) -- Export Aspect +// The entire class is exported. The vtable and typeinfo symbols must also be +// exported, +// +// PS4-DAG: @_ZTV10FullExport ={{.*}}dllexport +// WI-DAG: @_ZTV10FullExport ={{.*}}dllexport +// PS4-DAG: @_ZTI10FullExport ={{.*}}dllexport +// WI-DAG: @_ZTI10FullExport = dso_local dllexport constant { +struct __declspec(dllexport) FullExport // Easy case: Entire class is exported. +{ + virtual void getId() {} + virtual void Bump(); + virtual void Decrement(); +}; + +// This is the key function of the class 'FullExport', so the vtable and +// typeinfo symbols of 'FullExport' will be defined in this TU, and so they +// must be exported from this TU. +void FullExport::Bump() +{ + typeid(FullExport).name(); +} + +/////////////////////////////////////////////////////////////////// + +// Case (b) -- Import Aspect +// The class as a whole is not imported, but all non-inline virtual methods of +// the class are, so the vtable and typeinfo symbol must be imported. +// +// PS4-DAG: @_ZTV9FooImport ={{.*}}dllimport +// WI-DAG: @_ZTV9FooImport = linkonce_odr dso_local unnamed_addr constant { +// PS4-DAG: @_ZTI9FooImport ={{.*}}dllimport +// WI-DAG: @_ZTI9FooImport = linkonce_odr dso_local constant { + + +struct FooImport +{ + virtual void getId() const {} + __declspec(dllimport) virtual void Bump(); + __declspec(dllimport) virtual void Decrement(); +}; + +// 'FooImport::Bump()' is the key function, so the vtable and typeinfo symbol +// of 'FooImport' will be defined in the TU that contains the definition of +// 'Bump()' (and they must be exported from there). Here, we will reference +// the vtable and typeinfo symbol, so we must also import them. +void importTest() +{ + typeid(FooImport).name(); +} + +/////////////////////////////////////////////////////////////////// + +// Case (b) -- Export Aspect +// The class as a whole is not exported, but all non-inline virtual methods of +// the class are, so the vtable and typeinfo symbol must be exported. +// +// PS4-DAG: @_ZTV9FooExport ={{.*}}dllexport +// WI-DAG: @_ZTV9FooExport = dso_local unnamed_addr constant { +// PS4-DAG: @_ZTI9FooExport ={{.*}}dllexport +// WI-DAG: @_ZTI9FooExport = dso_local constant { +struct FooExport +{ + virtual void getId() const {} + __declspec(dllexport) virtual void Bump(); + __declspec(dllexport) virtual void Decrement(); +}; + +// This is the key function of the class 'FooExport', so the vtable and +// typeinfo symbol of 'FooExport' will be defined in this TU, and so they must +// be exported from this TU. +void FooExport::Bump() +{ + FooImport f; + typeid(FooExport).name(); +} + +/////////////////////////////////////////////////////////////////// + +// The tests below verify that the associated vtable and typeinfo symbols are +// not imported/exported. These are the converse of case (b). +// +// Note that ultimately, if the module doing the importing calls a constructor +// of the class with the vtable, or makes a reference to the typeinfo symbol of +// the class, then this will result in an unresolved reference (to the vtable +// or typeinfo symbol) when linking the importing module, and thus a link-time +// failure. +// +// Note that with the Microsoft toolchain there will also be a link-time +// failure when linking the module doing the importing. With the Microsoft +// toolchain, it will be an unresolved reference to the method 'Decrement()' +// of the approriate class, rather than to the vtable or typeinfo symbol of +// the class, because Microsoft defines the vtable and typeinfo symbol (weakly) +// everywhere they are used. + +// Converse of case (b) -- Import Aspect +// The class as a whole is not imported, and not all non-inline virtual methods +// are imported, so the vtable and typeinfo symbol are not to be imported. +// +// CHECK-PS4: @_ZTV11FooNoImport = external dso_local unnamed_addr constant { +// CHECK-WI: @_ZTV11FooNoImport = linkonce_odr dso_local unnamed_addr constant { +// CHECK-PS4: @_ZTI11FooNoImport = external dso_local constant i8*{{$}} +// CHECK-WI: @_ZTI11FooNoImport = linkonce_odr dso_local constant { +struct FooNoImport +{ + virtual void getId() const {} + __declspec(dllimport) virtual void Bump(); + virtual void Decrement(); // Not imported. + int mCounter; +}; + +void importNegativeTest() +{ + FooNoImport f; + typeid(FooNoImport).name(); +} + +/////////////////////////////////////////////////////////////////// + +// Converse of case (b) -- Export Aspect +// The class as a whole is not exported, and not all non-inline virtual methods +// are exported, so the vtable and typeinfo symbol are not to be exported. +// +// SCEI_PS4-DAG: @_ZTV11FooNoImport = external unnamed_addr constant { +// SCEI_WI-DAG: @_ZTV11FooNoExport = dso_local unnamed_addr constant { + +// WI-DAG: @_ZTV11FooNoExport = dso_local unnamed_addr constant { +// SCEI_PS4-DAG: @_ZTI11FooNoExport = constant { +// SCEI_WI-DAG: @_ZTI11FooNoExport = dso_local constant { +// WI-DAG: @_ZTI11FooNoExport = dso_local constant { +struct FooNoExport +{ + virtual void getId() const {} + __declspec(dllexport) virtual void Bump(); + virtual void Decrement(); // Not exported. + int mCounter; +}; + +void FooNoExport::Bump() +{ + typeid(FooNoExport).name(); +} diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl index 3769149c8c6d..b02e6308c343 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl @@ -748,7 +748,7 @@ kernel void test_s_setreg(uint val) { // CHECK-DAG: [[$WI_RANGE]] = !{i32 0, i32 1024} // CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025} -// CHECK-DAG: attributes #[[$NOUNWIND_READONLY:[0-9]+]] = { nounwind readonly } +// CHECK-DAG: attributes #[[$NOUNWIND_READONLY:[0-9]+]] = { nofree nounwind readonly } // CHECK-DAG: attributes #[[$READ_EXEC_ATTRS]] = { convergent } // CHECK-DAG: ![[$EXEC]] = !{!"exec"} // CHECK-DAG: ![[$EXEC_LO]] = !{!"exec_lo"} diff --git a/clang/test/CodeGenSYCL/convergent.cpp b/clang/test/CodeGenSYCL/convergent.cpp index 58be1b153c93..779f1592da0e 100644 --- a/clang/test/CodeGenSYCL/convergent.cpp +++ b/clang/test/CodeGenSYCL/convergent.cpp @@ -1,6 +1,5 @@ // RUN: %clang_cc1 -fsycl-is-device -emit-llvm -disable-llvm-passes \ -// RUN: -triple spir64-unknown-unknown-sycldevice -emit-llvm %s -o - | \ -// RUN: FileCheck %s +// RUN: -triple spir64 -emit-llvm %s -o - | FileCheck %s // CHECK-DAG: Function Attrs: // CHECK-DAG-SAME: convergent diff --git a/clang/test/CodeGenSYCL/filescope_asm.c b/clang/test/CodeGenSYCL/filescope_asm.c index 3c1c12fd589a..9c0d088ec0a2 100644 --- a/clang/test/CodeGenSYCL/filescope_asm.c +++ b/clang/test/CodeGenSYCL/filescope_asm.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsycl-is-device -triple spir64-unknown-unknown-sycldevice -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fsycl-is-device -triple spir64 -emit-llvm %s -o - | FileCheck %s // // Check that file-scope asm is ignored during device-side SYCL compilation. // diff --git a/clang/test/Driver/Inputs/gen-response.c b/clang/test/Driver/Inputs/gen-response.c deleted file mode 100644 index 84ffb40dbece..000000000000 --- a/clang/test/Driver/Inputs/gen-response.c +++ /dev/null @@ -1,8 +0,0 @@ -#define M -DTEST -#define M1 M M M M M M M M M M -#define M2 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 -#define M3 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 -#define M4 M3 M3 M3 M3 M3 M3 M3 M3 M3 M3 -#define M5 M4 M4 M4 M4 M4 M4 M4 M4 M4 M4 -#define TEXT M5 M5 M5 -TEXT diff --git a/clang/test/Driver/clang_f_opts.c b/clang/test/Driver/clang_f_opts.c index 3ea9410adbea..6077058ad5b2 100644 --- a/clang/test/Driver/clang_f_opts.c +++ b/clang/test/Driver/clang_f_opts.c @@ -58,6 +58,19 @@ // RUN: %clang -### -S -fprofile-sample-use=%S/Inputs/file.prof %s 2>&1 | FileCheck -check-prefix=CHECK-SAMPLE-PROFILE %s // CHECK-SAMPLE-PROFILE: "-fprofile-sample-use={{.*}}/file.prof" +// +// RUN: %clang -### -x cuda -nocudainc -nocudalib \ +// RUN: -c -fprofile-sample-use=%S/Inputs/file.prof %s 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-CUDA-SAMPLE-PROFILE %s +// -fprofile-sample-use should not be passed to the GPU compilation +// CHECK-CUDA-SAMPLE-PROFILE: "-cc1" +// CHECK-CUDA-SAMPLE-PROFILE-SAME: "-triple" "nvptx +// CHECK-CUDA-SAMPLE-PROFILE-NOT: "-fprofile-sample-use={{.*}}/file.prof" +// Host compilation should still have the option. +// CHECK-CUDA-SAMPLE-PROFILE: "-cc1" +// CHECK-CUDA-SAMPLE-PROFILE-SAME: "-fprofile-sample-use={{.*}}/file.prof" + + // RUN: %clang -### -S -fauto-profile=%S/Inputs/file.prof %s 2>&1 | FileCheck -check-prefix=CHECK-AUTO-PROFILE %s // CHECK-AUTO-PROFILE: "-fprofile-sample-use={{.*}}/file.prof" @@ -279,6 +292,7 @@ // RUN: -fno-delete-null-pointer-checks -fdelete-null-pointer-checks \ // RUN: -fno-inline-small-functions -finline-small-functions \ // RUN: -fno-fat-lto-objects -ffat-lto-objects \ +// RUN: -flto=auto -flto=jobserver \ // RUN: -fno-merge-constants -fmerge-constants \ // RUN: -fno-caller-saves -fcaller-saves \ // RUN: -fno-reorder-blocks -freorder-blocks \ diff --git a/clang/test/Driver/fsanitize.c b/clang/test/Driver/fsanitize.c index 5686d58d8e2f..7febfd02a1ad 100644 --- a/clang/test/Driver/fsanitize.c +++ b/clang/test/Driver/fsanitize.c @@ -695,7 +695,13 @@ // RUN: %clang -target x86_64-unknown-cloudabi -fsanitize=safe-stack %s -### 2>&1 | FileCheck %s -check-prefix=SAFESTACK-CLOUDABI // SAFESTACK-CLOUDABI: "-fsanitize=safe-stack" +// RUN: %clang -target x86_64--freebsd -fsanitize=kernel-address %s -### 2>&1 | FileCheck %s -check-prefix=KERNEL-ADDRESS-FREEBSD +// RUN: %clang -target aarch64--freebsd -fsanitize=kernel-address %s -### 2>&1 | FileCheck %s -check-prefix=KERNEL-ADDRESS-FREEBSD +// KERNEL-ADDRESS-FREEBSD: "-fsanitize=kernel-address" +// RUN: %clang -target x86_64--freebsd -fsanitize=kernel-memory %s -### 2>&1 | FileCheck %s -check-prefix=KERNEL-MEMORY-FREEBSD +// RUN: %clang -target aarch64--freebsd -fsanitize=kernel-memory %s -### 2>&1 | FileCheck %s -check-prefix=KERNEL-MEMORY-FREEBSD +// KERNEL-MEMORY-FREEBSD: "-fsanitize=kernel-memory" // * NetBSD; please keep ordered as in Sanitizers.def * diff --git a/clang/test/Driver/response-file.c b/clang/test/Driver/response-file.c index a7c5966c98d1..bd374cc15907 100644 --- a/clang/test/Driver/response-file.c +++ b/clang/test/Driver/response-file.c @@ -13,7 +13,7 @@ // But there's no guarantee that we actually will (the system limit could be // *huge*), so just check that invoking cc1 succeeds under these conditions. // -// RUN: %clang -E %S/Inputs/gen-response.c | grep DTEST > %t.1.txt +// RUN: %python -c 'print(*("-DTEST" for x in range(300000)))' >%t.1.txt // RUN: %clang -E @%t.1.txt %s -v 2>&1 | FileCheck %s -check-prefix=LONG // LONG: extern int it_works; diff --git a/clang/test/Driver/rocm-detect.hip b/clang/test/Driver/rocm-detect.hip index 5df5d2a9be06..68ae1edb4eb2 100644 --- a/clang/test/Driver/rocm-detect.hip +++ b/clang/test/Driver/rocm-detect.hip @@ -81,7 +81,7 @@ // SPACK: ROCm installation search path (Spack 4.0.0): [[DIR:.*]] // SPACK: ROCm installation search path: [[CLANG:.*]] -// SPACK: ROCm installation search path: [[CLANG]]/{{(llvm/)?}}lib/clang/{{[0-9.]+}} +// SPACK: ROCm installation search path: [[CLANG]]/{{(llvm/)?}}lib{{[0-9]*}}/clang/{{[0-9.]+}} // SPACK: ROCm installation search path: /opt/rocm // SPACK: InstalledDir: [[DIR]]/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin // SPACK: Found HIP installation: [[DIR]]/hip-4.0.0-5f63slrursbrvfe2txrrjkynbsywsob5, version 4.0.20214-a2917cd diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c index 515981eec506..46d8d5da3235 100644 --- a/clang/test/Driver/x86-march.c +++ b/clang/test/Driver/x86-march.c @@ -72,6 +72,10 @@ // RUN: | FileCheck %s -check-prefix=icelake-client // icelake-client: "-target-cpu" "icelake-client" // +// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=rocketlake 2>&1 \ +// RUN: | FileCheck %s -check-prefix=rocketlake +// rocketlake: "-target-cpu" "rocketlake" +// // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-server 2>&1 \ // RUN: | FileCheck %s -check-prefix=icelake-server // icelake-server: "-target-cpu" "icelake-server" diff --git a/clang/test/Frontend/Inputs/test.h b/clang/test/Frontend/Inputs/test.h index 98cc459a2426..67fdacb4cc4f 100644 --- a/clang/test/Frontend/Inputs/test.h +++ b/clang/test/Frontend/Inputs/test.h @@ -1 +1,7 @@ +#ifndef TEST_H +#define TEST_H + #include "test2.h" +#include "test2.h" + +#endif diff --git a/clang/test/Frontend/Inputs/test2.h b/clang/test/Frontend/Inputs/test2.h index 6d1a0d47b7f7..92250dca3d5d 100644 --- a/clang/test/Frontend/Inputs/test2.h +++ b/clang/test/Frontend/Inputs/test2.h @@ -1 +1,6 @@ +#ifndef TEST2_H +#define TEST2_H + int x; + +#endif diff --git a/clang/test/Frontend/print-header-includes.c b/clang/test/Frontend/print-header-includes.c index c5b711a87e00..c7f84e221150 100644 --- a/clang/test/Frontend/print-header-includes.c +++ b/clang/test/Frontend/print-header-includes.c @@ -6,6 +6,16 @@ // CHECK-NOT: . {{.*noline.h}} // CHECK: . {{.*test.h}} // CHECK: .. {{.*test2.h}} +// CHECK-NOT: .. {{.*test2.h}} + +// RUN: %clang_cc1 -I%S -isystem %S/Inputs/SystemHeaderPrefix \ +// RUN: -E -H -show-skipped-includes -o /dev/null %s 2> %t.stderr +// RUN: FileCheck --check-prefix=SKIPPED < %t.stderr %s + +// SKIPPED-NOT: . {{.*noline.h}} +// SKIPPED: . {{.*test.h}} +// SKIPPED: .. {{.*test2.h}} +// SKIPPED: .. {{.*test2.h}} // RUN: %clang_cc1 -I%S -include Inputs/test3.h -isystem %S/Inputs/SystemHeaderPrefix \ // RUN: -E -H -sys-header-deps -o /dev/null %s 2> %t.stderr diff --git a/clang/test/Misc/printer.c b/clang/test/Misc/printer.c index 085e02cbe5ce..339dda4b4e56 100644 --- a/clang/test/Misc/printer.c +++ b/clang/test/Misc/printer.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -emit-llvm -fexperimental-new-pass-manager -mllvm -print-before-all %s -o %t 2>&1 | FileCheck %s --check-prefix=CHECK-BEFORE // RUN: %clang_cc1 -emit-llvm -fexperimental-new-pass-manager -mllvm -print-after-all %s -o %t 2>&1 | FileCheck %s --check-prefix=CHECK-AFTER -// CHECK-BEFORE: *** IR Dump Before AlwaysInlinerPass *** -// CHECK-AFTER: *** IR Dump After AlwaysInlinerPass *** +// CHECK-BEFORE: *** IR Dump Before AlwaysInlinerPass +// CHECK-AFTER: *** IR Dump After AlwaysInlinerPass void foo() {} diff --git a/clang/test/Misc/serialized-diags-empty-filename.c b/clang/test/Misc/serialized-diags-empty-filename.c new file mode 100644 index 000000000000..32a9156e0215 --- /dev/null +++ b/clang/test/Misc/serialized-diags-empty-filename.c @@ -0,0 +1,8 @@ +// RUN: rm -f %t.diag +// RUN: not %clang -c %s --serialize-diagnostics %t.diag -o /dev/null +// RUN: c-index-test -read-diagnostics %t.diag 2>&1 | FileCheck %s + +# 1 "" 1 +void 1(); + +// CHECK: :1:6: error: diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 43ccdcc4a3cb..b248baabeb63 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -21,7 +21,7 @@ // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, +// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, @@ -33,7 +33,7 @@ // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, // X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, -// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, +// X86_64-SAME: icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, // X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, // X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, // X86_64-SAME: x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}} @@ -46,7 +46,7 @@ // TUNE_X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // TUNE_X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // TUNE_X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, +// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, // TUNE_X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // TUNE_X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // TUNE_X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, @@ -60,7 +60,7 @@ // TUNE_X86_64-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // TUNE_X86_64-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // TUNE_X86_64-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, +// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, // TUNE_X86_64-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // TUNE_X86_64-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // TUNE_X86_64-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, diff --git a/clang/test/OpenMP/masked_codegen.cpp b/clang/test/OpenMP/masked_codegen.cpp new file mode 100644 index 000000000000..97cb0375edb9 --- /dev/null +++ b/clang/test/OpenMP/masked_codegen.cpp @@ -0,0 +1,143 @@ +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=ALL,NORMAL +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=ALL,NORMAL +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=51 -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=TERM_DEBUG +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=51 -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=ALL,IRBUILDER +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=51 -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=ALL,IRBUILDER + +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=51 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fopenmp-version=51 -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} +// expected-no-diagnostics +#ifndef HEADER +#define HEADER + +// ALL: [[IDENT_T_TY:%.+]] = type { i32, i32, i32, i32, i8* } + +// ALL: define {{.*}}void [[FOO:@.+]]() + +void foo() { extern void mayThrow(); mayThrow(); } + +// ALL-LABEL: @main +// TERM_DEBUG-LABEL: @main +int main() { + // ALL: [[A_ADDR:%.+]] = alloca i8 + char a; + +// ALL: [[GTID:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:@.+]]) +// ALL: [[RES:%.+]] = call {{.*}}i32 @__kmpc_masked([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]], i32 0) +// ALL-NEXT: [[IS_MASKED:%.+]] = icmp ne i32 [[RES]], 0 +// ALL-NEXT: br i1 [[IS_MASKED]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]] +// ALL: [[THEN]] +// ALL-NEXT: store i8 2, i8* [[A_ADDR]] +// ALL-NEXT: call {{.*}}void @__kmpc_end_masked([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]]) +// ALL-NEXT: br label {{%?}}[[EXIT]] +// ALL: [[EXIT]] +#pragma omp masked + a = 2; +// IRBUILDER: [[GTID:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:@.+]]) +// ALL: [[RES:%.+]] = call {{.*}}i32 @__kmpc_masked([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]], i32 2) +// ALL-NEXT: [[IS_MASKED:%.+]] = icmp ne i32 [[RES]], 0 +// ALL-NEXT: br i1 [[IS_MASKED]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]] +// ALL: [[THEN]] +// IRBUILDER-NEXT: call {{.*}}void [[FOO]]() +// NORMAL-NEXT: invoke {{.*}}void [[FOO]]() +// ALL: call {{.*}}void @__kmpc_end_masked([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]]) +// ALL-NEXT: br label {{%?}}[[EXIT]] +// ALL: [[EXIT]] +#pragma omp masked filter(2) + foo(); +// ALL: store i32 9, i32* [[X:.+]], +// ALL: [[X_VAL:%.+]] = load i32, i32* [[X]] +// IRBUILDER: [[GTID:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:@.+]]) +// ALL: [[RES:%.+]] = call {{.*}}i32 @__kmpc_masked([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]], i32 [[X_VAL]]) +// ALL-NEXT: [[IS_MASKED:%.+]] = icmp ne i32 [[RES]], 0 +// ALL-NEXT: br i1 [[IS_MASKED]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]] +// ALL: [[THEN]] +// IRBUILDER-NEXT: call {{.*}}void [[FOO]]() +// NORMAL-NEXT: invoke {{.*}}void [[FOO]]() +// ALL: call {{.*}}void @__kmpc_end_masked([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]]) +// ALL-NEXT: br label {{%?}}[[EXIT]] +// ALL: [[EXIT]] + int x = 9; +#pragma omp masked filter(x) + foo(); + // ALL-NOT: call i32 @__kmpc_masked + // ALL-NOT: call void @__kmpc_end_masked + return a; +} + +// ALL-LABEL: lambda_masked +// TERM_DEBUG-LABEL: lambda_masked +void lambda_masked(int a, int b) { + auto l = [=]() { +#pragma omp masked + { + // ALL: call i32 @__kmpc_masked( + int c = a + b; + } + }; + + l(); + + auto l1 = [=]() { +#pragma omp parallel +#pragma omp masked filter(1) + { + // ALL: call i32 @__kmpc_masked( + int c = a + b; + } + }; + + l1(); + + int y = 1; + auto l2 = [=](int yy) { +#pragma omp parallel +#pragma omp masked filter(yy) + { + // ALL: call i32 @__kmpc_masked( + int c = a + b; + } + }; + + l2(y); +} + +// ALL-LABEL: parallel_masked +// TERM_DEBUG-LABEL: parallel_masked +void parallel_masked() { +#pragma omp parallel +#pragma omp masked filter(1) + // TERM_DEBUG-NOT: __kmpc_global_thread_num + // TERM_DEBUG: call i32 @__kmpc_masked({{.+}}), !dbg [[DBG_LOC_START:![0-9]+]] + // TERM_DEBUG: invoke void {{.*}}foo{{.*}}() + // TERM_DEBUG: unwind label %[[TERM_LPAD:.+]], + // TERM_DEBUG-NOT: __kmpc_global_thread_num + // TERM_DEBUG: call void @__kmpc_end_masked({{.+}}), !dbg [[DBG_LOC_END:![0-9]+]] + // TERM_DEBUG: [[TERM_LPAD]] + // TERM_DEBUG: call void @__clang_call_terminate + // TERM_DEBUG: unreachable + foo(); + + int x; +#pragma omp parallel +#pragma omp masked filter(x) + // TERM_DEBUG-NOT: __kmpc_global_thread_num + // TERM_DEBUG: call i32 @__kmpc_masked({{.+}}), !dbg [[DBG_LOC_START:![0-9]+]] + // TERM_DEBUG: invoke void {{.*}}foo{{.*}}() + // TERM_DEBUG: unwind label %[[TERM_LPAD:.+]], + // TERM_DEBUG-NOT: __kmpc_global_thread_num + // TERM_DEBUG: call void @__kmpc_end_masked({{.+}}), !dbg [[DBG_LOC_END:![0-9]+]] + // TERM_DEBUG: [[TERM_LPAD]] + // TERM_DEBUG: call void @__clang_call_terminate + // TERM_DEBUG: unreachable + foo(); +} +// TERM_DEBUG-DAG: [[DBG_LOC_START]] = !DILocation(line: [[@LINE-12]], +// TERM_DEBUG-DAG: [[DBG_LOC_END]] = !DILocation(line: [[@LINE-3]], + +#endif diff --git a/clang/test/OpenMP/parallel_for_scan_codegen.cpp b/clang/test/OpenMP/parallel_for_scan_codegen.cpp index d4d6208f43cc..7e42d7ec49e0 100644 --- a/clang/test/OpenMP/parallel_for_scan_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_scan_codegen.cpp @@ -10,7 +10,7 @@ #ifndef HEADER #define HEADER -void foo(); +void foo(int n); void bar(); // CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 %n) @@ -18,10 +18,16 @@ void baz(int n) { static float a[10]; static double b; - // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( + // CHECK: call i8* @llvm.stacksave() + // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] + + // float a_buffer[10][n]; + // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], + // double b_buffer[10]; + // CHECK: [[B_BUF:%.+]] = alloca double, i64 10, + // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( - // CHECK: call i8* @llvm.stacksave() // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // float a_buffer[10][n]; @@ -29,6 +35,9 @@ void baz(int n) { // double b_buffer[10]; // CHECK: [[B_BUF:%.+]] = alloca double, i64 10, + // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( + // CHECK: call void @llvm.stackrestore(i8* + #pragma omp parallel for reduction(inscan, +:a[:n], b) for (int i = 0; i < 10; ++i) { // CHECK: call void @__kmpc_for_static_init_4( @@ -37,13 +46,13 @@ void baz(int n) { // CHECK: store double 0.000000e+00, double* [[B_PRIV_ADDR:%.+]], // CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: [[INPUT_PHASE:.+]]: - // CHECK: call void @{{.+}}foo{{.+}}() + // CHECK: call void @{{.+}}foo{{.+}}( // a_buffer[i][0..n] = a_priv[[0..n]; // CHECK: [[BASE_IDX_I:%.+]] = load i32, i32* [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 - // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] - // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF]], i64 [[IDX]] + // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] + // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF:%.+]], i64 [[IDX]] // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], [10 x float]* [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[DEST:%.+]] = bitcast float* [[A_BUF_IDX]] to i8* @@ -51,7 +60,7 @@ void baz(int n) { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}[[DEST]], i8* {{.*}}[[SRC]], i64 [[BYTES]], i1 false) // b_buffer[i] = b_priv; - // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF]], i64 [[BASE_IDX]] + // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF:%.+]], i64 [[BASE_IDX]] // CHECK: [[B_PRIV:%.+]] = load double, double* [[B_PRIV_ADDR]], // CHECK: store double [[B_PRIV]], double* [[B_BUF_IDX]], // CHECK: br label %[[LOOP_CONTINUE:.+]] @@ -62,7 +71,7 @@ void baz(int n) { // CHECK: call void @llvm.stackrestore(i8* % // CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_barrier( - foo(); + foo(n); #pragma omp scan inclusive(a[:n], b) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) @@ -128,7 +137,7 @@ void baz(int n) { // CHECK: br label %[[DISPATCH:[^,]+]] // Skip the before scan body. - // CHECK: call void @{{.+}}foo{{.+}}() + // CHECK: call void @{{.+}}foo{{.+}}( // CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: br label %[[LOOP_CONTINUE:[^,]+]] @@ -158,17 +167,8 @@ void baz(int n) { // CHECK: [[LOOP_CONTINUE]]: // CHECK: call void @llvm.stackrestore(i8* % // CHECK: call void @__kmpc_for_static_fini( - // CHECK: call void @llvm.stackrestore(i8* } - // CHECK: call i8* @llvm.stacksave() - // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] - - // float a_buffer[10][n]; - // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], - - // double b_buffer[10]; - // CHECK: [[B_BUF:%.+]] = alloca double, i64 10, #pragma omp parallel for reduction(inscan, +:a[:n], b) for (int i = 0; i < 10; ++i) { // CHECK: call void @__kmpc_for_static_init_4( @@ -178,15 +178,15 @@ void baz(int n) { // CHECK: br label %[[DISPATCH:[^,]+]] // Skip the before scan body. - // CHECK: call void @{{.+}}foo{{.+}}() + // CHECK: call void @{{.+}}foo{{.+}}( // CHECK: [[EXIT_INSCAN:[^,]+]]: // a_buffer[i][0..n] = a_priv[[0..n]; // CHECK: [[BASE_IDX_I:%.+]] = load i32, i32* [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 - // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] - // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF]], i64 [[IDX]] + // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] + // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF:%.+]], i64 [[IDX]] // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], [10 x float]* [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[DEST:%.+]] = bitcast float* [[A_BUF_IDX]] to i8* @@ -194,7 +194,7 @@ void baz(int n) { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}[[DEST]], i8* {{.*}}[[SRC]], i64 [[BYTES]], i1 false) // b_buffer[i] = b_priv; - // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF]], i64 [[BASE_IDX]] + // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF:%.+]], i64 [[BASE_IDX]] // CHECK: [[B_PRIV:%.+]] = load double, double* [[B_PRIV_ADDR]], // CHECK: store double [[B_PRIV]], double* [[B_BUF_IDX]], // CHECK: br label %[[LOOP_CONTINUE:[^,]+]] @@ -210,7 +210,7 @@ void baz(int n) { // CHECK: call void @llvm.stackrestore(i8* % // CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_barrier( - foo(); + foo(n); #pragma omp scan exclusive(a[:n], b) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) @@ -276,7 +276,7 @@ void baz(int n) { // CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: [[SCAN_PHASE:.+]]: - // CHECK: call void @{{.+}}foo{{.+}}() + // CHECK: call void @{{.+}}foo{{.+}}( // CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: [[DISPATCH]]: @@ -305,7 +305,6 @@ void baz(int n) { // CHECK: [[LOOP_CONTINUE]]: // CHECK: call void @llvm.stackrestore(i8* % // CHECK: call void @__kmpc_for_static_fini( - // CHECK: call void @llvm.stackrestore(i8* } } diff --git a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp index e93c950fb84f..71c6447c0ff9 100644 --- a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp @@ -18,10 +18,15 @@ void baz(int n) { static float a[10]; static double b; - // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( + // CHECK: call i8* @llvm.stacksave() + // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] + + // float a_buffer[10][n]; + // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], + // CHECK: [[B_BUF:%.+]] = alloca double, i64 10, + // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( - // CHECK: call i8* @llvm.stacksave() // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // float a_buffer[10][n]; @@ -29,6 +34,9 @@ void baz(int n) { // double b_buffer[10]; // CHECK: [[B_BUF:%.+]] = alloca double, i64 10, + // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( + // CHECK: call void @llvm.stackrestore(i8* + #pragma omp parallel for simd reduction(inscan, +:a[:n], b) for (int i = 0; i < 10; ++i) { // CHECK: call void @__kmpc_for_static_init_4( @@ -42,8 +50,8 @@ void baz(int n) { // a_buffer[i][0..n] = a_priv[[0..n]; // CHECK: [[BASE_IDX_I:%.+]] = load i32, i32* [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 - // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] - // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF]], i64 [[IDX]] + // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] + // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF:%.+]], i64 [[IDX]] // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], [10 x float]* [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[DEST:%.+]] = bitcast float* [[A_BUF_IDX]] to i8* @@ -51,7 +59,7 @@ void baz(int n) { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}[[DEST]], i8* {{.*}}[[SRC]], i64 [[BYTES]], i1 false) // b_buffer[i] = b_priv; - // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF]], i64 [[BASE_IDX]] + // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF:%.+]], i64 [[BASE_IDX]] // CHECK: [[B_PRIV:%.+]] = load double, double* [[B_PRIV_ADDR]], // CHECK: store double [[B_PRIV]], double* [[B_BUF_IDX]], // CHECK: br label %[[LOOP_CONTINUE:.+]] @@ -158,17 +166,8 @@ void baz(int n) { // CHECK: [[LOOP_CONTINUE]]: // CHECK: call void @llvm.stackrestore(i8* % // CHECK: call void @__kmpc_for_static_fini( - // CHECK: call void @llvm.stackrestore(i8* } - // CHECK: call i8* @llvm.stacksave() - // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] - - // float a_buffer[10][n]; - // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], - - // double b_buffer[10]; - // CHECK: [[B_BUF:%.+]] = alloca double, i64 10, #pragma omp parallel for simd reduction(inscan, +:a[:n], b) for (int i = 0; i < 10; ++i) { // CHECK: call void @__kmpc_for_static_init_4( @@ -185,8 +184,8 @@ void baz(int n) { // a_buffer[i][0..n] = a_priv[[0..n]; // CHECK: [[BASE_IDX_I:%.+]] = load i32, i32* [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 - // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] - // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF]], i64 [[IDX]] + // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] + // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, float* [[A_BUF:%.+]], i64 [[IDX]] // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], [10 x float]* [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[DEST:%.+]] = bitcast float* [[A_BUF_IDX]] to i8* @@ -194,7 +193,7 @@ void baz(int n) { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}[[DEST]], i8* {{.*}}[[SRC]], i64 [[BYTES]], i1 false) // b_buffer[i] = b_priv; - // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF]], i64 [[BASE_IDX]] + // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, double* [[B_BUF:%.+]], i64 [[BASE_IDX]] // CHECK: [[B_PRIV:%.+]] = load double, double* [[B_PRIV_ADDR]], // CHECK: store double [[B_PRIV]], double* [[B_BUF_IDX]], // CHECK: br label %[[LOOP_CONTINUE:[^,]+]] @@ -305,7 +304,6 @@ void baz(int n) { // CHECK: [[LOOP_CONTINUE]]: // CHECK: call void @llvm.stackrestore(i8* % // CHECK: call void @__kmpc_for_static_fini( - // CHECK: call void @llvm.stackrestore(i8* } } diff --git a/clang/test/Parser/c2x-attributes.c b/clang/test/Parser/c2x-attributes.c index 393506e867fe..d75e9e2d2976 100644 --- a/clang/test/Parser/c2x-attributes.c +++ b/clang/test/Parser/c2x-attributes.c @@ -16,6 +16,14 @@ enum { [[]] Six }; // expected-error {{expected identifier}} // FIXME: this diagnostic can be improved. enum E3 [[]] { Seven }; // expected-error {{expected identifier or '('}} +[[deprecated([""])]] int WrongArgs; // expected-error {{expected expression}} +[[,,,,,]] int Commas1; // ok +[[,, maybe_unused]] int Commas2; // ok +[[maybe_unused,,,]] int Commas3; // ok +[[,,maybe_unused,]] int Commas4; // ok +[[foo bar]] int NoComma; // expected-error {{expected ','}} \ + // expected-warning {{unknown attribute 'foo' ignored}} + struct [[]] S1 { int i [[]]; int [[]] j; @@ -117,8 +125,7 @@ void test_asm(void) { } // Do not allow 'using' to introduce vendor attribute namespaces. -[[using vendor: attr1, attr2]] void f14(void); // expected-error {{expected ']'}} \ - // expected-warning {{unknown attribute 'vendor' ignored}} \ +[[using vendor: attr1, attr2]] void f14(void); // expected-error {{expected ','}} \ // expected-warning {{unknown attribute 'using' ignored}} struct [[]] S4 *s; // expected-error {{an attribute list cannot appear here}} diff --git a/clang/test/Parser/cxx-attributes.cpp b/clang/test/Parser/cxx-attributes.cpp index 53b098b6260a..d445e42bfe08 100644 --- a/clang/test/Parser/cxx-attributes.cpp +++ b/clang/test/Parser/cxx-attributes.cpp @@ -34,3 +34,11 @@ void fn() { int (*__attribute__((attr(i[1]))) pi); // expected-warning{{unknown attribute 'attr' ignored}} pi = &i[0]; } + +[[deprecated([""])]] int WrongArgs; // expected-error {{expected variable name or 'this' in lambda capture list}} +[[,,,,,]] int Commas1; // ok +[[,, maybe_unused]] int Commas2; // ok +[[maybe_unused,,,]] int Commas3; // ok +[[,,maybe_unused,]] int Commas4; // ok +[[foo bar]] int NoComma; // expected-error {{expected ','}} \ + // expected-warning {{unknown attribute 'foo' ignored}} diff --git a/clang/test/Parser/pragma-attribute.cpp b/clang/test/Parser/pragma-attribute.cpp index 4644bc18359e..d51f8159c263 100644 --- a/clang/test/Parser/pragma-attribute.cpp +++ b/clang/test/Parser/pragma-attribute.cpp @@ -165,9 +165,9 @@ _Pragma("clang attribute pop"); #pragma clang attribute push ([[]], apply_to = function) // A noop -#pragma clang attribute push ([[noreturn ""]], apply_to=function) // expected-error {{expected ']'}} +#pragma clang attribute push ([[noreturn ""]], apply_to=function) // expected-error {{expected ','}} #pragma clang attribute pop -#pragma clang attribute push ([[noreturn 42]]) // expected-error {{expected ']'}} expected-error {{expected ','}} +#pragma clang attribute push ([[noreturn 42]]) // expected-error 2 {{expected ','}} #pragma clang attribute push(__attribute__, apply_to=function) // expected-error {{expected '(' after 'attribute'}} #pragma clang attribute push(__attribute__(), apply_to=function) // expected-error {{expected '(' after '('}} diff --git a/clang/test/Preprocessor/init-x86.c b/clang/test/Preprocessor/init-x86.c index d22a2ab6e118..527cd3950888 100644 --- a/clang/test/Preprocessor/init-x86.c +++ b/clang/test/Preprocessor/init-x86.c @@ -1306,10 +1306,12 @@ // X86_64-CLOUDABI:#define __amd64 1 // X86_64-CLOUDABI:#define __amd64__ 1 // X86_64-CLOUDABI:#define __clang__ 1 +// X86_64-CLOUDABI:#define __clang_literal_encoding__ {{.*}} // X86_64-CLOUDABI:#define __clang_major__ {{.*}} // X86_64-CLOUDABI:#define __clang_minor__ {{.*}} // X86_64-CLOUDABI:#define __clang_patchlevel__ {{.*}} // X86_64-CLOUDABI:#define __clang_version__ {{.*}} +// X86_64-CLOUDABI:#define __clang_wide_literal_encoding__ {{.*}} // X86_64-CLOUDABI:#define __llvm__ 1 // X86_64-CLOUDABI:#define __x86_64 1 // X86_64-CLOUDABI:#define __x86_64__ 1 diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index 136200a97840..0329453c4136 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -115,10 +115,12 @@ // COMMON:#define __STDC__ 1 // COMMON:#define __VERSION__ {{.*}} // COMMON:#define __clang__ 1 +// COMMON:#define __clang_literal_encoding__ {{.*}} // COMMON:#define __clang_major__ {{[0-9]+}} // COMMON:#define __clang_minor__ {{[0-9]+}} // COMMON:#define __clang_patchlevel__ {{[0-9]+}} // COMMON:#define __clang_version__ {{.*}} +// COMMON:#define __clang_wide_literal_encoding__ {{.*}} // COMMON:#define __llvm__ 1 // // RUN: %clang_cc1 -E -dM -triple=x86_64-pc-win32 < /dev/null | FileCheck -match-full-lines -check-prefix C-DEFAULT %s @@ -1844,10 +1846,12 @@ // WEBASSEMBLY-NOT:#define __WINT_UNSIGNED__ // WEBASSEMBLY-NEXT:#define __WINT_WIDTH__ 32 // WEBASSEMBLY-NEXT:#define __clang__ 1 +// WEBASSEMBLY-NEXT:#define __clang_literal_encoding__ {{.*}} // WEBASSEMBLY-NEXT:#define __clang_major__ {{.*}} // WEBASSEMBLY-NEXT:#define __clang_minor__ {{.*}} // WEBASSEMBLY-NEXT:#define __clang_patchlevel__ {{.*}} // WEBASSEMBLY-NEXT:#define __clang_version__ "{{.*}}" +// WEBASSEMBLY-NEXT:#define __clang_wide_literal_encoding__ {{.*}} // WEBASSEMBLY-NEXT:#define __llvm__ 1 // WEBASSEMBLY-NOT:#define __unix // WEBASSEMBLY-NOT:#define __unix__ diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index bf253d1c1ff7..4e01d0273024 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1280,7 +1280,10 @@ // RUN: %clang -march=icelake-client -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ -// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M32 +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M32,CHECK_ICL_M32S +// RUN: %clang -march=rocketlake -m32 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M32,CHECK_RKL_M32S // CHECK_ICL_M32: #define __AES__ 1 // CHECK_ICL_M32: #define __AVX2__ 1 // CHECK_ICL_M32: #define __AVX512BITALG__ 1 @@ -1313,7 +1316,8 @@ // CHECK_ICL_M32: #define __RDPID__ 1 // CHECK_ICL_M32: #define __RDRND__ 1 // CHECK_ICL_M32: #define __RDSEED__ 1 -// CHECK_ICL_M32: #define __SGX__ 1 +// CHECK_ICL_M32S: #define __SGX__ 1 +// CHECK_RKL_M32S-NOT: #define __SGX__ 1 // CHECK_ICL_M32: #define __SHA__ 1 // CHECK_ICL_M32: #define __SSE2__ 1 // CHECK_ICL_M32: #define __SSE3__ 1 @@ -1337,7 +1341,10 @@ // RUN: %clang -march=icelake-client -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ -// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M64 +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M64,CHECK_ICL_M64S +// RUN: %clang -march=rocketlake -m64 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M64,CHECK_RKL_M64S // CHECK_ICL_M64: #define __AES__ 1 // CHECK_ICL_M64: #define __AVX2__ 1 // CHECK_ICL_M64: #define __AVX512BITALG__ 1 @@ -1370,7 +1377,8 @@ // CHECK_ICL_M64: #define __RDPID__ 1 // CHECK_ICL_M64: #define __RDRND__ 1 // CHECK_ICL_M64: #define __RDSEED__ 1 -// CHECK_ICL_M64: #define __SGX__ 1 +// CHECK_ICL_M64S: #define __SGX__ 1 +// CHECK_RKL_M64S-NOT: #define __SGX__ 1 // CHECK_ICL_M64: #define __SHA__ 1 // CHECK_ICL_M64: #define __SSE2__ 1 // CHECK_ICL_M64: #define __SSE3__ 1 diff --git a/clang/test/Sema/attr-musttail.c b/clang/test/Sema/attr-musttail.c new file mode 100644 index 000000000000..b17947c68ba9 --- /dev/null +++ b/clang/test/Sema/attr-musttail.c @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -verify -fsyntax-only %s + +int NotAProtoType(); // expected-note{{add 'void' to the parameter list to turn an old-style K&R function declaration into a prototype}} +int TestCalleeNotProtoType(void) { + __attribute__((musttail)) return NotAProtoType(); // expected-error{{'musttail' attribute requires that both caller and callee functions have a prototype}} +} + +int ProtoType(void); +int TestCallerNotProtoType() { // expected-note{{add 'void' to the parameter list to turn an old-style K&R function declaration into a prototype}} + __attribute__((musttail)) return ProtoType(); // expected-error{{'musttail' attribute requires that both caller and callee functions have a prototype}} +} + +int TestProtoType(void) { + return ProtoType(); +} diff --git a/clang/test/Sema/attr-musttail.m b/clang/test/Sema/attr-musttail.m new file mode 100644 index 000000000000..6549232d107a --- /dev/null +++ b/clang/test/Sema/attr-musttail.m @@ -0,0 +1,26 @@ +// RUN: %clang_cc1 -fsyntax-only -fblocks -Wno-objc-root-class -verify %s + +void TestObjcBlock(void) { + void (^x)(void) = ^(void) { + __attribute__((musttail)) return TestObjcBlock(); // expected-error{{'musttail' attribute cannot be used from a block}} + }; + __attribute__((musttail)) return x(); +} + +void ReturnsVoid(void); +void TestObjcBlockVar(void) { + __block int i = 0; // expected-note{{jump exits scope of __block variable}} + __attribute__((musttail)) return ReturnsVoid(); // expected-error{{cannot perform a tail call from this return statement}} +} + +__attribute__((objc_root_class)) +@interface TestObjcClass +@end + +@implementation TestObjcClass + +- (void)testObjCMethod { + __attribute__((musttail)) return ReturnsVoid(); // expected-error{{'musttail' attribute cannot be used from an Objective-C function}} +} + +@end diff --git a/clang/test/Sema/attr-x86-interrupt.c b/clang/test/Sema/attr-x86-interrupt.c index 952433e2cb8a..564704a56477 100644 --- a/clang/test/Sema/attr-x86-interrupt.c +++ b/clang/test/Sema/attr-x86-interrupt.c @@ -51,7 +51,7 @@ typedef unsigned int Arg2Type; __attribute__((no_caller_saved_registers)) #else // expected-note@+3 {{'foo9' declared here}} -// expected-error@+4 {{interrupt service routine may only call a function with attribute 'no_caller_saved_registers'}} +// expected-warning@+4 {{interrupt service routine should only call a function with attribute 'no_caller_saved_registers'}} #endif void foo9(int *a, Arg2Type b) {} __attribute__((interrupt)) void fooA(int *a, Arg2Type b) { diff --git a/clang/test/Sema/c2x-fallthrough.c b/clang/test/Sema/c2x-fallthrough.c index e5508e0a10f1..baa62aa8f140 100644 --- a/clang/test/Sema/c2x-fallthrough.c +++ b/clang/test/Sema/c2x-fallthrough.c @@ -65,7 +65,7 @@ void g(void) { return; case 0: - [[fallthrough, fallthrough]]; // expected-error {{multiple times}} + [[fallthrough, fallthrough]]; // ok case 1: [[fallthrough(0)]]; // expected-error {{argument list}} case 2: diff --git a/clang/test/Sema/c2x-maybe_unused-errors.c b/clang/test/Sema/c2x-maybe_unused-errors.c index 39ec2da9a152..72cefd10291a 100644 --- a/clang/test/Sema/c2x-maybe_unused-errors.c +++ b/clang/test/Sema/c2x-maybe_unused-errors.c @@ -3,7 +3,7 @@ struct [[maybe_unused]] S1 { // ok int a [[maybe_unused]]; }; -struct [[maybe_unused maybe_unused]] S2 { // expected-error {{attribute 'maybe_unused' cannot appear multiple times in an attribute specifier}} +struct [[maybe_unused, maybe_unused]] S2 { // ok int a; }; struct [[maybe_unused("Wrong")]] S3 { // expected-error {{'maybe_unused' cannot have an argument list}} diff --git a/clang/test/Sema/c2x-nodiscard.c b/clang/test/Sema/c2x-nodiscard.c index cf1f0818419a..812421757d34 100644 --- a/clang/test/Sema/c2x-nodiscard.c +++ b/clang/test/Sema/c2x-nodiscard.c @@ -3,7 +3,7 @@ struct [[nodiscard]] S1 { // ok int i; }; -struct [[nodiscard nodiscard]] S2 { // expected-error {{attribute 'nodiscard' cannot appear multiple times in an attribute specifier}} +struct [[nodiscard, nodiscard]] S2 { // ok int i; }; struct [[nodiscard("Wrong")]] S3 { // FIXME: may need an extension warning. diff --git a/clang/test/Sema/tautological-unsigned-char-zero-compare.cc b/clang/test/Sema/tautological-unsigned-char-zero-compare.cc new file mode 100644 index 000000000000..4d14954b3213 --- /dev/null +++ b/clang/test/Sema/tautological-unsigned-char-zero-compare.cc @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -fsyntax-only \ +// RUN: -fno-signed-char \ +// RUN: -Wtautological-unsigned-zero-compare \ +// RUN: -Wtautological-unsigned-char-zero-compare \ +// RUN: -verify=unsigned %s +// RUN: %clang_cc1 -fsyntax-only \ +// RUN: -Wtautological-unsigned-zero-compare \ +// RUN: -Wtautological-unsigned-char-zero-compare \ +// RUN: -verify=signed %s + +void f(char c, unsigned char uc, signed char cc) { + if (c < 0) + return; + // unsigned-warning@-2 {{comparison of char expression < 0 is always false, since char is interpreted as unsigned}} + if (uc < 0) + return; + // unsigned-warning@-2 {{comparison of unsigned expression < 0 is always false}} + // signed-warning@-3 {{comparison of unsigned expression < 0 is always false}} + if (cc < 0) + return; + // Promoted to integer expressions should not warn. + if (c - 4 < 0) + return; +} + +void ref(char &c, unsigned char &uc, signed char &cc) { + if (c < 0) + return; + // unsigned-warning@-2 {{comparison of char expression < 0 is always false, since char is interpreted as unsigned}} + if (uc < 0) + return; + // unsigned-warning@-2 {{comparison of unsigned expression < 0 is always false}} + // signed-warning@-3 {{comparison of unsigned expression < 0 is always false}} + if (cc < 0) + return; + // Promoted to integer expressions should not warn. + if (c - 4 < 0) + return; +} diff --git a/clang/test/Sema/vla.c b/clang/test/Sema/vla.c index fd66694e8b90..329f32b4f1f9 100644 --- a/clang/test/Sema/vla.c +++ b/clang/test/Sema/vla.c @@ -129,4 +129,9 @@ void test_fold_to_constant_array() { // expected-warning@+1{{variable length array folded to constant array as an extension}} char a8[2][ksize] = {{1,2,3,4},{4,3,2,1}}; + + // expected-warning@+1{{variable length array folded to constant array as an extension}} + char (*a9)[] = (char[2][ksize]) {{1,2,3,4},{4,3,2,1}}; + + char (*a10)[ksize] = 0; } diff --git a/clang/test/SemaCXX/aggregate-initialization.cpp b/clang/test/SemaCXX/aggregate-initialization.cpp index c71a7449d31d..3c12aca12d21 100644 --- a/clang/test/SemaCXX/aggregate-initialization.cpp +++ b/clang/test/SemaCXX/aggregate-initialization.cpp @@ -172,11 +172,20 @@ namespace IdiomaticStdArrayInitDoesNotWarn { }; ArrayAndBaseClass z = {1, 2, 3}; // expected-warning {{suggest braces}} - // It's not clear whether we should be warning in this case. If this - // pattern becomes idiomatic, it would be reasonable to suppress the - // warning here too. + // This pattern is used for tagged aggregates and must not warn template struct JustABaseClass : StdArray {}; - JustABaseClass w = {1, 2, 3}; // expected-warning {{suggest braces}} + JustABaseClass w = {1, 2, 3}; + // but this should be also ok + JustABaseClass v = {{1, 2, 3}}; + + template struct OnionBaseClass : JustABaseClass {}; + OnionBaseClass u = {1, 2, 3}; + OnionBaseClass t = {{{1, 2, 3}}}; + + struct EmptyBase {}; + + template struct AggregateAndEmpty : StdArray, EmptyBase {}; + AggregateAndEmpty p = {1, 2, 3}; // expected-warning {{suggest braces}} #endif #pragma clang diagnostic pop diff --git a/clang/test/SemaCXX/attr-cpuspecific.cpp b/clang/test/SemaCXX/attr-cpuspecific.cpp index 7ec8c6cd0ce2..861711b46383 100644 --- a/clang/test/SemaCXX/attr-cpuspecific.cpp +++ b/clang/test/SemaCXX/attr-cpuspecific.cpp @@ -98,14 +98,12 @@ struct SpecialFuncs { SpecialFuncs& __attribute__((cpu_specific(atom))) operator=(SpecialFuncs&&) = delete; }; -struct BadOutOfLine { +struct OutOfLine { int __attribute__((cpu_specific(atom, ivybridge))) foo(int); }; -int __attribute__((cpu_specific(atom, ivybridge))) BadOutOfLine::foo(int) { return 0; } -// expected-error@+2 {{out-of-line definition of 'foo' does not match any declaration in 'BadOutOfLine'}} -// expected-note@-2 {{member declaration nearly matches}} -int __attribute__((cpu_specific(sandybridge))) BadOutOfLine::foo(int) { return 1; } +int __attribute__((cpu_specific(atom, ivybridge))) OutOfLine::foo(int) { return 0; } +int __attribute__((cpu_specific(sandybridge))) OutOfLine::foo(int) { return 1; } // Ensure Cpp Spelling works. [[clang::cpu_specific(ivybridge,atom)]] int CppSpelling(){} diff --git a/clang/test/SemaCXX/attr-musttail.cpp b/clang/test/SemaCXX/attr-musttail.cpp new file mode 100644 index 000000000000..561184e7a24f --- /dev/null +++ b/clang/test/SemaCXX/attr-musttail.cpp @@ -0,0 +1,269 @@ +// RUN: %clang_cc1 -verify -fsyntax-only -fms-extensions -fcxx-exceptions -fopenmp -triple x86_64-linux %s + +int ReturnsInt1(); +int Func1() { + [[clang::musttail]] ReturnsInt1(); // expected-error {{'musttail' attribute only applies to return statements}} + [[clang::musttail(1, 2)]] return ReturnsInt1(); // expected-error {{'musttail' attribute takes no arguments}} + [[clang::musttail]] return 5; // expected-error {{'musttail' attribute requires that the return value is the result of a function call}} + [[clang::musttail]] return ReturnsInt1(); +} + +void NoFunctionCall() { + [[clang::musttail]] return; // expected-error {{'musttail' attribute requires that the return value is the result of a function call}} +} + +[[clang::musttail]] static int int_val = ReturnsInt1(); // expected-error {{'musttail' attribute cannot be applied to a declaration}} + +void NoParams(); // expected-note {{target function has different number of parameters (expected 1 but has 0)}} +void TestParamArityMismatch(int x) { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return NoParams(); // expected-error {{cannot perform a tail call to function 'NoParams' because its signature is incompatible with the calling function}} +} + +void LongParam(long x); // expected-note {{target function has type mismatch at 1st parameter (expected 'long' but has 'int')}} +void TestParamTypeMismatch(int x) { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return LongParam(x); // expected-error {{cannot perform a tail call to function 'LongParam' because its signature is incompatible with the calling function}} +} + +long ReturnsLong(); // expected-note {{target function has different return type ('int' expected but has 'long')}} +int TestReturnTypeMismatch() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return ReturnsLong(); // expected-error {{cannot perform a tail call to function 'ReturnsLong' because its signature is incompatible with the calling function}} +} + +struct Struct1 { + void MemberFunction(); // expected-note {{'MemberFunction' declared here}} +}; +void TestNonMemberToMember() { + Struct1 st; + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return st.MemberFunction(); // expected-error {{non-member function cannot perform a tail call to non-static member function 'MemberFunction'}} +} + +void ReturnsVoid(); // expected-note {{'ReturnsVoid' declared here}} +struct Struct2 { + void TestMemberToNonMember() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return ReturnsVoid(); // expected-error{{non-static member function cannot perform a tail call to non-member function 'ReturnsVoid'}} + } +}; + +class HasNonTrivialDestructor { +public: + ~HasNonTrivialDestructor() {} + int ReturnsInt(); +}; + +void ReturnsVoid2(); +void TestNonTrivialDestructorInScope() { + HasNonTrivialDestructor foo; // expected-note {{jump exits scope of variable with non-trivial destructor}} + [[clang::musttail]] return ReturnsVoid(); // expected-error {{cannot perform a tail call from this return statement}} +} + +int NonTrivialParam(HasNonTrivialDestructor x); +int TestNonTrivialParam(HasNonTrivialDestructor x) { + [[clang::musttail]] return NonTrivialParam(x); // expected-error {{tail call requires that the return value, all parameters, and any temporaries created by the expression are trivially destructible}} +} + +HasNonTrivialDestructor ReturnsNonTrivialValue(); +HasNonTrivialDestructor TestReturnsNonTrivialValue() { + // FIXME: the diagnostic cannot currently distinguish between needing to run a + // destructor for the return value and needing to run a destructor for some + // other temporary created in the return statement. + [[clang::musttail]] return (ReturnsNonTrivialValue()); // expected-error {{tail call requires that the return value, all parameters, and any temporaries created by the expression are trivially destructible}} +} + +HasNonTrivialDestructor TestReturnsNonTrivialNonFunctionCall() { + [[clang::musttail]] return HasNonTrivialDestructor(); // expected-error {{'musttail' attribute requires that the return value is the result of a function call}} +} + +struct UsesPointerToMember { + void (UsesPointerToMember::*p_mem)(); // expected-note {{'p_mem' declared here}} +}; +void TestUsesPointerToMember(UsesPointerToMember *foo) { + // "this" pointer cannot double as first parameter. + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return (foo->*(foo->p_mem))(); // expected-error {{non-member function cannot perform a tail call to pointer-to-member function 'p_mem'}} +} + +void ReturnsVoid2(); +void TestNestedClass() { + HasNonTrivialDestructor foo; + class Nested { + __attribute__((noinline)) static void NestedMethod() { + // Outer non-trivial destructor does not affect nested class. + [[clang::musttail]] return ReturnsVoid2(); + } + }; +} + +template +T TemplateFunc(T x) { // expected-note{{target function has different return type ('long' expected but has 'int')}} + return x ? 5 : 10; +} +int OkTemplateFunc(int x) { + [[clang::musttail]] return TemplateFunc(x); +} +template +T BadTemplateFunc(T x) { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return TemplateFunc(x); // expected-error {{cannot perform a tail call to function 'TemplateFunc' because its signature is incompatible with the calling function}} +} +long TestBadTemplateFunc(long x) { + return BadTemplateFunc(x); // expected-note {{in instantiation of}} +} + +void IntParam(int x); +void TestVLA(int x) { + HasNonTrivialDestructor vla[x]; // expected-note {{jump exits scope of variable with non-trivial destructor}} + [[clang::musttail]] return IntParam(x); // expected-error {{cannot perform a tail call from this return statement}} +} + +void TestNonTrivialDestructorSubArg(int x) { + [[clang::musttail]] return IntParam(NonTrivialParam(HasNonTrivialDestructor())); // expected-error {{tail call requires that the return value, all parameters, and any temporaries created by the expression are trivially destructible}} +} + +void VariadicFunction(int x, ...); +void TestVariadicFunction(int x, ...) { + [[clang::musttail]] return VariadicFunction(x); // expected-error {{'musttail' attribute may not be used with variadic functions}} +} + +int TakesIntParam(int x); // expected-note {{target function has type mismatch at 1st parameter (expected 'int' but has 'short')}} +int TakesShortParam(short x); // expected-note {{target function has type mismatch at 1st parameter (expected 'short' but has 'int')}} +int TestIntParamMismatch(int x) { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return TakesShortParam(x); // expected-error {{cannot perform a tail call to function 'TakesShortParam' because its signature is incompatible with the calling function}} +} +int TestIntParamMismatch2(short x) { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return TakesIntParam(x); // expected-error {{cannot perform a tail call to function 'TakesIntParam' because its signature is incompatible with the calling function}} +} + +struct TestClassMismatch1 { + void ToFunction(); // expected-note{{target function is a member of different class (expected 'TestClassMismatch2' but has 'TestClassMismatch1')}} +}; +TestClassMismatch1 *tcm1; +struct TestClassMismatch2 { + void FromFunction() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return tcm1->ToFunction(); // expected-error {{cannot perform a tail call to function 'ToFunction' because its signature is incompatible with the calling function}} + } +}; + +__regcall int RegCallReturnsInt(); // expected-note {{target function has calling convention regcall (expected cdecl)}} +int TestMismatchCallingConvention() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return RegCallReturnsInt(); // expected-error {{cannot perform a tail call to function 'RegCallReturnsInt' because it uses an incompatible calling convention}} +} + +int TestNonCapturingLambda() { + auto lambda = []() { return 12; }; // expected-note {{'operator()' declared here}} + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return lambda(); // expected-error {{non-member function cannot perform a tail call to non-static member function 'operator()'}} + + // This works. + auto lambda_fptr = static_cast(lambda); + [[clang::musttail]] return lambda_fptr(); + [[clang::musttail]] return (+lambda)(); +} + +int TestCapturingLambda() { + int x; + auto lambda = [x]() { return 12; }; // expected-note {{'operator()' declared here}} + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return lambda(); // expected-error {{non-member function cannot perform a tail call to non-static member function 'operator()'}} +} + +int TestNonTrivialTemporary(int) { + [[clang::musttail]] return TakesIntParam(HasNonTrivialDestructor().ReturnsInt()); // expected-error {{tail call requires that the return value, all parameters, and any temporaries created by the expression are trivially destructible}} +} + +void ReturnsVoid(); +struct TestDestructor { + ~TestDestructor() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return ReturnsVoid(); // expected-error {{destructor '~TestDestructor' must not return void expression}} // expected-error {{cannot perform a tail call from a destructor}} + } +}; + +struct ClassWithDestructor { // expected-note {{target destructor is declared here}} + void TestExplicitDestructorCall() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return this->~ClassWithDestructor(); // expected-error {{cannot perform a tail call to a destructor}} + } +}; + +struct HasNonTrivialCopyConstructor { + HasNonTrivialCopyConstructor(const HasNonTrivialCopyConstructor &); +}; +HasNonTrivialCopyConstructor ReturnsClassByValue(); +HasNonTrivialCopyConstructor TestNonElidableCopyConstructor() { + // This is an elidable constructor, but when it is written explicitly + // we decline to elide it. + [[clang::musttail]] return HasNonTrivialCopyConstructor(ReturnsClassByValue()); // expected-error{{'musttail' attribute requires that the return value is the result of a function call}} +} + +struct ClassWithConstructor { + ClassWithConstructor() = default; // expected-note {{target constructor is declared here}} +}; +void TestExplicitConstructorCall(ClassWithConstructor a) { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return a.ClassWithConstructor::ClassWithConstructor(); // expected-error{{cannot perform a tail call to a constructor}} expected-warning{{explicit constructor calls are a Microsoft extension}} +} + +void TestStatementExpression() { + ({ + HasNonTrivialDestructor foo; // expected-note {{jump exits scope of variable with non-trivial destructor}} + [[clang::musttail]] return ReturnsVoid2(); // expected-error {{cannot perform a tail call from this return statement}} + }); +} + +struct MyException {}; +void TestTryBlock() { + try { // expected-note {{jump exits try block}} + [[clang::musttail]] return ReturnsVoid2(); // expected-error {{cannot perform a tail call from this return statement}} + } catch (MyException &e) { + } +} + +using IntFunctionType = int(); +IntFunctionType *ReturnsIntFunction(); +long TestRValueFunctionPointer() { + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return ReturnsIntFunction()(); // expected-error{{cannot perform a tail call to function because its signature is incompatible with the calling function}} // expected-note{{target function has different return type ('long' expected but has 'int')}} +} + +void TestPseudoDestructor() { + int n; + using T = int; + [[clang::musttail]] // expected-note {{tail call required by 'musttail' attribute here}} + return n.~T(); // expected-error{{cannot perform a tail call to a destructor}} +} + +struct StructPMF { + typedef void (StructPMF::*PMF)(); + static void TestReturnsPMF(); +}; + +StructPMF *St; +StructPMF::PMF ReturnsPMF(); +void StructPMF::TestReturnsPMF() { + [[clang::musttail]] // expected-note{{tail call required by 'musttail' attribute here}} + return (St->*ReturnsPMF())(); // expected-error{{static member function cannot perform a tail call to pointer-to-member function}} +} + +// These tests are merely verifying that we don't crash with incomplete or +// erroneous ASTs. These cases crashed the compiler in early iterations. + +struct TestBadPMF { + int (TestBadPMF::*pmf)(); + void BadPMF() { + [[clang::musttail]] return ((*this)->*pmf)(); // expected-error {{left hand operand to ->* must be a pointer to class compatible with the right hand operand, but is 'TestBadPMF'}} + } +}; + +namespace ns {} +void TestCallNonValue() { + [[clang::musttail]] return ns; // expected-error {{unexpected namespace name 'ns': expected expression}} +} diff --git a/clang/test/SemaCXX/cxx2a-no-unique-address.cpp b/clang/test/SemaCXX/cxx2a-no-unique-address.cpp index 107466e33145..44d6d3acddde 100644 --- a/clang/test/SemaCXX/cxx2a-no-unique-address.cpp +++ b/clang/test/SemaCXX/cxx2a-no-unique-address.cpp @@ -10,8 +10,8 @@ struct [[no_unique_address]] S { // expected-error {{only applies to non-bit-fie [[no_unique_address]] static void sf(); // expected-error {{only applies to non-bit-field non-static data members}} unsupported-warning {{unknown}} [[no_unique_address]] int b : 3; // expected-error {{only applies to non-bit-field non-static data members}} unsupported-warning {{unknown}} - [[no_unique_address, no_unique_address]] int duplicated; // expected-error {{cannot appear multiple times}} - // unsupported-error@-1 {{cannot appear multiple times}} unsupported-warning@-1 2{{unknown}} + [[no_unique_address, no_unique_address]] int duplicated; // ok + // unsupported-warning@-1 2{{unknown}} [[no_unique_address]] [[no_unique_address]] int duplicated2; // unsupported-warning 2{{unknown}} [[no_unique_address()]] int arglist; // expected-error {{cannot have an argument list}} unsupported-warning {{unknown}} diff --git a/clang/tools/driver/cc1as_main.cpp b/clang/tools/driver/cc1as_main.cpp index 570e3e40ebdd..083fc0846ac1 100644 --- a/clang/tools/driver/cc1as_main.cpp +++ b/clang/tools/driver/cc1as_main.cpp @@ -342,7 +342,7 @@ static bool ExecuteAssembler(AssemblerInvocation &Opts, return Diags.Report(diag::err_target_unknown_triple) << Opts.Triple; ErrorOr> Buffer = - MemoryBuffer::getFileOrSTDIN(Opts.InputFile); + MemoryBuffer::getFileOrSTDIN(Opts.InputFile, /*IsText=*/true); if (std::error_code EC = Buffer.getError()) { Error = EC.message(); diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 9e5e67d3b97d..5ae67d91323d 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -9177,6 +9177,590 @@ TEST_F(FormatTest, FormatsAccessModifiers) { " int j;\n" "};\n", Style); + + FormatStyle NoEmptyLines = getLLVMStyle(); + NoEmptyLines.MaxEmptyLinesToKeep = 0; + verifyFormat("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "public:\n" + "protected:\n" + " int j;\n" + "};\n", + NoEmptyLines); + + NoEmptyLines.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Never; + verifyFormat("struct foo {\n" + "private:\n" + " void f() {}\n" + "private:\n" + " int i;\n" + "public:\n" + "protected:\n" + " int j;\n" + "};\n", + NoEmptyLines); + + NoEmptyLines.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "public:\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + NoEmptyLines); +} + +TEST_F(FormatTest, FormatsAfterAccessModifiers) { + + FormatStyle Style = getLLVMStyle(); + EXPECT_EQ(Style.EmptyLineAfterAccessModifier, FormatStyle::ELAAMS_Never); + verifyFormat("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + Style); + + // Check if lines are removed. + verifyFormat("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n" + " void f() {}\n" + "\n" + "private:\n" + "\n" + " int i;\n" + "\n" + "protected:\n" + "\n" + " int j;\n" + "};\n", + Style); + + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + "\n" + " void f() {}\n" + "\n" + "private:\n" + "\n" + " int i;\n" + "\n" + "protected:\n" + "\n" + " int j;\n" + "};\n", + Style); + + // Check if lines are added. + verifyFormat("struct foo {\n" + "private:\n" + "\n" + " void f() {}\n" + "\n" + "private:\n" + "\n" + " int i;\n" + "\n" + "protected:\n" + "\n" + " int j;\n" + "};\n", + "struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + Style); + + // Leave tests rely on the code layout, test::messUp can not be used. + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Leave; + Style.MaxEmptyLinesToKeep = 0u; + verifyFormat("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + Style); + + // Check if MaxEmptyLinesToKeep is respected. + EXPECT_EQ("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + " void f() {}\n" + "\n" + "private:\n" + "\n\n\n" + " int i;\n" + "\n" + "protected:\n" + "\n\n\n" + " int j;\n" + "};\n", + Style)); + + Style.MaxEmptyLinesToKeep = 1u; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n" + " void f() {}\n" + "\n" + "private:\n" + "\n" + " int i;\n" + "\n" + "protected:\n" + "\n" + " int j;\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n" + " void f() {}\n" + "\n" + "private:\n" + "\n" + " int i;\n" + "\n" + "protected:\n" + "\n" + " int j;\n" + "};\n", + Style)); + // Check if no lines are kept. + EXPECT_EQ("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + format("struct foo {\n" + "private:\n" + " void f() {}\n" + "\n" + "private:\n" + " int i;\n" + "\n" + "protected:\n" + " int j;\n" + "};\n", + Style)); + // Check if MaxEmptyLinesToKeep is respected. + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n" + " void f() {}\n" + "\n" + "private:\n" + "\n" + " int i;\n" + "\n" + "protected:\n" + "\n" + " int j;\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + " void f() {}\n" + "\n" + "private:\n" + "\n\n\n" + " int i;\n" + "\n" + "protected:\n" + "\n\n\n" + " int j;\n" + "};\n", + Style)); + + Style.MaxEmptyLinesToKeep = 10u; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + " void f() {}\n" + "\n" + "private:\n" + "\n\n\n" + " int i;\n" + "\n" + "protected:\n" + "\n\n\n" + " int j;\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + " void f() {}\n" + "\n" + "private:\n" + "\n\n\n" + " int i;\n" + "\n" + "protected:\n" + "\n\n\n" + " int j;\n" + "};\n", + Style)); + + // Test with comments. + Style = getLLVMStyle(); + verifyFormat("struct foo {\n" + "private:\n" + " // comment\n" + " void f() {}\n" + "\n" + "private: /* comment */\n" + " int i;\n" + "};\n", + Style); + verifyFormat("struct foo {\n" + "private:\n" + " // comment\n" + " void f() {}\n" + "\n" + "private: /* comment */\n" + " int i;\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n" + " // comment\n" + " void f() {}\n" + "\n" + "private: /* comment */\n" + "\n" + " int i;\n" + "};\n", + Style); + + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + "\n" + " // comment\n" + " void f() {}\n" + "\n" + "private: /* comment */\n" + "\n" + " int i;\n" + "};\n", + "struct foo {\n" + "private:\n" + " // comment\n" + " void f() {}\n" + "\n" + "private: /* comment */\n" + " int i;\n" + "};\n", + Style); + verifyFormat("struct foo {\n" + "private:\n" + "\n" + " // comment\n" + " void f() {}\n" + "\n" + "private: /* comment */\n" + "\n" + " int i;\n" + "};\n", + Style); + + // Test with preprocessor defines. + Style = getLLVMStyle(); + verifyFormat("struct foo {\n" + "private:\n" + "#ifdef FOO\n" + "#endif\n" + " void f() {}\n" + "};\n", + Style); + verifyFormat("struct foo {\n" + "private:\n" + "#ifdef FOO\n" + "#endif\n" + " void f() {}\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n" + "#ifdef FOO\n" + "#endif\n" + " void f() {}\n" + "};\n", + Style); + + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + "\n" + "#ifdef FOO\n" + "#endif\n" + " void f() {}\n" + "};\n", + "struct foo {\n" + "private:\n" + "#ifdef FOO\n" + "#endif\n" + " void f() {}\n" + "};\n", + Style); + verifyFormat("struct foo {\n" + "private:\n" + "\n" + "#ifdef FOO\n" + "#endif\n" + " void f() {}\n" + "};\n", + Style); +} + +TEST_F(FormatTest, FormatsAfterAndBeforeAccessModifiersInteraction) { + // Combined tests of EmptyLineAfterAccessModifier and + // EmptyLineBeforeAccessModifier. + FormatStyle Style = getLLVMStyle(); + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Always; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + "\n" + "protected:\n" + "};\n", + Style); + + Style.MaxEmptyLinesToKeep = 10u; + // Both remove all new lines. + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Never; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Never; + verifyFormat("struct foo {\n" + "private:\n" + "protected:\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style); + + // Leave tests rely on the code layout, test::messUp can not be used. + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Leave; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Leave; + Style.MaxEmptyLinesToKeep = 10u; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); + Style.MaxEmptyLinesToKeep = 3u; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); + Style.MaxEmptyLinesToKeep = 1u; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); // Based on new lines in original document and not + // on the setting. + + Style.MaxEmptyLinesToKeep = 10u; + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Always; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Leave; + // Newlines are kept if they are greater than zero, + // test::messUp removes all new lines which changes the logic + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Leave; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + // test::messUp removes all new lines which changes the logic + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Leave; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Never; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); // test::messUp removes all new lines which changes + // the logic. + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Never; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Leave; + verifyFormat("struct foo {\n" + "private:\n" + "protected:\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style); + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Always; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Never; + EXPECT_EQ("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + format("struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style)); // test::messUp removes all new lines which changes + // the logic. + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_Never; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + "protected:\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style); + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_LogicalBlock; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; + verifyFormat("struct foo {\n" + "private:\n" + "protected:\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style); + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_LogicalBlock; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Leave; + verifyFormat("struct foo {\n" + "private:\n" + "protected:\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style); + + Style.EmptyLineBeforeAccessModifier = FormatStyle::ELBAMS_LogicalBlock; + Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Never; + verifyFormat("struct foo {\n" + "private:\n" + "protected:\n" + "};\n", + "struct foo {\n" + "private:\n" + "\n\n\n" + "protected:\n" + "};\n", + Style); } TEST_F(FormatTest, FormatsArrays) { diff --git a/clang/unittests/Format/SortImportsTestJS.cpp b/clang/unittests/Format/SortImportsTestJS.cpp index 72c79ac71828..a0bd76877b9e 100644 --- a/clang/unittests/Format/SortImportsTestJS.cpp +++ b/clang/unittests/Format/SortImportsTestJS.cpp @@ -307,6 +307,56 @@ TEST_F(SortImportsTestJS, SortDefaultImports) { "import {A} from 'a';\n"); } +TEST_F(SortImportsTestJS, MergeImports) { + // basic operation + verifySort("import {X, Y} from 'a';\n" + "import {Z} from 'z';\n" + "\n" + "X + Y + Z;\n", + "import {X} from 'a';\n" + "import {Z} from 'z';\n" + "import {Y} from 'a';\n" + "\n" + "X + Y + Z;\n"); + + // merge only, no resorting. + verifySort("import {A, B} from 'foo';\n", "import {A} from 'foo';\n" + "import {B} from 'foo';"); + + // empty imports + verifySort("import {A} from 'foo';\n", "import {} from 'foo';\n" + "import {A} from 'foo';"); + + // ignores import * + verifySort("import * as foo from 'foo';\n" + "import {A} from 'foo';\n", + "import * as foo from 'foo';\n" + "import {A} from 'foo';\n"); + + // ignores default import + verifySort("import X from 'foo';\n" + "import {A} from 'foo';\n", + "import X from 'foo';\n" + "import {A} from 'foo';\n"); + + // keeps comments + // known issue: loses the 'also a' comment. + verifySort("// a\n" + "import {/* x */ X, /* y */ Y} from 'a';\n" + "// z\n" + "import {Z} from 'z';\n" + "\n" + "X + Y + Z;\n", + "// a\n" + "import {/* y */ Y} from 'a';\n" + "// z\n" + "import {Z} from 'z';\n" + "// also a\n" + "import {/* x */ X} from 'a';\n" + "\n" + "X + Y + Z;\n"); +} + } // end namespace } // end namespace format } // end namespace clang diff --git a/clang/unittests/Frontend/CompilerInvocationTest.cpp b/clang/unittests/Frontend/CompilerInvocationTest.cpp index 066d02b02fa9..5062a2e6cb8f 100644 --- a/clang/unittests/Frontend/CompilerInvocationTest.cpp +++ b/clang/unittests/Frontend/CompilerInvocationTest.cpp @@ -97,6 +97,18 @@ TEST(ContainsN, Two) { ASSERT_THAT(Array, ContainsN(StrEq("x"), 2)); } +// Copy constructor performs a deep copy of reference-counted pointers. + +TEST(CompilerInvocationTest, DeepCopyConstructor) { + CompilerInvocation A; + A.getAnalyzerOpts()->Config["Key"] = "Old"; + + CompilerInvocation B(A); + B.getAnalyzerOpts()->Config["Key"] = "New"; + + ASSERT_EQ(A.getAnalyzerOpts()->Config["Key"], "Old"); +} + // Boolean option with a keypath that defaults to true. // The only flag with a negative spelling can set the keypath to false. diff --git a/clang/unittests/Introspection/IntrospectionTest.cpp b/clang/unittests/Introspection/IntrospectionTest.cpp index 5e32d7d593c7..ad21748f11f8 100644 --- a/clang/unittests/Introspection/IntrospectionTest.cpp +++ b/clang/unittests/Introspection/IntrospectionTest.cpp @@ -30,19 +30,104 @@ template std::map FormatExpected(const MapType &Accessors) { std::map Result; - llvm::transform(Accessors, + llvm::transform(llvm::make_filter_range(Accessors, + [](const auto &Accessor) { + return Accessor.first.isValid(); + }), std::inserter(Result, Result.end()), [](const auto &Accessor) { - return std::make_pair( - LocationCallFormatterCpp::format(Accessor.second.get()), - Accessor.first); + return std::make_pair(LocationCallFormatterCpp::format( + *Accessor.second.get()), + Accessor.first); }); return Result; } #define STRING_LOCATION_PAIR(INSTANCE, LOC) Pair(#LOC, INSTANCE->LOC) +/** + A test formatter for a hypothetical language which needs + neither casts nor '->'. +*/ +class LocationCallFormatterSimple { +public: + static void print(const LocationCall &Call, llvm::raw_ostream &OS) { + if (Call.isCast()) { + if (const LocationCall *On = Call.on()) + print(*On, OS); + return; + } + if (const LocationCall *On = Call.on()) { + print(*On, OS); + OS << '.'; + } + OS << Call.name(); + if (Call.args().empty()) { + OS << "()"; + return; + } + OS << '(' << Call.args().front(); + for (const std::string &Arg : Call.args().drop_front()) { + OS << ", " << Arg; + } + OS << ')'; + } + + static std::string format(const LocationCall &Call) { + std::string Result; + llvm::raw_string_ostream OS(Result); + print(Call, OS); + OS.flush(); + return Result; + } +}; + +TEST(Introspection, SourceLocations_CallContainer) { + SourceLocationMap slm; + SharedLocationCall Prefix; + slm.insert(std::make_pair( + SourceLocation(), + llvm::makeIntrusiveRefCnt(Prefix, "getSourceRange"))); + EXPECT_EQ(slm.size(), 1u); + + auto callTypeLoc = + llvm::makeIntrusiveRefCnt(Prefix, "getTypeLoc"); + slm.insert(std::make_pair( + SourceLocation(), + llvm::makeIntrusiveRefCnt(callTypeLoc, "getSourceRange"))); + EXPECT_EQ(slm.size(), 2u); +} + +TEST(Introspection, SourceLocations_CallChainFormatting) { + SharedLocationCall Prefix; + auto chainedCall = llvm::makeIntrusiveRefCnt( + llvm::makeIntrusiveRefCnt(Prefix, "getTypeLoc"), + "getSourceRange"); + EXPECT_EQ(LocationCallFormatterCpp::format(*chainedCall), + "getTypeLoc().getSourceRange()"); +} + +TEST(Introspection, SourceLocations_Formatter) { + SharedLocationCall Prefix; + auto chainedCall = llvm::makeIntrusiveRefCnt( + llvm::makeIntrusiveRefCnt( + llvm::makeIntrusiveRefCnt( + llvm::makeIntrusiveRefCnt( + Prefix, "getTypeSourceInfo", LocationCall::ReturnsPointer), + "getTypeLoc"), + "getAs", LocationCall::IsCast), + "getNameLoc"); + + EXPECT_EQ("getTypeSourceInfo()->getTypeLoc().getAs()." + "getNameLoc()", + LocationCallFormatterCpp::format(*chainedCall)); + EXPECT_EQ("getTypeSourceInfo().getTypeLoc().getNameLoc()", + LocationCallFormatterSimple::format(*chainedCall)); +} + TEST(Introspection, SourceLocations_Stmt) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; auto AST = buildASTFromCode("void foo() {} void bar() { foo(); }", "foo.cpp", std::make_shared()); auto &Ctx = AST->getASTContext(); @@ -59,11 +144,6 @@ TEST(Introspection, SourceLocations_Stmt) { auto Result = NodeIntrospection::GetLocations(FooCall); - if (Result.LocationAccessors.empty() && Result.RangeAccessors.empty()) - { - return; - } - auto ExpectedLocations = FormatExpected(Result.LocationAccessors); @@ -81,6 +161,8 @@ TEST(Introspection, SourceLocations_Stmt) { } TEST(Introspection, SourceLocations_Decl) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; auto AST = buildASTFromCode(R"cpp( namespace ns1 { @@ -106,7 +188,7 @@ ns1::ns2::Foo ns1::ns2::Bar::Nested::method(int i, bool b) const auto BoundNodes = ast_matchers::match( decl(hasDescendant( - cxxMethodDecl(hasName("method")).bind("method"))), + cxxMethodDecl(hasName("method"), isDefinition()).bind("method"))), TU, Ctx); EXPECT_EQ(BoundNodes.size(), 1u); @@ -115,10 +197,6 @@ ns1::ns2::Foo ns1::ns2::Bar::Nested::method(int i, bool b) const auto Result = NodeIntrospection::GetLocations(MethodDecl); - if (Result.LocationAccessors.empty() && Result.RangeAccessors.empty()) { - return; - } - auto ExpectedLocations = FormatExpected(Result.LocationAccessors); @@ -126,11 +204,9 @@ ns1::ns2::Foo ns1::ns2::Bar::Nested::method(int i, bool b) const UnorderedElementsAre( STRING_LOCATION_PAIR(MethodDecl, getBeginLoc()), STRING_LOCATION_PAIR(MethodDecl, getBodyRBrace()), - STRING_LOCATION_PAIR(MethodDecl, getEllipsisLoc()), STRING_LOCATION_PAIR(MethodDecl, getInnerLocStart()), STRING_LOCATION_PAIR(MethodDecl, getLocation()), STRING_LOCATION_PAIR(MethodDecl, getOuterLocStart()), - STRING_LOCATION_PAIR(MethodDecl, getPointOfInstantiation()), STRING_LOCATION_PAIR(MethodDecl, getTypeSpecEndLoc()), STRING_LOCATION_PAIR(MethodDecl, getTypeSpecStartLoc()), STRING_LOCATION_PAIR(MethodDecl, getEndLoc()))); @@ -145,3 +221,705 @@ ns1::ns2::Foo ns1::ns2::Bar::Nested::method(int i, bool b) const STRING_LOCATION_PAIR(MethodDecl, getReturnTypeSourceRange()), STRING_LOCATION_PAIR(MethodDecl, getSourceRange()))); } + +TEST(Introspection, SourceLocations_NNS) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; + auto AST = + buildASTFromCode(R"cpp( +namespace ns +{ + struct A { + void foo(); +}; +} +void ns::A::foo() {} +)cpp", + "foo.cpp", std::make_shared()); + auto &Ctx = AST->getASTContext(); + auto &TU = *Ctx.getTranslationUnitDecl(); + + auto BoundNodes = ast_matchers::match( + decl(hasDescendant(nestedNameSpecifierLoc().bind("nns"))), TU, Ctx); + + EXPECT_EQ(BoundNodes.size(), 1u); + + const auto *NNS = BoundNodes[0].getNodeAs("nns"); + + auto Result = NodeIntrospection::GetLocations(NNS); + + auto ExpectedLocations = + FormatExpected(Result.LocationAccessors); + + EXPECT_THAT( + ExpectedLocations, + UnorderedElementsAre(STRING_LOCATION_PAIR(NNS, getBeginLoc()), + STRING_LOCATION_PAIR(NNS, getEndLoc()), + STRING_LOCATION_PAIR(NNS, getLocalBeginLoc()), + STRING_LOCATION_PAIR(NNS, getLocalEndLoc()))); + + auto ExpectedRanges = FormatExpected(Result.RangeAccessors); + + EXPECT_THAT( + ExpectedRanges, + UnorderedElementsAre(STRING_LOCATION_PAIR(NNS, getLocalSourceRange()), + STRING_LOCATION_PAIR(NNS, getSourceRange()))); +} + +TEST(Introspection, SourceLocations_TA_Type) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; + auto AST = + buildASTFromCode(R"cpp( +template + struct A { + void foo(); +}; + +void foo() +{ + A a; +} +)cpp", + "foo.cpp", std::make_shared()); + auto &Ctx = AST->getASTContext(); + auto &TU = *Ctx.getTranslationUnitDecl(); + + auto BoundNodes = ast_matchers::match( + decl(hasDescendant(templateArgumentLoc().bind("ta"))), TU, Ctx); + + EXPECT_EQ(BoundNodes.size(), 1u); + + const auto *TA = BoundNodes[0].getNodeAs("ta"); + + auto Result = NodeIntrospection::GetLocations(TA); + + auto ExpectedLocations = + FormatExpected(Result.LocationAccessors); + + EXPECT_THAT(ExpectedLocations, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getLocation()))); + + auto ExpectedRanges = FormatExpected(Result.RangeAccessors); + + EXPECT_THAT(ExpectedRanges, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getSourceRange()))); +} + +TEST(Introspection, SourceLocations_TA_Decl) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; + auto AST = + buildASTFromCode(R"cpp( +template +void test2() {} +void doNothing() {} +void test() { + test2(); +} +)cpp", + "foo.cpp", std::make_shared()); + auto &Ctx = AST->getASTContext(); + auto &TU = *Ctx.getTranslationUnitDecl(); + + auto BoundNodes = ast_matchers::match( + decl(hasDescendant(templateArgumentLoc().bind("ta"))), TU, Ctx); + + EXPECT_EQ(BoundNodes.size(), 1u); + + const auto *TA = BoundNodes[0].getNodeAs("ta"); + + auto Result = NodeIntrospection::GetLocations(TA); + + auto ExpectedLocations = + FormatExpected(Result.LocationAccessors); + + EXPECT_THAT(ExpectedLocations, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getLocation()))); + + auto ExpectedRanges = FormatExpected(Result.RangeAccessors); + + EXPECT_THAT(ExpectedRanges, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getSourceRange()))); +} + +TEST(Introspection, SourceLocations_TA_Nullptr) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; + auto AST = + buildASTFromCode(R"cpp( +template +void test2() {} +void doNothing() {} +void test() { + test2(); +} +)cpp", + "foo.cpp", std::make_shared()); + auto &Ctx = AST->getASTContext(); + auto &TU = *Ctx.getTranslationUnitDecl(); + + auto BoundNodes = ast_matchers::match( + decl(hasDescendant(templateArgumentLoc().bind("ta"))), TU, Ctx); + + EXPECT_EQ(BoundNodes.size(), 1u); + + const auto *TA = BoundNodes[0].getNodeAs("ta"); + + auto Result = NodeIntrospection::GetLocations(TA); + + auto ExpectedLocations = + FormatExpected(Result.LocationAccessors); + + EXPECT_THAT(ExpectedLocations, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getLocation()))); + + auto ExpectedRanges = FormatExpected(Result.RangeAccessors); + + EXPECT_THAT(ExpectedRanges, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getSourceRange()))); +} + +TEST(Introspection, SourceLocations_TA_Integral) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; + auto AST = + buildASTFromCode(R"cpp( +template +void test2() {} +void test() { + test2<42>(); +} +)cpp", + "foo.cpp", std::make_shared()); + auto &Ctx = AST->getASTContext(); + auto &TU = *Ctx.getTranslationUnitDecl(); + + auto BoundNodes = ast_matchers::match( + decl(hasDescendant(templateArgumentLoc().bind("ta"))), TU, Ctx); + + EXPECT_EQ(BoundNodes.size(), 1u); + + const auto *TA = BoundNodes[0].getNodeAs("ta"); + + auto Result = NodeIntrospection::GetLocations(TA); + + auto ExpectedLocations = + FormatExpected(Result.LocationAccessors); + + EXPECT_THAT(ExpectedLocations, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getLocation()))); + + auto ExpectedRanges = FormatExpected(Result.RangeAccessors); + + EXPECT_THAT(ExpectedRanges, + UnorderedElementsAre(STRING_LOCATION_PAIR(TA, getSourceRange()))); +} + +TEST(Introspection, SourceLocations_TA_Template) { + if (!NodeIntrospection::hasIntrospectionSupport()) + return; + auto AST = + buildASTFromCode(R"cpp( +template class A; +template