This project provides an insight into the internal verification of a 32-bit single cycle processor that implements the Reduced Instruction Set-V and displayed on seven segment on Basys3 FPGA board. The hardware structures were realized using Verilog Hardware Description Language.
processor-architecture fpga processor verilog instruction-set-architecture risc-v fpga-board 7-segment-display risc-v-architecture
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Updated
Dec 7, 2022 - Tcl