Autumn Minor Bug Fixes

This release contains minor bug fixes and features as requested during Autumn Term

• Current version v2.4.0

v2.4.0

• It is now possible to reorder the ports on a custom symbol made from a design sub-sheet by editing the sub-sheet and moving port components. The order used on the symbol will be the Y coordinate of the components. Wires will stay connected when ports are reordered.
• A bug renaming components in copy and paste has been corrected
• N bit register with enable can now have size altered after creation
• Canvas change detection (used to enable save button) will now be sensitive to movement of disconnected components
• Macos builds will now exit the app fully on exit. Previously they stayed on the tray without a window but would not correctly spawn another window.

v2.3.3

• Many changes to update the build.
• Very minor changes to make allowed names and error messages better
• On loading make default directory for load/save the user documents directory

v2.3.2

mend small glitch where autoscrolling causes components to fly off edge of screen

• Fix bug from #114, see thread there for additional info and what may be enhanced in the future

v2.3.1

Some issues that will be important when managing large designs are fixed.

• Fixed a bug in rename sheet function that caused the old sheet to reappear in the design after sheet change, unless project is closed and re-opened before sheet change.
• Fixed a bug in delete sheet function that prevented deletion of sheets, unless project is closed and re-opened before sheet change
• Improve formatting of sheet menu
• Fit circuit to window on errors only if all errors are not visible. This is better functionality for very large circuits where errors can best be seen at higher zoom.

v2.3.0

Minor usability improvements as requested: see issues.

• Close issue #113
• Close issue #112
• Close issue #111

Autumn 2021 - stress testing release

Latest release: v2.2.9

This is a minor upgrade with some significant bug fixes prior to stress-testing of the complete application, before the next academic year. In addition a few requested features by stress testers have been added.

v2.2.9

Features added from v2.2.8

• Small improvements in UI interlocks to prevent not useful tab selections
• Small changes to verilog output names

v2.2.8

Features added from v2.2.7

• Buswire speed has increased a lot on large designs, will make moving wires and components more fluid
• Extra interlocks on changing project when current file is not saved

v2.2.7

Bugs fixed from v2.2.6

• Wire jumps are now correctly added and removed

v2.2.6

Bugs fixed from v2.2.3

NB the older implementation v2.2.3 is kept here for reference

Features added from v2.2.3

• Some fine tuning of the new wire routing
• display bus compare in hex
• Full 5-segment manual routing is now allowed on left-to-right connections (ones that do not turn back on themselves). The difficult thing here is to get the behaviour when components are moved right. You want the manual changes to be sticky, but not too sticky. The new algorithm seems to do that OK.

v2.2.3

New features added from v2.2.2

• Better cycle detection (cycles through asynch RAMs are now highlighted properly)
• Better splitwire and mergewires components. Bit number indications + correct colors when selected or errored
• Improve RegisterE component (make number of bits changeable)
• Improve register and register E formatting - add number of bits to legend
• Minor improvements to draw block formatting

v2.2.2

Bugs fixed from v2.2.1

• Async RAM outputs old state bug fixed

v2.2.1

Bugs fixed from v2.2.0

• Buswire routing restricted eliminating weird routing (perhaps)
• Propagation error in Async RAM fixed

v2.2.0

New features added from v2.1.1

• Make wire routing look nicer for horizontal right-to-left wires
• New asynchronous read RAM added

Bugs fixed from v2.1.1

• App would crash sometimes when selecting wires (buswire error)
• Wire routing would sometimes go wrong leading to non-perpendicular wires (buswire error)

Summer 2021

Latest version: v2.1.1

Changes in v2.1.1

• Bug Fix
  • Fix occasional scroll reset to top-left while editing

Changes in v2.1.0

• New Features
  • Large speedup in fast simulation setup time, for better UX changing sheets etc with big designs

Beta Release

Beta Release

This release is the official beta release, after fixing the various bug reports and improving the features from the alpha release.

We will continue to fix bugs if any are reported and post new versions here if that happens.

Current version: 2.0.24

Changes in v2.0.24

• New Features
  • Better manual routing: part manually routed wired remember their manual routing while still auto-routing endpoints and resetting to auto when topology changes.
  • Spinners improved on most long delays
  • Group move delay improved

Changes in 2.0.23

• BugFixes
  • try again to fix simulation UI.

Changes in 2.0.22

• BugFixes
  • Remove pesky q=0 assignments in synch RAM & ROM Verilog that crash some synthesis tools (but make Verilog simulation behave better
  • NB this fix will mean that synch RAM and ROM outputs are X during 1st cycle of a Verilog simulation. They are probably still guaranteed to be 0 in the synthesised logic (though this is not entirely clear). Normally your code would not use these 1st cycle outputs, so it does not matter.

Changes in v2.0.21

• BugFixes
  • Fixed Verilog name generation for Issie names with strange characters
  • Fixed Verilog ROM generation (was causing syntax error)
  • Fixed Verilog multiple RAM or ROM modules

Changes in 2.0.19

• BugFixes
  • Fixed a bug where for some values of number of steps the 'run simulation multiple steps' progress bar logic would crash the app.

Changes in v2.0.18

• BugFixes
  • Fix case where a RAM created from a ram data file has data file changed externally. This now updates the RAM initialisation.

Changes in v2.0.17

• BugFixes
  • Fix Verilog output from constants defined with negative numbers

Changes in v2.0.16

• BugFixes
  • Make error highlighting work from step simulation, as should be. (Sorry this was not fixed earlier).

Changes in v2.0.15

• BugFixes
  • Verilog output: XNOR crash mended.
  • Verilog output: Syntax for RAMs in synthesis.
  • Verilog output: invalid verilog names fixed

Changes in v2.0.14

• Cosmetic changes only
• No bug fixes
• Features
  • Progress bar for long simulations
  • Simulation error messages made slightly more relevant.

Changes in v2.0.13

• BugFixes
  • Fix syntax regression in Verilog output introduced in v2.0.12
  • Fix properties description of RAM function

Changes in v2.0.12

• BugFixes
  • Verilog synthesis output is now correct (we think). Link to synthesis work-flow instructions posted. The (new) Verilog output functionality is now complete.
• Features
  • Custom component ports are now ordered on creating a new instance
    • Existing instances stay as is
    • New instances have ports ordered by the last saved vertical position of the relevant port Input or Output component
    • Allows user ordering of ports on custom component symbols

Changes in v2.0.11

• BugFixes
  • Verilog simulation output is now identical to issie output over all current tests
• Features
  • Verilog output can be generated in either simulation or "ready to synthesise" form
  • Breaking Change. Synchronous RAMs during write cycle now put the previous cycle's read data (memOld[addrOld]) on dout. previous Issie simulation had put dout = din in a write cycle so that the read set up in the previous cycle was lost. The new spec is consistent with the RAMs synthesised, and more useful for pipelined designs, but the change in spec may alter correctness of designs if you rely on dout = din when synchronous RAM WEN=1. It is quite easy to create the old RAM spec from a new RAM and a MUX, so those affected could do that.

Changes in v2.0.10

• BugFixes
  • Fix a bug where wire labels can sometimes cause waveform simulation (but not step simulation) to crash.

Changes in v2.0.9

• Features
  • Very large simulation speed-up

Changes in v2.0.8

• Features
  • Copy/Paste leaves Wire Labels without changing them. This will be wanted when the Label's driver is not pasted with the label, and not wanted in some other cases so it is not clear whether this is the best solution. But it is only a tiny code change so worth making given user feedback. Probably the final solution should be an algorithm that analyses the circuit being pasted and adapts to this. Feedback welcome.

Changes in v2.0.7

• Features

  • Speed up very long/large simulations (taking more than 20s) by remembering only last 600 steps

• BugFixes

  • Complete legacy simulation removal (not correctly done in 2.0.6)

Changes in v2.0.6

• BugFixes
  • Fixes a problem where some large circuits caused legacy simulation to crash - by disabling all elements of legacy simulation.

Changes in v2.0.5

• BugFixes
  • Fixed a bug where Wave Simulator wire selection would persist upon starting a Step Simulation

Changes in v2.0.4

• BugFixes
  • Fixed errors in ROM and Asynchronous ROM components

Changes in 2.0.3

• BugFixes
  • Fixed a bug where long simulations did not deliver correct results

Changes in 2.0.2

• Features
  • "Goto" step in step simulation
• Bugfixes
  • Fixed a bug where step simulation would be incorrect due to remembered previous simulation

Changes in 2.0.1

• Features
  • Changed Ctrl+W from fit canvas to screen to fit circuit to screen
• Bugfixes
  • Fixed a bug that caused the scroll position to be incorrect when changing sheets, causing the mouse to be offset
  • Fixed a bug that caused RAM viewer in wave simulator to be incorrect

Changes in v2.0.0 (from v1.9.0)

• Features

  • Added automatic rescaling of custom components to fit port/label names
  • Added a popup to allow the user to automatically update custom components upon saving a sheet. Ports can be renamed without reconnection
  • Improved data entry and display for constants
  • Added better error reporting if opening a project on disk with wrong access permissions

• Bugfixes

  • Fixed a bug that caused components with attributes such as width to not increment the automatic renaming properly
  • Fixed a bug that caused the mouse coordinates to be slightly north west making it difficult to click on wires / ports properly
  • Fixed a bug that caused the WaveSim error sidebar to automatically disappear
  • Fixed a bug that prevented error highlighting in the simulate tab
  • Fixed a bug that caused the components to not be movable after the circuit had a WaveSim error

Alpha release

Latest binaries released here: v1.9.7

• Old draw block has been replaced with an F# draw library

Full list of changes

• New component
  • Viewer component can be added to any net on any sheet, and will allow both Step and Wave simulation to see the net it is attached to, even if this is a subsheet.
• Gates
  • New-style IEEE rectangular 2 input gates replace old-style different shape gates
  • See also future works
• Keybinds
  • Copy: Ctrl+C
  • Paste: Ctrl+V
  • Undo: Ctrl+Z
  • Redo: Ctrl+Y
  • Save: Ctrl+S
  • Zoom in application: Ctrl+Shift+=
  • Zoom out application: Ctrl+Shift+-
  • Zoom in canvas: Shift+=
  • Zoom out canvas: Shift+-
  • Zoom in/out canvas: Ctrl+Mousewheel
  • Zoom canvas to fit screen: Ctrl+W
  • Select all: Ctrl+A
  • Cancel operation: Esc
• UI
  • Drag mouse left click creates a selection box
  • Holding Ctrl toggles selection
• Features / Bugfixes
  • Verilog output (experimental)
    • Circuit can be output as a single Verilog file for synthesis or Verilog 3rd party simulation
    • Current output file, pasted into online Icarus v10 Verilog simulator, prints out the simulation, seems to work on some big designs.
  • Simulation
    • New fast simulation released informally in v1.2.0
    • Fixes all previous bugs (completely)
    • Robust algorithm - designed for quick fixes if there are any alpha bugs
    • Approx 10X faster than old simulation.
  • Manual wire routing
    • Left click and drag a wire to move it manually
    • Move an attached component to reset to automatic routing
    • UPDATES TO COME: This current system is not ideal, and a better version of it is high on the priority list
  • Adding/pasting components
    • Adding a component will no longer spawn it at a random canvas position
    • Click to drop implemented
    • Upon selecting the component in the catalogue, move the mouse and click to place the component
    • When pasting, upon pressing Ctrl+V the copied components will be shown at the mouse location, and can be placed anywhere that does not overlap components
    • Overlapping components will be shown in red
  • Automatic label naming
    • Pasting copied symbols will automatically update the names by altering (or adding) the number suffix
  • Subsheets (AKA "custom components")
    • On changing the inputs or outputs of a sheet used as a subsheet all of its instances are updated
    • Where ports can be matched existing connections will remain connected
  • Saving
    • Autosave has been removed as ISSIE no longer crashes randomly
    • The 'Save' button will be opaque and green if there are unsaved changes
    • Switching sheet will save changes automatically
    • If you try to exit the program with unsaved changes, a prompt will come up asking if you wish to close without saving, or go back and save
  • Sheet corruption fixed
  • Undo/Redo
    • Now undoes/redoes an entire pasted section rather than 1 by 1
  • Memories ROM/RAM
    • ROM or initial RAM contents may be exported to files, or imported from them
    • New signed and unsigned multiplier ROM option
  • Waveform simulator
    • Remembers previous order
    • Preselection
  • Constant components
    • Constants can be entered in signed or unsigned decimal, hex, binary
    • Constant components remember and display the format in which the number was entered (e.g. 0xff instead of -1)
    • Constant properties display different representations of constant
    • Constants can now be up to 64 bit in length.
• Lag/latency
  • Vastly improved most slow operations (right hand tab, load project, change sheet, waveform simulation etc)
  • Throttling has been added so that in the event of slow hardware or if you are doing large operations e.g. moving many components at once, the program will drop frames in order to prevent lag. In this case it will appear more stuttery, but be more responsive and useable. Most people should not notice any stuttering problems.

Fix simulation release: end of March

This release incorporates a completely new simulator (1500 lines F#) which cannot have the "propagation" bugs affecting the old simulator and is also typically about 10X faster. Simulation should now be completely deterministic.

• The simulator is still not fully tested but appears to work for the (large) examples where the old simulator failed.
• The simulator is not yet optimised: additional speedup is possible but for ~ 500 components it is probably not needed.
• Added benefit is that wave simulations are now much faster than before
• Other problems with Issie remain unchanged

v1.1.7 March 2021

Fix very obscure Issie simulation bug

On large designs with multiple sheets sometimes data would fail to be propagated. This version is experimental and adds code that aggressively propagates data. It appears to fix the existing bug.

The simulation code is due a major rewrite that does away entirely with value propagation in clocked simulation, which is a very bad idea and the source of many current problems.

• Fix Issie simulation propagation bug

Fix "Issie ate my sheets"

Issie has had a long-standing UI problem where under some circumstances multiple repeated design sheet renames or changes, made before the first change has completed, can result in over-written sheets.

This release cures one version of this, which can be found where the sheet open button is pressed repeatedly before the sheet open operation has terminated. After the fix - if you click multiple times Issie will re-open the same sheet multiple times - taking even longer - but not destroying data.

It is hoped that this fix has cured the problem completely.

Until the UI is rewritten from scratch eliminating these problems note that patience is needed when you have large designs - Issie can take 10s to open a new sheet and you need to wait.

The UI is obviously not good in this respect - but a full rewrite must await enough time to complete it.

• fix problem where repeated pressing of open or rename sheet buttons can result in sheets overwritten.

Spring Term 2nd half bug fixes

• Mend RAM view in waveform viewer

v1.1.4 minor UI change

• make selection of fixed vs interactive connection router more transparent
• fix minor bug in wavesim label names
• fix rare bug fixed where cyclic connections through wire labels can cause Issie to crash
• fix exceptions loading corrupt connections causing file operations to be blocked
• fix step simulation RAM viewer

NB - this is the final release before start of Spring term work.

EDIT 16:15 3/2/21 - A bug fix added to v1.1.4 windows and macOS mending a rare error that caused Issie to crash instead of reporting an error message when you create a combinational loop through two wire labels.
EDIT 21:45 4/2/21 - Added a fix so loading corrupt connections does not prevent Issie from loading and using the rest of the file.
EDIT 14:00 5/2/21 - added fix to RAM memory display in step simulation