From 70c1234ad052e092b2d022370a80035a36300095 Mon Sep 17 00:00:00 2001
From: Trammell hudson <hudson@trmm.net>
Date: Fri, 18 Jan 2019 22:57:07 -0500
Subject: [PATCH 1/2] test: generate 24 Mhz clk for tinyfpga_bootloader
 endpoint

---
 tests/file_list.txt    | 1 +
 tests/top_tb_header.vh | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/tests/file_list.txt b/tests/file_list.txt
index 1c65819..076f817 100644
--- a/tests/file_list.txt
+++ b/tests/file_list.txt
@@ -1,5 +1,6 @@
 test.v
 ../../common/edge_detect.v
+../../common/strobe.v
 ../../common/tinyfpga_bootloader.v
 ../../common/usb_fs_in_arb.v
 ../../common/usb_fs_in_pe.v
diff --git a/tests/top_tb_header.vh b/tests/top_tb_header.vh
index db174bf..a0d656b 100644
--- a/tests/top_tb_header.vh
+++ b/tests/top_tb_header.vh
@@ -25,6 +25,7 @@ module top_tb;
     end
 
     reg clk_48mhz;
+    reg clk = 0;
     reg reset = 0;
 
     initial begin
@@ -34,6 +35,8 @@ module top_tb;
       end
     end
 
+    always @(posedge clk_48mhz) clk <= !clk;
+
     // usb interface
     wire usb_p_tx_raw;
     wire usb_n_tx_raw;
@@ -59,6 +62,7 @@ module top_tb;
 
     tinyfpga_bootloader dut (
       .clk_48mhz(clk_48mhz),
+      .clk(clk),
       .reset(reset),
 
       .usb_p_tx(usb_p_tx_raw),

From dac0dc3566e5642ab4fc2504d2c41e511baca362 Mon Sep 17 00:00:00 2001
From: Trammell hudson <hudson@trmm.net>
Date: Fri, 18 Jan 2019 22:58:19 -0500
Subject: [PATCH 2/2] usb: iverilog fixes for clock-crossing strobes

---
 common/usb_fs_rx.v |  9 +++++++--
 common/usb_fs_tx.v | 14 ++++++++++++--
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/common/usb_fs_rx.v b/common/usb_fs_rx.v
index fed9906..ab9c73c 100644
--- a/common/usb_fs_rx.v
+++ b/common/usb_fs_rx.v
@@ -343,14 +343,19 @@ module usb_fs_rx (
   end
 
   // cross the packet start signal to the endpoint clk domain
-  strobe pkt_start_strobe(clk_48mhz, clk, packet_start, pkt_start);
+  strobe pkt_start_strobe(
+	.clk_in(clk_48mhz),
+	.clk_out(clk),
+	.strobe_in(packet_start),
+	.strobe_out(pkt_start)
+  );
 
   // at the end of the packet, capture the parameters to the clk domain
   strobe #(.WIDTH(26)) pkt_end_strobe(
 	clk_48mhz, clk,
 	packet_end, pkt_end,
 	{ pid_48, addr_48, endp_48, frame_num_48 },
-	{ pid, addr, endp, frame_num },
+	{ pid, addr, endp, frame_num }
   );
   assign pid_48 = full_pid[4:1]; 
 
diff --git a/common/usb_fs_tx.v b/common/usb_fs_tx.v
index 723f318..34d2377 100644
--- a/common/usb_fs_tx.v
+++ b/common/usb_fs_tx.v
@@ -44,7 +44,12 @@ module usb_fs_tx (
   // convert tx_data_get from 48 to clk
   //wire tx_data_get_48 = tx_data_get;
   reg tx_data_get_48;
-  strobe tx_data_get_strobe(clk_48mhz, clk, tx_data_get_48, tx_data_get);
+  strobe tx_data_get_strobe(
+	.clk_in(clk_48mhz),
+	.clk_out(clk),
+	.strobe_in(tx_data_get_48),
+	.strobe_out(tx_data_get)
+  );
 
   reg [7:0] data_shift_reg = 0;
   reg [7:0] oe_shift_reg = 0;
@@ -77,7 +82,12 @@ module usb_fs_tx (
   end
 
   wire pkt_end_48 = bit_strobe && se0_shift_reg[1:0] == 2'b01;
-  strobe pkt_end_strobe(clk_48mhz, pkt_end_48, clk, pkt_end);
+  strobe pkt_end_strobe(
+	.clk_in(clk_48mhz),
+	.clk_out(clk),
+	.strobe_in(pkt_end_48),
+	.strobe_out(pkt_end)
+  );
 
   reg data_payload = 0;