diff --git a/make.py b/make.py
index d5d27ca7..d5e5d009 100755
--- a/make.py
+++ b/make.py
@@ -105,7 +105,7 @@ def main():
     platform = get_platform(args)
 
     exec("from targets.{}.{} import SoC".format(args.platform, args.target.lower(), args.target), globals())
-    soc = SoC(platform, **soc_sdram_argdict(args), **dict(args.target_option))
+    soc = SoC(platform, ident=SoC.__name__, **soc_sdram_argdict(args), **dict(args.target_option))
     if hasattr(soc, 'configure_iprange'):
         soc.configure_iprange(args.iprange)
 
diff --git a/targets/netv2/base.py b/targets/netv2/base.py
index db33c575..15a54a86 100755
--- a/targets/netv2/base.py
+++ b/targets/netv2/base.py
@@ -94,7 +94,6 @@ def __init__(self, platform, **kwargs):
         SoCSDRAM.__init__(self, platform, clk_freq,
             integrated_rom_size=0x8000,
             integrated_sram_size=0x8000,
-            ident="NeTV2 LiteX Base SoC",
             **kwargs)
 
         self.submodules.crg = _CRG(platform)
diff --git a/targets/netv2/bridge_pcie.py b/targets/netv2/bridge_pcie.py
index 656d6224..3965d06a 100644
--- a/targets/netv2/bridge_pcie.py
+++ b/targets/netv2/bridge_pcie.py
@@ -64,7 +64,6 @@ def __init__(self, platform, with_uart_bridge=True, **kwargs):
             shadow_base=0x00000000,
             csr_data_width=32,
             with_uart=False,
-            ident="NeTV2 LiteX PCIe SoC",
             with_timer=False,
             **kwargs)
         self.submodules.crg = _CRG(platform)
diff --git a/targets/netv2/bridge_uart.py b/targets/netv2/bridge_uart.py
index cad73fd6..d1eaf3bd 100644
--- a/targets/netv2/bridge_uart.py
+++ b/targets/netv2/bridge_uart.py
@@ -113,7 +113,6 @@ def __init__(self, platform, **kwargs):
         SoCSDRAM.__init__(self, platform, clk_freq,
             integrated_rom_size=0x8000,
             integrated_sram_size=0x8000,
-            ident="NeTV2 LiteX Base SoC",
             with_uart=False,
             **kwargs)