Vermicel is a simple RISC processor core that implements most of the RISC-V base instruction set (RV32I).
I have developed this core as an exercice to practice SystemVerilog (I am much more experienced in VHDL) and as a platform for my personal embedded computing experiments.
Vermicel is in a very early stage of development, and it is unlikely to ever become production-ready. Full compliance to the RISC-V specification is not guaranteed either. So, if you are looking for a RISC-V core to use in your product, there are a lot of other implementations available.
This project is licensed under the terms of the CERN Open Hardware Licence Version 2 - Weakly Reciprocal (CERN-OHL-W). For details please see the LICENSE file or https://ohwr.org/project/cernohl/wikis/Documents/CERN-OHL-version-2
The test suite in folder tests/rv32ui comes from the riscv-tests project,
with modifications from the picorv32 project.
The license of this test suite can be found in tests/rv32ui/LICENSE.
The source tree contains the following elements:
| Folder | Content |
|---|---|
asm |
Base assembly code (startup module) |
benchmarks |
Performance measurement programs. |
common |
Common SystemVerilog code (data types, bus interface) |
core |
Vermicel, the CPU core itself |
devices |
A minimal set of peripherals to create simple systems (RAM, timer, UART) |
example |
Verdemo, a "Hello World" SoC built around Vermicel |
scripts |
Various scripts for linting, simulation, synthesis, software compilation |
tests |
The test suite |
Vermicel, has two possible implementations that can be chosen
using its PIPELINE parameter:
- Versequence (
PIPELINE=0): a sequential architecture that uses a state machine. - Verpipeline (
PIPELINE=1): a 5-stage pipeline architecture.
Both implementations are composed of the same modules:
- Verdecode: the instruction decoder.
- Verithmetic: the Arithemetic and Logic Unit (ALU).
- Vercompare: the comparator, a close collaborator of Vergoto.
- Vergoto: the branch calculation unit.
- Vergister: the general-purpose register bank.
- Veralign: responsible for formatting the values on the data bus.
They are assisted by:
- Verbus: the bus interface.
- Verdata_pkg: a package with common data types.
- Veropcodes_pkg: a package with the main RISC-V opcodes.
- Vermicel_pkg: a package with constant declarations.
Vermicel comes with a minimal set of devices:
- Vermemory: a dual-port SRAM block.
- Verserial: a serial communication controller (UART).
- Vertimer: a timer.
- Verdemo: a synthesizable "Hello world" SoC.
- Verbench: a simulation environment to measure execution time with various programs:
- Verbonacci: computes the Fibonacci series.
- Vercopy: performs string copy operations.
Vermicel has been developed, tested and synthesized using these tools:
- Simulator: Verilator 5.009
- Synthesis: Xilinx Vivado 2019.1
- Software compilation: RISC-V GNU toolchain with GCC 12.2.0, binutils 2.40
- Build automation: GNU make 4.3
The example system supports the following FPGA boards:
- Digilent Basys 3
- Digilent Arty A7
Run all tests:
make -C tests
Run one or more specific tests:
TESTS="Vermicel_tb rv32ui_tb" make -C tests
Clean the tests folder:
make -C tests clean
Run all benchmarks:
make -C benchmarks
Run one or more specific benchmarks:
BENCHMARKS="Verminacci" make -C benchmarks
Clean the benchmarks folder:
make -C benchmarks clean
This command will generate bitstreams for all target boards:
make -C example
Generate a bitstream for one or more specific boards:
BOARDS=Basys3 make -C example