Chip_Designer.xise

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
  </header>

  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>

  <files>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/clk_divider_32Mhz.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/debounce.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/bus8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/clk_divider_32Mhz_low_speed.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/Counter8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/papilio_clocks.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/clk_divider_30to1hz.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Building_Blocks/clk_divider.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/HQVGA/HQVGA_char_ram_8x8_sp.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/HQVGA/zpuino_vga_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/HQVGA/HQVGA.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/HQVGA/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/HQVGA/generic_dp_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/half_step_driver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/quad_inst.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/full_step_driver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/Wishbone_to_Registers_n.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/RCL_Quadrature_Decoder_x8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/RCL_PWM_x48.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Robot_Control_Library/PWMGenerator.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZPUino/wbpll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZPUino/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZPUino/vga_generic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZPUino/VGA_ZPUino.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/gh_binary2gray.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/wb_master_np_to_slave_p.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/vga_zxspectrum.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/gh_gray2binary.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/gh_fifo_async_rrd_sr_wf.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/gh_sram_1wp_2rp_sc.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/VGA_ZXSpectrum/vga_zxspectrum_zpuino.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/BitCoin_Miner_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/j0.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/Gameduino.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/generated.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/fifo.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/ck_div.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/sdram_hamster.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_Pro_V2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/sdram_wrap.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_Pro_V2_blackbox.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Hyperion_Papilio_One_V2_blackbox.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Hyperion_Papilio_One_500K_V2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_One_V2_blackbox.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_One_500K_V2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_One_250K_V2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/sram_ctrl8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_DUO_V2_blackbox.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_One_250K_V2_blackbox.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_DUO_V2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_2/pad.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/RGB_Matrix/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/RGB_Matrix/VIDEO_zpuino_wb_rgb_panel.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/RGB_Matrix/RGB_Matrix_Wing.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/BitCoin_Miner_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/BitCoin_Miner.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to300_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to288_dcm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to800_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to200_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to100_dcm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to50_dcm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to960_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to25_dcm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to350_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to100_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/clocks/clk_32to400_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/dac_dsm3v.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/sid_6581.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_wb_pokey.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/dac_dsm2v.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/dac_simplesd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/Wishbone_to_Registers.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/VIDEO_zpuino_wb_vga_zxspectrum.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/Wishbone_to_Registers_x10.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_I2C.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/sid_coeffs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/prescaler.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_wb_sid6581.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/MISC_zpuino_sa_splitter2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_wb_dual_sigmadeltaDAC.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/Wishbone_Empty_Slot.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/zpuino_uart_mv_filter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/spiclkgen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_SPI.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/tx_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/uart_brgen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/MISC_zpuino_sa_splitter4.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/sid_components.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/VIDEO_zpuino_wb_rgb_panel.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/MISC_zpuino_wb_SevenSeg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_wb_YM2149.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/rgbctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_sa_audiomixer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/zpuino_uart_rx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/sid_filters.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/zpuino_sigmadelta.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_wb_passthrough.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/AUDIO_zpuino_sa_sigmadeltaDAC.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/sid_voice.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/AVR_Wishbone_Bridge/AVR_Wishbone_Bridge_Test.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/AVR_Wishbone_Bridge/AVR_Wishbone_Bridge.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/AVR_Wishbone_Bridge/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/muldex_8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/muldex_16.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/spi_transmitter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/waveform_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/rle_fmt.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/rle.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/bscan_spi_spartan6.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/rle_enc.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/stage.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/flags.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/receiver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/spi_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/sincos_lut.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/trigger.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/prescaler.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BENCHY_zpuino_wb_waveform_generator.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BRAM8k36bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/sampler.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/group_selector.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/spi_receiver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/eia232.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/clockman_papilio.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/sram_bram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/decoder.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/demux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/testmode.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/filter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer16.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/Mem_Gen_36bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BENCHY_sa_SumpBlaze_LogicAnalyzer8_jtag.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/transmitter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/muldex.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Benchy/BRAM6k36bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_Default_Wing_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_SDCard.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_Audio.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_DUO_Wing_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/LogicStart_MegaWing_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Spartan6_Reset.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/LogicStart_Shield_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_VGA8.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Computing_Shield_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_Analog.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_Default_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Arcade_MegaWing_Pinout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_GPIO.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Clocks/clk_32to64_dcm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Clocks/include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="include_symbols.edif" xil_pn:type="FILE_EDIF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="tremolo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
    <file xil_pn:name="DSP_Wing.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <library xil_pn:name="DesignLab"/>
    </file>
  </files>

  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Default.wcfg" xil_pn:valueState="non-default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DSP_Wing|BEHAVIORAL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="../DSP_Wing.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DSP_Wing" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Instantiation Template Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Output File Name" xil_pn:value="Papilio_SOC_Base_Papilio_Pro" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Papilio_SOC_Base_Papilio_Pro_map.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Papilio_SOC_Base_Papilio_Pro_timesim.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Papilio_SOC_Base_Papilio_Pro_synthesis.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Papilio_SOC_Base_Papilio_Pro_translate.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Description" xil_pn:value="Template to make your own Papilio Community Core Library." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Papilio_SOC_Base_Papilio_Pro" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/DSP_Wing" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.DSP_Wing" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.DSP_Wing" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="Chip_Designer" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Simulate_DSP_Wing|sim" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="Papilio_SOC_Base" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-04T16:52:44" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0BF1410E9CA045EFA8E8B9B45DA92BD1" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
  </properties>

  <bindings/>

  <libraries>
    <library xil_pn:name="DesignLab"/>
    <library xil_pn:name="test"/>
  </libraries>

  <autoManagedFiles>
    <!-- The following files are identified by `include statements in verilog -->
    <!-- source files and are automatically managed by Project Navigator.     -->
    <!--                                                                      -->
    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/Gameduino/revision.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/main_pll.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/sha-256-functions.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/uart_transmitter.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/serial.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/uart_receiver.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/raw7seg.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../../DesignLab-1.0.7/libraries/BitCoin_Miner/sha256_transform.v" xil_pn:type="FILE_VERILOG"/>
  </autoManagedFiles>

</project>