32bit_tree_adder.vcd

$date
	Sun Dec  3 21:27:01 2017
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module test $end
$var wire 6 ! sum [5:0] $end
$var reg 32 " in [31:0] $end
$scope module m1 $end
$var wire 32 # in [31:0] $end
$var wire 6 $ sum [5:0] $end
$scope begin genblk1[0] $end
$scope module h1 $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 ' s $end
$var wire 1 ( c $end
$upscope $end
$upscope $end
$scope begin genblk1[1] $end
$scope module h1 $end
$var wire 1 ) a $end
$var wire 1 * b $end
$var wire 1 + s $end
$var wire 1 , c $end
$upscope $end
$upscope $end
$scope begin genblk1[2] $end
$scope module h1 $end
$var wire 1 - a $end
$var wire 1 . b $end
$var wire 1 / s $end
$var wire 1 0 c $end
$upscope $end
$upscope $end
$scope begin genblk1[3] $end
$scope module h1 $end
$var wire 1 1 a $end
$var wire 1 2 b $end
$var wire 1 3 s $end
$var wire 1 4 c $end
$upscope $end
$upscope $end
$scope begin genblk1[4] $end
$scope module h1 $end
$var wire 1 5 a $end
$var wire 1 6 b $end
$var wire 1 7 s $end
$var wire 1 8 c $end
$upscope $end
$upscope $end
$scope begin genblk1[5] $end
$scope module h1 $end
$var wire 1 9 a $end
$var wire 1 : b $end
$var wire 1 ; s $end
$var wire 1 < c $end
$upscope $end
$upscope $end
$scope begin genblk1[6] $end
$scope module h1 $end
$var wire 1 = a $end
$var wire 1 > b $end
$var wire 1 ? s $end
$var wire 1 @ c $end
$upscope $end
$upscope $end
$scope begin genblk1[7] $end
$scope module h1 $end
$var wire 1 A a $end
$var wire 1 B b $end
$var wire 1 C s $end
$var wire 1 D c $end
$upscope $end
$upscope $end
$scope begin genblk1[8] $end
$scope module h1 $end
$var wire 1 E a $end
$var wire 1 F b $end
$var wire 1 G s $end
$var wire 1 H c $end
$upscope $end
$upscope $end
$scope begin genblk1[9] $end
$scope module h1 $end
$var wire 1 I a $end
$var wire 1 J b $end
$var wire 1 K s $end
$var wire 1 L c $end
$upscope $end
$upscope $end
$scope begin genblk1[10] $end
$scope module h1 $end
$var wire 1 M a $end
$var wire 1 N b $end
$var wire 1 O s $end
$var wire 1 P c $end
$upscope $end
$upscope $end
$scope begin genblk1[11] $end
$scope module h1 $end
$var wire 1 Q a $end
$var wire 1 R b $end
$var wire 1 S s $end
$var wire 1 T c $end
$upscope $end
$upscope $end
$scope begin genblk1[12] $end
$scope module h1 $end
$var wire 1 U a $end
$var wire 1 V b $end
$var wire 1 W s $end
$var wire 1 X c $end
$upscope $end
$upscope $end
$scope begin genblk1[13] $end
$scope module h1 $end
$var wire 1 Y a $end
$var wire 1 Z b $end
$var wire 1 [ s $end
$var wire 1 \ c $end
$upscope $end
$upscope $end
$scope begin genblk1[14] $end
$scope module h1 $end
$var wire 1 ] a $end
$var wire 1 ^ b $end
$var wire 1 _ s $end
$var wire 1 ` c $end
$upscope $end
$upscope $end
$scope begin genblk1[15] $end
$scope module h1 $end
$var wire 1 a a $end
$var wire 1 b b $end
$var wire 1 c s $end
$var wire 1 d c $end
$upscope $end
$upscope $end
$scope begin genblk2[0] $end
$scope module a2 $end
$var wire 2 e a [1:0] $end
$var wire 2 f b [1:0] $end
$var wire 2 g s [1:0] $end
$var wire 1 h c $end
$upscope $end
$upscope $end
$scope begin genblk2[1] $end
$scope module a2 $end
$var wire 2 i a [1:0] $end
$var wire 2 j b [1:0] $end
$var wire 2 k s [1:0] $end
$var wire 1 l c $end
$upscope $end
$upscope $end
$scope begin genblk2[2] $end
$scope module a2 $end
$var wire 2 m a [1:0] $end
$var wire 2 n b [1:0] $end
$var wire 2 o s [1:0] $end
$var wire 1 p c $end
$upscope $end
$upscope $end
$scope begin genblk2[3] $end
$scope module a2 $end
$var wire 2 q a [1:0] $end
$var wire 2 r b [1:0] $end
$var wire 2 s s [1:0] $end
$var wire 1 t c $end
$upscope $end
$upscope $end
$scope begin genblk2[4] $end
$scope module a2 $end
$var wire 2 u a [1:0] $end
$var wire 2 v b [1:0] $end
$var wire 2 w s [1:0] $end
$var wire 1 x c $end
$upscope $end
$upscope $end
$scope begin genblk2[5] $end
$scope module a2 $end
$var wire 2 y a [1:0] $end
$var wire 2 z b [1:0] $end
$var wire 2 { s [1:0] $end
$var wire 1 | c $end
$upscope $end
$upscope $end
$scope begin genblk2[6] $end
$scope module a2 $end
$var wire 2 } a [1:0] $end
$var wire 2 ~ b [1:0] $end
$var wire 2 !" s [1:0] $end
$var wire 1 "" c $end
$upscope $end
$upscope $end
$scope begin genblk2[7] $end
$scope module a2 $end
$var wire 2 #" a [1:0] $end
$var wire 2 $" b [1:0] $end
$var wire 2 %" s [1:0] $end
$var wire 1 &" c $end
$upscope $end
$upscope $end
$scope begin genblk3[0] $end
$scope module a3 $end
$var wire 3 '" a [2:0] $end
$var wire 3 (" b [2:0] $end
$var wire 3 )" s [2:0] $end
$var wire 1 *" c $end
$upscope $end
$upscope $end
$scope begin genblk3[1] $end
$scope module a3 $end
$var wire 3 +" a [2:0] $end
$var wire 3 ," b [2:0] $end
$var wire 3 -" s [2:0] $end
$var wire 1 ." c $end
$upscope $end
$upscope $end
$scope begin genblk3[2] $end
$scope module a3 $end
$var wire 3 /" a [2:0] $end
$var wire 3 0" b [2:0] $end
$var wire 3 1" s [2:0] $end
$var wire 1 2" c $end
$upscope $end
$upscope $end
$scope begin genblk3[3] $end
$scope module a3 $end
$var wire 3 3" a [2:0] $end
$var wire 3 4" b [2:0] $end
$var wire 3 5" s [2:0] $end
$var wire 1 6" c $end
$upscope $end
$upscope $end
$scope begin genblk4[0] $end
$scope module a4 $end
$var wire 4 7" a [3:0] $end
$var wire 4 8" b [3:0] $end
$var wire 4 9" s [3:0] $end
$var wire 1 :" c $end
$upscope $end
$upscope $end
$scope begin genblk4[1] $end
$scope module a4 $end
$var wire 4 ;" a [3:0] $end
$var wire 4 <" b [3:0] $end
$var wire 4 =" s [3:0] $end
$var wire 1 >" c $end
$upscope $end
$upscope $end
$scope module a5 $end
$var wire 5 ?" s [4:0] $end
$var wire 1 @" c $end
$var wire 5 A" b [4:0] $end
$var wire 5 B" a [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx B"
bx A"
x@"
bx ?"
x>"
bx ="
bx <"
bx ;"
x:"
bx 9"
bx 8"
bx 7"
x6"
bx 5"
bx 4"
bx 3"
x2"
bx 1"
bx 0"
bx /"
x."
bx -"
bx ,"
bx +"
x*"
bx )"
bx ("
bx '"
x&"
bx %"
bx $"
bx #"
x""
bx !"
bx ~
bx }
x|
bx {
bx z
bx y
xx
bx w
bx v
bx u
xt
bx s
bx r
bx q
xp
bx o
bx n
bx m
xl
bx k
bx j
bx i
xh
bx g
bx f
bx e
xd
xc
xb
xa
x`
x_
x^
x]
x\
x[
xZ
xY
xX
xW
xV
xU
xT
xS
xR
xQ
xP
xO
xN
xM
xL
xK
xJ
xI
xH
xG
xF
xE
xD
xC
xB
xA
x@
x?
x>
x=
x<
x;
x:
x9
x8
x7
x6
x5
x4
x3
x2
x1
x0
x/
x.
x-
x,
x+
x*
x)
x(
x'
x&
x%
bx $
bx #
bx "
bx !
$end
#1
b0 ?"
b0 !
b0 $
0@"
b0 9"
b0 B"
0:"
b0 ="
b0 A"
0>"
b0 )"
b0 7"
0*"
b0 -"
b0 8"
0."
b0 1"
b0 ;"
02"
b0 5"
b0 <"
06"
b0 g
b0 '"
0h
b0 k
b0 ("
0l
b0 o
b0 +"
0p
b0 s
b0 ,"
0t
b0 w
b0 /"
0x
b0 {
b0 0"
0|
b0 !"
b0 3"
0""
b0 %"
b0 4"
0&"
0'
b0 e
0(
0+
b0 f
0,
0/
b0 i
00
03
b0 j
04
07
b0 m
08
0;
b0 n
0<
0?
b0 q
0@
0C
b0 r
0D
0G
b0 u
0H
0K
b0 v
0L
0O
b0 y
0P
0S
b0 z
0T
0W
b0 }
0X
0[
b0 ~
0\
0_
b0 #"
0`
0c
b0 $"
0d
0%
0&
0)
0*
0-
0.
01
02
05
06
09
0:
0=
0>
0A
0B
0E
0F
0I
0J
0M
0N
0Q
0R
0U
0V
0Y
0Z
0]
0^
0a
0b
b0 "
b0 #
#6
b10 !
b10 $
b10 ?"
b10 B"
b10 9"
b10 7"
b10 )"
b10 '"
b10 g
b1 e
1'
b1 f
1+
1%
1)
b101 "
b101 #
#11
b11 !
b11 $
b11 ?"
b11 B"
b11 9"
b11 7"
b11 )"
b11 '"
b11 g
0'
b10 e
1(
1&
b111 "
b111 #