diff --git a/src/imp/atomic128/intrinsics.rs b/src/imp/atomic128/intrinsics.rs index 6982bd1f..21b5be20 100644 --- a/src/imp/atomic128/intrinsics.rs +++ b/src/imp/atomic128/intrinsics.rs @@ -452,7 +452,7 @@ unsafe fn atomic_umin(dst: *mut u128, val: u128, order: Ordering) -> u128 { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces unsafe fn atomic_not(dst: *mut u128, order: Ordering) -> u128 { // SAFETY: the caller must uphold the safety contract. - unsafe { atomic_xor(dst, u128::MAX, order) } + unsafe { atomic_xor(dst, !0, order) } } #[cfg(not(any(target_arch = "x86_64", target_arch = "s390x")))] diff --git a/src/imp/atomic128/powerpc64.rs b/src/imp/atomic128/powerpc64.rs index bb4164ec..5edc147f 100644 --- a/src/imp/atomic128/powerpc64.rs +++ b/src/imp/atomic128/powerpc64.rs @@ -726,7 +726,7 @@ use atomic_not_pwr8 as atomic_not; #[inline] unsafe fn atomic_not_pwr8(dst: *mut u128, order: Ordering) -> u128 { // SAFETY: the caller must uphold the safety contract. - unsafe { atomic_xor_pwr8(dst, u128::MAX, order) } + unsafe { atomic_xor_pwr8(dst, !0, order) } } #[cfg(portable_atomic_llvm_16)] diff --git a/src/imp/core_atomic.rs b/src/imp/core_atomic.rs index c7f713b5..fc9ba6fd 100644 --- a/src/imp/core_atomic.rs +++ b/src/imp/core_atomic.rs @@ -370,8 +370,7 @@ macro_rules! atomic_int { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub(crate) fn fetch_not(&self, order: Ordering) -> $int_type { - const NOT_MASK: $int_type = (0 as $int_type).wrapping_sub(1); - self.fetch_xor(NOT_MASK, order) + self.fetch_xor(!0, order) } #[cfg(not(all( any(target_arch = "x86", target_arch = "x86_64"), diff --git a/src/imp/riscv.rs b/src/imp/riscv.rs index 37360775..eba0cc3d 100644 --- a/src/imp/riscv.rs +++ b/src/imp/riscv.rs @@ -282,8 +282,7 @@ macro_rules! atomic { #[inline] pub(crate) fn fetch_not(&self, order: Ordering) -> $value_type { - const NOT_MASK: $value_type = (0 as $value_type).wrapping_sub(1); - self.fetch_xor(NOT_MASK, order) + self.fetch_xor(!0, order) } #[inline] @@ -350,8 +349,7 @@ macro_rules! atomic_sub_word { #[inline] pub(crate) fn fetch_not(&self, order: Ordering) -> $value_type { - const NOT_MASK: $value_type = (0 as $value_type).wrapping_sub(1); - self.fetch_xor(NOT_MASK, order) + self.fetch_xor(!0, order) } } }; diff --git a/src/tests/helper.rs b/src/tests/helper.rs index 10cac332..65831c60 100644 --- a/src/tests/helper.rs +++ b/src/tests/helper.rs @@ -437,12 +437,9 @@ macro_rules! __test_atomic_int { assert_eq!(a.load(Ordering::Relaxed), 1); assert_eq!(a.fetch_max(0, order), 1); assert_eq!(a.load(Ordering::Relaxed), 1); - let a = <$atomic_type>::new((0 as $int_type).wrapping_sub(1)); - assert_eq!(a.fetch_max(0, order), (0 as $int_type).wrapping_sub(1)); - assert_eq!( - a.load(Ordering::Relaxed), - core::cmp::max((0 as $int_type).wrapping_sub(1), 0) - ); + let a = <$atomic_type>::new(!0); + assert_eq!(a.fetch_max(0, order), !0); + assert_eq!(a.load(Ordering::Relaxed), core::cmp::max(!0, 0)); } } #[test] @@ -460,12 +457,9 @@ macro_rules! __test_atomic_int { assert_eq!(a.load(Ordering::Relaxed), 0); assert_eq!(a.fetch_min(1, order), 0); assert_eq!(a.load(Ordering::Relaxed), 0); - let a = <$atomic_type>::new((0 as $int_type).wrapping_sub(1)); - assert_eq!(a.fetch_min(0, order), (0 as $int_type).wrapping_sub(1)); - assert_eq!( - a.load(Ordering::Relaxed), - core::cmp::min((0 as $int_type).wrapping_sub(1), 0) - ); + let a = <$atomic_type>::new(!0); + assert_eq!(a.fetch_min(0, order), !0); + assert_eq!(a.load(Ordering::Relaxed), core::cmp::min(!0, 0)); } } #[test] @@ -495,8 +489,8 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(5); assert_eq!(a.fetch_neg(order), 5); - assert_eq!(a.load(Ordering::Relaxed), (5 as $int_type).wrapping_neg()); - assert_eq!(a.fetch_neg(order), (5 as $int_type).wrapping_neg()); + assert_eq!(a.load(Ordering::Relaxed), <$int_type>::wrapping_neg(5)); + assert_eq!(a.fetch_neg(order), <$int_type>::wrapping_neg(5)); assert_eq!(a.load(Ordering::Relaxed), 5); let a = <$atomic_type>::new(<$int_type>::MIN); assert_eq!(a.fetch_neg(order), <$int_type>::MIN); @@ -512,7 +506,7 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(5); a.neg(order); - assert_eq!(a.load(Ordering::Relaxed), (5 as $int_type).wrapping_neg()); + assert_eq!(a.load(Ordering::Relaxed), <$int_type>::wrapping_neg(5)); a.neg(order); assert_eq!(a.load(Ordering::Relaxed), 5); let a = <$atomic_type>::new(<$int_type>::MIN); @@ -782,7 +776,7 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(x); let b = a.bit_set(bit, order); - let mask = (1 as $int_type).wrapping_shl(bit); + let mask = <$int_type>::wrapping_shl(1, bit); assert_eq!(a.load(Ordering::Relaxed), x | mask); assert_eq!(b, x & mask != 0); } @@ -792,7 +786,7 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(x); let b = a.bit_clear(bit, order); - let mask = (1 as $int_type).wrapping_shl(bit); + let mask = <$int_type>::wrapping_shl(1, bit); assert_eq!(a.load(Ordering::Relaxed), x & !mask); assert_eq!(b, x & mask != 0); } @@ -802,7 +796,7 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(x); let b = a.bit_toggle(bit, order); - let mask = (1 as $int_type).wrapping_shl(bit); + let mask = <$int_type>::wrapping_shl(1, bit); assert_eq!(a.load(Ordering::Relaxed), x ^ mask); assert_eq!(b, x & mask != 0); } diff --git a/src/utils.rs b/src/utils.rs index 3e555354..258a3945 100644 --- a/src/utils.rs +++ b/src/utils.rs @@ -220,19 +220,19 @@ macro_rules! impl_default_bit_opts { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub(crate) fn bit_set(&self, bit: u32, order: Ordering) -> bool { - let mask = (1 as $int_type).wrapping_shl(bit); + let mask = <$int_type>::wrapping_shl(1, bit); self.fetch_or(mask, order) & mask != 0 } #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub(crate) fn bit_clear(&self, bit: u32, order: Ordering) -> bool { - let mask = (1 as $int_type).wrapping_shl(bit); + let mask = <$int_type>::wrapping_shl(1, bit); self.fetch_and(!mask, order) & mask != 0 } #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub(crate) fn bit_toggle(&self, bit: u32, order: Ordering) -> bool { - let mask = (1 as $int_type).wrapping_shl(bit); + let mask = <$int_type>::wrapping_shl(1, bit); self.fetch_xor(mask, order) & mask != 0 } } diff --git a/tests/api-test/src/helper.rs b/tests/api-test/src/helper.rs index 2f7f2043..c6a91a3d 100644 --- a/tests/api-test/src/helper.rs +++ b/tests/api-test/src/helper.rs @@ -243,8 +243,8 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(5); assert_eq!(a.fetch_neg(order), 5); - assert_eq!(a.load(Ordering::Relaxed), (5 as $int_type).wrapping_neg()); - assert_eq!(a.fetch_neg(order), (5 as $int_type).wrapping_neg()); + assert_eq!(a.load(Ordering::Relaxed), <$int_type>::wrapping_neg(5)); + assert_eq!(a.fetch_neg(order), <$int_type>::wrapping_neg(5)); assert_eq!(a.load(Ordering::Relaxed), 5); } } @@ -253,7 +253,7 @@ macro_rules! __test_atomic_int { for &order in &test_helper::SWAP_ORDERINGS { let a = <$atomic_type>::new(5); a.neg(order); - assert_eq!(a.load(Ordering::Relaxed), (5 as $int_type).wrapping_neg()); + assert_eq!(a.load(Ordering::Relaxed), <$int_type>::wrapping_neg(5)); a.neg(order); assert_eq!(a.load(Ordering::Relaxed), 5); }