From cdff8e26a58aad78ba10a5cad39ffd0bc06247e1 Mon Sep 17 00:00:00 2001 From: Hidenori Shinohara Date: Tue, 9 Jan 2024 13:30:57 -0500 Subject: [PATCH 1/5] initial changes, Alu tests pass, but fib doesn't --- core/src/alu/shift/{mod.rs => left.rs} | 72 ++++++++++---------------- core/src/prover/runtime.rs | 10 ++-- core/src/runtime/mod.rs | 7 ++- core/src/runtime/segment.rs | 7 ++- 4 files changed, 43 insertions(+), 53 deletions(-) rename core/src/alu/shift/{mod.rs => left.rs} (87%) diff --git a/core/src/alu/shift/mod.rs b/core/src/alu/shift/left.rs similarity index 87% rename from core/src/alu/shift/mod.rs rename to core/src/alu/shift/left.rs index 18aa006097..38441b0d11 100644 --- a/core/src/alu/shift/mod.rs +++ b/core/src/alu/shift/left.rs @@ -48,14 +48,14 @@ use crate::disassembler::WORD_SIZE; use crate::runtime::{Opcode, Segment}; use crate::utils::{pad_to_power_of_two, Chip}; -pub const NUM_SHIFT_COLS: usize = size_of::>(); +pub const NUM_LEFT_SHIFT_COLS: usize = size_of::>(); pub const BYTE_SIZE: usize = 8; /// The column layout for the chip. #[derive(AlignedBorrow, Default, Debug)] #[repr(C)] -pub struct ShiftCols { +pub struct LeftShiftCols { /// The output operand. pub a: Word, @@ -83,41 +83,33 @@ pub struct ShiftCols { /// A boolean array whose `i`th element indicates whether `num_bytes_to_shift = i`. pub shift_by_n_bytes: [T; WORD_SIZE], - /// Selector flags for the operation to perform. - pub is_sll: T, - pub is_srl: T, - pub is_sra: T, - pub is_real: T, } -/// A chip that implements bitwise operations for the opcodes SLL, SLLI, SRL, SRLI, SRA, and SRAI. -pub struct ShiftChip; +/// A chip that implements bitwise operations for the opcodes SLL and SLLI. +pub struct LeftShiftChip; -impl ShiftChip { +impl LeftShiftChip { pub fn new() -> Self { Self {} } } -impl Chip for ShiftChip { +impl Chip for LeftShiftChip { fn generate_trace(&self, segment: &mut Segment) -> RowMajorMatrix { // Generate the trace rows for each event. let rows = segment - .shift_events + .left_shift_events .par_iter() .map(|event| { - let mut row = [F::zero(); NUM_SHIFT_COLS]; - let cols: &mut ShiftCols = unsafe { transmute(&mut row) }; + let mut row = [F::zero(); NUM_LEFT_SHIFT_COLS]; + let cols: &mut LeftShiftCols = unsafe { transmute(&mut row) }; let a = event.a.to_le_bytes(); let b = event.b.to_le_bytes(); let c = event.c.to_le_bytes(); cols.a = Word(a.map(F::from_canonical_u8)); cols.b = Word(b.map(F::from_canonical_u8)); cols.c = Word(c.map(F::from_canonical_u8)); - cols.is_sll = F::from_bool(event.opcode == Opcode::SLL); - cols.is_srl = F::from_bool(event.opcode == Opcode::SRL); - cols.is_sra = F::from_bool(event.opcode == Opcode::SRA); cols.is_real = F::one(); for i in 0..BYTE_SIZE { cols.c_least_sig_byte[i] = F::from_canonical_u32((event.c >> i) & 1); @@ -162,45 +154,44 @@ impl Chip for ShiftChip { // Convert the trace to a row major matrix. let mut trace = RowMajorMatrix::new( rows.into_iter().flatten().collect::>(), - NUM_SHIFT_COLS, + NUM_LEFT_SHIFT_COLS, ); // Pad the trace to a power of two. - pad_to_power_of_two::(&mut trace.values); + pad_to_power_of_two::(&mut trace.values); // Create the template for the padded rows. These are fake rows that don't fail on some // sanity checks. let padded_row_template = { - let mut row = [F::zero(); NUM_SHIFT_COLS]; - let cols: &mut ShiftCols = unsafe { transmute(&mut row) }; - cols.is_sll = F::one(); + let mut row = [F::zero(); NUM_LEFT_SHIFT_COLS]; + let cols: &mut LeftShiftCols = unsafe { transmute(&mut row) }; cols.shift_by_n_bits[0] = F::one(); cols.shift_by_n_bytes[0] = F::one(); cols.bit_shift_multiplier = F::one(); row }; - debug_assert!(padded_row_template.len() == NUM_SHIFT_COLS); - for i in segment.shift_events.len() * NUM_SHIFT_COLS..trace.values.len() { - trace.values[i] = padded_row_template[i % NUM_SHIFT_COLS]; + debug_assert!(padded_row_template.len() == NUM_LEFT_SHIFT_COLS); + for i in segment.left_shift_events.len() * NUM_LEFT_SHIFT_COLS..trace.values.len() { + trace.values[i] = padded_row_template[i % NUM_LEFT_SHIFT_COLS]; } trace } } -impl BaseAir for ShiftChip { +impl BaseAir for LeftShiftChip { fn width(&self) -> usize { - NUM_SHIFT_COLS + NUM_LEFT_SHIFT_COLS } } -impl Air for ShiftChip +impl Air for LeftShiftChip where AB: CurtaAirBuilder, { fn eval(&self, builder: &mut AB) { let main = builder.main(); - let local: &ShiftCols = main.row_slice(0).borrow(); + let local: &LeftShiftCols = main.row_slice(0).borrow(); let zero: AB::Expr = AB::F::zero().into(); let one: AB::Expr = AB::F::one().into(); @@ -318,24 +309,15 @@ where one.clone(), ); - builder.assert_bool(local.is_sll); - builder.assert_bool(local.is_srl); - builder.assert_bool(local.is_sra); - - // Exactly one of them must be true. - builder.assert_eq(local.is_sll + local.is_srl + local.is_sra, one.clone()); - builder.assert_bool(local.is_real); // Receive the arguments. builder.receive_alu( - local.is_sll * AB::F::from_canonical_u32(Opcode::SLL as u32) - + local.is_srl * AB::F::from_canonical_u32(Opcode::SRL as u32) - + local.is_sra * AB::F::from_canonical_u32(Opcode::SRA as u32), + AB::F::from_canonical_u32(Opcode::SLL as u32), local.a, local.b, local.c, - local.is_sll + local.is_srl + local.is_sra, + local.is_real, ); // A dummy constraint to keep the degree at least 3. @@ -371,13 +353,13 @@ mod tests { }; use p3_commit::ExtensionMmcs; - use super::ShiftChip; + use super::LeftShiftChip; #[test] fn generate_trace() { let mut segment = Segment::default(); - segment.shift_events = vec![AluEvent::new(0, Opcode::SLL, 16, 8, 1)]; - let chip = ShiftChip::new(); + segment.left_shift_events = vec![AluEvent::new(0, Opcode::SLL, 16, 8, 1)]; + let chip = LeftShiftChip::new(); let trace: RowMajorMatrix = chip.generate_trace(&mut segment); println!("{:?}", trace.values) } @@ -456,8 +438,8 @@ mod tests { } let mut segment = Segment::default(); - segment.shift_events = shift_events; - let chip = ShiftChip::new(); + segment.left_shift_events = shift_events; + let chip = LeftShiftChip::new(); let trace: RowMajorMatrix = chip.generate_trace(&mut segment); let proof = prove::(&config, &chip, &mut challenger, trace); diff --git a/core/src/prover/runtime.rs b/core/src/prover/runtime.rs index 5a1fd60e3f..1447fd7cb0 100644 --- a/core/src/prover/runtime.rs +++ b/core/src/prover/runtime.rs @@ -12,7 +12,7 @@ use p3_commit::{Pcs, UnivariatePcs, UnivariatePcsWithLde}; use p3_uni_stark::decompose_and_flatten; use p3_util::log2_ceil_usize; -use crate::alu::{AddChip, BitwiseChip, LtChip, ShiftChip, SubChip}; +use crate::alu::{AddChip, BitwiseChip, LeftShiftChip, LtChip, RightShiftChip, SubChip}; use crate::prover::debug_constraints; use p3_field::{ExtensionField, PrimeField, PrimeField32, TwoAdicField}; use p3_matrix::Matrix; @@ -52,14 +52,15 @@ impl Segment { EF: ExtensionField, SC: StarkConfig, { - const NUM_CHIPS: usize = 10; + const NUM_CHIPS: usize = 11; // Initialize chips. let program = ProgramChip::new(); let cpu = CpuChip::new(); let add = AddChip::new(); let sub = SubChip::new(); let bitwise = BitwiseChip::new(); - let shift = ShiftChip::new(); + let right_shift = RightShiftChip::new(); + let left_shift = LeftShiftChip::new(); let lt = LtChip::new(); let bytes = ByteChip::::new(); let memory_init = MemoryInitChip::new(true); @@ -70,7 +71,8 @@ impl Segment { Box::new(add), Box::new(sub), Box::new(bitwise), - Box::new(shift), + Box::new(right_shift), + Box::new(left_shift), Box::new(lt), Box::new(bytes), Box::new(memory_init), diff --git a/core/src/runtime/mod.rs b/core/src/runtime/mod.rs index 70c3f84ec7..94ad63cae3 100644 --- a/core/src/runtime/mod.rs +++ b/core/src/runtime/mod.rs @@ -260,8 +260,11 @@ impl Runtime { Opcode::XOR | Opcode::OR | Opcode::AND => { self.segment.bitwise_events.push(event); } - Opcode::SLL | Opcode::SRL | Opcode::SRA => { - self.segment.shift_events.push(event); + Opcode::SLL => { + self.segment.left_shift_events.push(event); + } + Opcode::SRL | Opcode::SRA => { + self.segment.right_shift_events.push(event); } Opcode::SLT | Opcode::SLTU => { self.segment.lt_events.push(event); diff --git a/core/src/runtime/segment.rs b/core/src/runtime/segment.rs index 3b44116bc0..45da470aae 100644 --- a/core/src/runtime/segment.rs +++ b/core/src/runtime/segment.rs @@ -34,8 +34,11 @@ pub struct Segment { /// A trace of the XOR, XORI, OR, ORI, AND, and ANDI events. pub bitwise_events: Vec, - /// A trace of the SLL, SLLI, SRL, SRLI, SRA, and SRAI events. - pub shift_events: Vec, + /// A trace of the SLL and SLLI events. + pub left_shift_events: Vec, + + /// A trace of the SRL, SRLI, SRA, and SRAI events. + pub right_shift_events: Vec, /// A trace of the SLT, SLTI, SLTU, and SLTIU events. pub lt_events: Vec, From 07ca5d1f726f5093fa77262d26d0b111404d1f36 Mon Sep 17 00:00:00 2001 From: Hidenori Shinohara Date: Tue, 9 Jan 2024 13:33:13 -0500 Subject: [PATCH 2/5] add right.rs --- core/src/alu/shift/right.rs | 198 ++++++++++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 core/src/alu/shift/right.rs diff --git a/core/src/alu/shift/right.rs b/core/src/alu/shift/right.rs new file mode 100644 index 0000000000..33320c3dd3 --- /dev/null +++ b/core/src/alu/shift/right.rs @@ -0,0 +1,198 @@ +use core::borrow::{Borrow, BorrowMut}; +use core::mem::size_of; +use core::mem::transmute; +use p3_air::{Air, BaseAir}; + +use p3_field::AbstractField; +use p3_field::PrimeField; +use p3_matrix::dense::RowMajorMatrix; +use p3_matrix::MatrixRowSlices; +use rayon::iter::{IntoParallelRefIterator, ParallelIterator}; +use valida_derive::AlignedBorrow; + +use crate::air::{CurtaAirBuilder, Word}; + +use crate::runtime::{Opcode, Segment}; +use crate::utils::{pad_to_power_of_two, Chip}; + +pub const RIGHT_NUM_SHIFT_COLS: usize = size_of::>(); + +/// The column layout for the chip. +#[derive(AlignedBorrow, Default)] +pub struct RightShiftCols { + /// The output operand. + pub a: Word, + + /// The first input operand. + pub b: Word, + + /// The second input operand. + pub c: Word, + + /// Selector flags for the operation to perform. + pub is_srl: T, + pub is_sra: T, +} + +/// A chip that implements bitwise operations for the opcodes SRL, SRLI, SRA, and SRAI. +pub struct RightShiftChip; + +impl RightShiftChip { + pub fn new() -> Self { + Self {} + } +} + +impl Chip for RightShiftChip { + fn generate_trace(&self, segment: &mut Segment) -> RowMajorMatrix { + // Generate the trace rows for each event. + let rows = segment + .right_shift_events + .par_iter() + .map(|event| { + let mut row = [F::zero(); RIGHT_NUM_SHIFT_COLS]; + let cols: &mut RightShiftCols = unsafe { transmute(&mut row) }; + let a = event.a.to_le_bytes(); + let b = event.b.to_le_bytes(); + let c = event.c.to_le_bytes(); + cols.a = Word(a.map(F::from_canonical_u8)); + cols.b = Word(b.map(F::from_canonical_u8)); + cols.c = Word(c.map(F::from_canonical_u8)); + cols.is_srl = F::from_bool(event.opcode == Opcode::SRL); + cols.is_sra = F::from_bool(event.opcode == Opcode::SRA); + row + }) + .collect::>(); + + // Convert the trace to a row major matrix. + let mut trace = RowMajorMatrix::new( + rows.into_iter().flatten().collect::>(), + RIGHT_NUM_SHIFT_COLS, + ); + + // Pad the trace to a power of two. + pad_to_power_of_two::(&mut trace.values); + + trace + } +} + +impl BaseAir for RightShiftChip { + fn width(&self) -> usize { + RIGHT_NUM_SHIFT_COLS + } +} + +impl Air for RightShiftChip +where + AB: CurtaAirBuilder, +{ + fn eval(&self, builder: &mut AB) { + let main = builder.main(); + let local: &RightShiftCols = main.row_slice(0).borrow(); + + builder.assert_zero( + local.a[0] * local.b[0] * local.c[0] - local.a[0] * local.b[0] * local.c[0], + ); + + // Receive the arguments. + builder.receive_alu( + local.is_srl * AB::F::from_canonical_u32(Opcode::SRL as u32) + + local.is_sra * AB::F::from_canonical_u32(Opcode::SRA as u32), + local.a, + local.b, + local.c, + local.is_srl + local.is_sra, + ); + } +} + +#[cfg(test)] +mod tests { + use p3_challenger::DuplexChallenger; + use p3_dft::Radix2DitParallel; + use p3_field::Field; + + use p3_baby_bear::BabyBear; + use p3_field::extension::BinomialExtensionField; + use p3_fri::{FriBasedPcs, FriConfigImpl, FriLdt}; + use p3_keccak::Keccak256Hash; + use p3_ldt::QuotientMmcs; + use p3_matrix::dense::RowMajorMatrix; + use p3_mds::coset_mds::CosetMds; + use p3_merkle_tree::FieldMerkleTreeMmcs; + use p3_poseidon2::{DiffusionMatrixBabybear, Poseidon2}; + use p3_symmetric::{CompressionFunctionFromHasher, SerializingHasher32}; + use p3_uni_stark::{prove, verify, StarkConfigImpl}; + use rand::thread_rng; + + use crate::{ + alu::AluEvent, + runtime::{Opcode, Segment}, + utils::Chip, + }; + use p3_commit::ExtensionMmcs; + + use super::RightShiftChip; + + #[test] + fn generate_trace() { + let mut segment = Segment::default(); + segment.right_shift_events = vec![AluEvent::new(0, Opcode::SRL, 6, 12, 1)]; + let chip = RightShiftChip::new(); + let trace: RowMajorMatrix = chip.generate_trace(&mut segment); + println!("{:?}", trace.values) + } + + #[test] + fn prove_babybear() { + type Val = BabyBear; + type Domain = Val; + type Challenge = BinomialExtensionField; + type PackedChallenge = BinomialExtensionField<::Packing, 4>; + + type MyMds = CosetMds; + let mds = MyMds::default(); + + type Perm = Poseidon2; + let perm = Perm::new_from_rng(8, 22, mds, DiffusionMatrixBabybear, &mut thread_rng()); + + type MyHash = SerializingHasher32; + let hash = MyHash::new(Keccak256Hash {}); + + type MyCompress = CompressionFunctionFromHasher; + let compress = MyCompress::new(hash); + + type ValMmcs = FieldMerkleTreeMmcs; + let val_mmcs = ValMmcs::new(hash, compress); + + type ChallengeMmcs = ExtensionMmcs; + let challenge_mmcs = ChallengeMmcs::new(val_mmcs.clone()); + + type Dft = Radix2DitParallel; + let dft = Dft {}; + + type Challenger = DuplexChallenger; + + type Quotient = QuotientMmcs; + type MyFriConfig = FriConfigImpl; + let fri_config = MyFriConfig::new(40, challenge_mmcs); + let ldt = FriLdt { config: fri_config }; + + type Pcs = FriBasedPcs; + type MyConfig = StarkConfigImpl; + + let pcs = Pcs::new(dft, val_mmcs, ldt); + let config = StarkConfigImpl::new(pcs); + let mut challenger = Challenger::new(perm.clone()); + + let mut segment = Segment::default(); + segment.right_shift_events = vec![AluEvent::new(0, Opcode::SRL, 6, 12, 1)].repeat(1000); + let chip = RightShiftChip::new(); + let trace: RowMajorMatrix = chip.generate_trace(&mut segment); + let proof = prove::(&config, &chip, &mut challenger, trace); + + let mut challenger = Challenger::new(perm); + verify(&config, &chip, &mut challenger, &proof).unwrap(); + } +} From 1f11614b65e9326f62a9693e164c276045f34daf Mon Sep 17 00:00:00 2001 From: Hidenori Shinohara Date: Tue, 9 Jan 2024 13:53:30 -0500 Subject: [PATCH 3/5] {Right,Left}Shift => Shift{Right,Left} --- core/src/alu/shift/left.rs | 26 +++++++++++++------------- core/src/alu/shift/right.rs | 16 ++++++++-------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/core/src/alu/shift/left.rs b/core/src/alu/shift/left.rs index 38441b0d11..8e5518a725 100644 --- a/core/src/alu/shift/left.rs +++ b/core/src/alu/shift/left.rs @@ -48,14 +48,14 @@ use crate::disassembler::WORD_SIZE; use crate::runtime::{Opcode, Segment}; use crate::utils::{pad_to_power_of_two, Chip}; -pub const NUM_LEFT_SHIFT_COLS: usize = size_of::>(); +pub const NUM_SHIFT_LEFT_COLS: usize = size_of::>(); pub const BYTE_SIZE: usize = 8; /// The column layout for the chip. #[derive(AlignedBorrow, Default, Debug)] #[repr(C)] -pub struct LeftShiftCols { +pub struct ShiftLeftCols { /// The output operand. pub a: Word, @@ -102,8 +102,8 @@ impl Chip for LeftShiftChip { .left_shift_events .par_iter() .map(|event| { - let mut row = [F::zero(); NUM_LEFT_SHIFT_COLS]; - let cols: &mut LeftShiftCols = unsafe { transmute(&mut row) }; + let mut row = [F::zero(); NUM_SHIFT_LEFT_COLS]; + let cols: &mut ShiftLeftCols = unsafe { transmute(&mut row) }; let a = event.a.to_le_bytes(); let b = event.b.to_le_bytes(); let c = event.c.to_le_bytes(); @@ -154,25 +154,25 @@ impl Chip for LeftShiftChip { // Convert the trace to a row major matrix. let mut trace = RowMajorMatrix::new( rows.into_iter().flatten().collect::>(), - NUM_LEFT_SHIFT_COLS, + NUM_SHIFT_LEFT_COLS, ); // Pad the trace to a power of two. - pad_to_power_of_two::(&mut trace.values); + pad_to_power_of_two::(&mut trace.values); // Create the template for the padded rows. These are fake rows that don't fail on some // sanity checks. let padded_row_template = { - let mut row = [F::zero(); NUM_LEFT_SHIFT_COLS]; - let cols: &mut LeftShiftCols = unsafe { transmute(&mut row) }; + let mut row = [F::zero(); NUM_SHIFT_LEFT_COLS]; + let cols: &mut ShiftLeftCols = unsafe { transmute(&mut row) }; cols.shift_by_n_bits[0] = F::one(); cols.shift_by_n_bytes[0] = F::one(); cols.bit_shift_multiplier = F::one(); row }; - debug_assert!(padded_row_template.len() == NUM_LEFT_SHIFT_COLS); - for i in segment.left_shift_events.len() * NUM_LEFT_SHIFT_COLS..trace.values.len() { - trace.values[i] = padded_row_template[i % NUM_LEFT_SHIFT_COLS]; + debug_assert!(padded_row_template.len() == NUM_SHIFT_LEFT_COLS); + for i in segment.left_shift_events.len() * NUM_SHIFT_LEFT_COLS..trace.values.len() { + trace.values[i] = padded_row_template[i % NUM_SHIFT_LEFT_COLS]; } trace @@ -181,7 +181,7 @@ impl Chip for LeftShiftChip { impl BaseAir for LeftShiftChip { fn width(&self) -> usize { - NUM_LEFT_SHIFT_COLS + NUM_SHIFT_LEFT_COLS } } @@ -191,7 +191,7 @@ where { fn eval(&self, builder: &mut AB) { let main = builder.main(); - let local: &LeftShiftCols = main.row_slice(0).borrow(); + let local: &ShiftLeftCols = main.row_slice(0).borrow(); let zero: AB::Expr = AB::F::zero().into(); let one: AB::Expr = AB::F::one().into(); diff --git a/core/src/alu/shift/right.rs b/core/src/alu/shift/right.rs index 33320c3dd3..4652fbf792 100644 --- a/core/src/alu/shift/right.rs +++ b/core/src/alu/shift/right.rs @@ -15,11 +15,11 @@ use crate::air::{CurtaAirBuilder, Word}; use crate::runtime::{Opcode, Segment}; use crate::utils::{pad_to_power_of_two, Chip}; -pub const RIGHT_NUM_SHIFT_COLS: usize = size_of::>(); +pub const NUM_SHIFT_RIGHT_COLS: usize = size_of::>(); /// The column layout for the chip. #[derive(AlignedBorrow, Default)] -pub struct RightShiftCols { +pub struct ShiftRightCols { /// The output operand. pub a: Word, @@ -50,8 +50,8 @@ impl Chip for RightShiftChip { .right_shift_events .par_iter() .map(|event| { - let mut row = [F::zero(); RIGHT_NUM_SHIFT_COLS]; - let cols: &mut RightShiftCols = unsafe { transmute(&mut row) }; + let mut row = [F::zero(); NUM_SHIFT_RIGHT_COLS]; + let cols: &mut ShiftRightCols = unsafe { transmute(&mut row) }; let a = event.a.to_le_bytes(); let b = event.b.to_le_bytes(); let c = event.c.to_le_bytes(); @@ -67,11 +67,11 @@ impl Chip for RightShiftChip { // Convert the trace to a row major matrix. let mut trace = RowMajorMatrix::new( rows.into_iter().flatten().collect::>(), - RIGHT_NUM_SHIFT_COLS, + NUM_SHIFT_RIGHT_COLS, ); // Pad the trace to a power of two. - pad_to_power_of_two::(&mut trace.values); + pad_to_power_of_two::(&mut trace.values); trace } @@ -79,7 +79,7 @@ impl Chip for RightShiftChip { impl BaseAir for RightShiftChip { fn width(&self) -> usize { - RIGHT_NUM_SHIFT_COLS + NUM_SHIFT_RIGHT_COLS } } @@ -89,7 +89,7 @@ where { fn eval(&self, builder: &mut AB) { let main = builder.main(); - let local: &RightShiftCols = main.row_slice(0).borrow(); + let local: &ShiftRightCols = main.row_slice(0).borrow(); builder.assert_zero( local.a[0] * local.b[0] * local.c[0] - local.a[0] * local.b[0] * local.c[0], From 2593a9df2482d81b7a549042db95a13403b21f87 Mon Sep 17 00:00:00 2001 From: Hidenori Shinohara Date: Tue, 9 Jan 2024 13:56:49 -0500 Subject: [PATCH 4/5] move left.rs, right.rs to sll/mod.rs and sr/mod.rs --- core/src/alu/{shift/left.rs => sll/mod.rs} | 0 core/src/alu/{shift/right.rs => sr/mod.rs} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename core/src/alu/{shift/left.rs => sll/mod.rs} (100%) rename core/src/alu/{shift/right.rs => sr/mod.rs} (100%) diff --git a/core/src/alu/shift/left.rs b/core/src/alu/sll/mod.rs similarity index 100% rename from core/src/alu/shift/left.rs rename to core/src/alu/sll/mod.rs diff --git a/core/src/alu/shift/right.rs b/core/src/alu/sr/mod.rs similarity index 100% rename from core/src/alu/shift/right.rs rename to core/src/alu/sr/mod.rs From a6fc724b8c3f1d5d6d547a6ebbfbe846faa4cfe5 Mon Sep 17 00:00:00 2001 From: Hidenori Shinohara Date: Tue, 9 Jan 2024 14:04:46 -0500 Subject: [PATCH 5/5] left shift -> shift left, right shift -> shift right --- core/src/alu/mod.rs | 6 ++++-- core/src/alu/sll/mod.rs | 8 ++++---- core/src/alu/sr/mod.rs | 6 +++--- core/src/runtime/mod.rs | 4 ++-- core/src/runtime/segment.rs | 4 ++-- 5 files changed, 15 insertions(+), 13 deletions(-) diff --git a/core/src/alu/mod.rs b/core/src/alu/mod.rs index d7352e8142..6cad2d1395 100644 --- a/core/src/alu/mod.rs +++ b/core/src/alu/mod.rs @@ -2,13 +2,15 @@ pub mod add; pub mod bitwise; pub mod lt; pub mod mul; -pub mod shift; +pub mod sll; +pub mod sr; pub mod sub; pub use add::*; pub use bitwise::*; pub use lt::*; -pub use shift::*; +pub use sll::*; +pub use sr::*; pub use sub::*; use crate::runtime::Opcode; diff --git a/core/src/alu/sll/mod.rs b/core/src/alu/sll/mod.rs index 8e5518a725..3528243b8e 100644 --- a/core/src/alu/sll/mod.rs +++ b/core/src/alu/sll/mod.rs @@ -99,7 +99,7 @@ impl Chip for LeftShiftChip { fn generate_trace(&self, segment: &mut Segment) -> RowMajorMatrix { // Generate the trace rows for each event. let rows = segment - .left_shift_events + .shift_left_events .par_iter() .map(|event| { let mut row = [F::zero(); NUM_SHIFT_LEFT_COLS]; @@ -171,7 +171,7 @@ impl Chip for LeftShiftChip { row }; debug_assert!(padded_row_template.len() == NUM_SHIFT_LEFT_COLS); - for i in segment.left_shift_events.len() * NUM_SHIFT_LEFT_COLS..trace.values.len() { + for i in segment.shift_left_events.len() * NUM_SHIFT_LEFT_COLS..trace.values.len() { trace.values[i] = padded_row_template[i % NUM_SHIFT_LEFT_COLS]; } @@ -358,7 +358,7 @@ mod tests { #[test] fn generate_trace() { let mut segment = Segment::default(); - segment.left_shift_events = vec![AluEvent::new(0, Opcode::SLL, 16, 8, 1)]; + segment.shift_left_events = vec![AluEvent::new(0, Opcode::SLL, 16, 8, 1)]; let chip = LeftShiftChip::new(); let trace: RowMajorMatrix = chip.generate_trace(&mut segment); println!("{:?}", trace.values) @@ -438,7 +438,7 @@ mod tests { } let mut segment = Segment::default(); - segment.left_shift_events = shift_events; + segment.shift_left_events = shift_events; let chip = LeftShiftChip::new(); let trace: RowMajorMatrix = chip.generate_trace(&mut segment); let proof = prove::(&config, &chip, &mut challenger, trace); diff --git a/core/src/alu/sr/mod.rs b/core/src/alu/sr/mod.rs index 4652fbf792..88e66d0f8c 100644 --- a/core/src/alu/sr/mod.rs +++ b/core/src/alu/sr/mod.rs @@ -47,7 +47,7 @@ impl Chip for RightShiftChip { fn generate_trace(&self, segment: &mut Segment) -> RowMajorMatrix { // Generate the trace rows for each event. let rows = segment - .right_shift_events + .shift_right_events .par_iter() .map(|event| { let mut row = [F::zero(); NUM_SHIFT_RIGHT_COLS]; @@ -138,7 +138,7 @@ mod tests { #[test] fn generate_trace() { let mut segment = Segment::default(); - segment.right_shift_events = vec![AluEvent::new(0, Opcode::SRL, 6, 12, 1)]; + segment.shift_right_events = vec![AluEvent::new(0, Opcode::SRL, 6, 12, 1)]; let chip = RightShiftChip::new(); let trace: RowMajorMatrix = chip.generate_trace(&mut segment); println!("{:?}", trace.values) @@ -187,7 +187,7 @@ mod tests { let mut challenger = Challenger::new(perm.clone()); let mut segment = Segment::default(); - segment.right_shift_events = vec![AluEvent::new(0, Opcode::SRL, 6, 12, 1)].repeat(1000); + segment.shift_right_events = vec![AluEvent::new(0, Opcode::SRL, 6, 12, 1)].repeat(1000); let chip = RightShiftChip::new(); let trace: RowMajorMatrix = chip.generate_trace(&mut segment); let proof = prove::(&config, &chip, &mut challenger, trace); diff --git a/core/src/runtime/mod.rs b/core/src/runtime/mod.rs index 94ad63cae3..957b3324a2 100644 --- a/core/src/runtime/mod.rs +++ b/core/src/runtime/mod.rs @@ -261,10 +261,10 @@ impl Runtime { self.segment.bitwise_events.push(event); } Opcode::SLL => { - self.segment.left_shift_events.push(event); + self.segment.shift_left_events.push(event); } Opcode::SRL | Opcode::SRA => { - self.segment.right_shift_events.push(event); + self.segment.shift_right_events.push(event); } Opcode::SLT | Opcode::SLTU => { self.segment.lt_events.push(event); diff --git a/core/src/runtime/segment.rs b/core/src/runtime/segment.rs index 45da470aae..9356fede2c 100644 --- a/core/src/runtime/segment.rs +++ b/core/src/runtime/segment.rs @@ -35,10 +35,10 @@ pub struct Segment { pub bitwise_events: Vec, /// A trace of the SLL and SLLI events. - pub left_shift_events: Vec, + pub shift_left_events: Vec, /// A trace of the SRL, SRLI, SRA, and SRAI events. - pub right_shift_events: Vec, + pub shift_right_events: Vec, /// A trace of the SLT, SLTI, SLTU, and SLTIU events. pub lt_events: Vec,