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DMA - Make ChannelsTuple a struct
1 parent 4b61d29 commit 7938b47

6 files changed

+39
-36
lines changed

examples/adc-continious-dma.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ fn main() -> ! {
6262

6363
info!("Setup DMA");
6464
let first_buffer = cortex_m::singleton!(: [u16; 15] = [0; 15]).unwrap();
65-
let mut transfer = channels.0.into_circ_peripheral_to_memory_transfer(
65+
let mut transfer = channels.ch1.into_circ_peripheral_to_memory_transfer(
6666
adc.enable_dma(AdcDma::Continuous),
6767
&mut first_buffer[..],
6868
config,

examples/adc-one-shot-dma.rs

+3-3
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ fn main() -> ! {
6161

6262
info!("Setup DMA");
6363
let first_buffer = cortex_m::singleton!(: [u16; 2] = [0; 2]).unwrap();
64-
let mut transfer = channels.0.into_peripheral_to_memory_transfer(
64+
let mut transfer = channels.ch1.into_peripheral_to_memory_transfer(
6565
adc.enable_dma(AdcDma::Single),
6666
&mut first_buffer[..],
6767
config,
@@ -74,10 +74,10 @@ fn main() -> ! {
7474
info!("Conversion Done");
7575

7676
transfer.pause(|adc| adc.cancel_conversion());
77-
let (s0, adc, first_buffer) = transfer.free();
77+
let (ch1, adc, first_buffer) = transfer.free();
7878
let adc = adc.disable();
7979

80-
channels.0 = s0;
80+
channels.ch1 = ch1;
8181

8282
let millivolts = adc.sample_to_millivolts(first_buffer[0]);
8383
info!("pa3: {}mV", millivolts);

examples/spi-dma.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ fn main() -> ! {
6262
*item = index as u8;
6363
}
6464
let dma_buf = cortex_m::singleton!(: [u8; BUFFER_SIZE] = buf).unwrap();
65-
let mut transfer_dma = channels.0.into_memory_to_peripheral_transfer(
65+
let mut transfer_dma = channels.ch1.into_memory_to_peripheral_transfer(
6666
spi.enable_tx_dma(),
6767
&mut dma_buf[..],
6868
config,

examples/uart-dma-rx.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ fn main() -> ! {
6565

6666
let (_tx, rx) = usart.split();
6767

68-
let mut transfer = channels.0.into_circ_peripheral_to_memory_transfer(
68+
let mut transfer = channels.ch1.into_circ_peripheral_to_memory_transfer(
6969
rx.enable_dma(),
7070
&mut rx_buffer[..],
7171
config,

examples/uart-dma-tx.rs

+5-4
Original file line numberDiff line numberDiff line change
@@ -64,10 +64,11 @@ fn main() -> ! {
6464
let (tx, _rx) = usart.split();
6565

6666
// Setup DMA for USART2 TX with dma channel 1.
67-
let mut transfer =
68-
channels
69-
.0
70-
.into_memory_to_peripheral_transfer(tx.enable_dma(), &mut tx_buffer[..], config);
67+
let mut transfer = channels.ch1.into_memory_to_peripheral_transfer(
68+
tx.enable_dma(),
69+
&mut tx_buffer[..],
70+
config,
71+
);
7172

7273
transfer.start(|_tx| {});
7374
loop {

src/dma/channel.rs

+28-26
Original file line numberDiff line numberDiff line change
@@ -71,23 +71,25 @@ pub struct DmaInterrupts {
7171
}
7272

7373
/// Alias for a tuple with all DMA channels.
74-
pub struct ChannelsTuple<T>(
75-
pub Channel1<T>,
76-
pub Channel2<T>,
77-
pub Channel3<T>,
78-
pub Channel4<T>,
79-
pub Channel5<T>,
80-
pub Channel6<T>,
81-
#[cfg(not(any(feature = "stm32g431", feature = "stm32g441",)))] pub Channel7<T>,
82-
#[cfg(not(any(feature = "stm32g431", feature = "stm32g441",)))] pub Channel8<T>,
83-
);
74+
pub struct Channels<T> {
75+
pub ch1: Channel1<T>,
76+
pub ch2: Channel2<T>,
77+
pub ch3: Channel3<T>,
78+
pub ch4: Channel4<T>,
79+
pub ch5: Channel5<T>,
80+
pub ch6: Channel6<T>,
81+
#[cfg(not(any(feature = "stm32g431", feature = "stm32g441",)))]
82+
pub ch7: Channel7<T>,
83+
#[cfg(not(any(feature = "stm32g431", feature = "stm32g441",)))]
84+
pub ch8: Channel8<T>,
85+
}
8486

8587
pub trait DMAExt<I> {
86-
fn split(self, rcc: &Rcc) -> ChannelsTuple<I>;
88+
fn split(self, rcc: &Rcc) -> Channels<I>;
8789
}
8890

8991
impl DMAExt<Self> for DMA1 {
90-
fn split(self, rcc: &Rcc) -> ChannelsTuple<DMA1> {
92+
fn split(self, rcc: &Rcc) -> Channels<DMA1> {
9193
// Enable DMAMux is not yet enabled
9294
if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
9395
// Enable peripheral
@@ -97,12 +99,12 @@ impl DMAExt<Self> for DMA1 {
9799
// Enable peripheral
98100
rcc.rb.ahb1enr().modify(|_, w| w.dma1en().set_bit());
99101

100-
ChannelsTuple::new(self)
102+
Channels::new(self)
101103
}
102104
}
103105

104106
impl DMAExt<Self> for DMA2 {
105-
fn split(self, rcc: &Rcc) -> ChannelsTuple<DMA2> {
107+
fn split(self, rcc: &Rcc) -> Channels<DMA2> {
106108
// Enable DMAMux is not yet enabled
107109
if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
108110
// Enable peripheral
@@ -112,25 +114,25 @@ impl DMAExt<Self> for DMA2 {
112114
// Enable peripheral
113115
rcc.rb.ahb1enr().modify(|_, w| w.dma2en().set_bit());
114116

115-
ChannelsTuple::new(self)
117+
Channels::new(self)
116118
}
117119
}
118120

119-
impl<I: Instance> ChannelsTuple<I> {
121+
impl<I: Instance> Channels<I> {
120122
/// Splits the DMA peripheral into channels.
121123
pub(crate) fn new(_regs: I) -> Self {
122-
Self(
123-
Channel1 { _dma: PhantomData },
124-
Channel2 { _dma: PhantomData },
125-
Channel3 { _dma: PhantomData },
126-
Channel4 { _dma: PhantomData },
127-
Channel5 { _dma: PhantomData },
128-
Channel6 { _dma: PhantomData },
124+
Self {
125+
ch1: Channel1 { _dma: PhantomData },
126+
ch2: Channel2 { _dma: PhantomData },
127+
ch3: Channel3 { _dma: PhantomData },
128+
ch4: Channel4 { _dma: PhantomData },
129+
ch5: Channel5 { _dma: PhantomData },
130+
ch6: Channel6 { _dma: PhantomData },
129131
#[cfg(not(any(feature = "stm32g431", feature = "stm32g441",)))]
130-
Channel7 { _dma: PhantomData },
132+
ch7: Channel7 { _dma: PhantomData },
131133
#[cfg(not(any(feature = "stm32g431", feature = "stm32g441",)))]
132-
Channel8 { _dma: PhantomData },
133-
)
134+
ch8: Channel8 { _dma: PhantomData },
135+
}
134136
}
135137
}
136138

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