From 2caf4f2a0465d0fc52879e5577add527eb9d1b4c Mon Sep 17 00:00:00 2001 From: wbuck Date: Sun, 10 Jan 2021 11:15:18 -0500 Subject: [PATCH 01/10] Use embedded_time --- Cargo.toml | 1 + src/i2c.rs | 4 ++-- src/prelude.rs | 3 ++- src/pwm.rs | 4 ++-- src/rcc.rs | 2 +- src/serial.rs | 5 +++-- src/spi.rs | 2 +- src/time.rs | 2 ++ src/timer.rs | 3 ++- src/watchdog.rs | 8 ++++---- 10 files changed, 20 insertions(+), 14 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index fbe18b5b3..3fd5fa2fb 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -33,6 +33,7 @@ nb = "0.1" paste = "1" rtcc = "0.2" stm32f3 = "0.12" +embedded-time = "0.10" [dependencies.embedded-hal-can] version = "0.1.0" diff --git a/src/i2c.rs b/src/i2c.rs index ce7eb1c80..52ba94c9b 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -6,13 +6,13 @@ use core::convert::TryFrom; use core::ops::Deref; +use embedded_time::rate::Hertz; use crate::{ gpio::{gpioa, gpiob, AF4}, hal::blocking::i2c::{Read, Write, WriteRead}, pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC}, rcc::{Clocks, APB1}, - time::{Hertz, U32Ext}, }; #[cfg(not(feature = "gpio-f333"))] @@ -451,7 +451,7 @@ macro_rules! i2c { fn clock(clocks: &Clocks) -> Hertz { // NOTE(unsafe) atomic read with no side effects match unsafe { (*RCC::ptr()).cfgr3.read().$i2cXsw().variant() } { - I2C1SW_A::HSI => 8.mhz().into(), + I2C1SW_A::HSI => Hertz(8_000_000), I2C1SW_A::SYSCLK => clocks.sysclk(), } } diff --git a/src/prelude.rs b/src/prelude.rs index 02ca404ab..00a254b44 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -6,7 +6,8 @@ pub use crate::flash::FlashExt as _stm32f3xx_hal_flash_FlashExt; pub use crate::gpio::GpioExt as _stm32f3xx_hal_gpio_GpioExt; pub use crate::hal::prelude::*; pub use crate::rcc::RccExt as _stm32f3xx_hal_rcc_RccExt; -pub use crate::time::U32Ext as _stm32f3xx_hal_time_U32Ext; +pub use embedded_time::duration::*; +pub use embedded_time::rate::*; #[cfg(feature = "unproven")] pub use crate::{ hal::digital::v2::InputPin as _embedded_hal_digital_InputPin, diff --git a/src/pwm.rs b/src/pwm.rs index c3978420d..4bf4654ad 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -159,10 +159,10 @@ use crate::{ gpio::{self, gpioa, gpiob}, hal::PwmPin, pac::{RCC, TIM15, TIM16, TIM17, TIM2}, - rcc::Clocks, - time::Hertz, + rcc::Clocks }; use core::marker::PhantomData; +use embedded_time::rate::Hertz; #[cfg(any( feature = "stm32f302xb", diff --git a/src/rcc.rs b/src/rcc.rs index 876b0d5df..2f74df71d 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -60,7 +60,7 @@ use crate::pac::{ }; use crate::flash::ACR; -use crate::time::Hertz; +use embedded_time::rate::Hertz; /// Extension trait that constrains the `RCC` peripheral pub trait RccExt { diff --git a/src/serial.rs b/src/serial.rs index 0a8353d75..7bdaf3f24 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -5,10 +5,11 @@ use crate::{ hal::{blocking, serial}, pac::{USART1, USART2, USART3}, rcc::{Clocks, APB1, APB2}, - time::Bps, }; + use cfg_if::cfg_if; use core::{convert::Infallible, marker::PhantomData, ptr}; +use embedded_time::rate::Baud; cfg_if! { if #[cfg(any(feature = "stm32f302", feature = "stm32f303"))] { @@ -111,7 +112,7 @@ macro_rules! hal { pub fn $usartX( usart: $USARTX, pins: (TX, RX), - baud_rate: Bps, + baud_rate: Baud, clocks: Clocks, apb: &mut $APB, ) -> Self diff --git a/src/spi.rs b/src/spi.rs index ea86cf504..0aba12b66 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -131,8 +131,8 @@ use crate::rcc::APB1; feature = "stm32f398" ))] use crate::rcc::APB2; -use crate::time::Hertz; use core::marker::PhantomData; +use embedded_time::rate::Hertz; /// SPI error #[derive(Debug)] diff --git a/src/time.rs b/src/time.rs index 759f54b11..12249e876 100644 --- a/src/time.rs +++ b/src/time.rs @@ -1,5 +1,6 @@ //! Time units +/* use cortex_m::peripheral::DWT; use crate::rcc::Clocks; @@ -126,3 +127,4 @@ impl Instant { DWT::get_cycle_count().wrapping_sub(self.now) } } +*/ diff --git a/src/timer.rs b/src/timer.rs index 591351010..8563489fb 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -52,9 +52,10 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6}; use crate::pac::{TIM3, TIM7}; use void::Void; +use embedded_time::rate::Hertz; use crate::rcc::{Clocks, APB1, APB2}; -use crate::time::Hertz; + /// Associated clocks with timers pub trait PclkSrc { diff --git a/src/watchdog.rs b/src/watchdog.rs index ef723014a..11115ec91 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -7,7 +7,7 @@ use crate::hal::watchdog::{Watchdog, WatchdogEnable}; use crate::pac::{DBGMCU, IWDG}; -use crate::time::MilliSeconds; +use embedded_time::duration::Milliseconds; const LSI_KHZ: u32 = 40; const MAX_PR: u8 = 8; @@ -54,13 +54,13 @@ impl IndependentWatchDog { } /// Returns the interval in ms - pub fn interval(&self) -> MilliSeconds { + pub fn interval(&self) -> Milliseconds { while self.is_pr_updating() {} let pr = self.iwdg.pr.read().pr().bits(); let rl = self.iwdg.rlr.read().rl().bits(); let ms = Self::timeout_period(pr, rl); - MilliSeconds(ms) + Milliseconds(ms) } /// pr: Prescaler divider bits, rl: reload value @@ -93,7 +93,7 @@ impl IndependentWatchDog { } impl WatchdogEnable for IndependentWatchDog { - type Time = MilliSeconds; + type Time = Milliseconds; fn start>(&mut self, period: T) { self.setup(period.into().0); From 303e7218020968f6594a8628040c6e4c0a3f1865 Mon Sep 17 00:00:00 2001 From: wbuck Date: Sun, 10 Jan 2021 11:34:39 -0500 Subject: [PATCH 02/10] Re-export embedded_time --- src/i2c.rs | 2 +- src/lib.rs | 3 ++- src/prelude.rs | 2 -- src/pwm.rs | 4 ++-- src/rcc.rs | 2 +- src/serial.rs | 2 +- src/spi.rs | 2 +- src/timer.rs | 3 +-- src/watchdog.rs | 2 +- 9 files changed, 10 insertions(+), 12 deletions(-) diff --git a/src/i2c.rs b/src/i2c.rs index 52ba94c9b..34988e609 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -6,13 +6,13 @@ use core::convert::TryFrom; use core::ops::Deref; -use embedded_time::rate::Hertz; use crate::{ gpio::{gpioa, gpiob, AF4}, hal::blocking::i2c::{Read, Write, WriteRead}, pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC}, rcc::{Clocks, APB1}, + time::rate::Hertz, }; #[cfg(not(feature = "gpio-f333"))] diff --git a/src/lib.rs b/src/lib.rs index da4c2fec7..c3b42b850 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -101,6 +101,8 @@ pub use embedded_hal as hal; pub use nb; pub use nb::block; +pub use embedded_time as time; + #[cfg(feature = "defmt")] pub(crate) use defmt::{assert, panic, unreachable, unwrap}; #[cfg(feature = "defmt")] @@ -187,7 +189,6 @@ cfg_if::cfg_if! { pub mod rtc; pub mod serial; pub mod spi; - pub mod time; pub mod timer; } } diff --git a/src/prelude.rs b/src/prelude.rs index 00a254b44..b074bb994 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -6,8 +6,6 @@ pub use crate::flash::FlashExt as _stm32f3xx_hal_flash_FlashExt; pub use crate::gpio::GpioExt as _stm32f3xx_hal_gpio_GpioExt; pub use crate::hal::prelude::*; pub use crate::rcc::RccExt as _stm32f3xx_hal_rcc_RccExt; -pub use embedded_time::duration::*; -pub use embedded_time::rate::*; #[cfg(feature = "unproven")] pub use crate::{ hal::digital::v2::InputPin as _embedded_hal_digital_InputPin, diff --git a/src/pwm.rs b/src/pwm.rs index 4bf4654ad..555652908 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -159,10 +159,10 @@ use crate::{ gpio::{self, gpioa, gpiob}, hal::PwmPin, pac::{RCC, TIM15, TIM16, TIM17, TIM2}, - rcc::Clocks + rcc::Clocks, + time::rate::Hertz, }; use core::marker::PhantomData; -use embedded_time::rate::Hertz; #[cfg(any( feature = "stm32f302xb", diff --git a/src/rcc.rs b/src/rcc.rs index 2f74df71d..bf568082c 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -60,7 +60,7 @@ use crate::pac::{ }; use crate::flash::ACR; -use embedded_time::rate::Hertz; +use crate::time::rate::Hertz; /// Extension trait that constrains the `RCC` peripheral pub trait RccExt { diff --git a/src/serial.rs b/src/serial.rs index 7bdaf3f24..643c206fd 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -5,11 +5,11 @@ use crate::{ hal::{blocking, serial}, pac::{USART1, USART2, USART3}, rcc::{Clocks, APB1, APB2}, + time::rate::Baud }; use cfg_if::cfg_if; use core::{convert::Infallible, marker::PhantomData, ptr}; -use embedded_time::rate::Baud; cfg_if! { if #[cfg(any(feature = "stm32f302", feature = "stm32f303"))] { diff --git a/src/spi.rs b/src/spi.rs index 0aba12b66..1a43de3ce 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -132,7 +132,7 @@ use crate::rcc::APB1; ))] use crate::rcc::APB2; use core::marker::PhantomData; -use embedded_time::rate::Hertz; +use crate::time::rate::Hertz; /// SPI error #[derive(Debug)] diff --git a/src/timer.rs b/src/timer.rs index 8563489fb..832182073 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -52,8 +52,7 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6}; use crate::pac::{TIM3, TIM7}; use void::Void; -use embedded_time::rate::Hertz; - +use crate::time::rate::Hertz; use crate::rcc::{Clocks, APB1, APB2}; diff --git a/src/watchdog.rs b/src/watchdog.rs index 11115ec91..3a5d148f6 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -7,7 +7,7 @@ use crate::hal::watchdog::{Watchdog, WatchdogEnable}; use crate::pac::{DBGMCU, IWDG}; -use embedded_time::duration::Milliseconds; +use crate::time::duration::Milliseconds; const LSI_KHZ: u32 = 40; const MAX_PR: u8 = 8; From 2c81f7e94af54a59c34bf95cede661040fe24319 Mon Sep 17 00:00:00 2001 From: wbuck Date: Sun, 10 Jan 2021 12:01:02 -0500 Subject: [PATCH 03/10] Remove custom time impl --- src/time.rs | 130 ---------------------------------------------------- 1 file changed, 130 deletions(-) delete mode 100644 src/time.rs diff --git a/src/time.rs b/src/time.rs deleted file mode 100644 index 12249e876..000000000 --- a/src/time.rs +++ /dev/null @@ -1,130 +0,0 @@ -//! Time units - -/* -use cortex_m::peripheral::DWT; - -use crate::rcc::Clocks; - -/// Bits per second -#[derive(PartialEq, PartialOrd, Clone, Copy)] -pub struct Bps(pub u32); - -/// Hertz -#[derive(PartialEq, PartialOrd, Clone, Copy)] -pub struct Hertz(pub u32); - -/// KiloHertz -#[derive(PartialEq, PartialOrd, Clone, Copy)] -pub struct KiloHertz(pub u32); - -/// MegaHertz -#[derive(PartialEq, PartialOrd, Clone, Copy)] -pub struct MegaHertz(pub u32); - -/// Time unit -#[derive(PartialEq, PartialOrd, Clone, Copy)] -pub struct MilliSeconds(pub u32); - -/// Extension trait that adds convenience methods to the `u32` type -pub trait U32Ext { - /// Wrap in `Bps` - fn bps(self) -> Bps; - - /// Wrap in `Hertz` - fn hz(self) -> Hertz; - - /// Wrap in `KiloHertz` - fn khz(self) -> KiloHertz; - - /// Wrap in `MegaHertz` - fn mhz(self) -> MegaHertz; - - /// Wrap in `MilliSeconds` - fn ms(self) -> MilliSeconds; -} - -impl U32Ext for u32 { - fn bps(self) -> Bps { - Bps(self) - } - - fn hz(self) -> Hertz { - Hertz(self) - } - - fn khz(self) -> KiloHertz { - KiloHertz(self) - } - - fn mhz(self) -> MegaHertz { - MegaHertz(self) - } - - fn ms(self) -> MilliSeconds { - MilliSeconds(self) - } -} - -impl From for Hertz { - fn from(val: KiloHertz) -> Self { - Self(val.0 * 1_000) - } -} - -impl From for Hertz { - fn from(val: MegaHertz) -> Self { - Self(val.0 * 1_000_000) - } -} - -impl From for KiloHertz { - fn from(val: MegaHertz) -> Self { - Self(val.0 * 1_000) - } -} - -/// A monotonic nondecreasing timer -#[derive(Clone, Copy)] -pub struct MonoTimer { - frequency: Hertz, -} - -impl MonoTimer { - /// Creates a new `Monotonic` timer - pub fn new(mut dwt: DWT, clocks: Clocks) -> Self { - dwt.enable_cycle_counter(); - - // now the CYCCNT counter can't be stopped or resetted - drop(dwt); - - MonoTimer { - frequency: clocks.hclk(), - } - } - - /// Returns the frequency at which the monotonic timer is operating at - pub fn frequency(self) -> Hertz { - self.frequency - } - - /// Returns an `Instant` corresponding to "now" - pub fn now(self) -> Instant { - Instant { - now: DWT::get_cycle_count(), - } - } -} - -/// A measurement of a monotonically nondecreasing clock -#[derive(Clone, Copy)] -pub struct Instant { - now: u32, -} - -impl Instant { - /// Ticks elapsed since the `Instant` was created - pub fn elapsed(self) -> u32 { - DWT::get_cycle_count().wrapping_sub(self.now) - } -} -*/ From 9fa59409dc7d7fbda3bf048a5142bdda8943655b Mon Sep 17 00:00:00 2001 From: wbuck Date: Sun, 10 Jan 2021 22:13:51 -0500 Subject: [PATCH 04/10] Fix examples and tests - Updated all examples to use embedded-time - Updated all tests to use embedded-time --- examples/can.rs | 13 +++-- examples/i2c_scanner.rs | 10 +++- examples/pwm.rs | 14 ++--- examples/serial_dma.rs | 3 +- examples/spi.rs | 11 ++-- examples/usb_serial.rs | 11 ++-- tests/rcc.rs | 113 ++++++++++++++++++++-------------------- 7 files changed, 98 insertions(+), 77 deletions(-) diff --git a/examples/can.rs b/examples/can.rs index a72adf968..bbddd9b25 100644 --- a/examples/can.rs +++ b/examples/can.rs @@ -6,12 +6,15 @@ use panic_semihosting as _; use stm32f3xx_hal as hal; +use core::convert::TryFrom; + use cortex_m::asm; use cortex_m_rt::entry; use hal::prelude::*; use hal::stm32; use hal::watchdog::IndependentWatchDog; +use hal::time::{duration::*, rate::*}; use hal::can::{Can, CanFilter, CanFrame, CanId, Filter, Frame, Receiver, Transmitter}; use nb::block; @@ -31,10 +34,10 @@ fn main() -> ! { let _clocks = rcc .cfgr - .use_hse(32.mhz()) - .sysclk(32.mhz()) - .pclk1(16.mhz()) - .pclk2(16.mhz()) + .use_hse(Hertz::try_from(32u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(32u32.MHz()).unwrap()) + .pclk1(Hertz::try_from(16u32.MHz()).unwrap()) + .pclk2(Hertz::try_from(16u32.MHz()).unwrap()) .freeze(&mut flash.acr); // Configure CAN RX and TX pins (AF9) @@ -60,7 +63,7 @@ fn main() -> ! { // Watchdog makes sure this gets restarted periodically if nothing happens let mut iwdg = IndependentWatchDog::new(dp.IWDG); iwdg.stop_on_debug(&dp.DBGMCU, true); - iwdg.start(100.ms()); + iwdg.start(100u32.milliseconds()); // Send an initial message! asm::delay(100_000); diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index cda4b365a..2c903315d 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -10,11 +10,14 @@ use core::ops::Range; use panic_semihosting as _; +use core::convert::TryFrom; + use cortex_m::asm; use cortex_m_rt::entry; use cortex_m_semihosting::{hprint, hprintln}; use stm32f3xx_hal::{self as hal, pac, prelude::*}; +use hal::time::rate::*; const VALID_ADDR_RANGE: Range = 0x08..0x78; @@ -33,7 +36,12 @@ fn main() -> ! { gpiob.pb6.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SCL gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA ); - let mut i2c = hal::i2c::I2c::new(dp.I2C1, pins, 100.khz(), clocks, &mut rcc.apb1); + let mut i2c = hal::i2c::I2c::new( + dp.I2C1, + pins, + Hertz::try_from(100u32.kHz()).unwrap(), + clocks, + &mut rcc.apb1); hprintln!("Start i2c scanning...").expect("Error using hprintln."); hprintln!().unwrap(); diff --git a/examples/pwm.rs b/examples/pwm.rs index 4457aa0d6..f70afc7f1 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -7,6 +7,8 @@ use panic_semihosting as _; use stm32f3xx_hal as hal; +use core::convert::TryFrom; + use cortex_m::asm; use cortex_m_rt::entry; @@ -18,7 +20,7 @@ use hal::gpio::GpioExt; use hal::pac; use hal::pwm::{tim16, tim2, tim3, tim8}; use hal::rcc::RccExt; -use hal::time::U32Ext; +use hal::time::rate::*; #[entry] fn main() -> ! { @@ -28,7 +30,7 @@ fn main() -> ! { // Configure our clocks let mut flash = dp.FLASH.constrain(); let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(16.mhz()).freeze(&mut flash.acr); + let clocks = rcc.cfgr.sysclk(Hertz::try_from(16u32.MHz()).unwrap()).freeze(&mut flash.acr); // Prep the pins we need in their correct alternate function let mut gpioa = dp.GPIOA.split(&mut rcc.ahb); @@ -53,7 +55,7 @@ fn main() -> ! { let tim3_channels = tim3( dp.TIM3, 1280, // resolution of duty cycle - 50.hz(), // frequency of period + 50u32.Hz(), // frequency of period &clocks, // To get the timer's clock speed ); @@ -102,7 +104,7 @@ fn main() -> ! { let tim2_channels = tim2( dp.TIM2, 160000, // resolution of duty cycle - 50.hz(), // frequency of period + 50u32.Hz(), // frequency of period &clocks, // To get the timer's clock speed ); @@ -117,7 +119,7 @@ fn main() -> ! { let mut tim16_ch1 = tim16( dp.TIM16, 1280, // resolution of duty cycle - 50.hz(), // frequency of period + 50u32.Hz(), // frequency of period &clocks, // To get the timer's clock speed ) .output_to_pb8(pb8); @@ -131,7 +133,7 @@ fn main() -> ! { let tim8_channels = tim8( dp.TIM8, 1280, // resolution of duty cycle - 50.hz(), // frequency of period + 50u32.Hz(), // frequency of period &clocks, // To get the timer's clock speed ); diff --git a/examples/serial_dma.rs b/examples/serial_dma.rs index e3c051ff7..04a8e544d 100644 --- a/examples/serial_dma.rs +++ b/examples/serial_dma.rs @@ -10,6 +10,7 @@ use panic_semihosting as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; use stm32f3xx_hal::{pac, prelude::*, serial::Serial}; +use stm32f3xx_hal::time::rate::*; #[entry] fn main() -> ! { @@ -25,7 +26,7 @@ fn main() -> ! { gpioa.pa9.into_af7(&mut gpioa.moder, &mut gpioa.afrh), gpioa.pa10.into_af7(&mut gpioa.moder, &mut gpioa.afrh), ); - let serial = Serial::usart1(dp.USART1, pins, 9600.bps(), clocks, &mut rcc.apb2); + let serial = Serial::usart1(dp.USART1, pins, 9600.Bd(), clocks, &mut rcc.apb2); let (tx, rx) = serial.split(); let dma1 = dp.DMA1.split(&mut rcc.ahb); diff --git a/examples/spi.rs b/examples/spi.rs index 085bbdd0c..73a9e25a9 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -7,12 +7,15 @@ use panic_semihosting as _; use stm32f3xx_hal as hal; +use core::convert::TryFrom; + use cortex_m::asm; use cortex_m_rt::entry; use hal::pac; use hal::prelude::*; use hal::spi::{Mode, Phase, Polarity, Spi}; +use hal::time::rate::*; #[entry] fn main() -> ! { @@ -24,9 +27,9 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(8.mhz()) - .sysclk(48.mhz()) - .pclk1(24.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) + .pclk1(Hertz::try_from(24u32.MHz()).unwrap()) .freeze(&mut flash.acr); // Configure pins for SPI @@ -43,7 +46,7 @@ fn main() -> ! { dp.SPI1, (sck, miso, mosi), spi_mode, - 3.mhz(), + Hertz::try_from(3u32.MHz()).unwrap(), clocks, &mut rcc.apb2, ); diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index fbf099ced..1bc4f05d9 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -10,9 +10,12 @@ use stm32f3xx_hal as hal; use cortex_m::asm::delay; use cortex_m_rt::entry; +use core::convert::TryFrom; + use hal::pac; use hal::prelude::*; use hal::usb::{Peripheral, UsbBus}; +use hal::time::rate::*; use usb_device::prelude::*; use usbd_serial::{SerialPort, USB_CLASS_CDC}; @@ -26,10 +29,10 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(8.mhz()) - .sysclk(48.mhz()) - .pclk1(24.mhz()) - .pclk2(24.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) + .pclk1(Hertz::try_from(24u32.MHz()).unwrap()) + .pclk2(Hertz::try_from(24u32.MHz()).unwrap()) .freeze(&mut flash.acr); assert!(clocks.usbclk_valid()); diff --git a/tests/rcc.rs b/tests/rcc.rs index e2f637316..3226a5223 100644 --- a/tests/rcc.rs +++ b/tests/rcc.rs @@ -6,7 +6,8 @@ use panic_probe as _; #[defmt_test::tests] mod tests { - use stm32f3xx_hal::{pac, prelude::*}; + use core::convert::TryFrom; + use stm32f3xx_hal::{pac, prelude::*, time::rate::*}; // Test the defaults with no configuration #[test] @@ -18,10 +19,10 @@ mod tests { let clock = rcc.cfgr.freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 8.mhz().into()); - defmt::assert!(clock.hclk() == 8.mhz().into()); - defmt::assert!(clock.pclk2() == 8.mhz().into()); - defmt::assert!(clock.pclk1() == 8.mhz().into()); + defmt::assert!(clock.sysclk() == 8u32.MHz()); + defmt::assert!(clock.hclk() == 8u32.MHz()); + defmt::assert!(clock.pclk2() == 8u32.MHz()); + defmt::assert!(clock.pclk1() == 8u32.MHz()); defmt::assert!(!clock.usbclk_valid()); } @@ -37,14 +38,14 @@ mod tests { let clock = rcc .cfgr - .use_hse(8.mhz()) - .sysclk(15.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(15u32.MHz()).unwrap()) .freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 15.mhz().into()); - defmt::assert!(clock.hclk() == 15.mhz().into()); - defmt::assert!(clock.pclk2() == 15.mhz().into()); - defmt::assert!(clock.pclk1() == 15.mhz().into()); + defmt::assert!(clock.sysclk() == 15u32.MHz()); + defmt::assert!(clock.hclk() == 15u32.MHz()); + defmt::assert!(clock.pclk2() == 15u32.MHz()); + defmt::assert!(clock.pclk1() == 15u32.MHz()); defmt::assert!(!clock.usbclk_valid()); } @@ -64,12 +65,12 @@ mod tests { feature = "stm32f303xe", feature = "stm32f398", ))] { - let clock = rcc.cfgr.sysclk(72.mhz()).freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(Hertz::try_from(72u32.MHz()).unwrap()).freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 72.mhz().into()); - defmt::assert!(clock.hclk() == 72.mhz().into()); - defmt::assert!(clock.pclk2() == 72.mhz().into()); - defmt::assert!(clock.pclk1() == 36.mhz().into()); + defmt::assert!(clock.sysclk() == 72u32.MHz()); + defmt::assert!(clock.hclk() == 72u32.MHz()); + defmt::assert!(clock.pclk2() == 72u32.MHz()); + defmt::assert!(clock.pclk1() == 36u32.MHz()); } else { // Notice the strange part about 67 being reduced to 64? // @@ -78,12 +79,12 @@ mod tests { // and the resolution is therefor lower. // Because of the implementation the clock is then approximated to // the highest possible value (64 Mhz). - let clock = rcc.cfgr.sysclk(67.mhz()).freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(Hertz::try_from(67u32.MHz()).unwrap()).freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 64.mhz().into()); - defmt::assert!(clock.hclk() == 64.mhz().into()); - defmt::assert!(clock.pclk2() == 64.mhz().into()); - defmt::assert!(clock.pclk1() == 32.mhz().into()); + defmt::assert!(clock.sysclk() == 64u32.MHz()); + defmt::assert!(clock.hclk() == 64u32.MHz()); + defmt::assert!(clock.pclk2() == 64u32.MHz()); + defmt::assert!(clock.pclk1() == 32u32.MHz()); } } @@ -100,14 +101,14 @@ mod tests { let clock = rcc .cfgr - .use_hse(8.mhz()) - .sysclk(32.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(32u32.MHz()).unwrap()) .freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 32.mhz().into()); - defmt::assert!(clock.hclk() == 32.mhz().into()); - defmt::assert!(clock.pclk2() == 32.mhz().into()); - defmt::assert!(clock.pclk1() == 32.mhz().into()); + defmt::assert!(clock.sysclk() == 32u32.MHz()); + defmt::assert!(clock.hclk() == 32u32.MHz()); + defmt::assert!(clock.pclk2() == 32u32.MHz()); + defmt::assert!(clock.pclk1() == 32u32.MHz()); defmt::assert!(!clock.usbclk_valid()); } @@ -122,14 +123,14 @@ mod tests { let clock = rcc .cfgr - .use_hse(8.mhz()) - .sysclk(48.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .sysclk( Hertz::try_from(48u32.MHz()).unwrap()) .freeze(&mut flash.acr); // works - defmt::assert!(clock.sysclk() == 48.mhz().into()); - defmt::assert!(clock.hclk() == 48.mhz().into()); - defmt::assert!(clock.pclk2() == 48.mhz().into()); - defmt::assert!(clock.pclk1() == 24.mhz().into()); + defmt::assert!(clock.sysclk() == 48u32.MHz()); + defmt::assert!(clock.hclk() == 48u32.MHz()); + defmt::assert!(clock.pclk2() == 48u32.MHz()); + defmt::assert!(clock.pclk1() == 24u32.MHz()); defmt::assert!(clock.usbclk_valid()); } @@ -142,21 +143,21 @@ mod tests { let clock = rcc .cfgr - .use_hse(8.mhz()) - .hclk(48.mhz()) - .sysclk(48.mhz()) - .pclk1(12.mhz()) - .pclk2(12.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .hclk(Hertz::try_from(48u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) + .pclk1(Hertz::try_from(12u32.MHz()).unwrap()) + .pclk2(Hertz::try_from(12u32.MHz()).unwrap()) .freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 48.mhz().into()); - defmt::assert!(clock.hclk() == 48.mhz().into()); - defmt::assert!(clock.pclk2() == 12.mhz().into()); - defmt::assert!(clock.pclk1() == 12.mhz().into()); + defmt::assert!(clock.sysclk() == 48u32.MHz()); + defmt::assert!(clock.hclk() == 48u32.MHz()); + defmt::assert!(clock.pclk2() == 12u32.MHz()); + defmt::assert!(clock.pclk1() == 12u32.MHz()); defmt::assert!(clock.usbclk_valid()); } - // Another multiple of 8.mhz() external crystal + // Another multiple of 8.MHz() external crystal #[test] fn hse_sysclk_64mhz() { let dp = unsafe { pac::Peripherals::steal() }; @@ -166,15 +167,15 @@ mod tests { let clock = rcc .cfgr - .use_hse(8.mhz()) - .pclk1(16.mhz()) - .sysclk(64.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .pclk1( Hertz::try_from(16u32.MHz()).unwrap()) + .sysclk( Hertz::try_from(64u32.MHz()).unwrap()) .freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 64.mhz().into()); - defmt::assert!(clock.hclk() == 64.mhz().into()); - defmt::assert!(clock.pclk2() == 64.mhz().into()); - defmt::assert!(clock.pclk1() == 16.mhz().into()); + defmt::assert!(clock.sysclk() == 64u32.MHz()); + defmt::assert!(clock.hclk() == 64u32.MHz()); + defmt::assert!(clock.pclk2() == 64u32.MHz()); + defmt::assert!(clock.pclk1() == 16u32.MHz()); defmt::assert!(!clock.usbclk_valid()); } @@ -189,14 +190,14 @@ mod tests { let clock = rcc .cfgr - .use_hse(8.mhz()) - .sysclk(72.mhz()) + .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) + .sysclk( Hertz::try_from(72u32.MHz()).unwrap()) .freeze(&mut flash.acr); - defmt::assert!(clock.sysclk() == 72.mhz().into()); - defmt::assert!(clock.hclk() == 72.mhz().into()); - defmt::assert!(clock.pclk2() == 72.mhz().into()); - defmt::assert!(clock.pclk1() == 36.mhz().into()); + defmt::assert!(clock.sysclk() == 72u32.MHz()); + defmt::assert!(clock.hclk() == 72u32.MHz()); + defmt::assert!(clock.pclk2() == 72u32.MHz()); + defmt::assert!(clock.pclk1() == 36u32.MHz()); defmt::assert!(clock.usbclk_valid()); } } From 71a5cc073b70fe72da10e384a7fa0a298e81aced Mon Sep 17 00:00:00 2001 From: wbuck Date: Sun, 10 Jan 2021 22:35:48 -0500 Subject: [PATCH 05/10] Fix formatting --- examples/can.rs | 2 +- examples/i2c_scanner.rs | 14 ++++++++------ examples/pwm.rs | 21 ++++++++++++--------- examples/serial_dma.rs | 3 +-- examples/usb_serial.rs | 2 +- src/serial.rs | 2 +- src/spi.rs | 2 +- src/timer.rs | 6 ++---- tests/rcc.rs | 8 ++++---- 9 files changed, 31 insertions(+), 29 deletions(-) diff --git a/examples/can.rs b/examples/can.rs index bbddd9b25..d530ad84a 100644 --- a/examples/can.rs +++ b/examples/can.rs @@ -13,8 +13,8 @@ use cortex_m_rt::entry; use hal::prelude::*; use hal::stm32; -use hal::watchdog::IndependentWatchDog; use hal::time::{duration::*, rate::*}; +use hal::watchdog::IndependentWatchDog; use hal::can::{Can, CanFilter, CanFrame, CanId, Filter, Frame, Receiver, Transmitter}; use nb::block; diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index 2c903315d..73b005935 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -16,8 +16,8 @@ use cortex_m::asm; use cortex_m_rt::entry; use cortex_m_semihosting::{hprint, hprintln}; -use stm32f3xx_hal::{self as hal, pac, prelude::*}; use hal::time::rate::*; +use stm32f3xx_hal::{self as hal, pac, prelude::*}; const VALID_ADDR_RANGE: Range = 0x08..0x78; @@ -36,12 +36,14 @@ fn main() -> ! { gpiob.pb6.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SCL gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA ); + let mut i2c = hal::i2c::I2c::new( - dp.I2C1, - pins, - Hertz::try_from(100u32.kHz()).unwrap(), - clocks, - &mut rcc.apb1); + dp.I2C1, + pins, + Hertz::try_from(100u32.kHz()).unwrap(), + clocks, + &mut rcc.apb1, + ); hprintln!("Start i2c scanning...").expect("Error using hprintln."); hprintln!().unwrap(); diff --git a/examples/pwm.rs b/examples/pwm.rs index f70afc7f1..621001669 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -30,7 +30,10 @@ fn main() -> ! { // Configure our clocks let mut flash = dp.FLASH.constrain(); let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(Hertz::try_from(16u32.MHz()).unwrap()).freeze(&mut flash.acr); + let clocks = rcc + .cfgr + .sysclk(Hertz::try_from(16u32.MHz()).unwrap()) + .freeze(&mut flash.acr); // Prep the pins we need in their correct alternate function let mut gpioa = dp.GPIOA.split(&mut rcc.ahb); @@ -54,9 +57,9 @@ fn main() -> ! { // A four channel general purpose timer that's broadly available let tim3_channels = tim3( dp.TIM3, - 1280, // resolution of duty cycle + 1280, // resolution of duty cycle 50u32.Hz(), // frequency of period - &clocks, // To get the timer's clock speed + &clocks, // To get the timer's clock speed ); // Channels without pins cannot be enabled, so we can't forget to @@ -103,9 +106,9 @@ fn main() -> ! { // A 32-bit timer, so we can set a larger resolution let tim2_channels = tim2( dp.TIM2, - 160000, // resolution of duty cycle + 160000, // resolution of duty cycle 50u32.Hz(), // frequency of period - &clocks, // To get the timer's clock speed + &clocks, // To get the timer's clock speed ); let mut tim2_ch3 = tim2_channels.2.output_to_pb10(pb10); @@ -118,9 +121,9 @@ fn main() -> ! { // just use it directly let mut tim16_ch1 = tim16( dp.TIM16, - 1280, // resolution of duty cycle + 1280, // resolution of duty cycle 50u32.Hz(), // frequency of period - &clocks, // To get the timer's clock speed + &clocks, // To get the timer's clock speed ) .output_to_pb8(pb8); tim16_ch1.set_duty(tim16_ch1.get_max_duty() / 20); // 5% duty cyle @@ -132,9 +135,9 @@ fn main() -> ! { // to complementary pins (works just like standard pins) let tim8_channels = tim8( dp.TIM8, - 1280, // resolution of duty cycle + 1280, // resolution of duty cycle 50u32.Hz(), // frequency of period - &clocks, // To get the timer's clock speed + &clocks, // To get the timer's clock speed ); let mut tim8_ch1 = tim8_channels.0.output_to_pc10(pc10); diff --git a/examples/serial_dma.rs b/examples/serial_dma.rs index 04a8e544d..a5469091e 100644 --- a/examples/serial_dma.rs +++ b/examples/serial_dma.rs @@ -9,8 +9,7 @@ use panic_semihosting as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; -use stm32f3xx_hal::{pac, prelude::*, serial::Serial}; -use stm32f3xx_hal::time::rate::*; +use stm32f3xx_hal::{pac, prelude::*, serial::Serial, time::rate::*}; #[entry] fn main() -> ! { diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index 1bc4f05d9..bae9c5b97 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -14,8 +14,8 @@ use core::convert::TryFrom; use hal::pac; use hal::prelude::*; -use hal::usb::{Peripheral, UsbBus}; use hal::time::rate::*; +use hal::usb::{Peripheral, UsbBus}; use usb_device::prelude::*; use usbd_serial::{SerialPort, USB_CLASS_CDC}; diff --git a/src/serial.rs b/src/serial.rs index 643c206fd..7aac6e51a 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -5,7 +5,7 @@ use crate::{ hal::{blocking, serial}, pac::{USART1, USART2, USART3}, rcc::{Clocks, APB1, APB2}, - time::rate::Baud + time::rate::Baud, }; use cfg_if::cfg_if; diff --git a/src/spi.rs b/src/spi.rs index 1a43de3ce..43a3c10cf 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -131,8 +131,8 @@ use crate::rcc::APB1; feature = "stm32f398" ))] use crate::rcc::APB2; -use core::marker::PhantomData; use crate::time::rate::Hertz; +use core::marker::PhantomData; /// SPI error #[derive(Debug)] diff --git a/src/timer.rs b/src/timer.rs index 832182073..ee223e156 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -50,11 +50,9 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6}; feature = "stm32f398" ))] use crate::pac::{TIM3, TIM7}; - -use void::Void; -use crate::time::rate::Hertz; use crate::rcc::{Clocks, APB1, APB2}; - +use crate::time::rate::Hertz; +use void::Void; /// Associated clocks with timers pub trait PclkSrc { diff --git a/tests/rcc.rs b/tests/rcc.rs index 3226a5223..6cfafc5d3 100644 --- a/tests/rcc.rs +++ b/tests/rcc.rs @@ -124,7 +124,7 @@ mod tests { let clock = rcc .cfgr .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk( Hertz::try_from(48u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) .freeze(&mut flash.acr); // works defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -168,8 +168,8 @@ mod tests { let clock = rcc .cfgr .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .pclk1( Hertz::try_from(16u32.MHz()).unwrap()) - .sysclk( Hertz::try_from(64u32.MHz()).unwrap()) + .pclk1(Hertz::try_from(16u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(64u32.MHz()).unwrap()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); @@ -191,7 +191,7 @@ mod tests { let clock = rcc .cfgr .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk( Hertz::try_from(72u32.MHz()).unwrap()) + .sysclk(Hertz::try_from(72u32.MHz()).unwrap()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); From 547f975bc24db1439dd4c5b09332a73e8600a68d Mon Sep 17 00:00:00 2001 From: wbuck Date: Mon, 11 Jan 2021 21:29:12 -0500 Subject: [PATCH 06/10] Return Result where Rate conversion may fail --- examples/can.rs | 14 ++++++----- examples/i2c_scanner.rs | 10 +------- examples/pwm.rs | 7 +----- examples/spi.rs | 16 +++++++------ examples/usb_serial.rs | 14 ++++++----- src/i2c.rs | 18 +++++++++----- src/rcc.rs | 44 ++++++++++++++++++---------------- src/spi.rs | 22 ++++++++++------- tests/rcc.rs | 53 ++++++++++++++++++++++++++--------------- 9 files changed, 110 insertions(+), 88 deletions(-) diff --git a/examples/can.rs b/examples/can.rs index d530ad84a..98544c188 100644 --- a/examples/can.rs +++ b/examples/can.rs @@ -6,8 +6,6 @@ use panic_semihosting as _; use stm32f3xx_hal as hal; -use core::convert::TryFrom; - use cortex_m::asm; use cortex_m_rt::entry; @@ -34,10 +32,14 @@ fn main() -> ! { let _clocks = rcc .cfgr - .use_hse(Hertz::try_from(32u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(32u32.MHz()).unwrap()) - .pclk1(Hertz::try_from(16u32.MHz()).unwrap()) - .pclk2(Hertz::try_from(16u32.MHz()).unwrap()) + .use_hse(32u32.MHz()) + .unwrap() + .sysclk(32u32.MHz()) + .unwrap() + .pclk1(16u32.MHz()) + .unwrap() + .pclk2(16u32.MHz()) + .unwrap() .freeze(&mut flash.acr); // Configure CAN RX and TX pins (AF9) diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index 73b005935..d432cad8b 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -10,8 +10,6 @@ use core::ops::Range; use panic_semihosting as _; -use core::convert::TryFrom; - use cortex_m::asm; use cortex_m_rt::entry; use cortex_m_semihosting::{hprint, hprintln}; @@ -37,13 +35,7 @@ fn main() -> ! { gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA ); - let mut i2c = hal::i2c::I2c::new( - dp.I2C1, - pins, - Hertz::try_from(100u32.kHz()).unwrap(), - clocks, - &mut rcc.apb1, - ); + let mut i2c = hal::i2c::I2c::new(dp.I2C1, pins, 100u32.kHz(), clocks, &mut rcc.apb1).unwrap(); hprintln!("Start i2c scanning...").expect("Error using hprintln."); hprintln!().unwrap(); diff --git a/examples/pwm.rs b/examples/pwm.rs index 621001669..375038d26 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -7,8 +7,6 @@ use panic_semihosting as _; use stm32f3xx_hal as hal; -use core::convert::TryFrom; - use cortex_m::asm; use cortex_m_rt::entry; @@ -30,10 +28,7 @@ fn main() -> ! { // Configure our clocks let mut flash = dp.FLASH.constrain(); let mut rcc = dp.RCC.constrain(); - let clocks = rcc - .cfgr - .sysclk(Hertz::try_from(16u32.MHz()).unwrap()) - .freeze(&mut flash.acr); + let clocks = rcc.cfgr.sysclk(16u32.MHz()).unwrap().freeze(&mut flash.acr); // Prep the pins we need in their correct alternate function let mut gpioa = dp.GPIOA.split(&mut rcc.ahb); diff --git a/examples/spi.rs b/examples/spi.rs index 73a9e25a9..0c93d9eb2 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -7,8 +7,6 @@ use panic_semihosting as _; use stm32f3xx_hal as hal; -use core::convert::TryFrom; - use cortex_m::asm; use cortex_m_rt::entry; @@ -27,9 +25,12 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) - .pclk1(Hertz::try_from(24u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .sysclk(48u32.MHz()) + .unwrap() + .pclk1(24u32.MHz()) + .unwrap() .freeze(&mut flash.acr); // Configure pins for SPI @@ -46,10 +47,11 @@ fn main() -> ! { dp.SPI1, (sck, miso, mosi), spi_mode, - Hertz::try_from(3u32.MHz()).unwrap(), + 3u32.MHz(), clocks, &mut rcc.apb2, - ); + ) + .unwrap(); // Create an `u8` array, which can be transfered via SPI. let msg_send: [u8; 8] = [0xD, 0xE, 0xA, 0xD, 0xB, 0xE, 0xE, 0xF]; diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index bae9c5b97..7624f54c9 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -10,8 +10,6 @@ use stm32f3xx_hal as hal; use cortex_m::asm::delay; use cortex_m_rt::entry; -use core::convert::TryFrom; - use hal::pac; use hal::prelude::*; use hal::time::rate::*; @@ -29,10 +27,14 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) - .pclk1(Hertz::try_from(24u32.MHz()).unwrap()) - .pclk2(Hertz::try_from(24u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .sysclk(48u32.MHz()) + .unwrap() + .pclk1(24u32.MHz()) + .unwrap() + .pclk2(24u32.MHz()) + .unwrap() .freeze(&mut flash.acr); assert!(clocks.usbclk_valid()); diff --git a/src/i2c.rs b/src/i2c.rs index 34988e609..6cd493e9e 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -4,7 +4,7 @@ //! //! [examples/i2c_scanner.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/i2c_scanner.rs -use core::convert::TryFrom; +use core::convert::{TryFrom, TryFrom}; use core::ops::Deref; use crate::{ @@ -12,7 +12,7 @@ use crate::{ hal::blocking::i2c::{Read, Write, WriteRead}, pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC}, rcc::{Clocks, APB1}, - time::rate::Hertz, + time::rate::{Hertz, Rate}, }; #[cfg(not(feature = "gpio-f333"))] @@ -111,14 +111,20 @@ macro_rules! busy_wait { impl I2c { /// Configures the I2C peripheral to work in master mode - pub fn new(i2c: I2C, pins: (SCL, SDA), freq: F, clocks: Clocks, apb1: &mut APB1) -> Self + pub fn new( + i2c: I2C, + pins: (SCL, SDA), + freq: F, + clocks: Clocks, + apb1: &mut APB1, + ) -> Result>>::Error> where I2C: Instance, SCL: SclPin, SDA: SdaPin, - F: Into, + F: Rate + TryInto>, { - let freq = freq.into().0; + let freq = (freq.try_into()? as Hertz).0; crate::assert!(freq <= 1_000_000); @@ -195,7 +201,7 @@ impl I2c { // Enable the peripheral i2c.cr1.modify(|_, w| w.pe().set_bit()); - Self { i2c, pins } + Ok(Self { i2c, pins }) } /// Releases the I2C peripheral and associated pins diff --git a/src/rcc.rs b/src/rcc.rs index bf568082c..92b1365b2 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -54,13 +54,15 @@ //! For more details read the documentation of the [`CFGR`] methods to //! find out how to setup the clock. +use core::convert::TryInto; + use crate::pac::{ rcc::{self, cfgr, cfgr2}, RCC, }; use crate::flash::ACR; -use crate::time::rate::Hertz; +use crate::time::rate::{Hertz, Rate}; /// Extension trait that constrains the `RCC` peripheral pub trait RccExt { @@ -333,12 +335,12 @@ impl CFGR { /// /// Will result in a hang if an external oscillator is not connected or it fails to start, /// unless [css](CFGR::enable_css) is enabled. - pub fn use_hse(mut self, freq: F) -> Self + pub fn use_hse(mut self, freq: F) -> Result>>::Error> where - F: Into, + F: Rate + TryInto>, { - self.hse = Some(freq.into().0); - self + self.hse = Some((freq.try_into()? as Hertz).0); + Ok(self) } /// Enable `HSE` bypass. @@ -364,12 +366,12 @@ impl CFGR { } /// Sets a frequency for the AHB bus - pub fn hclk(mut self, freq: F) -> Self + pub fn hclk(mut self, freq: F) -> Result>>::Error> where - F: Into, + F: Rate + TryInto>, { - self.hclk = Some(freq.into().0); - self + self.hclk = Some((freq.try_into()? as Hertz).0); + Ok(self) } /// Sets a frequency for the `APB1` bus @@ -378,12 +380,12 @@ impl CFGR { /// /// If not manually set, it will be set to [`CFGR::sysclk`] frequency /// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz - pub fn pclk1(mut self, freq: F) -> Self + pub fn pclk1(mut self, freq: F) -> Result>>::Error> where - F: Into, + F: Rate + TryInto>, { - self.pclk1 = Some(freq.into().0); - self + self.pclk1 = Some((freq.try_into()? as Hertz).0); + Ok(self) } /// Sets a frequency for the `APB2` bus @@ -399,12 +401,12 @@ impl CFGR { /// /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] /// - pub fn pclk2(mut self, freq: F) -> Self + pub fn pclk2(mut self, freq: F) -> Result>>::Error> where - F: Into, + F: Rate + TryInto>, { - self.pclk2 = Some(freq.into().0); - self + self.pclk2 = Some((freq.try_into()? as Hertz).0); + Ok(self) } /// Sets the system (core) frequency @@ -422,12 +424,12 @@ impl CFGR { /// even when using the internal oscillator: /// /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] - pub fn sysclk(mut self, freq: F) -> Self + pub fn sysclk(mut self, freq: F) -> Result>>::Error> where - F: Into, + F: Rate + TryInto>, { - self.sysclk = Some(freq.into().0); - self + self.sysclk = Some((freq.try_into()? as Hertz).0); + Ok(self) } /// Calculate the values for the pll multiplier (`PLLMUL`) and the pll divisior (`PLLDIV`). diff --git a/src/spi.rs b/src/spi.rs index 43a3c10cf..4f10d8a92 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -4,7 +4,7 @@ //! //! [examples/spi.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/spi.rs -use core::ptr; +use core::{convert::TryInto, ptr}; use crate::hal::spi::FullDuplex; pub use crate::hal::spi::{Mode, Phase, Polarity}; @@ -131,7 +131,7 @@ use crate::rcc::APB1; feature = "stm32f398" ))] use crate::rcc::APB2; -use crate::time::rate::Hertz; +use crate::time::rate::{Hertz, Rate}; use core::marker::PhantomData; /// SPI error @@ -424,9 +424,9 @@ macro_rules! hal { freq: F, clocks: Clocks, apb2: &mut $APBX, - ) -> Self + ) -> Result>>::Error> where - F: Into, + F: Rate + TryInto>, SCK: SckPin<$SPIX>, MISO: MisoPin<$SPIX>, MOSI: MosiPin<$SPIX>, @@ -445,6 +445,7 @@ macro_rules! hal { w.ssoe().disabled() }); + let freq: Hertz = freq.try_into()?; // CPHA: phase // CPOL: polarity // MSTR: master mode @@ -468,7 +469,7 @@ macro_rules! hal { Polarity::IdleHigh => w.cpol().idle_high(), }; - w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq.into())); + w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq)); w.spe() .enabled() @@ -484,7 +485,7 @@ macro_rules! hal { .unidirectional() }); - Spi { spi, pins, _word: PhantomData } + Ok(Spi { spi, pins, _word: PhantomData }) } /// Releases the SPI peripheral and associated pins @@ -494,13 +495,18 @@ macro_rules! hal { /// Change the baud rate of the SPI pub fn reclock(&mut self, freq: F, clocks: Clocks) - where F: Into + -> Result<(), >>::Error> + where + F: Rate + TryInto>, { self.spi.cr1.modify(|_, w| w.spe().disabled()); + + let freq: Hertz = freq.try_into()?; self.spi.cr1.modify(|_, w| { - w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq.into())); + w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq)); w.spe().enabled() }); + Ok(()) } fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> spi1::cr1::BR_A { diff --git a/tests/rcc.rs b/tests/rcc.rs index 6cfafc5d3..f2d7d0663 100644 --- a/tests/rcc.rs +++ b/tests/rcc.rs @@ -6,7 +6,6 @@ use panic_probe as _; #[defmt_test::tests] mod tests { - use core::convert::TryFrom; use stm32f3xx_hal::{pac, prelude::*, time::rate::*}; // Test the defaults with no configuration @@ -38,8 +37,10 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(15u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .sysclk(15u32.MHz()) + .unwrap() .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 15u32.MHz()); @@ -65,7 +66,7 @@ mod tests { feature = "stm32f303xe", feature = "stm32f398", ))] { - let clock = rcc.cfgr.sysclk(Hertz::try_from(72u32.MHz()).unwrap()).freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(72u32.MHz()).unwrap().freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); defmt::assert!(clock.hclk() == 72u32.MHz()); @@ -79,7 +80,7 @@ mod tests { // and the resolution is therefor lower. // Because of the implementation the clock is then approximated to // the highest possible value (64 Mhz). - let clock = rcc.cfgr.sysclk(Hertz::try_from(67u32.MHz()).unwrap()).freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(67u32.MHz()).unwrap().freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); defmt::assert!(clock.hclk() == 64u32.MHz()); @@ -101,8 +102,10 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(32u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .sysclk(32u32.MHz()) + .unwrap() .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 32u32.MHz()); @@ -123,8 +126,10 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .sysclk(48u32.MHz()) + .unwrap() .freeze(&mut flash.acr); // works defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -143,11 +148,16 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .hclk(Hertz::try_from(48u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(48u32.MHz()).unwrap()) - .pclk1(Hertz::try_from(12u32.MHz()).unwrap()) - .pclk2(Hertz::try_from(12u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .hclk(48u32.MHz()) + .unwrap() + .sysclk(48u32.MHz()) + .unwrap() + .pclk1(12u32.MHz()) + .unwrap() + .pclk2(12u32.MHz()) + .unwrap() .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -167,9 +177,12 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .pclk1(Hertz::try_from(16u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(64u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .pclk1(16u32.MHz()) + .unwrap() + .sysclk(64u32.MHz()) + .unwrap() .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); @@ -190,8 +203,10 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz::try_from(8u32.MHz()).unwrap()) - .sysclk(Hertz::try_from(72u32.MHz()).unwrap()) + .use_hse(8u32.MHz()) + .unwrap() + .sysclk(72u32.MHz()) + .unwrap() .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); From 9b082a25b7def9af9622df24fe0e5635efdc6071 Mon Sep 17 00:00:00 2001 From: wbuck Date: Mon, 11 Jan 2021 21:37:54 -0500 Subject: [PATCH 07/10] Replace TryFrom with TryInto --- src/i2c.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/i2c.rs b/src/i2c.rs index 6cd493e9e..b8e0b4e87 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -4,7 +4,7 @@ //! //! [examples/i2c_scanner.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/i2c_scanner.rs -use core::convert::{TryFrom, TryFrom}; +use core::convert::{TryFrom, TryInto}; use core::ops::Deref; use crate::{ From c6bd1ce6fc6a5455ae0cf9064bfdd49918f57143 Mon Sep 17 00:00:00 2001 From: wbuck Date: Tue, 9 Mar 2021 10:58:41 -0500 Subject: [PATCH 08/10] Take concrete Hertz type - Remove generic TryFrom constraint on functions taking a Rate type - Make all functions taking a Rate type take the Hertz type instead --- examples/can.rs | 12 ++++------ examples/pwm.rs | 2 +- examples/spi.rs | 9 +++----- examples/usb_serial.rs | 12 ++++------ src/rcc.rs | 49 +++++++++++++-------------------------- src/timer.rs | 2 +- tests/rcc.rs | 52 +++++++++++++++--------------------------- 7 files changed, 47 insertions(+), 91 deletions(-) diff --git a/examples/can.rs b/examples/can.rs index 98544c188..ca2d6bdb9 100644 --- a/examples/can.rs +++ b/examples/can.rs @@ -32,14 +32,10 @@ fn main() -> ! { let _clocks = rcc .cfgr - .use_hse(32u32.MHz()) - .unwrap() - .sysclk(32u32.MHz()) - .unwrap() - .pclk1(16u32.MHz()) - .unwrap() - .pclk2(16u32.MHz()) - .unwrap() + .use_hse(Hertz(32_000_000)) + .sysclk(Hertz(32_000_000)) + .pclk1(Hertz(16_000_000)) + .pclk2(Hertz(16_000_000)) .freeze(&mut flash.acr); // Configure CAN RX and TX pins (AF9) diff --git a/examples/pwm.rs b/examples/pwm.rs index 375038d26..7d3eb925d 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -28,7 +28,7 @@ fn main() -> ! { // Configure our clocks let mut flash = dp.FLASH.constrain(); let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(16u32.MHz()).unwrap().freeze(&mut flash.acr); + let clocks = rcc.cfgr.sysclk(Hertz(16_000_000)).freeze(&mut flash.acr); // Prep the pins we need in their correct alternate function let mut gpioa = dp.GPIOA.split(&mut rcc.ahb); diff --git a/examples/spi.rs b/examples/spi.rs index 0c93d9eb2..8d890824d 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -25,12 +25,9 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .sysclk(48u32.MHz()) - .unwrap() - .pclk1(24u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .sysclk(Hertz(48_000_000)) + .pclk1(Hertz(24_000_000)) .freeze(&mut flash.acr); // Configure pins for SPI diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index 7624f54c9..267ba256d 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -27,14 +27,10 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .sysclk(48u32.MHz()) - .unwrap() - .pclk1(24u32.MHz()) - .unwrap() - .pclk2(24u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .sysclk(Hertz(48_000_000)) + .pclk1(Hertz(24_000_000)) + .pclk2(Hertz(24_000_000)) .freeze(&mut flash.acr); assert!(clocks.usbclk_valid()); diff --git a/src/rcc.rs b/src/rcc.rs index 92b1365b2..1a50209b2 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -54,15 +54,13 @@ //! For more details read the documentation of the [`CFGR`] methods to //! find out how to setup the clock. -use core::convert::TryInto; - use crate::pac::{ rcc::{self, cfgr, cfgr2}, RCC, }; use crate::flash::ACR; -use crate::time::rate::{Hertz, Rate}; +use crate::time::rate::Hertz; /// Extension trait that constrains the `RCC` peripheral pub trait RccExt { @@ -335,12 +333,9 @@ impl CFGR { /// /// Will result in a hang if an external oscillator is not connected or it fails to start, /// unless [css](CFGR::enable_css) is enabled. - pub fn use_hse(mut self, freq: F) -> Result>>::Error> - where - F: Rate + TryInto>, - { - self.hse = Some((freq.try_into()? as Hertz).0); - Ok(self) + pub fn use_hse(mut self, freq: Hertz) -> Self { + self.hse = Some(freq.0); + self } /// Enable `HSE` bypass. @@ -366,12 +361,9 @@ impl CFGR { } /// Sets a frequency for the AHB bus - pub fn hclk(mut self, freq: F) -> Result>>::Error> - where - F: Rate + TryInto>, - { - self.hclk = Some((freq.try_into()? as Hertz).0); - Ok(self) + pub fn hclk(mut self, freq: Hertz) -> Self { + self.hclk = Some(freq.0); + self } /// Sets a frequency for the `APB1` bus @@ -380,12 +372,9 @@ impl CFGR { /// /// If not manually set, it will be set to [`CFGR::sysclk`] frequency /// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz - pub fn pclk1(mut self, freq: F) -> Result>>::Error> - where - F: Rate + TryInto>, - { - self.pclk1 = Some((freq.try_into()? as Hertz).0); - Ok(self) + pub fn pclk1(mut self, freq: Hertz) -> Self { + self.pclk1 = Some(freq.0); + self } /// Sets a frequency for the `APB2` bus @@ -401,12 +390,9 @@ impl CFGR { /// /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] /// - pub fn pclk2(mut self, freq: F) -> Result>>::Error> - where - F: Rate + TryInto>, - { - self.pclk2 = Some((freq.try_into()? as Hertz).0); - Ok(self) + pub fn pclk2(mut self, freq: Hertz) -> Self { + self.pclk2 = Some(freq.0); + self } /// Sets the system (core) frequency @@ -424,12 +410,9 @@ impl CFGR { /// even when using the internal oscillator: /// /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] - pub fn sysclk(mut self, freq: F) -> Result>>::Error> - where - F: Rate + TryInto>, - { - self.sysclk = Some((freq.try_into()? as Hertz).0); - Ok(self) + pub fn sysclk(mut self, freq: Hertz) -> Self { + self.sysclk = Some(freq.0); + self } /// Calculate the values for the pll multiplier (`PLLMUL`) and the pll divisior (`PLLDIV`). diff --git a/src/timer.rs b/src/timer.rs index ee223e156..cf610d8fd 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -91,7 +91,7 @@ macro_rules! hal { fn start(&mut self, timeout: T) where - T: Into, + T: Into, { self.stop(); diff --git a/tests/rcc.rs b/tests/rcc.rs index f2d7d0663..76ed5d31c 100644 --- a/tests/rcc.rs +++ b/tests/rcc.rs @@ -37,10 +37,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .sysclk(15u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .sysclk(Hertz(15_000_000)) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 15u32.MHz()); @@ -66,7 +64,7 @@ mod tests { feature = "stm32f303xe", feature = "stm32f398", ))] { - let clock = rcc.cfgr.sysclk(72u32.MHz()).unwrap().freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(Hertz(72_000_000)).freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); defmt::assert!(clock.hclk() == 72u32.MHz()); @@ -80,7 +78,7 @@ mod tests { // and the resolution is therefor lower. // Because of the implementation the clock is then approximated to // the highest possible value (64 Mhz). - let clock = rcc.cfgr.sysclk(67u32.MHz()).unwrap().freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(Hertz(67_000_000)).freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); defmt::assert!(clock.hclk() == 64u32.MHz()); @@ -102,10 +100,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .sysclk(32u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .sysclk(Hertz(32_000_000)) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 32u32.MHz()); @@ -126,10 +122,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .sysclk(48u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .sysclk(Hertz(48_000_000)) .freeze(&mut flash.acr); // works defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -148,16 +142,11 @@ mod tests { let clock = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .hclk(48u32.MHz()) - .unwrap() - .sysclk(48u32.MHz()) - .unwrap() - .pclk1(12u32.MHz()) - .unwrap() - .pclk2(12u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .hclk(Hertz(48_000_000)) + .sysclk(Hertz(48_000_000)) + .pclk1(Hertz(12_000_000)) + .pclk2(Hertz(12_000_000)) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -177,12 +166,9 @@ mod tests { let clock = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .pclk1(16u32.MHz()) - .unwrap() - .sysclk(64u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .pclk1(Hertz(16_000_000)) + .sysclk(Hertz(64_000_000)) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); @@ -203,10 +189,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(8u32.MHz()) - .unwrap() - .sysclk(72u32.MHz()) - .unwrap() + .use_hse(Hertz(8_000_000)) + .sysclk(Hertz(72_000_000)) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); From e32b3f32e3f733e76b2d5bd086a9d36937d55e37 Mon Sep 17 00:00:00 2001 From: wbuck Date: Wed, 10 Mar 2021 10:30:54 -0500 Subject: [PATCH 09/10] Change rcc API to take frequencies in MHz --- CHANGELOG.md | 27 +++++++++++++++++++++ examples/can.rs | 8 +++--- examples/i2c_scanner.rs | 10 ++++++-- examples/pwm.rs | 2 +- examples/spi.rs | 13 +++++----- examples/usb_serial.rs | 8 +++--- src/i2c.rs | 25 ++++++------------- src/rcc.rs | 54 +++++++++++++++++++++++++++++++---------- src/spi.rs | 22 ++++++----------- tests/rcc.rs | 36 +++++++++++++-------------- 10 files changed, 125 insertions(+), 80 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3999c31e7..d5c7ed624 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,32 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +## [v0.7.0] - 2021-03-10 + +### Added + +- Replace custom time based units with types defined in the [embedded-time][] crate ([#191]) + +### Breaking changes + +- The `rcc` public API now expects time based units in `Megahertz`. + If the supplied frequency cannot be converted to `Hertz` the code + will `panic`. This will occur if the supplied `Megahertz` frequency + cannot fit into `u32::MAX` when converting to `Hertz` + +```rust +// The supplied frequencies must be in `MHz`. +let clocks = rcc + .cfgr + .use_hse(8u32.MHz()) + .hclk(48u32.MHz()) + .sysclk(48u32.MHz()) + .pclk1(12u32.MHz()) + .pclk2(12u32.MHz()) +``` + +[embedded-time]: https://github.com/FluenTech/embedded-time/ + ## [v0.6.1] - 2020-12-10 ### Changed @@ -262,6 +288,7 @@ let clocks = rcc - Support `stm32f303` device +[#192]: https://github.com/stm32-rs/stm32f3xx-hal/pull/192 [#184]: https://github.com/stm32-rs/stm32f3xx-hal/pull/184 [#172]: https://github.com/stm32-rs/stm32f3xx-hal/pull/172 [#170]: https://github.com/stm32-rs/stm32f3xx-hal/pull/170 diff --git a/examples/can.rs b/examples/can.rs index ca2d6bdb9..f7b86d493 100644 --- a/examples/can.rs +++ b/examples/can.rs @@ -32,10 +32,10 @@ fn main() -> ! { let _clocks = rcc .cfgr - .use_hse(Hertz(32_000_000)) - .sysclk(Hertz(32_000_000)) - .pclk1(Hertz(16_000_000)) - .pclk2(Hertz(16_000_000)) + .use_hse(32u32.MHz()) + .sysclk(32u32.MHz()) + .pclk1(16u32.MHz()) + .pclk2(16u32.MHz()) .freeze(&mut flash.acr); // Configure CAN RX and TX pins (AF9) diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index d432cad8b..18d615e3b 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -6,7 +6,7 @@ #![no_std] #![no_main] -use core::ops::Range; +use core::{convert::TryInto, ops::Range}; use panic_semihosting as _; @@ -35,7 +35,13 @@ fn main() -> ! { gpiob.pb7.into_af4(&mut gpiob.moder, &mut gpiob.afrl), // SDA ); - let mut i2c = hal::i2c::I2c::new(dp.I2C1, pins, 100u32.kHz(), clocks, &mut rcc.apb1).unwrap(); + let mut i2c = hal::i2c::I2c::new( + dp.I2C1, + pins, + 100_000u32.kHz().try_into().unwrap(), + clocks, + &mut rcc.apb1, + ); hprintln!("Start i2c scanning...").expect("Error using hprintln."); hprintln!().unwrap(); diff --git a/examples/pwm.rs b/examples/pwm.rs index 7d3eb925d..1fb8ff4a9 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -28,7 +28,7 @@ fn main() -> ! { // Configure our clocks let mut flash = dp.FLASH.constrain(); let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(Hertz(16_000_000)).freeze(&mut flash.acr); + let clocks = rcc.cfgr.sysclk(16u32.MHz()).freeze(&mut flash.acr); // Prep the pins we need in their correct alternate function let mut gpioa = dp.GPIOA.split(&mut rcc.ahb); diff --git a/examples/spi.rs b/examples/spi.rs index 8d890824d..49aa3c6a9 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -3,6 +3,8 @@ #![no_std] #![no_main] +use core::convert::TryInto; + use panic_semihosting as _; use stm32f3xx_hal as hal; @@ -25,9 +27,9 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .sysclk(Hertz(48_000_000)) - .pclk1(Hertz(24_000_000)) + .use_hse(8u32.MHz()) + .sysclk(48u32.MHz()) + .pclk1(24u32.MHz()) .freeze(&mut flash.acr); // Configure pins for SPI @@ -44,11 +46,10 @@ fn main() -> ! { dp.SPI1, (sck, miso, mosi), spi_mode, - 3u32.MHz(), + 3u32.MHz().try_into().unwrap(), clocks, &mut rcc.apb2, - ) - .unwrap(); + ); // Create an `u8` array, which can be transfered via SPI. let msg_send: [u8; 8] = [0xD, 0xE, 0xA, 0xD, 0xB, 0xE, 0xE, 0xF]; diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index 267ba256d..8c754d5de 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -27,10 +27,10 @@ fn main() -> ! { let clocks = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .sysclk(Hertz(48_000_000)) - .pclk1(Hertz(24_000_000)) - .pclk2(Hertz(24_000_000)) + .use_hse(8u32.MHz()) + .sysclk(48u32.MHz()) + .pclk1(24u32.MHz()) + .pclk2(24u32.MHz()) .freeze(&mut flash.acr); assert!(clocks.usbclk_valid()); diff --git a/src/i2c.rs b/src/i2c.rs index b8e0b4e87..95d6572e9 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -4,7 +4,7 @@ //! //! [examples/i2c_scanner.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/i2c_scanner.rs -use core::convert::{TryFrom, TryInto}; +use core::convert::TryFrom; use core::ops::Deref; use crate::{ @@ -12,7 +12,7 @@ use crate::{ hal::blocking::i2c::{Read, Write, WriteRead}, pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC}, rcc::{Clocks, APB1}, - time::rate::{Hertz, Rate}, + time::rate::Hertz, }; #[cfg(not(feature = "gpio-f333"))] @@ -111,22 +111,13 @@ macro_rules! busy_wait { impl I2c { /// Configures the I2C peripheral to work in master mode - pub fn new( - i2c: I2C, - pins: (SCL, SDA), - freq: F, - clocks: Clocks, - apb1: &mut APB1, - ) -> Result>>::Error> + pub fn new(i2c: I2C, pins: (SCL, SDA), freq: Hertz, clocks: Clocks, apb1: &mut APB1) -> Self where I2C: Instance, SCL: SclPin, SDA: SdaPin, - F: Rate + TryInto>, { - let freq = (freq.try_into()? as Hertz).0; - - crate::assert!(freq <= 1_000_000); + crate::assert!(freq.0 <= 1_000_000); I2C::enable_clock(apb1); @@ -139,8 +130,8 @@ impl I2c { // t_SYNC1 + t_SYNC2 > 4 * t_I2CCLK // t_SCL ~= t_SYNC1 + t_SYNC2 + t_SCLL + t_SCLH let i2cclk = I2C::clock(&clocks).0; - let ratio = i2cclk / freq - 4; - let (presc, scll, sclh, sdadel, scldel) = if freq >= 100_000 { + let ratio = i2cclk / freq.0 - 4; + let (presc, scll, sclh, sdadel, scldel) = if freq.0 >= 100_000 { // fast-mode or fast-mode plus // here we pick SCLL + 1 = 2 * (SCLH + 1) let presc = ratio / 387; @@ -148,7 +139,7 @@ impl I2c { let sclh = ((ratio / (presc + 1)) - 3) / 3; let scll = 2 * (sclh + 1) - 1; - let (sdadel, scldel) = if freq > 400_000 { + let (sdadel, scldel) = if freq.0 > 400_000 { // fast-mode plus let sdadel = 0; let scldel = i2cclk / 4_000_000 / (presc + 1) - 1; @@ -201,7 +192,7 @@ impl I2c { // Enable the peripheral i2c.cr1.modify(|_, w| w.pe().set_bit()); - Ok(Self { i2c, pins }) + Self { i2c, pins } } /// Releases the I2C peripheral and associated pins diff --git a/src/rcc.rs b/src/rcc.rs index 1a50209b2..4456ff4d5 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -9,6 +9,8 @@ //! ``` //! # use cortex_m_rt::entry; //! # use stm32f3xx_hal::prelude::*; +//! #use hal::time::rate::*; +//! //! # #[entry] //! # fn main() -> ! { //! // Get our peripherals @@ -33,18 +35,18 @@ //! let clocks = rcc.cfgr //! // Using the external oscillator //! // Set the frequency to that of the external oscillator -//! .use_hse(8.mhz()) +//! .use_hse(8.MHz()) //! // Set the frequency for the AHB bus, //! // which the root of every following clock peripheral -//! .hclk(48.mhz()) +//! .hclk(48.MHz()) //! // The sysclk is equivalent to the core clock -//! .sysclk(48.mhz()) +//! .sysclk(48.MHz()) //! // The following are peripheral clocks, which are both //! // needed to configure specific peripherals. //! // Looking at the peripheral function parameters //! // should give more insight, which peripheral clock is needed. -//! .pclk1(12.mhz()) -//! .pclk2(12.mhz()) +//! .pclk1(12.MHz()) +//! .pclk2(12.MHz()) //! // Freeze / apply the configuration and setup all clocks //! .freeze(&mut flash.acr); //! # } @@ -59,8 +61,10 @@ use crate::pac::{ RCC, }; +use core::convert::TryInto; + use crate::flash::ACR; -use crate::time::rate::Hertz; +use crate::time::rate::*; /// Extension trait that constrains the `RCC` peripheral pub trait RccExt { @@ -333,7 +337,12 @@ impl CFGR { /// /// Will result in a hang if an external oscillator is not connected or it fails to start, /// unless [css](CFGR::enable_css) is enabled. - pub fn use_hse(mut self, freq: Hertz) -> Self { + /// + /// # Panics + /// + /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. + pub fn use_hse(mut self, freq: Megahertz) -> Self { + let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); self.hse = Some(freq.0); self } @@ -360,8 +369,13 @@ impl CFGR { self } - /// Sets a frequency for the AHB bus - pub fn hclk(mut self, freq: Hertz) -> Self { + /// Sets a frequency for the AHB bus. + /// + /// # Panics + /// + /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. + pub fn hclk(mut self, freq: Megahertz) -> Self { + let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); self.hclk = Some(freq.0); self } @@ -372,7 +386,12 @@ impl CFGR { /// /// If not manually set, it will be set to [`CFGR::sysclk`] frequency /// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz - pub fn pclk1(mut self, freq: Hertz) -> Self { + /// + /// # Panics + /// + /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. + pub fn pclk1(mut self, freq: Megahertz) -> Self { + let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); self.pclk1 = Some(freq.0); self } @@ -390,7 +409,11 @@ impl CFGR { /// /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] /// - pub fn pclk2(mut self, freq: Hertz) -> Self { + /// # Panics + /// + /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. + pub fn pclk2(mut self, freq: Megahertz) -> Self { + let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); self.pclk2 = Some(freq.0); self } @@ -410,7 +433,12 @@ impl CFGR { /// even when using the internal oscillator: /// /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] - pub fn sysclk(mut self, freq: Hertz) -> Self { + /// + /// # Panics + /// + /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. + pub fn sysclk(mut self, freq: Megahertz) -> Self { + let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); self.sysclk = Some(freq.0); self } @@ -645,7 +673,7 @@ impl CFGR { // This ensures, that no panic happens, when // pclk1 is not manually set. - // As hclk highest value is 72.mhz() + // As hclk highest value is 72.MHz() // dividing by 2 should always be sufficient if self.pclk1.is_none() && pclk1 > 36_000_000 { ppre1_bits = cfgr::PPRE1_A::DIV2; diff --git a/src/spi.rs b/src/spi.rs index 4f10d8a92..297e07e0f 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -4,7 +4,7 @@ //! //! [examples/spi.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.0/examples/spi.rs -use core::{convert::TryInto, ptr}; +use core::ptr; use crate::hal::spi::FullDuplex; pub use crate::hal::spi::{Mode, Phase, Polarity}; @@ -131,7 +131,7 @@ use crate::rcc::APB1; feature = "stm32f398" ))] use crate::rcc::APB2; -use crate::time::rate::{Hertz, Rate}; +use crate::time::rate::Hertz; use core::marker::PhantomData; /// SPI error @@ -417,16 +417,15 @@ macro_rules! hal { $( impl Spi<$SPIX, (SCK, MISO, MOSI), WORD> { /// Configures the SPI peripheral to operate in full duplex master mode - pub fn $spiX( + pub fn $spiX( spi: $SPIX, pins: (SCK, MISO, MOSI), mode: Mode, - freq: F, + freq: Hertz, clocks: Clocks, apb2: &mut $APBX, - ) -> Result>>::Error> + ) -> Self where - F: Rate + TryInto>, SCK: SckPin<$SPIX>, MISO: MisoPin<$SPIX>, MOSI: MosiPin<$SPIX>, @@ -445,7 +444,6 @@ macro_rules! hal { w.ssoe().disabled() }); - let freq: Hertz = freq.try_into()?; // CPHA: phase // CPOL: polarity // MSTR: master mode @@ -485,7 +483,7 @@ macro_rules! hal { .unidirectional() }); - Ok(Spi { spi, pins, _word: PhantomData }) + Spi { spi, pins, _word: PhantomData } } /// Releases the SPI peripheral and associated pins @@ -494,19 +492,13 @@ macro_rules! hal { } /// Change the baud rate of the SPI - pub fn reclock(&mut self, freq: F, clocks: Clocks) - -> Result<(), >>::Error> - where - F: Rate + TryInto>, - { + pub fn reclock(&mut self, freq: Hertz, clocks: Clocks) { self.spi.cr1.modify(|_, w| w.spe().disabled()); - let freq: Hertz = freq.try_into()?; self.spi.cr1.modify(|_, w| { w.br().variant(Self::compute_baud_rate(clocks.$pclkX(), freq)); w.spe().enabled() }); - Ok(()) } fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> spi1::cr1::BR_A { diff --git a/tests/rcc.rs b/tests/rcc.rs index 76ed5d31c..68fe51f04 100644 --- a/tests/rcc.rs +++ b/tests/rcc.rs @@ -37,8 +37,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .sysclk(Hertz(15_000_000)) + .use_hse(8u32.MHz()) + .sysclk(15u32.MHz()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 15u32.MHz()); @@ -64,7 +64,7 @@ mod tests { feature = "stm32f303xe", feature = "stm32f398", ))] { - let clock = rcc.cfgr.sysclk(Hertz(72_000_000)).freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(72u32.MHz()).freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); defmt::assert!(clock.hclk() == 72u32.MHz()); @@ -78,7 +78,7 @@ mod tests { // and the resolution is therefor lower. // Because of the implementation the clock is then approximated to // the highest possible value (64 Mhz). - let clock = rcc.cfgr.sysclk(Hertz(67_000_000)).freeze(&mut flash.acr); + let clock = rcc.cfgr.sysclk(67u32.MHz()).freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); defmt::assert!(clock.hclk() == 64u32.MHz()); @@ -100,8 +100,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .sysclk(Hertz(32_000_000)) + .use_hse(8u32.MHz()) + .sysclk(32u32.MHz()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 32u32.MHz()); @@ -122,8 +122,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .sysclk(Hertz(48_000_000)) + .use_hse(8u32.MHz()) + .sysclk(48u32.MHz()) .freeze(&mut flash.acr); // works defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -142,11 +142,11 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .hclk(Hertz(48_000_000)) - .sysclk(Hertz(48_000_000)) - .pclk1(Hertz(12_000_000)) - .pclk2(Hertz(12_000_000)) + .use_hse(8u32.MHz()) + .hclk(48u32.MHz()) + .sysclk(48u32.MHz()) + .pclk1(12u32.MHz()) + .pclk2(12u32.MHz()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 48u32.MHz()); @@ -166,9 +166,9 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .pclk1(Hertz(16_000_000)) - .sysclk(Hertz(64_000_000)) + .use_hse(8u32.MHz()) + .pclk1(16u32.MHz()) + .sysclk(64u32.MHz()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 64u32.MHz()); @@ -189,8 +189,8 @@ mod tests { let clock = rcc .cfgr - .use_hse(Hertz(8_000_000)) - .sysclk(Hertz(72_000_000)) + .use_hse(8u32.MHz()) + .sysclk(72u32.MHz()) .freeze(&mut flash.acr); defmt::assert!(clock.sysclk() == 72u32.MHz()); From 5be98c14a5bfae850721c40f55341d07adb5e25e Mon Sep 17 00:00:00 2001 From: wbuck Date: Wed, 10 Mar 2021 16:21:18 -0500 Subject: [PATCH 10/10] Fix i2c_scanner example and use integer method for time types --- CHANGELOG.md | 2 +- examples/i2c_scanner.rs | 2 +- src/i2c.rs | 10 +++++----- src/pwm.rs | 24 ++++++++++++------------ src/rcc.rs | 16 ++++++++-------- src/serial.rs | 4 ++-- src/spi.rs | 4 ++-- src/timer.rs | 4 ++-- src/watchdog.rs | 4 ++-- 9 files changed, 35 insertions(+), 35 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 1dc345c54..3ce17f58b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,7 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added -- Replace custom time based units with types defined in the [embedded-time][] crate ([#191]) +- Replace custom time based units with types defined in the [embedded-time][] crate ([#192]) ### Breaking changes diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index 18d615e3b..a68cc4e4a 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -38,7 +38,7 @@ fn main() -> ! { let mut i2c = hal::i2c::I2c::new( dp.I2C1, pins, - 100_000u32.kHz().try_into().unwrap(), + 100u32.kHz().try_into().unwrap(), clocks, &mut rcc.apb1, ); diff --git a/src/i2c.rs b/src/i2c.rs index 81aec294b..8ecf8e370 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -12,7 +12,7 @@ use crate::{ hal::blocking::i2c::{Read, Write, WriteRead}, pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC}, rcc::{Clocks, APB1}, - time::rate::Hertz, + time::rate::*, }; #[cfg(not(feature = "gpio-f333"))] @@ -117,7 +117,7 @@ impl I2c { SCL: SclPin, SDA: SdaPin, { - crate::assert!(freq.0 <= 1_000_000); + crate::assert!(*freq.integer() <= 1_000_000); I2C::enable_clock(apb1); @@ -130,8 +130,8 @@ impl I2c { // t_SYNC1 + t_SYNC2 > 4 * t_I2CCLK // t_SCL ~= t_SYNC1 + t_SYNC2 + t_SCLL + t_SCLH let i2cclk = I2C::clock(&clocks).0; - let ratio = i2cclk / freq.0 - 4; - let (presc, scll, sclh, sdadel, scldel) = if freq.0 >= 100_000 { + let ratio = i2cclk / *freq.integer() - 4; + let (presc, scll, sclh, sdadel, scldel) = if *freq.integer() >= 100_000 { // fast-mode or fast-mode plus // here we pick SCLL + 1 = 2 * (SCLH + 1) let presc = ratio / 387; @@ -139,7 +139,7 @@ impl I2c { let sclh = ((ratio / (presc + 1)) - 3) / 3; let scll = 2 * (sclh + 1) - 1; - let (sdadel, scldel) = if freq.0 > 400_000 { + let (sdadel, scldel) = if *freq.integer() > 400_000 { // fast-mode plus let sdadel = 0; let scldel = i2cclk / 4_000_000 / (presc + 1) - 1; diff --git a/src/pwm.rs b/src/pwm.rs index 86f6cb1dc..759320eb4 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -16,7 +16,7 @@ ``` // (Other imports omitted) - use stm32f3xx-hal::pwm::tim3; + use stm32f3xx-hal::{pwm::tim3, time::rate::*}; let dp = stm32f303::Peripherals::take().unwrap(); @@ -25,9 +25,9 @@ let clocks = rcc.cfgr.freeze(&mut flash.acr); // Set the resolution of our duty cycle to 9000 and our period to - // 50hz. + // 50Hz. let mut (c1_no_pins, _, _, c4_no_pins) = - tim3(device.TIM3, 9000, 50.hz(), clocks); + tim3(device.TIM3, 9000, 50.Hz(), clocks); ``` In this case, we're only going to use channel 1 and channel 4. @@ -65,7 +65,7 @@ ch4.enable(); ``` - All three pins will output a 50hz period. PA6 and PB4 will share a + All three pins will output a 50Hz period. PA6 and PB4 will share a duty cycle, but the duty cycle for PB1 can be controlled independently. @@ -84,7 +84,7 @@ ``` // (Other imports omitted) - use stm32f3xx-hal::pwm::tim16; + use stm32f3xx-hal::{pwm::tim16, time::rate::*}; let dp = stm32f303::Peripherals::take().unwrap(); @@ -93,8 +93,8 @@ let clocks = rcc.cfgr.freeze(&mut flash.acr); // Set the resolution of our duty cycle to 9000 and our period to - // 50hz. - let mut c1_no_pins = tim16(device.TIM3, 9000, 50.hz(), clocks); + // 50Hz. + let mut c1_no_pins = tim16(device.TIM3, 9000, 50.Hz(), clocks); ``` ## Complementary timers @@ -109,7 +109,7 @@ ``` // (Other imports omitted) - use stm32f3xx-hal::pwm::tim1; + use stm32f3xx-hal::{pwm::tim1, time::rate::*}; let dp = stm32f303::Peripherals::take().unwrap(); @@ -118,8 +118,8 @@ let clocks = rcc.cfgr.freeze(&mut flash.acr); // Set the resolution of our duty cycle to 9000 and our period to - // 50hz. - let mut (ch1_no_pins, _, _, _) = tim1(device.TIM3, 9000, 50.hz(), clocks); + // 50Hz. + let mut (ch1_no_pins, _, _, _) = tim1(device.TIM3, 9000, 50.Hz(), clocks); let mut gpioa = dp.GPIOB.split(&mut rcc.ahb); let pa7 = gpioa.pa7.into_af6(&mut gpioa.moder, &mut gpioa.afrl); @@ -160,7 +160,7 @@ use crate::{ hal::PwmPin, pac::{RCC, TIM15, TIM16, TIM17, TIM2}, rcc::Clocks, - time::rate::Hertz, + time::rate::*, }; use core::marker::PhantomData; @@ -282,7 +282,7 @@ macro_rules! pwm_timer_private { // It might make sense to move into the clocks as a crate-only property. // TODO: ppre1 is used in timer.rs (never ppre2), should this be dynamic? let clock_freq = clocks.$pclkz().0 * if clocks.ppre1() == 1 { 1 } else { 2 }; - let prescale_factor = clock_freq / res as u32 / freq.0; + let prescale_factor = clock_freq / res as u32 / *freq.integer(); // NOTE(write): uses all bits of this register. tim.psc.write(|w| w.psc().bits(prescale_factor as u16 - 1)); diff --git a/src/rcc.rs b/src/rcc.rs index 4456ff4d5..e1683e346 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -8,8 +8,7 @@ //! //! ``` //! # use cortex_m_rt::entry; -//! # use stm32f3xx_hal::prelude::*; -//! #use hal::time::rate::*; +//! # use stm32f3xx-hal::{prelude::*, time::rate::*}; //! //! # #[entry] //! # fn main() -> ! { @@ -25,7 +24,8 @@ //! //! ``` //! # use cortex_m_rt::entry; -//! # use stm32f3xx_hal::prelude::*; +//! # use stm32f3xx-hal::{prelude::*, time::rate::*}; +//! # //! # #[entry] //! # fn main() -> ! { //! # let dp = pac::Peripherals::take().unwrap(); @@ -343,7 +343,7 @@ impl CFGR { /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. pub fn use_hse(mut self, freq: Megahertz) -> Self { let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); - self.hse = Some(freq.0); + self.hse = Some(*freq.integer()); self } @@ -376,7 +376,7 @@ impl CFGR { /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. pub fn hclk(mut self, freq: Megahertz) -> Self { let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); - self.hclk = Some(freq.0); + self.hclk = Some(*freq.integer()); self } @@ -392,7 +392,7 @@ impl CFGR { /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. pub fn pclk1(mut self, freq: Megahertz) -> Self { let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); - self.pclk1 = Some(freq.0); + self.pclk1 = Some(*freq.integer()); self } @@ -414,7 +414,7 @@ impl CFGR { /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. pub fn pclk2(mut self, freq: Megahertz) -> Self { let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); - self.pclk2 = Some(freq.0); + self.pclk2 = Some(*freq.integer()); self } @@ -439,7 +439,7 @@ impl CFGR { /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`. pub fn sysclk(mut self, freq: Megahertz) -> Self { let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError"); - self.sysclk = Some(freq.0); + self.sysclk = Some(*freq.integer()); self } diff --git a/src/serial.rs b/src/serial.rs index 7aac6e51a..26f1ef7fc 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -5,7 +5,7 @@ use crate::{ hal::{blocking, serial}, pac::{USART1, USART2, USART3}, rcc::{Clocks, APB1, APB2}, - time::rate::Baud, + time::rate::*, }; use cfg_if::cfg_if; @@ -125,7 +125,7 @@ macro_rules! hal { apb.rstr().modify(|_, w| w.$usartXrst().set_bit()); apb.rstr().modify(|_, w| w.$usartXrst().clear_bit()); - let brr = clocks.$pclkX().0 / baud_rate.0; + let brr = clocks.$pclkX().0 / *baud_rate.integer(); crate::assert!(brr >= 16, "impossible baud rate"); // NOTE(write): uses all bits of this register. usart.brr.write(|w| unsafe { w.bits(brr) }); diff --git a/src/spi.rs b/src/spi.rs index 297e07e0f..aaca21646 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -131,7 +131,7 @@ use crate::rcc::APB1; feature = "stm32f398" ))] use crate::rcc::APB2; -use crate::time::rate::Hertz; +use crate::time::rate::*; use core::marker::PhantomData; /// SPI error @@ -503,7 +503,7 @@ macro_rules! hal { fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> spi1::cr1::BR_A { use spi1::cr1::BR_A; - match clocks.0 / freq.0 { + match clocks.0 / *freq.integer() { 0 => crate::unreachable!(), 1..=2 => BR_A::DIV2, 3..=5 => BR_A::DIV4, diff --git a/src/timer.rs b/src/timer.rs index cf610d8fd..96e61450d 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -51,7 +51,7 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6}; ))] use crate::pac::{TIM3, TIM7}; use crate::rcc::{Clocks, APB1, APB2}; -use crate::time::rate::Hertz; +use crate::time::rate::*; use void::Void; /// Associated clocks with timers @@ -95,7 +95,7 @@ macro_rules! hal { { self.stop(); - let frequency = timeout.into().0; + let frequency = *timeout.into().integer(); let timer_clock = $TIMX::get_clk(&self.clocks); let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 } / frequency; diff --git a/src/watchdog.rs b/src/watchdog.rs index cf084af72..d62e8e469 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -7,7 +7,7 @@ use crate::hal::watchdog::{Watchdog, WatchdogEnable}; use crate::pac::{DBGMCU, IWDG}; -use crate::time::duration::Milliseconds; +use crate::time::duration::*; const LSI_KHZ: u32 = 40; const MAX_PR: u8 = 8; @@ -96,7 +96,7 @@ impl WatchdogEnable for IndependentWatchDog { type Time = Milliseconds; fn start>(&mut self, period: T) { - self.setup(period.into().0); + self.setup(*period.into().integer()); self.iwdg.kr.write(|w| w.key().start()); }