From d05347080c9230cb79cd79e7a2d4b1499b8e10d0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 6 Jan 2023 01:39:40 +0100 Subject: [PATCH] Minor corrections for G0/L0/WB/WL-series - Minor fixes for G0-series from #1293 - [doc] Added core-IDs for WB/WL-series - [doc] Correction for G0/L0-series core-IDs --- config/chips/G05x_G06x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- inc/stm32.h | 14 +++++++++----- src/stlink-lib/common.c | 3 +-- 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index ae074e584..d136dca8e 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -6,7 +6,7 @@ chip_id 0x456 // STM32_CHIPID_G0_CAT4 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x4800 // 18 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index f21fd65a0..fa4f1d0c8 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -6,7 +6,7 @@ chip_id 0x467 // STM32_CHIPID_G0_CAT3 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x24000 // 144 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE diff --git a/inc/stm32.h b/inc/stm32.h index 8557c9ce7..79bda425d 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -10,8 +10,8 @@ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0444 Section 40.5.5) G0 SW-DP + // (RM0377 Section 27.5.3) L0 SW-DP STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP @@ -29,9 +29,13 @@ enum stm32_core_id { STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG // (RM0090 Section 47.6.3) G4 JTAG STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + // (RM0473 Section 33.4.4) WB SW-DP + // (RM0453 Section 38.4.1) WL SW-DP STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG + // (RM0473 Section 33.4.1) WB JTAG + // (RM0453 Section 38.3.8) WL JTAG STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP // (RM0456 Section 65.3.3) U5 SW-DP STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP @@ -106,13 +110,13 @@ enum stm32_chipids { STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L011 = 0x457, STM32_CHIPID_F410 = 0x458, - STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, STM32_CHIPID_L45x_L46x = 0x462, STM32_CHIPID_F413 = 0x463, STM32_CHIPID_L41x_L42x = 0x464, - STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G0_CAT1 = 0x466, /* G03x/G04x */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0Bx/G0Cx */ STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index cb037fb2f..f3cc0e2a2 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -279,8 +279,7 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; }