From 9acf0744a1a23fe3790d82bf2da8c3009257c54a Mon Sep 17 00:00:00 2001 From: Neetha John Date: Fri, 6 Aug 2021 10:36:10 -0700 Subject: [PATCH] Revert "Revert "Update default cable len to 0m for TD2"" (#8354) * Update default cable len to 0m for TD2 (#8298) * Update sonic-cfggen tests with the correct cable len Signed-off-by: Neetha John As part of the buffer reclamation efforts for TD2, setting the default cable len to 0m which means unused ports will have a cable len of 0m. Why I did it To align with the changes in Azure/sonic-swss#1830 How to verify it - With the default cable len set to 0m and the associated changes in swss, CABLE_LENGTH table had '0m' set for unused ports and accordingly more space was reserved for the shared pool - Cfggen tests passed with the cable len update --- .../Arista-7050-QX32/buffers_defaults_t0.j2 | 2 +- .../Arista-7050-QX32/buffers_defaults_t1.j2 | 2 +- .../Arista-7050QX-32S-S4Q31/buffers_defaults_t0.j2 | 2 +- .../Arista-7050QX-32S-S4Q31/buffers_defaults_t1.j2 | 2 +- .../Arista-7050QX32S-Q32/buffers_defaults_t0.j2 | 2 +- .../Arista-7050QX32S-Q32/buffers_defaults_t1.j2 | 2 +- .../Force10-S6000/buffers_defaults_def.j2 | 2 +- .../Force10-S6000/buffers_defaults_t0.j2 | 2 +- .../Force10-S6000/buffers_defaults_t1.j2 | 2 +- src/sonic-config-engine/tests/test_multinpu_cfggen.py | 4 ++-- 10 files changed, 11 insertions(+), 11 deletions(-) diff --git a/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t0.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t0.j2 +++ b/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t0.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t1.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t1.j2 +++ b/device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/buffers_defaults_t1.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t0.j2 index d93aa34893d6..3c0a68f1da88 100644 --- a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t0.j2 +++ b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t0.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t1.j2 index d93aa34893d6..3c0a68f1da88 100644 --- a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t1.j2 +++ b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/buffers_defaults_t1.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t0.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t0.j2 +++ b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t0.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t1.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t1.j2 +++ b/device/arista/x86_64-arista_7050_qx32s/Arista-7050QX32S-Q32/buffers_defaults_t1.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_def.j2 b/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_def.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_def.j2 +++ b/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_def.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t0.j2 b/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t0.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t0.j2 +++ b/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t0.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t1.j2 b/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t1.j2 index 38e34eb571e8..dc04b2265f33 100644 --- a/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t1.j2 +++ b/device/dell/x86_64-dell_s6000_s1220-r0/Force10-S6000/buffers_defaults_t1.j2 @@ -1,4 +1,4 @@ -{%- set default_cable = '300m' %} +{%- set default_cable = '0m' %} {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} diff --git a/src/sonic-config-engine/tests/test_multinpu_cfggen.py b/src/sonic-config-engine/tests/test_multinpu_cfggen.py index 1a91772092ab..8a79be743848 100644 --- a/src/sonic-config-engine/tests/test_multinpu_cfggen.py +++ b/src/sonic-config-engine/tests/test_multinpu_cfggen.py @@ -407,14 +407,14 @@ def test_buffers_multi_asic_template(self): output['CABLE_LENGTH'], { 'AZURE': { - 'Ethernet8': '300m', + 'Ethernet8': '0m', 'Ethernet0': '300m', 'Ethernet4': '300m', 'Ethernet-BP4': '5m', 'Ethernet-BP0': '5m', 'Ethernet-BP12': '5m', 'Ethernet-BP8': '5m', - 'Ethernet12': '300m' + 'Ethernet12': '0m' } } )