From edaac023104f697c73263d1f060fe0053401e803 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Tue, 5 Nov 2024 18:10:12 -0800 Subject: [PATCH] using gpuAsyncCore from AxiePcieReg --- firmware/python/DrpTDetGpu/_DevKcu1500.py | 7 +------ firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd | 2 +- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/firmware/python/DrpTDetGpu/_DevKcu1500.py b/firmware/python/DrpTDetGpu/_DevKcu1500.py index 2120e5c..59ba31d 100644 --- a/firmware/python/DrpTDetGpu/_DevKcu1500.py +++ b/firmware/python/DrpTDetGpu/_DevKcu1500.py @@ -25,6 +25,7 @@ def __init__(self, self.add(pcie.AxiPcieCore( useSpi=True, + useGpu=True, offset = 0x0000_0000, numDmaLanes = numDmaLanes, expand = False, @@ -58,12 +59,6 @@ def __init__(self, expand = False, )) - self.add(pcie.AxiGpuAsyncCore( - name = 'AxiGpuAsyncCore', - offset = 0x00D0_0000, - expand = False, - )) - self.add(drp.I2CBus( name = 'I2CBus', offset = 0x00E0_0000, diff --git a/firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd b/firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd index 958ab28..9329e28 100644 --- a/firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd +++ b/firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd @@ -166,7 +166,7 @@ architecture top_level of DrpTDetGpu is constant I2C_INDEX_C : integer := 3; constant CORE_I2C_C : boolean := false; - constant NUM_AXIL0_MASTERS_C : integer := ite(CORE_I2C_C, 4, 5); + constant NUM_AXIL0_MASTERS_C : integer := ite(CORE_I2C_C, 3, 4); signal mAxil0ReadMasters : AxiLiteReadMasterArray (NUM_AXIL0_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); signal mAxil0ReadSlaves : AxiLiteReadSlaveArray (NUM_AXIL0_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_OK_C); signal mAxil0WriteMasters : AxiLiteWriteMasterArray(NUM_AXIL0_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C);