From 518bfc587c86891c16018ffe8b4d5d5971a721ae Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Mon, 6 Jan 2020 15:30:01 -0800 Subject: [PATCH] Fix SPI polarity/phase and chip select Signed-off-by: Nathaniel Graff --- src/drivers/sifive_spi0.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/sifive_spi0.c b/src/drivers/sifive_spi0.c index d4a503a2..34f8e0a5 100644 --- a/src/drivers/sifive_spi0.c +++ b/src/drivers/sifive_spi0.c @@ -82,19 +82,19 @@ static int configure_spi(struct __metal_driver_sifive_spi0 *spi, /* Set Polarity */ if (config->polarity) { METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) |= - (1 << METAL_SPI_SCKMODE_PHA_SHIFT); + (1 << METAL_SPI_SCKMODE_POL_SHIFT); } else { METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) &= - ~(1 << METAL_SPI_SCKMODE_PHA_SHIFT); + ~(1 << METAL_SPI_SCKMODE_POL_SHIFT); } /* Set Phase */ if (config->phase) { METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) |= - (1 << METAL_SPI_SCKMODE_POL_SHIFT); + (1 << METAL_SPI_SCKMODE_PHA_SHIFT); } else { METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) &= - ~(1 << METAL_SPI_SCKMODE_POL_SHIFT); + ~(1 << METAL_SPI_SCKMODE_PHA_SHIFT); } /* Set Endianness */ @@ -123,7 +123,7 @@ static int configure_spi(struct __metal_driver_sifive_spi0 *spi, } /* Set CS line */ - METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSID) = 1 << (config->csid); + METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSID) = config->csid; /* Toggle off memory-mapped SPI flash mode, toggle on programmable IO mode * It seems that with this line uncommented, the debugger cannot have access