From 73a67338e79e0e60bf24810367b3fe19df7f71ff Mon Sep 17 00:00:00 2001
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Date: Wed, 23 Oct 2019 15:36:10 -0700
Subject: [PATCH] Revert "Always clear feature disable register"

QEMU and Spike don't properly emulate this CSR and crash when we attempt
to clear it.

This reverts commit 0ba2ed26867a71f0c872bf4bd47db707c081d0a2.
---
 src/entry.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/entry.S b/src/entry.S
index a75d8c2f..b2107097 100644
--- a/src/entry.S
+++ b/src/entry.S
@@ -28,8 +28,11 @@ _enter:
      * the boot process. */
     la t0, early_trap_vector
     csrw mtvec, t0
-    /* Always clear the feature disable register for all cores series*/
+    /* enable chicken bit if core is bullet series*/
+    la t0, __metal_chicken_bit
+    beqz t0, 1f
     csrwi 0x7C1, 0
+1:
 
     /* There may be pre-initialization routines inside the MBI code that run in
      * C, so here we set up a C environment.  First we set up a stack pointer,