diff --git a/microsemi/common/tcl/libero.tcl b/microsemi/common/tcl/libero.tcl index a5158892..64ccb122 100644 --- a/microsemi/common/tcl/libero.tcl +++ b/microsemi/common/tcl/libero.tcl @@ -35,12 +35,12 @@ puts "FlashPro Express folder: $FPExpressDir" file mkdir $FPExpressDir ########################################### -set CoreJTAGDebugver {2.0.100} -set PF_DDR3ver {2.1.101} -set PF_DDR4ver {2.1.101} -set PF_CCCver {1.0.112} -set PF_INIT_MONITORver {2.0.101} -set PF_CORERESETPFver {2.0.112} +set CoreJTAGDebugver {3.0.100} +set PF_DDR3ver {2.3.201} +set PF_DDR4ver {2.3.201} +set PF_CCCver {1.0.115} +set PF_INIT_MONITORver {2.0.103} +set PF_CORERESETPFver {2.1.100} set PF_PCIEver {1.0.230} set PF_XCVR_REF_CLKver {1.0.103} set PF_TX_PLLver {1.0.109} @@ -87,22 +87,34 @@ set HDL {VERILOG} set Block 0 set SAPI 0 set vmflow 1 -set synth 1 +set synth 1 set fanout {10} #########ORIGINAl SETTINGS############# -new_project -ondemand_build_dh 1 -location "$Proj" -name "$Prjname" -project_description {} -block_mode $Block -standalone_peripheral_initialization $SAPI -use_enhanced_constraint_flow $use_enhanced_constraint_flow -hdl $HDL -family $family -die $die -package $package -speed $speed -die_voltage $die_voltage -part_range $part_range -adv_options IO_DEFT_STD:$IOTech -adv_options RESTRICTPROBEPINS:$ResProbe -adv_options RESTRICTSPIPINS:$ResSPI -adv_options TEMPR:$TEMPR -adv_options VCCI_1.2_VOLTR:$IOVOLTR_12 -adv_options VCCI_1.5_VOLTR:$IOVOLTR_15 -adv_options VCCI_1.8_VOLTR:$IOVOLTR_18 -adv_options VCCI_2.5_VOLTR:$IOVOLTR_25 -adv_options VCCI_3.3_VOLTR:$IOVOLTR_33 -adv_options VOLTR:$VOLTR +if {"$chisel_board" == "polarfireevalkit"} then { + new_project -ondemand_build_dh 1 -location "$Proj" -name "$Prjname" -project_description {} -block_mode $Block -standalone_peripheral_initialization $SAPI -use_enhanced_constraint_flow $use_enhanced_constraint_flow -hdl $HDL -family $family -die $die -package $package -speed $speed -die_voltage $die_voltage -part_range $part_range -adv_options IO_DEFT_STD:$IOTech -adv_options RESTRICTPROBEPINS:$ResProbe -adv_options RESTRICTSPIPINS:$ResSPI -adv_options TEMPR:$TEMPR -adv_options VCCI_1.2_VOLTR:$IOVOLTR_12 -adv_options VCCI_1.5_VOLTR:$IOVOLTR_15 -adv_options VCCI_1.8_VOLTR:$IOVOLTR_18 -adv_options VCCI_2.5_VOLTR:$IOVOLTR_25 -adv_options VCCI_3.3_VOLTR:$IOVOLTR_33 -adv_options VOLTR:$VOLTR +} elseif {"$chisel_board" == "polarfireavalancheboard"} then { + new_project -location "$Proj" -name "$Prjname" -project_description {} -block_mode $Block -standalone_peripheral_initialization $SAPI -use_enhanced_constraint_flow $use_enhanced_constraint_flow -ondemand_build_dh 1 -hdl $HDL -family $family -die $die -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {IND} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:IND} -adv_options {UNUSED_MSS_IO_RESISTOR_PULL:None} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:IND} +} else { + puts "Target not supported by this script or no target selected." +} + # # Import Chisel generated verilog files into Libero project # import_files \ -convert_EDN_to_HDL 0 \ - -hdl_source "$chisel_build_dir/$chisel_project.$chisel_config.v" \ - -hdl_source "../../rocket-chip/src/main/resources/vsrc/AsyncResetReg.v" \ - -hdl_source "../../rocket-chip/src/main/resources/vsrc/plusarg_reader.v" + -hdl_source "$chisel_build_dir/$chisel_project.$chisel_config.v" + # -hdl_source "../../../rocket-chip/src/main/resources/vsrc/AsyncResetReg.v" \ + # -hdl_source "../../../rocket-chip/src/main/resources/vsrc/plusarg_reader.v" +import_files \ + -convert_EDN_to_HDL 0 \ + -library {work} \ + -hdl_source {../../../../rocket-chip/src/main/resources/vsrc/AsyncResetReg.v} \ + -hdl_source {../../../../rocket-chip/src/main/resources/vsrc/plusarg_reader.v} # # Execute all design entry scripts generated from Chisel flow. # @@ -117,40 +129,62 @@ foreach f $tclfiles { # Build design hierarchy and set project root to design's top level # build_design_hierarchy - -#set_root -module {U500PolarFireEvalKitFPGAChip::work} +if {"$chisel_board" == "polarfireevalkit"} then { + set_root -module {U500PolarFireEvalKitFPGAChip::work} +} elseif {"$chisel_board" == "polarfireavalancheboard"} then { + set_root -module {U500PolarFireAvalancheKitFPGAChip::work} +} set proj_root $chisel_model append proj_root "::work" puts "project root: $proj_root" set_root -module $proj_root # -# Import IO, Placement and timing constrainst +#Import IO, Placement and timing constrainst # + puts "-----------------------------------------------------------------" puts "------------------ Applying design constraints ------------------" puts "-----------------------------------------------------------------" import_files \ - -io_pdc ../../fpga-shells/microsemi/$chisel_board/constraints/pin_constraints.pdc - -import_files \ - -fp_pdc ../../fpga-shells/microsemi/$chisel_board/constraints/floor_plan.pdc - + -io_pdc "../../$chisel_board/constraints/pin_constraints.pdc" + import_files \ - -convert_EDN_to_HDL 0 \ - -sdc ../../fpga-shells/microsemi/$chisel_board/constraints/false_paths.sdc - -organize_tool_files -tool {PLACEROUTE} \ - -file $Proj/constraint/io/pin_constraints.pdc \ - -file $Proj/constraint/fp/floor_plan.pdc \ - -file $Proj/constraint/false_paths.sdc \ - -module $proj_root -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $Proj/constraint/false_paths.sdc \ - -module $proj_root -input_type {constraint} + -fp_pdc "../../$chisel_board/constraints/floor_plan.pdc" + +if {"$chisel_board" == "polarfireevalkit"} then { + # Evaluation kit + import_files \ + -convert_EDN_to_HDL 0 \ + -sdc "../../$chisel_board/constraints/false_paths.sdc" + + organize_tool_files -tool {PLACEROUTE} \ + -file $Proj/constraint/io/pin_constraints.pdc \ + -file $Proj/constraint/fp/floor_plan.pdc \ + -file $Proj/constraint/false_paths.sdc \ + -module $proj_root -input_type {constraint} +} elseif {"$chisel_board" == "polarfireavalancheboard"} then { + import_files \ + -convert_EDN_to_HDL 0 \ + -sdc "../../$chisel_board/constraints/clock_groups.sdc" + organize_tool_files -tool {SYNTHESIZE} \ + -file $Proj/constraint/clock_groups.sdc \ + -module $proj_root -input_type {constraint} + + organize_tool_files -tool {PLACEROUTE} \ + -file $Proj/constraint/io/pin_constraints.pdc \ + -file $Proj/constraint/fp/floor_plan.pdc \ + -file $Proj/constraint/clock_groups.sdc \ + -module $proj_root -input_type {constraint} + organize_tool_files -tool {VERIFYTIMING} \ + -file $Proj/constraint/clock_groups.sdc \ + -module $proj_root -input_type {constraint} +} + + + run_tool -name {CONSTRAINT_MANAGEMENT} derive_constraints_sdc @@ -182,12 +216,12 @@ run_tool -name {GENERATEPROGRAMMINGDATA} run_tool -name {GENERATEPROGRAMMINGFILE} -export_prog_job \ - -job_file_name $chisel_model \ - -export_dir $FPExpressDir \ - -bitstream_file_type {TRUSTED_FACILITY} \ - -bitstream_file_components {} - +#export_prog_job \ +# -job_file_name $chisel_model \ +# -export_dir $FPExpressDir \ +# -bitstream_file_type {TRUSTED_FACILITY} \ +# -bitstream_file_components {} +# #proc export_programming_job_g5 { name location components } { # export_prog_job \ diff --git a/microsemi/polarfireavalancheboard/constraints/clock_groups.sdc b/microsemi/polarfireavalancheboard/constraints/clock_groups.sdc new file mode 100644 index 00000000..95dfd2d1 --- /dev/null +++ b/microsemi/polarfireavalancheboard/constraints/clock_groups.sdc @@ -0,0 +1,8 @@ +set_clock_groups -name {Coreplex} -logically_exclusive -group [ get_clocks {hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT0 } ] +#set_clock_groups -name {PCIe_AXI} -logically_exclusive -group [ get_clocks { hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT1 } ] +set_clock_groups -name {DDR_subsystem_1} -logically_exclusive -group [ get_clocks { dut_/polarfireddrsubsys_1/island/blackbox/CCC_0/pll_inst_0/OUT1 } ] +set_clock_groups -name {DDR_subsystem_0} -logically_exclusive -group [ get_clocks { dut_/polarfireddrsubsys_1/island/blackbox/CCC_0/pll_inst_0/OUT0 } ] + + + + diff --git a/microsemi/polarfireavalancheboard/constraints/floor_plan.pdc b/microsemi/polarfireavalancheboard/constraints/floor_plan.pdc new file mode 100644 index 00000000..cc00ed4c --- /dev/null +++ b/microsemi/polarfireavalancheboard/constraints/floor_plan.pdc @@ -0,0 +1,34 @@ +# Microsemi Physical design constraints file + +# Version: v12.0 12.500.0.22 + +# Design Name: U500PolarFireAvalancheKitFPGAChip + +# Input Netlist Format: EDIF + +# Family: PolarFire , Die: MPF300T_ES , Package: FCG484 , Speed grade: STD + +# Date generated: Wed Mar 6 09:55:23 2019 + + +# +# Local clock constraints +# + + +# +# Region constraints +# + + +# +# Core cell constraints +# + +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/DDRPHY_BLK_0/LANE_1_CTRL/I_LANECTRL -fixed true -x 1823 -y 378 +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/DDRPHY_BLK_0/LANE_0_CTRL/I_LANECTRL -fixed true -x 659 -y 378 +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/DDRPHY_BLK_0/LANE_1_IOD_READ_TRAINING/I_IOD_0 -fixed true -x 1812 -y 378 +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/CCC_0/pll_inst_0 -fixed true -x 1 -y 377 +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/DDRPHY_BLK_0/IOD_BCLK_TRAINING/I_IOD_0 -fixed true -x 60 -y 378 +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/DDRPHY_BLK_0/LANE_0_IOD_READ_TRAINING/I_IOD_0 -fixed true -x 648 -y 378 +set_location -inst_name dut_/polarfireddrsubsys_1/island/blackbox/DLL_0/dll_inst_0 -fixed true -x 3 -y 377 diff --git a/microsemi/polarfireavalancheboard/constraints/pin_constraints.pdc b/microsemi/polarfireavalancheboard/constraints/pin_constraints.pdc new file mode 100644 index 00000000..95f783bd --- /dev/null +++ b/microsemi/polarfireavalancheboard/constraints/pin_constraints.pdc @@ -0,0 +1,415 @@ +# Microsemi I/O Physical Design Constraints file + +# User I/O Constraints file + +# Version: v12.0 12.500.0.22 + +# Family: PolarFire , Die: MPF300T_ES , Package: FCG484 + +# Date generated: Wed Mar 6 09:59:39 2019 + +# +# User Locked I/O Bank Settings +# + +# +# Unlocked I/O Bank Settings +# The I/O Bank Settings can be locked by directly editing this file +# or by making changes in the I/O Attribute Editor +# + +# +# User Locked I/O settings +# + +set_io -port_name {ddr_A[0]} \ + -pin_name U5 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[1]} \ + -pin_name U4 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[2]} \ + -pin_name V4 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[3]} \ + -pin_name W3 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[4]} \ + -pin_name V5 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[5]} \ + -pin_name W4 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[6]} \ + -pin_name Y3 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[7]} \ + -pin_name AA3 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[8]} \ + -pin_name Y4 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[9]} \ + -pin_name Y5 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[10]} \ + -pin_name AA2 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[11]} \ + -pin_name AB2 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[12]} \ + -pin_name V6 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[13]} \ + -pin_name W6 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_A[14]} \ + -pin_name AB3 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_BA[0]} \ + -pin_name V7 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_BA[1]} \ + -pin_name Y6 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_BA[2]} \ + -pin_name U7 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_CAS_N \ + -pin_name AA5 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_CK0 \ + -pin_name V2 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_CK0_N \ + -pin_name W2 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_CKE \ + -pin_name W8 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_CS_N \ + -pin_name W7 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_DM[0]} \ + -pin_name Y9 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_DM[1]} \ + -pin_name R15 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name {ddr_DQS[0]} \ + -pin_name T10 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQS[1]} \ + -pin_name R13 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQS_N[0]} \ + -pin_name U10 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQS_N[1]} \ + -pin_name T12 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[0]} \ + -pin_name T7 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[1]} \ + -pin_name T8 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[2]} \ + -pin_name U8 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[3]} \ + -pin_name U9 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[4]} \ + -pin_name R10 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[5]} \ + -pin_name V9 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[6]} \ + -pin_name V10 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[7]} \ + -pin_name W9 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[8]} \ + -pin_name V14 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[9]} \ + -pin_name U14 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[10]} \ + -pin_name R12 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[11]} \ + -pin_name T11 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[12]} \ + -pin_name U15 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[13]} \ + -pin_name T13 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[14]} \ + -pin_name U13 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name {ddr_DQ[15]} \ + -pin_name T15 \ + -fixed true \ + -DIRECTION INOUT + + +set_io -port_name ddr_ODT \ + -pin_name AA7 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_RAS_N \ + -pin_name AA6 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_RESET_N \ + -pin_name AB7 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_SHIELD0 \ + -pin_name R9 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_SHIELD1 \ + -pin_name V15 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name ddr_WE_N \ + -pin_name AB5 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name led_0 \ + -pin_name D6 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name led_1 \ + -pin_name D7 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name led_2 \ + -pin_name D8 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name led_3 \ + -pin_name D9 \ + -fixed true \ + -DIRECTION OUTPUT + + +set_io -port_name pf_user_reset_n \ + -pin_name F5 \ + -fixed true \ + -DIRECTION INPUT + + +set_io -port_name uart_rx \ + -pin_name F16 \ + -fixed true \ + -DIRECTION INPUT + + +set_io -port_name uart_tx \ + -pin_name F17 \ + -fixed true \ + -DIRECTION OUTPUT + + + +# +# Dedicated Peripheral I/O Settings +# + + +# +# Unlocked I/O settings +# The I/Os in this section are unplaced or placed but are not locked +# the other listed attributes have been applied +# + + +# +#Ports using Dedicated Pins + +# + +set_io -port_name jtag_TCK \ + -pin_name F8 \ + -DIRECTION INPUT + + +set_io -port_name jtag_TDI \ + -pin_name G8 \ + -DIRECTION INPUT + + +set_io -port_name jtag_TDO \ + -pin_name F6 \ + -DIRECTION OUTPUT + + +set_io -port_name jtag_TMS \ + -pin_name F7 \ + -DIRECTION INPUT + + +set_io -port_name jtag_TRSTB \ + -pin_name G7 \ + -DIRECTION INPUT + + diff --git a/src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireAvalancheBoardDDR3.scala b/src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireAvalancheBoardDDR3.scala new file mode 100644 index 00000000..8e124b9f --- /dev/null +++ b/src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireAvalancheBoardDDR3.scala @@ -0,0 +1,165 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.microsemi.polarfireddr3 + +import Chisel._ +import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.config.Parameters +//import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import sifive.fpgashells.ip.microsemi.polarfireddr3.{PolarFireAvalancheBoardDDR3IOClocksReset, PolarFireAvalancheBoardDDR3IODDR, DDR3_Subsys_AvalancheBoard} + +case class PolarFireAvalancheBoardDDR3Params( + address : Seq[AddressSet] +) + +class PolarFireAvalancheBoardDDR3Pads(depth : BigInt) extends PolarFireAvalancheBoardDDR3IODDR(depth) { + def this(c : PolarFireAvalancheBoardDDR3Params) { + this(AddressRange.fromSets(c.address).head.size) + } +} + +class PolarFireAvalancheBoardDDR3IO(depth : BigInt) extends PolarFireAvalancheBoardDDR3IODDR(depth) with PolarFireAvalancheBoardDDR3IOClocksReset + +class PolarFireAvalancheBoardDDR3Island(c : PolarFireAvalancheBoardDDR3Params)(implicit p: Parameters) extends LazyModule with CrossesToOnlyOneClockDomain { + val ranges = AddressRange.fromSets(c.address) + require (ranges.size == 1, "DDR range must be contiguous") + val offset = ranges.head.base + val depth = ranges.head.size + val crossing = AsynchronousCrossing(8) + + require((depth<=0x100000000L),"PolarFire Evaluation Kit supports upto 4GB depth configuraton") + + val device = new MemoryDevice + val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = c.address, + resources = device.reg, + regionType = RegionType.UNCACHED, + executable = true, + supportsWrite = TransferSizes(1, 256*8), + supportsRead = TransferSizes(1, 256*8))), + beatBytes = 8))) + + lazy val module = new LazyModuleImp(this) { + val io = IO(new Bundle { + val port = new PolarFireAvalancheBoardDDR3IO(depth) + }) + + //MIG black box instantiation + val blackbox = Module(new DDR3_Subsys_AvalancheBoard(depth)) + val (axi_async, _) = node.in(0) + + //pins to top level + + //inouts + attach(io.port.DQ,blackbox.io.DQ) + attach(io.port.DQS_N,blackbox.io.DQS_N) + attach(io.port.DQS,blackbox.io.DQS) + + //outputs + io.port.A := blackbox.io.A + io.port.BA := blackbox.io.BA + io.port.RAS_N := blackbox.io.RAS_N + io.port.CAS_N := blackbox.io.CAS_N + io.port.WE_N := blackbox.io.WE_N + io.port.RESET_N := blackbox.io.RESET_N + io.port.CK0 := blackbox.io.CK0 + io.port.CK0_N := blackbox.io.CK0_N + io.port.CKE := blackbox.io.CKE + io.port.CS_N := blackbox.io.CS_N + io.port.DM := blackbox.io.DM + io.port.ODT := blackbox.io.ODT + + io.port.CTRLR_READY := blackbox.io.CTRLR_READY + io.port.SHIELD0 := blackbox.io.SHIELD0 + io.port.SHIELD1 := blackbox.io.SHIELD1 + + //inputs + val awaddr = axi_async.aw.bits.addr - UInt(offset) + val araddr = axi_async.ar.bits.addr - UInt(offset) + + //slave AXI interface write address ports + blackbox.io.axi0_awid := axi_async.aw.bits.id + blackbox.io.axi0_awaddr := awaddr //truncated + blackbox.io.axi0_awlen := axi_async.aw.bits.len + blackbox.io.axi0_awsize := axi_async.aw.bits.size + blackbox.io.axi0_awburst := axi_async.aw.bits.burst + blackbox.io.axi0_awlock := axi_async.aw.bits.lock + blackbox.io.axi0_awcache := UInt("b0011") + blackbox.io.axi0_awprot := axi_async.aw.bits.prot + blackbox.io.axi0_awvalid := axi_async.aw.valid + axi_async.aw.ready := blackbox.io.axi0_awready + + //slave interface write data ports + blackbox.io.axi0_wdata := axi_async.w.bits.data + blackbox.io.axi0_wstrb := axi_async.w.bits.strb + blackbox.io.axi0_wlast := axi_async.w.bits.last + blackbox.io.axi0_wvalid := axi_async.w.valid + axi_async.w.ready := blackbox.io.axi0_wready + + //slave interface write response + blackbox.io.axi0_bready := axi_async.b.ready + axi_async.b.bits.id := blackbox.io.axi0_bid + axi_async.b.bits.resp := blackbox.io.axi0_bresp + axi_async.b.valid := blackbox.io.axi0_bvalid + + //slave AXI interface read address ports + blackbox.io.axi0_arid := axi_async.ar.bits.id + blackbox.io.axi0_araddr := araddr // truncated + blackbox.io.axi0_arlen := axi_async.ar.bits.len + blackbox.io.axi0_arsize := axi_async.ar.bits.size + blackbox.io.axi0_arburst := axi_async.ar.bits.burst + blackbox.io.axi0_arlock := axi_async.ar.bits.lock + blackbox.io.axi0_arcache := UInt("b0011") + blackbox.io.axi0_arprot := axi_async.ar.bits.prot + blackbox.io.axi0_arvalid := axi_async.ar.valid + axi_async.ar.ready := blackbox.io.axi0_arready + + //slace AXI interface read data ports + blackbox.io.axi0_rready := axi_async.r.ready + axi_async.r.bits.id := blackbox.io.axi0_rid + axi_async.r.bits.data := blackbox.io.axi0_rdata + axi_async.r.bits.resp := blackbox.io.axi0_rresp + axi_async.r.bits.last := blackbox.io.axi0_rlast + axi_async.r.valid := blackbox.io.axi0_rvalid + + //misc +// blackbox.io.AXI0_AWUSERTAG := UInt("b0000") + blackbox.io.SYS_RESET_N :=io.port.SYS_RESET_N + blackbox.io.PLL_REF_CLK :=io.port.PLL_REF_CLK + + io.port.SYS_CLK := blackbox.io.SYS_CLK + io.port.PLL_LOCK := blackbox.io.PLL_LOCK + } +} + +class PolarFireAvalancheBoardDDR3(c : PolarFireAvalancheBoardDDR3Params)(implicit p: Parameters) extends LazyModule { + val ranges = AddressRange.fromSets(c.address) + val depth = ranges.head.size + + val buffer = LazyModule(new TLBuffer) + val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1)) + val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) + val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes))) + val yank = LazyModule(new AXI4UserYanker) + val island = LazyModule(new PolarFireAvalancheBoardDDR3Island(c)) + + val node: TLInwardNode = + island.crossAXI4In(island.node) := yank.node := deint.node := indexer.node := toaxi4.node := buffer.node + + lazy val module = new LazyModuleImp(this) { + val io = IO(new Bundle { + val port = new PolarFireAvalancheBoardDDR3IO(depth) + }) + + io.port <> island.module.io.port + + // Shove the island + island.module.clock := io.port.SYS_CLK + island.module.reset := !io.port.CTRLR_READY + } +} diff --git a/src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireAvalancheBoardDDR3Periphery.scala b/src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireAvalancheBoardDDR3Periphery.scala new file mode 100644 index 00000000..7384566f --- /dev/null +++ b/src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireAvalancheBoardDDR3Periphery.scala @@ -0,0 +1,37 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.microsemi.polarfireddr3 + +import Chisel._ +import freechips.rocketchip.config._ +//import freechips.rocketchip.coreplex.HasMemoryBus +import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressRange} + +case object MemoryMicrosemiAvalancheBoardDDR3Key extends Field[PolarFireAvalancheBoardDDR3Params] + +//trait HasMemoryPolarFireAvalancheBoardDDR3 extends HasMemoryBus { +trait HasMemoryPolarFireAvalancheBoardDDR3 { this: BaseSubsystem => + val module: HasMemoryPolarFireAvalancheBoardDDR3ModuleImp + + val polarfireddrsubsys = LazyModule(new PolarFireAvalancheBoardDDR3(p(MemoryMicrosemiAvalancheBoardDDR3Key))) + + polarfireddrsubsys.node := mbus.toDRAMController(Some("PolarFireDDR"))() +} + +trait HasMemoryPolarFireAvalancheBoardDDR3Bundle { + val polarfireddrsubsys: PolarFireAvalancheBoardDDR3IO + def connectPolarFireAvalancheBoardDDR3ToPads(pads: PolarFireAvalancheBoardDDR3Pads) { + pads <> polarfireddrsubsys + } +} + +trait HasMemoryPolarFireAvalancheBoardDDR3ModuleImp extends LazyModuleImp + with HasMemoryPolarFireAvalancheBoardDDR3Bundle { + val outer: HasMemoryPolarFireAvalancheBoardDDR3 + val ranges = AddressRange.fromSets(p(MemoryMicrosemiAvalancheBoardDDR3Key).address) + require (ranges.size == 1, "DDR range must be contiguous") + val depth = ranges.head.size + val polarfireddrsubsys = IO(new PolarFireAvalancheBoardDDR3IO(depth)) + + polarfireddrsubsys <> outer.polarfireddrsubsys.module.io.port +} diff --git a/src/main/scala/ip/microsemi/corejtagdebug/corejtagdebug.scala b/src/main/scala/ip/microsemi/corejtagdebug/corejtagdebug.scala index 3c7feb05..9d6edba5 100644 --- a/src/main/scala/ip/microsemi/corejtagdebug/corejtagdebug.scala +++ b/src/main/scala/ip/microsemi/corejtagdebug/corejtagdebug.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.util.{ElaborationArtefacts} import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ -// Black Box for Microsemi DirectCore IP block Actel:DirectCore:COREJTAGDEBUG:2.0.100 +// Black Box for Microsemi DirectCore IP block Actel:DirectCore:COREJTAGDEBUG:3.0.100 trait CoreJtagDebugIOJTAGPads extends Bundle { @@ -20,11 +20,11 @@ trait CoreJtagDebugIOJTAGPads extends Bundle { trait CoreJtagDebugIOTarget extends Bundle { - val TGT_TCK = Clock(OUTPUT) - val TGT_TDI = Bool(OUTPUT) - val TGT_TMS = Bool(OUTPUT) - val TGT_TRST = Bool(OUTPUT) - val TGT_TDO = Bool(INPUT) + val TGT_TCK_0 = Clock(OUTPUT) + val TGT_TDI_0 = Bool(OUTPUT) + val TGT_TMS_0 = Bool(OUTPUT) + val TGT_TRSTB_0 = Bool(OUTPUT) + val TGT_TDO_0 = Bool(INPUT) } //scalastyle:off @@ -33,37 +33,54 @@ class CoreJtagDebugBlock(implicit val p:Parameters) extends BlackBox { override def desiredName = "corejtagdebug_wrapper" - val io = new CoreJtagDebugIOJTAGPads with CoreJtagDebugIOTarget { - // chain inputs - val UTDO_IN_0 = Bool(INPUT) - val UTDO_IN_1 = Bool(INPUT) - val UTDO_IN_2 = Bool(INPUT) - val UTDO_IN_3 = Bool(INPUT) - val UTDODRV_0 = Bool(INPUT) - val UTDODRV_1 = Bool(INPUT) - val UTDODRV_2 = Bool(INPUT) - val UTDODRV_3 = Bool(INPUT) - - // chain outputs - val UTDI_OUT = Bool(OUTPUT) - val URSTB_OUT = Bool(OUTPUT) - val UIREG_OUT = Bits(OUTPUT,8) - val UDRUPD_OUT = Bool(OUTPUT) - val UDRSH_OUT = Bool(OUTPUT) - val UDRCK_OUT = Bool(OUTPUT) - val UDRCAP_OUT = Bool(OUTPUT) - } + val io = new CoreJtagDebugIOJTAGPads with CoreJtagDebugIOTarget { } ElaborationArtefacts.add( "Libero.corejtagdebug.tcl", """ -create_design -id Actel:DirectCore:COREJTAGDEBUG:2.0.100 -design_name {corejtagdebug_wrapper} -config_file {} -params {} -inhibit_configurator 0 + +create_design -id Actel:DirectCore:COREJTAGDEBUG:3.0.100 -design_name {corejtagdebug_wrapper} -config_file {} -params {} -inhibit_configurator 0 open_smartdesign -design {corejtagdebug_wrapper} configure_design -component {corejtagdebug_wrapper} -library {} -configure_vlnv_instance -component {corejtagdebug_wrapper} -library {} -name {corejtagdebug_wrapper_0} -params {"IR_CODE:0x55" "ACTIVE_HIGH_TGT_RESET:1"} -validate_rules 0 +configure_vlnv_instance -component {corejtagdebug_wrapper} -library {} -name {corejtagdebug_wrapper_0} -params {"FAMILY:26" \ +"IR_CODE_TGT_0:0x55" \ +"IR_CODE_TGT_1:0x56" \ +"IR_CODE_TGT_2:0x57" \ +"IR_CODE_TGT_3:0x58" \ +"IR_CODE_TGT_4:0x59" \ +"IR_CODE_TGT_5:0x5a" \ +"IR_CODE_TGT_6:0x5b" \ +"IR_CODE_TGT_7:0x5c" \ +"IR_CODE_TGT_8:0x5d" \ +"IR_CODE_TGT_9:0x5e" \ +"IR_CODE_TGT_10:0x5f" \ +"IR_CODE_TGT_11:0x60" \ +"IR_CODE_TGT_12:0x61" \ +"IR_CODE_TGT_13:0x62" \ +"IR_CODE_TGT_14:0x63" \ +"IR_CODE_TGT_15:0x64" \ +"NUM_DEBUG_TGTS:1" \ +"Testbench:User" \ +"TGT_ACTIVE_HIGH_RESET_0:true" \ +"TGT_ACTIVE_HIGH_RESET_1:true" \ +"TGT_ACTIVE_HIGH_RESET_2:true" \ +"TGT_ACTIVE_HIGH_RESET_3:true" \ +"TGT_ACTIVE_HIGH_RESET_4:true" \ +"TGT_ACTIVE_HIGH_RESET_5:true" \ +"TGT_ACTIVE_HIGH_RESET_6:true" \ +"TGT_ACTIVE_HIGH_RESET_7:true" \ +"TGT_ACTIVE_HIGH_RESET_8:true" \ +"TGT_ACTIVE_HIGH_RESET_9:true" \ +"TGT_ACTIVE_HIGH_RESET_10:true" \ +"TGT_ACTIVE_HIGH_RESET_11:true" \ +"TGT_ACTIVE_HIGH_RESET_12:true" \ +"TGT_ACTIVE_HIGH_RESET_13:true" \ +"TGT_ACTIVE_HIGH_RESET_14:true" \ +"TGT_ACTIVE_HIGH_RESET_15:true" \ +"UJTAG_BYPASS:false" } -validate_rules 0 fix_vlnv_instance -component {corejtagdebug_wrapper} -library {} -name {corejtagdebug_wrapper_0} open_smartdesign -design {corejtagdebug_wrapper} -configure_design -component {corejtagdebug_wrapper} -library {} +configure_design -component {corejtagdebug_wrapper} -library {} """ ) diff --git a/src/main/scala/ip/microsemi/polarfire_ccc/PolarFireCCC.scala b/src/main/scala/ip/microsemi/polarfire_ccc/PolarFireCCC.scala index a09444b9..fb3fbf67 100644 --- a/src/main/scala/ip/microsemi/polarfire_ccc/PolarFireCCC.scala +++ b/src/main/scala/ip/microsemi/polarfire_ccc/PolarFireCCC.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ import sifive.fpgashells.clocks._ -// Black Box for Microsemi PolarFire Clock Conditioning Circuit (CCC) Actel:SgCore:PF_CCC:1.0.112 +// Black Box for Microsemi PolarFire Clock Conditioning Circuit (CCC) Actel:SgCore:PF_CCC:1.0.115 class PolarFireCCCIOPads(c : PLLParameters) extends Bundle { val REF_CLK_0 = Clock(INPUT) val OUT0_FABCLK_0 = if (c.req.size >= 1) Some(Clock(OUTPUT)) else None @@ -68,7 +68,7 @@ class PolarFireCCC(c : PLLParameters)(implicit val p:Parameters) extends BlackBo elaborateArtefactsString_temp += s""" "PLL_FEEDBACK_MODE_0:${if (c.input.feedback) "External" else "Post-VCO"}" \\""" elaborateArtefactsString += - s""" create_design -id Actel:SgCore:PF_CCC:1.0.112 -design_name {${moduleName}} -config_file {} -params {} -inhibit_configurator 0 + s""" create_design -id Actel:SgCore:PF_CCC:1.0.115 -design_name {${moduleName}} -config_file {} -params {} -inhibit_configurator 0 | open_smartdesign -design {${moduleName}} | configure_design -component {${moduleName}} -library {} | configure_vlnv_instance -component {${moduleName}} -library {} -name {${moduleName}_0} \\ diff --git a/src/main/scala/ip/microsemi/polarfire_clock_divider/PolarFireClockDivider.scala b/src/main/scala/ip/microsemi/polarfire_clock_divider/PolarFireClockDivider.scala index 775f30d6..2964b92a 100644 --- a/src/main/scala/ip/microsemi/polarfire_clock_divider/PolarFireClockDivider.scala +++ b/src/main/scala/ip/microsemi/polarfire_clock_divider/PolarFireClockDivider.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.util.{ElaborationArtefacts} import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ -// Black Box for Actel:SgCore:PF_CLK_DIV:1.0.101 +// Black Box for Actel:SgCore:PF_CLK_DIV:1.0.103 trait PolarFireClockDividerIOPads extends Bundle { @@ -27,7 +27,7 @@ class PolarFireClockDivider(implicit val p:Parameters) extends BlackBox ElaborationArtefacts.add( "Libero.polarfire_clock_divider.tcl", """ -create_design -id Actel:SgCore:PF_CLK_DIV:1.0.101 -design_name {pf_clk_divider} -config_file {} -params {} -inhibit_configurator 0 +create_design -id Actel:SgCore:PF_CLK_DIV:1.0.103 -design_name {pf_clk_divider} -config_file {} -params {} -inhibit_configurator 0 open_smartdesign -design {pf_clk_divider} configure_design -component {pf_clk_divider} -library {} configure_vlnv_instance -component {pf_clk_divider} -library {} -name {pf_clk_divider_0} -params {"DIVIDER:2"} -validate_rules 0 diff --git a/src/main/scala/ip/microsemi/polarfire_ddr3/PolarFireDDR3_AvalancheBoard.scala b/src/main/scala/ip/microsemi/polarfire_ddr3/PolarFireDDR3_AvalancheBoard.scala new file mode 100644 index 00000000..12090104 --- /dev/null +++ b/src/main/scala/ip/microsemi/polarfire_ddr3/PolarFireDDR3_AvalancheBoard.scala @@ -0,0 +1,129 @@ +// See LICENSE for license details. +package sifive.fpgashells.ip.microsemi.polarfireddr3 + +import Chisel._ +import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.util.{ElaborationArtefacts} +import freechips.rocketchip.util.GenericParameterizedBundle +import freechips.rocketchip.config._ + +// Black Box for Microsemi PolarFire DDR3 controller version 2.3.201 + +class PolarFireAvalancheBoardDDR3IODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { + + val A = Bits(OUTPUT,15) + val BA = Bits(OUTPUT,3) + val RAS_N = Bool(OUTPUT) + val CAS_N = Bool(OUTPUT) + val WE_N = Bool(OUTPUT) + val CTRLR_READY = Bool(OUTPUT) + val SHIELD0 = Bool(OUTPUT) + val SHIELD1 = Bool(OUTPUT) + val CK0 = Bits(OUTPUT,1) + val CK0_N = Bits(OUTPUT,1) + val CKE = Bits(OUTPUT,1) + val CS_N = Bits(OUTPUT,1) + val DM = Bits(OUTPUT,2) + val ODT = Bits(OUTPUT,1) + val RESET_N = Bool(OUTPUT) + + val DQ = Analog(16.W) + val DQS = Analog(2.W) + val DQS_N = Analog(2.W) +} + +trait PolarFireAvalancheBoardDDR3IOClocksReset extends Bundle { + + val SYS_RESET_N = Bool(INPUT) + val PLL_REF_CLK = Clock(INPUT) + + val SYS_CLK = Clock(OUTPUT) + val PLL_LOCK = Bool(OUTPUT) + +} + +//scalastyle:off +//turn off linter: blackbox name must match verilog module +class DDR3_Subsys_AvalancheBoard(depth : BigInt)(implicit val p:Parameters) extends BlackBox +{ + override def desiredName = "pf_ddr" + + val io = new PolarFireAvalancheBoardDDR3IODDR(depth) with PolarFireAvalancheBoardDDR3IOClocksReset { + //axi slave interface + //slave interface write address ports + val axi0_awid = Bits(INPUT,4) + val axi0_awaddr = Bits(INPUT,32) + val axi0_awlen = Bits(INPUT,8) + val axi0_awsize = Bits(INPUT,3) + val axi0_awburst = Bits(INPUT,2) + val axi0_awlock = Bits(INPUT,2) + val axi0_awcache = Bits(INPUT,4) + val axi0_awprot = Bits(INPUT,3) + val axi0_awvalid = Bool(INPUT) + val axi0_awready = Bool(OUTPUT) + //slave interface write data ports + val axi0_wdata = Bits(INPUT,64) + val axi0_wstrb = Bits(INPUT,8) + val axi0_wlast = Bool(INPUT) + val axi0_wvalid = Bool(INPUT) + val axi0_wready = Bool(OUTPUT) + //slave interface write response ports + val axi0_bready = Bool(INPUT) + val axi0_bid = Bits(OUTPUT,4) + val axi0_bresp = Bits(OUTPUT,2) + val axi0_bvalid = Bool(OUTPUT) + //slave interface read address ports + val axi0_arid = Bits(INPUT,4) + val axi0_araddr = Bits(INPUT,32) + val axi0_arlen = Bits(INPUT,8) + val axi0_arsize = Bits(INPUT,3) + val axi0_arburst = Bits(INPUT,2) + val axi0_arlock = Bits(INPUT,2) + val axi0_arcache = Bits(INPUT,4) + val axi0_arprot = Bits(INPUT,3) + val axi0_arvalid = Bool(INPUT) + val axi0_arready = Bool(OUTPUT) + //slave interface read data ports + val axi0_rready = Bool(INPUT) + val axi0_rid = Bits(OUTPUT,4) + val axi0_rdata = Bits(OUTPUT,64) + val axi0_rresp = Bits(OUTPUT,2) + val axi0_rlast = Bool(OUTPUT) + val axi0_rvalid = Bool(OUTPUT) + //misc + //val AXI0_AWUSERTAG = Bits(INPUT,4) + //val AXI0_BUSERTAG = Bits(OUTPUT,4) + } + + ElaborationArtefacts.add( + "AddIPInstance.polarfire_ddr3.libero.tcl", + """ +create_design -id Actel:SystemBuilder:PF_DDR3:2.3.201 -design_name {pf_ddr} -config_file {} -params {} -inhibit_configurator 0 +open_smartdesign -design pf_ddr +sysbld_configure_page -component pf_ddr -page PF_DDR3_UI -param WIDTH:16 \ + -param CLOCK_DDR:533.333 \ + -param CLOCK_PLL_REFERENCE:133.33325 \ + -param CCC_PLL_CLOCK_MULTIPLIER:4 \ + -param ROW_ADDR_WIDTH:15 \ + -param CAS_LATENCY:7 \ + -param RTT_NOM:RZQ6 \ + -param CAS_WRITE_LATENCY:6 \ + -param OUTPUT_DRIVE_STRENGTH:RZQ7 \ + -param TIMING_RAS:37.5 \ + -param TIMING_RCD:11.25 \ + -param TIMING_RP:11.25 \ + -param TIMING_RC:48.75 \ + -param TIMING_WR:15 \ + -param TIMING_FAW:50 \ + -param TIMING_WTR:4 \ + -param TIMING_RRD:10 \ + -param TIMING_RTP:7.5 \ + -param TIMING_RFC:260 \ + -param AXI_ID_WIDTH:6 +save_design -component pf_ddr -library {} -file {} +generate_design -component pf_ddr -library {} -file {} -generator {} -recursive 1 +close_design -component pf_ddr +""" + ) +} +//scalastyle:ons diff --git a/src/main/scala/ip/microsemi/polarfire_init_monitor/PolarFireInitMonitor.scala b/src/main/scala/ip/microsemi/polarfire_init_monitor/PolarFireInitMonitor.scala index 3b1b9671..14429fba 100644 --- a/src/main/scala/ip/microsemi/polarfire_init_monitor/PolarFireInitMonitor.scala +++ b/src/main/scala/ip/microsemi/polarfire_init_monitor/PolarFireInitMonitor.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.util.{ElaborationArtefacts} import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ -// Black Box for Microsemi PolarFire Clock Conditioning Circuit (CCC) Actel:SgCore:PF_INIT_MONITOR:2.0.101 +// Black Box for Microsemi PolarFire Init Monitor Actel:SgCore:PF_INIT_MONITOR:2.0.103 trait PolarFireInitMonitorIOPads extends Bundle { @@ -30,7 +30,7 @@ class PolarFireInitMonitor(implicit val p:Parameters) extends BlackBox ElaborationArtefacts.add( "Libero.pf_init_monitor.tcl", """ -create_design -id Actel:SgCore:PF_INIT_MONITOR:2.0.101 -design_name {polarfire_init_monitor} -config_file {} -params {} -inhibit_configurator 0 +create_design -id Actel:SgCore:PF_INIT_MONITOR:2.0.103 -design_name {polarfire_init_monitor} -config_file {} -params {} -inhibit_configurator 0 open_smartdesign -design {polarfire_init_monitor} configure_design -component {polarfire_init_monitor} -library {} fix_vlnv_instance -component {polarfire_init_monitor} -library {} -name {polarfire_init_monitor_0} diff --git a/src/main/scala/shell/microsemi/PolarFireAvalancheKitShell.scala b/src/main/scala/shell/microsemi/PolarFireAvalancheKitShell.scala new file mode 100644 index 00000000..5e7355d0 --- /dev/null +++ b/src/main/scala/shell/microsemi/PolarFireAvalancheKitShell.scala @@ -0,0 +1,227 @@ +// See LICENSE for license details. +package sifive.fpgashells.shell.microsemi.polarfireavalanchekitshell + +import Chisel._ +import chisel3.core.{Input, Output, attach} +import chisel3.experimental.{RawModule, Analog, withClockAndReset} + +import freechips.rocketchip.config._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg, ResetCatchAndSync, ElaborationArtefacts, HeterogeneousBag} + +import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ + +import sifive.fpgashells.ip.microsemi.{CLKINT} + +import sifive.fpgashells.devices.microsemi.polarfireddr3._ +import sifive.fpgashells.ip.microsemi.corejtagdebug._ +import sifive.fpgashells.ip.microsemi.polarfireccc._ +import sifive.fpgashells.ip.microsemi.polarfireinitmonitor._ +import sifive.fpgashells.ip.microsemi.polarfirereset._ + +import sifive.fpgashells.ip.microsemi.polarfire_oscillator._ +import sifive.fpgashells.ip.microsemi.polarfireclockdivider._ + +import sifive.fpgashells.clocks._ + + +//------------------------------------------------------------------------- +// PolarFire Avalanche Kit Shell +//------------------------------------------------------------------------- + +trait HasDDR3 { this: PolarFireAvalancheKitShell => + + require(!p.lift(MemoryMicrosemiAvalancheBoardDDR3Key).isEmpty) + val ddr = IO(new PolarFireAvalancheBoardDDR3Pads(p(MemoryMicrosemiAvalancheBoardDDR3Key))) + + def connectMIG(dut: HasMemoryPolarFireAvalancheBoardDDR3ModuleImp): Unit = { + // Clock & Reset + dut.polarfireddrsubsys.PLL_REF_CLK := mig_clock_in + dut.polarfireddrsubsys.SYS_RESET_N := sys_reset_n + + mig_clock_out := dut.polarfireddrsubsys.SYS_CLK + mig_plllock_out := dut.polarfireddrsubsys.PLL_LOCK + ddr_ctrlr_ready := dut.polarfireddrsubsys.CTRLR_READY + + ddr <> dut.polarfireddrsubsys + } +} + +abstract class PolarFireAvalancheKitShell(implicit val p: Parameters) extends RawModule { + + //----------------------------------------------------------------------- + // Interface + //----------------------------------------------------------------------- + + // Reset push-button - active low + val pf_user_reset_n = IO(Input(Bool())) + + // LED + val led = IO(Vec(4, Output(Bool()))) + + // UART + val uart_tx = IO(Output(Bool())) + val uart_rx = IO(Input(Bool())) + + // JTAG + val jtag_TRSTB = IO(Input(Bool())) + val jtag_TCK = IO(Input(Clock())) + val jtag_TMS = IO(Input(Bool())) + val jtag_TDI = IO(Input(Bool())) + val jtag_TDO = IO(Output(Bool())) + + //----------------------------------------------------------------------- + // Wire declarations + //----------------------------------------------------------------------- + + val sys_clock = Wire(Clock()) + val sys_reset_n = Wire(Bool()) + + val dut_clock = Wire(Clock()) + val dut_reset = Wire(Bool()) + val dut_reset_i = Wire(Bool()) + val dut_reset_sync = Wire(Bool()) + + val dut_ndreset = Wire(Bool()) + + val mig_mmcm_locked = Wire(Bool()) + val mig_sys_reset = Wire(Bool()) + + val mig_clock = Wire(Clock()) + val mig_reset = Wire(Bool()) + val mig_resetn = Wire(Bool()) + + val mig_clock_in = Wire(Clock()) + val mig_clock_out = Wire(Clock()) + val mig_plllock_out = Wire(Bool()) + + val fpga_reset = Wire(Bool()) + val ddr_ctrlr_ready = Wire(Bool()) + val ref_clk0 = Wire(Clock()) + + //----------------------------------------------------------------------- + // PolarFire Oscillator Instatiation + //----------------------------------------------------------------------- + + val pf_oscillator = Module(new PolarFireOscillator) + ref_clk0 := pf_oscillator.io.RCOSC_160MHZ_GL + + //----------------------------------------------------------------------- + // DDR3 Subsystem Clocks + //----------------------------------------------------------------------- + val ddr3_clk_ccc = Module(new PolarFireCCC( + PLLParameters( + name = "ddr3_clk_ccc", + PLLInClockParameters(166.666), + Seq( + PLLOutClockParameters(133.333))))) + + ddr3_clk_ccc.io.REF_CLK_0 := ref_clk0 + val ddr3_clk_in = ddr3_clk_ccc.io.OUT0_FABCLK_0.get + val ddr3_clk_in_lock = ddr3_clk_ccc.io.PLL_LOCK_0 + mig_clock_in := ddr3_clk_in + + //----------------------------------------------------------------------- + // Coreplex Clock Generator + //----------------------------------------------------------------------- + val hart_clk_ccc = Module(new PolarFireCCC(PLLParameters( + name = "hart_clk_ccc", + PLLInClockParameters(166.666), + Seq( + PLLOutClockParameters(25))))) + + val hart_clk_25 = hart_clk_ccc.io.OUT0_FABCLK_0.get + val hart_clk_lock = hart_clk_ccc.io.PLL_LOCK_0 + + // DUT clock + hart_clk_ccc.io.REF_CLK_0 := mig_clock_out + dut_clock := hart_clk_25 + + + + //----------------------------------------------------------------------- + // System reset + //----------------------------------------------------------------------- + val pf_init_monitor = Module(new PolarFireInitMonitor) + + val pf_reset = Module(new PolarFireReset) + + pf_reset.io.CLK := ddr3_clk_in + pf_reset.io.PLL_LOCK := ddr3_clk_in_lock + pf_reset.io.INIT_DONE := pf_init_monitor.io.DEVICE_INIT_DONE + pf_reset.io.EXT_RST_N := pf_user_reset_n + + pf_reset.io.SS_BUSY := UInt("b0") + pf_reset.io.FF_US_RESTORE := UInt("b0") + + fpga_reset := !pf_reset.io.FABRIC_RESET_N + + sys_reset_n := pf_reset.io.FABRIC_RESET_N + + mig_resetn := !mig_reset + + + dut_reset_i := !pf_reset.io.FABRIC_RESET_N | !hart_clk_lock | !ddr_ctrlr_ready + + withClockAndReset(dut_clock, fpga_reset) { + dut_reset := ResetCatchAndSync(dut_clock, dut_reset_i, 10) + } + + //overrided in connectMIG and connect PCIe + //provide defaults to allow above reset sequencing logic to work without both + mig_clock := dut_clock + mig_mmcm_locked := UInt("b1") + + + led(3) := dut_ndreset + led(2) := !pf_user_reset_n + led(1) := fpga_reset + led(0) := dut_reset + + + //--------------------------------------------------------------------- + // Debug JTAG + //--------------------------------------------------------------------- + + // JTAG inside the FPGA fabric through user JTAG FPGA macro (UJTAG) + + val fpga_jtag = Module(new CoreJtagDebugBlock) + + def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): SystemJTAGIO = { + val djtag = dut.debug.systemjtag.get + + djtag.jtag.TCK := fpga_jtag.io.TGT_TCK_0 + djtag.jtag.TMS := fpga_jtag.io.TGT_TMS_0 + djtag.jtag.TDI := fpga_jtag.io.TGT_TDI_0 + fpga_jtag.io.TGT_TDO_0 := djtag.jtag.TDO.data + + fpga_jtag.io.TRSTB := jtag_TRSTB + fpga_jtag.io.TCK := jtag_TCK + fpga_jtag.io.TMS := jtag_TMS + fpga_jtag.io.TDI := jtag_TDI + jtag_TDO := fpga_jtag.io.TDO + + djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + + djtag.reset := fpga_reset + dut_ndreset := dut.debug.ndreset + djtag + } + + //----------------------------------------------------------------------- + // UART + //----------------------------------------------------------------------- + + def connectUART(dut: HasPeripheryUARTModuleImp): Unit = { + val uartParams = p(PeripheryUARTKey) + if (!uartParams.isEmpty) { + // uart connections + dut.uart(0).rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync")) + uart_tx := dut.uart(0).txd + } + } + + +}