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An ideal cpu can be broken down into 3 parts
1: Memory
2: Control Unit
3: Arithmetic Logic Unit
Each of these 3 parts can be broken down into smaller units: memory can be
broken down into main-memory and registers, the Control Unit can be broken down
into decode-fetch-execute and the ALU can be broken down into arithmetic,
logical and comparison circuits.
Along with each of these components we'll also write an assembler and some test
programs.
Note on RISC-V ISA:
The immediate variants of riscv instructions allow performing an operation
between a register and a constant instead of 2 registers, e.g. `addi x2 x3 -10`
as opposed to a normal `add x2 x3 x4`.
Endiannes refers to the address of the most and least significant bytes of a word.
A big-endian system stores the most significant byte of a word at the smallest
memory address and the least significant byte at the largest. A little-endian
system stores the least-significant byte at the smallest address.
### INSTRUCTION LAYOUTS
Instructions are big-endian.
There are 3 types of instructions (bit ranges are inclusive):
S-type (CTL)
31 29 28 0
[op ] [fn ]
R-type (ALUR and MD)
31 29 28 26 25 21 20 16 15 11 10 0
[op ] [fn ] [r_a ] [r_b ] [r_c ] [empty ]
I-type (IO, ALUI, JUMP, BRANCH and MEM)
31 29 28 26 25 21 20 16 15 0
[op ] [fn ] [r_a ] [r_b ] [imm ]
### IO Redesign
3 types of IO calls:
1. `op reg`
produces a single byte IO operation using
the address stored in the register.
2. `op imm`
produces a single byte IO operation using
the address stored in the immediate field.
3. `op reg1 reg2`
produces an n byte IO operation on the non inclusive
address range between the values of reg1 and reg2.
The third kind of IO call allows strings to be quickly
written to or read from, while the other two are more
suited for when the number of bytes that will be read
is unknown.
OUTD, OUTB, OUTH and OUTC are special IO calls that allow
printing the contents of a register as decimal, binary, hex
or a character. These calls may be of type 1 or 2