From 15a45477bc466a5c21985b6aabb0ceb6c2f51be8 Mon Sep 17 00:00:00 2001 From: andreroesti Date: Fri, 15 Nov 2024 21:08:36 -0800 Subject: [PATCH] fix typo and set more reasonable branch misprediction latency penalty --- CustomStages/MCADFetchDelayStage.cpp | 2 +- MCAWorker.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/CustomStages/MCADFetchDelayStage.cpp b/CustomStages/MCADFetchDelayStage.cpp index bdaf684..2148048 100644 --- a/CustomStages/MCADFetchDelayStage.cpp +++ b/CustomStages/MCADFetchDelayStage.cpp @@ -54,7 +54,7 @@ llvm::Error MCADFetchDelayStage::execute(llvm::mca::InstRef &IR) { LLVM_DEBUG(dbgs() << "[MCAD FetchDelayStage] Previous branch at "); LLVM_DEBUG(dbgs().write_hex(instrAddr->addr)); LLVM_DEBUG(dbgs() << " mispredicted, delaying next instruction by " - << delayCyclesLeft << "cycle(s).\n"); + << delayCyclesLeft << " cycle(s).\n"); } else { LLVM_DEBUG(dbgs() << "[MCAD FetchDelayStage] Previous branch at "); LLVM_DEBUG(dbgs().write_hex(instrAddr->addr)); diff --git a/MCAWorker.cpp b/MCAWorker.cpp index c125771..b05797a 100644 --- a/MCAWorker.cpp +++ b/MCAWorker.cpp @@ -182,7 +182,7 @@ std::unique_ptr MCAWorker::createDefaultPipeline() { MCAPO.StoreQueueSize, MCAPO.AssumeNoAlias, &MDRegistry); auto HWS = std::make_unique(SM, *LSU); - auto BPU = std::make_unique(100); + auto BPU = std::make_unique(20); // Create the pipeline stages. auto Fetch = std::make_unique(SrcMgr); @@ -227,7 +227,7 @@ std::unique_ptr MCAWorker::createInOrderPipeline() { auto LSU = std::make_unique(SM, MCAPO.LoadQueueSize, MCAPO.StoreQueueSize, MCAPO.AssumeNoAlias, &MDRegistry); - auto BPU = std::make_unique(100); + auto BPU = std::make_unique(20); // Create the pipeline stages. auto Entry = std::make_unique(SrcMgr);