From f53f2fa2e894c4709d7b09995331f30c596d0724 Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Thu, 8 Mar 2018 11:52:41 +0000 Subject: [PATCH 1/3] librustc_back: bump ISA level of mipsel targets to mips32r2 --- src/librustc_back/target/mipsel_unknown_linux_gnu.rs | 4 ++-- src/librustc_back/target/mipsel_unknown_linux_musl.rs | 4 ++-- src/librustc_back/target/mipsel_unknown_linux_uclibc.rs | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/librustc_back/target/mipsel_unknown_linux_gnu.rs b/src/librustc_back/target/mipsel_unknown_linux_gnu.rs index 2c38444d050fb..94f82adfacde1 100644 --- a/src/librustc_back/target/mipsel_unknown_linux_gnu.rs +++ b/src/librustc_back/target/mipsel_unknown_linux_gnu.rs @@ -25,8 +25,8 @@ pub fn target() -> TargetResult { linker_flavor: LinkerFlavor::Gcc, options: TargetOptions { - cpu: "mips32".to_string(), - features: "+mips32".to_string(), + cpu: "mips32r2".to_string(), + features: "+mips32r2".to_string(), max_atomic_width: Some(32), // see #36994 diff --git a/src/librustc_back/target/mipsel_unknown_linux_musl.rs b/src/librustc_back/target/mipsel_unknown_linux_musl.rs index b09d96eb9cbcb..6bef2fe2ea717 100644 --- a/src/librustc_back/target/mipsel_unknown_linux_musl.rs +++ b/src/librustc_back/target/mipsel_unknown_linux_musl.rs @@ -13,8 +13,8 @@ use target::{Target, TargetResult}; pub fn target() -> TargetResult { let mut base = super::linux_musl_base::opts(); - base.cpu = "mips32".to_string(); - base.features = "+mips32,+soft-float".to_string(); + base.cpu = "mips32r2".to_string(); + base.features = "+mips32r2,+soft-float".to_string(); base.max_atomic_width = Some(32); // see #36994 base.exe_allocation_crate = None; diff --git a/src/librustc_back/target/mipsel_unknown_linux_uclibc.rs b/src/librustc_back/target/mipsel_unknown_linux_uclibc.rs index 5d2ba548769ff..a5dbdd1118359 100644 --- a/src/librustc_back/target/mipsel_unknown_linux_uclibc.rs +++ b/src/librustc_back/target/mipsel_unknown_linux_uclibc.rs @@ -25,8 +25,8 @@ pub fn target() -> TargetResult { linker_flavor: LinkerFlavor::Gcc, options: TargetOptions { - cpu: "mips32".to_string(), - features: "+mips32,+soft-float".to_string(), + cpu: "mips32r2".to_string(), + features: "+mips32r2,+soft-float".to_string(), max_atomic_width: Some(32), // see #36994 From fccaf252df7d5426ae5b0d8b8359357fe526fc58 Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Thu, 8 Mar 2018 11:53:19 +0000 Subject: [PATCH 2/3] librustc_back: enable fpxx on 32-bit hardfloat mips targets See this page for details about FPXX: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Using FPXX is the most compatible floating point mode available and allows the generated code to work in both FR0 and FR1 modes of the processor. Using MSA (MIPS SIMD) requires FR1, so to use any MSA code we need a compatible floating point mode. This commit also sets nooddspreg (disabling the use of odd numbered single precision float registers) as recommended when enabling FPXX. --- src/librustc_back/target/mips_unknown_linux_gnu.rs | 2 +- src/librustc_back/target/mipsel_unknown_linux_gnu.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/librustc_back/target/mips_unknown_linux_gnu.rs b/src/librustc_back/target/mips_unknown_linux_gnu.rs index 5a43e1c4c7a0f..cffd1daed99f2 100644 --- a/src/librustc_back/target/mips_unknown_linux_gnu.rs +++ b/src/librustc_back/target/mips_unknown_linux_gnu.rs @@ -25,7 +25,7 @@ pub fn target() -> TargetResult { linker_flavor: LinkerFlavor::Gcc, options: TargetOptions { cpu: "mips32r2".to_string(), - features: "+mips32r2".to_string(), + features: "+mips32r2,+fpxx,+nooddspreg".to_string(), max_atomic_width: Some(32), // see #36994 diff --git a/src/librustc_back/target/mipsel_unknown_linux_gnu.rs b/src/librustc_back/target/mipsel_unknown_linux_gnu.rs index 94f82adfacde1..555855b8f815d 100644 --- a/src/librustc_back/target/mipsel_unknown_linux_gnu.rs +++ b/src/librustc_back/target/mipsel_unknown_linux_gnu.rs @@ -26,7 +26,7 @@ pub fn target() -> TargetResult { options: TargetOptions { cpu: "mips32r2".to_string(), - features: "+mips32r2".to_string(), + features: "+mips32r2,+fpxx,+nooddspreg".to_string(), max_atomic_width: Some(32), // see #36994 From 0711a7a72f5828825357a4eb5db70aedb2dabef4 Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Thu, 8 Mar 2018 12:04:09 +0000 Subject: [PATCH 3/3] librustc_trans: add fp64 to mips features whitelist On 32-bit MIPS, enabling MSA requires also enabling the 64-bit FPU. --- src/librustc_trans/llvm_util.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/librustc_trans/llvm_util.rs b/src/librustc_trans/llvm_util.rs index 45445a48e233e..afe32f3f66933 100644 --- a/src/librustc_trans/llvm_util.rs +++ b/src/librustc_trans/llvm_util.rs @@ -104,7 +104,7 @@ const POWERPC_WHITELIST: &'static [&'static str] = &["altivec", "power8-vector", "power9-vector", "vsx"]; -const MIPS_WHITELIST: &'static [&'static str] = &["msa"]; +const MIPS_WHITELIST: &'static [&'static str] = &["fp64", "msa"]; pub fn to_llvm_feature<'a>(sess: &Session, s: &'a str) -> &'a str { let arch = if sess.target.target.arch == "x86_64" {