diff --git a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
index 042a9a140710c..762084291a696 100644
--- a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
+++ b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
@@ -21,16 +21,16 @@ pub(crate) fn target() -> Target {
             linker: Some("rust-lld".into()),
             relocation_model: RelocModel::Static,
             panic_strategy: PanicStrategy::Abort,
-            // The Cortex-R52 has two variants with respect to floating-point support:
-            // 1. fp-armv8, SP-only, with 16 DP (32 SP) registers
-            // 2. neon-fp-armv8, SP+DP, with 32 DP registers
-            // Use the lesser of these two options as the default, as it will produce code
-            // compatible with either variant.
+            // Armv8-R requires a minimum set of floating-point features equivalent to:
+            // fp-armv8, SP-only, with 16 DP (32 SP) registers
+            // LLVM defines Armv8-R to include these features automatically.
+            //
+            // The Cortex-R52 supports these default features and optionally includes:
+            // neon-fp-armv8, SP+DP, with 32 DP registers
             //
             // Reference:
             // Arm Cortex-R52 Processor Technical Reference Manual
             // - Chapter 15 Advanced SIMD and floating-point support
-            features: "+fp-armv8,-fp64,-d32".into(),
             max_atomic_width: Some(64),
             emit_debug_gdb_scripts: false,
             // GCC defaults to 8 for arm-none here.
diff --git a/tests/run-make/arm-target-cpu-fp/armv8r_none_eabihf_cortex_r52.checks b/tests/run-make/arm-target-cpu-fp/armv8r_none_eabihf_cortex_r52.checks
new file mode 100644
index 0000000000000..d333699010e1b
--- /dev/null
+++ b/tests/run-make/arm-target-cpu-fp/armv8r_none_eabihf_cortex_r52.checks
@@ -0,0 +1,10 @@
+CHECK-LABEL: vadd_q:
+CHECK: vld{{.*}}
+CHECK: vld{{.*}}
+CHECK: vadd.f32{{.*}}q
+CHECK: vst{{.*}} [r0]
+CHECK: bx lr
+
+CHECK-LABEL: vadd_f64:
+CHECK: vadd.f64 d0, d0, d1
+CHECK: bx lr
diff --git a/tests/run-make/arm-target-cpu-fp/lib.rs b/tests/run-make/arm-target-cpu-fp/lib.rs
new file mode 100644
index 0000000000000..990261ac9904c
--- /dev/null
+++ b/tests/run-make/arm-target-cpu-fp/lib.rs
@@ -0,0 +1,13 @@
+#![no_std]
+
+#[no_mangle]
+pub fn vadd_q(x: &mut [f32; 4], y: &[f32; 4]) {
+    for i in 0..4 {
+        x[i] += y[i];
+    }
+}
+
+#[no_mangle]
+pub fn vadd_f64(x: f64, y: f64) -> f64 {
+    x + y
+}
diff --git a/tests/run-make/arm-target-cpu-fp/rmake.rs b/tests/run-make/arm-target-cpu-fp/rmake.rs
new file mode 100644
index 0000000000000..f0de45040c0f0
--- /dev/null
+++ b/tests/run-make/arm-target-cpu-fp/rmake.rs
@@ -0,0 +1,37 @@
+// This tests that target-cpu correctly enables additional floating-point features.
+
+use run_make_support::{llvm_filecheck, llvm_objdump, rustc, static_lib_name};
+
+struct TestCase {
+    target: &'static str,
+    cpu: &'static str,
+}
+
+static CASES: &[TestCase] = &[TestCase { target: "armv8r-none-eabihf", cpu: "cortex-r52" }];
+
+fn main() {
+    for case in CASES {
+        let lib = static_lib_name(case.cpu);
+
+        rustc()
+            .edition("2021")
+            .arg(format!("--target={}", case.target))
+            .arg(format!("-Ctarget-cpu={}", case.cpu))
+            .arg("-Copt-level=3")
+            .crate_type("rlib")
+            .input("lib.rs")
+            .output(&lib)
+            .run();
+
+        let dis = llvm_objdump()
+            .arg("--arch-name=arm")
+            .arg(format!("--mcpu={}", case.cpu))
+            .disassemble()
+            .input(&lib)
+            .run()
+            .stdout_utf8();
+
+        let check_file = format!("{}_{}.checks", case.target, case.cpu).replace("-", "_");
+        llvm_filecheck().patterns(check_file).stdin_buf(dis).run();
+    }
+}