Pass target-cpu to C compilers

[kornelski]

It's possible to set target compilation architecture via RUSTFLAGS="-C target-cpu=<arch>".

As far as I can tell, the C compiler is not made aware of this, so it won't be producing matching binaries. It affects performance and I suspect it may also affect correctness when it affects C calling convention (newer SSE registers are used).

So I think it'd be best if the cc crate detected Rust's compilation target and automatically configured the C compiler to match (abstracting away compiler-specific flags and possibly cpu arch naming mismatches, so that build scripts don't have to reinvent this).

[kornelski]

I've cross-referenced https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html and rustc --print target-cpus

Most of them match exactly. Below is the list of odd ones.

The extra options on GCC side can be ignored (they're mostly exotic/outdated and not fully supported anyway).

The extra options on LLVM side may need to be mapped to a closest equivalent.

march	Back-end	Description
skx	LLVM	skx processor
slm	LLVM	slm processor
atom	LLVM	atom processor
core-avx-i	LLVM	core-avx-i processor
core-avx2	LLVM	core-avx2 processor
corei7	LLVM	corei7 processor
corei7-avx	LLVM	corei7-avx processor
generic	LLVM	generic processor
penryn	LLVM	penryn processor
x86-64	LLVM	x86-64 processor
yonah	LLVM	yonah processor
eden-x2	GCC	VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support. (No scheduling is implemented for this chip.)
eden-x4	GCC	VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 instruction set support. (No scheduling is implemented for this chip.)
esther	GCC	VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support. (No scheduling is implemented for this chip.)
knm	GCC	Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
nehemiah	GCC	VIA Eden Nehemiah CPU with MMX and SSE instruction set support. (No scheduling is implemented for this chip.)
samuel-2	GCC	VIA Eden Samuel 2 CPU with MMX and 3DNow! instruction set support. (No scheduling is implemented for this chip.)
c7	GCC	VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support. (No scheduling is implemented for this chip.)
nano	GCC	Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. (No scheduling is implemented for this chip.)
nano-1000	GCC	VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. (No scheduling is implemented for this chip.)
nano-2000	GCC	VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. (No scheduling is implemented for this chip.)
nano-3000	GCC	VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. (No scheduling is implemented for this chip.)
nano-x2	GCC	VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. (No scheduling is implemented for this chip.)
nano-x4	GCC	VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. (No scheduling is implemented for this chip.)

[lilith]

related: conan-io/conan#847

[lilith]

I would suggest (since these have to be mapped and handled separately per ToolFamily), that you start with a minimal list and expand support as they are requested by other projects.

GCC 4.8 requires corei7-avx (rather than sandybridge) and core-avx2 (rather than haswell). I don't see gcc version detection, and I think those values are forward compatible.

Maybe we should start with a mapping table and add columns for MSVC, CLANG, and GCC. I would imagine that we'd have to target baseline versions and only enable advanced mappings if we know the compiler version.

[lilith]

For this crate, what are the minimum supported versions of clang, gcc, and msvc?

[gnzlbg]

The same applies to target-features.

[nazar-pc]

I need this for WASM (target-cpu=mvp) in order to address paritytech/polkadot-sdk#3192 with LLVM 16+.