From 5a3c20d76e936e91dc0ebffca445eb9af41ffb3e Mon Sep 17 00:00:00 2001 From: ved-rivos <91900059+ved-rivos@users.noreply.github.com> Date: Sat, 12 Aug 2023 20:52:11 -0500 Subject: [PATCH 1/2] Update readme.adoc Signed-off-by: ved-rivos <91900059+ved-rivos@users.noreply.github.com> --- readme.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/readme.adoc b/readme.adoc index cb8d508..2f4d9c2 100644 --- a/readme.adoc +++ b/readme.adoc @@ -1,6 +1,6 @@ = RISC-V Hardware Updating of PTE A/D Bits -The Ssadu extension adds support and CSR control for hardware updating of PTE A/D bits. +The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits. = License From 3f64c8d1ec7e1c267a9e3d8f6ce7faf0b2e54af6 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Wed, 6 Sep 2023 09:59:13 -0500 Subject: [PATCH 2/2] clarify speculation --- svadu.adoc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/svadu.adoc b/svadu.adoc index 6d3795b..bafccf1 100644 --- a/svadu.adoc +++ b/svadu.adoc @@ -18,11 +18,12 @@ A/D bits. The A and D bits are managed by these extensions as follows: The PTE update must be atomic with respect to other accesses to the PTE, and must atomically check that the PTE is valid and grants sufficient permissions as part of conditionally making the update. Updates of the A bit may be - performed as a result of speculation, but updates to the D bit must be exact - (i.e., non-speculative), and observed in program order by the local hart. When - two-stage address translation is active, updates of the D bit in G-stage PTEs - may be performed as a result of speculative updates of the A bit in VS-stage - PTEs. + + performed as a result of speculation, even if the associated memory access + ultimately is not performed architecturally. However, updates to the D bit, + resulting from an explicit store, must be exact (i.e., non-speculative), and + observed in program order by the local hart. When two-stage address + translation is active, updates of the D bit in G-stage PTEs may be performed + as a result of speculative updates of the A bit in VS-stage PTEs. + + The PTE update must appear in the global memory order before the memory access that caused the PTE update and before any subsequent explicit memory access to @@ -40,6 +41,9 @@ A/D bits. The A and D bits are managed by these extensions as follows: [NOTE] ==== +The PTE updates due to memory accesses ordered-after a FENCE are not themselves +ordered by the FENCE. + Simpler implementations that cannot precisely order the PTE update before subsequent explicit memory accesses to the associated virtual page by the local hart may simply order the PTE update before all subsequent explicit memory