From 61d71c176ab222c51c70388b72733d842760ef9c Mon Sep 17 00:00:00 2001 From: eckhard-delfs-qualcomm <140648031+eckhard-delfs-qualcomm@users.noreply.github.com> Date: Fri, 4 Oct 2024 19:34:15 +0200 Subject: [PATCH 1/3] SFENCE.VMA description As suggested by ved in https://github.com/riscv/riscv-smmtt/issues/72 Signed-off-by: eckhard-delfs-qualcomm <140648031+eckhard-delfs-qualcomm@users.noreply.github.com> --- chapter3.adoc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/chapter3.adoc b/chapter3.adoc index c942741..44de528 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -188,8 +188,15 @@ respective sections in this specification. The `MFENCE.SPA` fence instruction is used to synchronize updates to supervisor domain access-permissions with current execution. `MFENCE.SPA` is only valid in M-mode. If operand rs1≠x0, it -specifies a single physical address, and if rs2≠x0, it specifies -a single SDID. Executing a `MFENCE.SPA` guarantees that any previous stores +specifies a single physical address, and if rs2≠x0, it specifies a single SDID. +The behavior of `MFENCE.SPA` depends on rs1 and rs2 as follows: + +* If rs1=x0 and rs2=x0, the fence orders all reads and writes to the MTT for all supervisor domain address spaces. +* If rs1=x0 and rs2≠x0, the fence orders all reads and writes to the MTT for the supervisor domain address space identified by the SDID in rs2. +* If rs1≠x0 and rs2=x0, the fence orders all reads and writes made to the MTT that correspond to the physical address in rs1, for all supervisor domain address spaces. +* If rs1≠x0 and rs2≠x0, the fence orders all reads and writes made to the MTT that correspond to the physical address in rs1, for the supervisor domain address space identified by the SDID in rs2. + +Executing a `MFENCE.SPA` guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by that hart done for supervisor domain access-permission structures for non-M-mode instructions that follow the `MFENCE.SPA`. From f13c3950646af681fb9b99c8e87217cc907c166a Mon Sep 17 00:00:00 2001 From: eckhard-delfs-qualcomm <140648031+eckhard-delfs-qualcomm@users.noreply.github.com> Date: Mon, 7 Oct 2024 18:42:15 +0200 Subject: [PATCH 2/3] Update chapter3.adoc line breaks inserted Signed-off-by: eckhard-delfs-qualcomm <140648031+eckhard-delfs-qualcomm@users.noreply.github.com> --- chapter3.adoc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/chapter3.adoc b/chapter3.adoc index 44de528..d47b765 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -191,10 +191,16 @@ domain access-permissions with current execution. specifies a single physical address, and if rs2≠x0, it specifies a single SDID. The behavior of `MFENCE.SPA` depends on rs1 and rs2 as follows: -* If rs1=x0 and rs2=x0, the fence orders all reads and writes to the MTT for all supervisor domain address spaces. -* If rs1=x0 and rs2≠x0, the fence orders all reads and writes to the MTT for the supervisor domain address space identified by the SDID in rs2. -* If rs1≠x0 and rs2=x0, the fence orders all reads and writes made to the MTT that correspond to the physical address in rs1, for all supervisor domain address spaces. -* If rs1≠x0 and rs2≠x0, the fence orders all reads and writes made to the MTT that correspond to the physical address in rs1, for the supervisor domain address space identified by the SDID in rs2. +* If rs1=x0 and rs2=x0, the fence orders all reads and writes to the MTT for +all supervisor domain address spaces. +* If rs1=x0 and rs2≠x0, the fence orders all reads and writes to the MTT for +the supervisor domain address space identified by the SDID in rs2. +* If rs1≠x0 and rs2=x0, the fence orders all reads and writes made to the MTT +that correspond to the physical address in rs1, for all supervisor domain +address spaces. +* If rs1≠x0 and rs2≠x0, the fence orders all reads and writes made to the MTT +that correspond to the physical address in rs1, for the supervisor domain +address space identified by the SDID in rs2. Executing a `MFENCE.SPA` guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by From 2acd3ad2ddb6119090b2a99bc9553f71fb6b8627 Mon Sep 17 00:00:00 2001 From: Ravi Sahita Date: Tue, 8 Oct 2024 20:24:07 -0700 Subject: [PATCH 3/3] Apply suggestions from PR review Signed-off-by: Ravi Sahita --- chapter3.adoc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/chapter3.adoc b/chapter3.adoc index d47b765..d7745ed 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -189,6 +189,12 @@ The `MFENCE.SPA` fence instruction is used to synchronize updates to supervisor domain access-permissions with current execution. `MFENCE.SPA` is only valid in M-mode. If operand rs1≠x0, it specifies a single physical address, and if rs2≠x0, it specifies a single SDID. + +If rs1 corresponds to an `MTT_L1_DIR` mapping, the fence applies to +a 4 KiB page. If rs1 corresponds to a `2M_PAGES` or `4M_PAGES` mapping, +the fence applies to a 2 MiB or 4 MiB range. If rs1 corresponds to one +of the 1G_* mappings, the fence applies to a 1 GiB range. + The behavior of `MFENCE.SPA` depends on rs1 and rs2 as follows: * If rs1=x0 and rs2=x0, the fence orders all reads and writes to the MTT for