diff --git a/src/images/wavedrom/cr-registers-new.edn b/src/images/wavedrom/cr-registers-new.edn deleted file mode 100644 index 05331c82..00000000 --- a/src/images/wavedrom/cr-registers-new.edn +++ /dev/null @@ -1,62 +0,0 @@ -[wavedrom, ,svg] -.... -### CR : Register -${wd({reg: [ - {bits: 2, name: 'op' }, - {bits: 5, name: 'rs2' }, - {bits: 5, name: 'rd / rs1ʹ }, - {bits: 4, name: 'funct4' }, - - {bits: 2, name: 'op' }, - {bits: 5, name: 'imm' }, - {bits: 5, name: 'rd / rs1' }, - {bits: 1, name: 'imm' }, - {bits: 3, name: 'funct3' }, - - {bits: 2, name: 'op' }, - {bits: 5, name: 'rs2' }, - {bits: 6, name: 'imm' }, - {bits: 3, name: 'funct3' }, - - {bits: 2, name: 'op' }, - {bits: 3, name: 'rdʹ' }, - {bits: 8, name: 'imm' }, - {bits: 3, name: 'funct3' }, - - {bits: 2, name: 'op' }, - {bits: 3, name: 'rdʹ' }, - {bits: 2, name: 'imm' }, - {bits: 3, name: 'rs1ʹ' }, - {bits: 3, name: 'imm' }, - {bits: 3, name: 'funct3' }, - - {bits: 2, name: 'op' }, - {bits: 3, name: 'rs2ʹ' }, - {bits: 2, name: 'imm' }, - {bits: 3, name: 'rs1ʹ' }, - {bits: 3, name: 'imm' }, - {bits: 3, name: 'funct3' }, - - {bits: 2, name: 'op' }, - {bits: 3, name: 'rs2ʹ' }, - {bits: 2, name: 'funct2' }, - {bits: 3, name: 'rd` / rs1ʹ' }, - {bits: 6, name: 'funct6' }, - - {bits: 2, name: 'op' }, - {bits: 5, name: 'offset' }, - {bits: 3, name: 'rd` / rs1ʹ' }, - {bits: 3, name: 'offset' }, - {bits: 3, name: 'funct3' }, - - {bits: 2, name: 'op' }, - {bits: 11, name: 'jump target' }, - {bits: 3, name: 'funct3' }, -], config: { - hflip: true, - compact: true, - bits: 16 * 9, lanes: 9, - margin: {right: width / 4}, - label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']} -}})} -.... diff --git a/src/images/wavedrom/fnmaddsub.edn b/src/images/wavedrom/fnmaddsub.edn deleted file mode 100644 index ce63985c..00000000 --- a/src/images/wavedrom/fnmaddsub.edn +++ /dev/null @@ -1,16 +0,0 @@ - -//FNMSUP and FNMADD - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, - {bits: 5, name: 'rd', attr: 'dest'}, - {bits: 3, name: 'funct3', attr: 'RM'}, - {bits: 5, name: 'rs1', attr: 'src1'}, - {bits: 5, name: 'rs2', attr: 'src2'}, - {bits: 2, name: 'fmt', attr: 'S'}, - {bits: 5, name: 'rs3', attr: 'src3'}, -]} -.... - diff --git a/src/images/wavedrom/half-store.edn b/src/images/wavedrom/half-store.edn deleted file mode 100644 index bdb9058e..00000000 --- a/src/images/wavedrom/half-store.edn +++ /dev/null @@ -1,11 +0,0 @@ -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: 'STORE-FP'}, - {bits: 5, name: 'imm[4:0]', attr: 'offset'}, - {bits: 3, name: 'width', attr: 'H'}, - {bits: 5, name: 'rs1', attr: 'base'}, - {bits: 5, name: 'rs2', attr: 'src'}, - {bits: 12, name: 'imm[11:5]', attr: 'offset'}, -]} -.... \ No newline at end of file diff --git a/src/images/wavedrom/hint-nopv_rv32i.edn b/src/images/wavedrom/hint-nopv_rv32i.edn deleted file mode 100644 index b26a6d1f..00000000 --- a/src/images/wavedrom/hint-nopv_rv32i.edn +++ /dev/null @@ -1,55 +0,0 @@ -//### RV32I -//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9) -//{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} ) -[wavedrom, ,svg] -.... -{reg: [ - {name: 'OP-IMM', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']}, - {bits: 17} -], config: {hspace: width}} -.... -//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-IMM', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']}, - {bits: 10}, - {name: 'imm?', bits: 7, attr: [0, 0, 32]} -], config: {hspace: width}} -.... -//{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'opcode', bits: 7, attr: ['AUIPC', 'LUI']}, - {name: 'rd', bits: 5, attr: 0}, - {bits: 20} -], config: {hspace: width}} -.... -//{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP', bits: 7, attr: 0b0110011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ', - {bits: 10}, - {name: 'funct7', bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]} -], config: {hspace: width}} -.... - -//RV32I_extra = ( -// 3 * 31 + -// 31 + -// 7 * 31 + -// 3 * 31 + -// 2 * 31 -//) - diff --git a/src/images/wavedrom/hint-nopv_rv64i.edn b/src/images/wavedrom/hint-nopv_rv64i.edn deleted file mode 100644 index ee78cf8d..00000000 --- a/src/images/wavedrom/hint-nopv_rv64i.edn +++ /dev/null @@ -1,57 +0,0 @@ -//### RV64I -//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4) -//All RV32I NOPs plus: -//ADDIW x0, ? ( ${ 1 << 17 } ) -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-IMM-32', bits: 7, attr: 0b0011011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: 'ADDIW'}, - {bits: 17} -], config: {hspace: width}} -.... -//Extra bit for the shift ammont: -//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg: [ - {name: 'OP-IMM', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']}, - {bits: 10}, - {name: 'imm?', bits: 7, attr: [1, 33, 33]} -], config: {hspace: width}} -.... -//{SLLIW, SRLIW, SRAIW} x0, ?( ${ 3 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-IMM-32', bits: 7, attr: 0b0011011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['SLLIW', 'SRLIW', 'SRAIW']}, - {bits: 10}, - {name: 'imm?', bits: 7, attr: [0, 32, 32]} -], config: {hspace: width}} -.... -//SLL, SLT, SRA ( ??? ) -//{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ? ( ${ 5 * 1 << 10 } ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-32', bits: 7, attr: 0b0111011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']}, - {bits: 10}, - {name: 'funct7', bits: 7, attr: [0, 0, 32, 0, 32]} -], config: {hspace: width}} -.... - -//RV64I_extra = ( -// 4 * 31 + -// 5 * 31 + -// 31 -//` diff --git a/src/images/wavedrom/immediate_variants2.adoc b/src/images/wavedrom/immediate_variants2.adoc deleted file mode 100644 index 05402be8..00000000 --- a/src/images/wavedrom/immediate_variants2.adoc +++ /dev/null @@ -1,56 +0,0 @@ -## 2.3 Immediate Encoding Variants -### Figure 2.3 - -RISC-V base instruction formats showing immediate variants. - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 7, name: 'funct7'} -], config: {label: {right: 'R-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 12, name: 'imm[11:0]'}, -], config: {label: {right: 'I-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'imm[4:0]'}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 7, name: 'imm[11:5]'} -], config: {label: {right: 'S-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 1, name: '[11]'}, - {bits: 4, name: 'imm[4:1]'}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 6, name: 'imm[10:5]'}, - {bits: 1, name: '[12]'} -], config: {label: {right: 'B-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 20, name: 'imm[31:12]'} -], config: {label: {right: 'U-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 8, name: 'imm[19:12]'}, - {bits: 1, name: '[11]'}, - {bits: 10, name: 'imm[10:1]'}, - {bits: 1, name: '[20]'} -], config: {label: {right: 'J-Type'}}})} \ No newline at end of file diff --git a/src/images/wavedrom/nop-v.edn b/src/images/wavedrom/nop-v.edn deleted file mode 100644 index 0c990e46..00000000 --- a/src/images/wavedrom/nop-v.edn +++ /dev/null @@ -1,29 +0,0 @@ -//# NOP-V - -The RISC-V [User-Level ISA Specification](https://riscv.org/specifications/) defines NOP instruction as follows: - -* The NOP instruction does not change any user-visible state, except for advancing the pc. -* NOP is encoded as \`ADDI x0, x0, 0\`. - -[wavedrom, , ] ----- -{reg:[ - {name: 'opcode', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: 0}, - {name: 'rs1', bits: 5, attr: 0}, - {name: 'imm', bits: 12, attr: 0} -], config: {hspace: width}} ----- - - -NOTE: NOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although **there are many possible ways** to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output. - -How many other possible ways to encode NOP? ----- -rd = 0 ----- - -Any Integer Computational instruction writing into \`x0\` is NOP. - -` diff --git a/src/images/wavedrom/sploat2.adoc b/src/images/wavedrom/sploat2.adoc deleted file mode 100644 index e69de29b..00000000 diff --git a/src/images/wavedrom/zifencei-fetch.edn b/src/images/wavedrom/zifencei-fetch.edn deleted file mode 100644 index 660c1349..00000000 --- a/src/images/wavedrom/zifencei-fetch.edn +++ /dev/null @@ -1,12 +0,0 @@ -//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0 - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: 'MISC-MEM'}, - {bits: 5, name: 'rd', attr: 0}, - {bits: 3, name: 'funct3', attr: 'FENCE.I'}, - {bits: 5, name: 'rs1', attr: 0}, - {bits: 12, name: 'func12', attr: 0}, -]} -....