diff --git a/StarFive/Dubhe-90-2023-12-14/Dubhe-90-2023-12-14-notes.txt b/StarFive/Dubhe-90-2023-12-14/Dubhe-90-2023-12-14-notes.txt new file mode 100644 index 0000000..d24052b --- /dev/null +++ b/StarFive/Dubhe-90-2023-12-14/Dubhe-90-2023-12-14-notes.txt @@ -0,0 +1,23 @@ +CPU: Dubhe-90 +bit_date: 20231027 +bit_commit: fd548641dc49fd8d2a4d4a423eac76a41b0111ed +bit_branch: lsu_re + +Toolchain: 2023.12.14 +Toolchain_commit: 99e2d2bac5144f5152ba6d3fbf04bdd9b9ba4381 +Toolchain_path: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.12.14/riscv64-glibc-ubuntu-20.04-llvm-nightly-2023.12.14-nightly.tar.gz + +ref_model: spike +ref_mode_commit: a729aff03d0a1bd8fa179f636b4b5f21da28b75b +ref_mode_commit_date: 2023 Dec 11 GMT+8 +ref_model_path: https://github.com/riscv-software-src/riscv-isa-sim.git + +ACT_framework: riscof 1.25.3 +ACT_commit: a25e3155d3a62a042a2c5d976b386e3df5874d70 +ACT_commit_date: 2023 Jan 30 GMT+8 +ACT_path: https://github.com/riscv/riscof.git + +riscv-arch-test: 3.8.0 +riscv-arch-test_commit: f484d91992a438870f2412ea6d1219631f40b6c0 +riscv-arch-test_commit_date: 2023 Oct 27 GMT+8 +riscv-arch-test_path: https://github.com/riscv-non-isa/riscv-arch-test.git diff --git a/StarFive/Dubhe-90-2023-12-14/Dubhe-90_isa.yaml b/StarFive/Dubhe-90-2023-12-14/Dubhe-90_isa.yaml new file mode 100755 index 0000000..4143034 --- /dev/null +++ b/StarFive/Dubhe-90-2023-12-14/Dubhe-90_isa.yaml @@ -0,0 +1,73 @@ +hart_ids: [0] +hart0: + ISA: RV64IMAFDCSHUZicsr_Zicntr_Zifencei_Zihintpause_Zba_Zbb_Zbc_Zbs + physical_addr_sz: 56 + User_Spec_Version: '2.2' + supported_xlen: [64] + misa: + reset-val: 0x80000000001411AD + rv64: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x2] + wr_illegal: + - Unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] bitmask [0x01411AD, 0x0000000] + wr_illegal: + - Unchanged + mvendorid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + address: 3857 + priv_mode: M + reset-val: 0 + marchid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + ro_constant: 0 + address: 3858 + priv_mode: M + reset-val: 0 + mimpid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + ro_constant: 0 + address: 3859 + priv_mode: M + reset-val: 0 diff --git a/StarFive/Dubhe-90-2023-12-14/Dubhe-90_isa_checked.yaml b/StarFive/Dubhe-90-2023-12-14/Dubhe-90_isa_checked.yaml new file mode 100755 index 0000000..ff19008 --- /dev/null +++ b/StarFive/Dubhe-90-2023-12-14/Dubhe-90_isa_checked.yaml @@ -0,0 +1,5167 @@ +hart_ids: [0] +hart0: + ISA: RV64IMAFDCSHUZicsr_Zicntr_Zifencei_Zihintpause_Zba_Zbb_Zbc_Zbs + physical_addr_sz: 56 + User_Spec_Version: '2.2' + supported_xlen: + - 64 + misa: + reset-val: 0x80000000001411AD + rv32: + accessible: false + rv64: + accessible: true + fields: + - extensions + - mxl + - + - + - 26 + - 61 + mxl: + implemented: true + description: Encodes the native base integer ISA width. + shadow: + shadow_type: rw + msb: 63 + lsb: 62 + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x2] + wr_illegal: + - unchanged + extensions: + implemented: true + description: Encodes the presence of the standard extensions, with + a single bit per letter of the alphabet. + shadow: + shadow_type: rw + msb: 25 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] bitmask [0x1411AD, 0x00000000] + wr_illegal: + - unchanged + description: misa is a read-write register reporting the ISA supported by + the hart. + address: 769 + priv_mode: M + hstatus: + rv32: + accessible: false + rv64: + accessible: false + description: The hstatus register keeps track of and controls the hart’s current + operating state. + address: 1536 + priv_mode: H + reset-val: 1 + marchid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + ro_constant: 0 + address: 3858 + priv_mode: M + reset-val: 0 + description: MXLEN-bit read-only register encoding the base microarchitecture + of the hart. + mimpid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + ro_constant: 0 + address: 3859 + priv_mode: M + reset-val: 0 + description: Provides a unique encoding of the version of the processor implementation. + Privilege_Spec_Version: '1.10' + hw_data_misaligned_support: false + pmp_granularity: 0 + custom_exceptions: + custom_interrupts: + pte_ad_hw_update: false + mtval_update: 0b11111111 + mstatus: + rv32: + accessible: false + rv64: + accessible: true + fields: + - uie + - sie + - mie + - upie + - spie + - mpie + - spp + - mpp + - fs + - xs + - mprv + - sum + - mxr + - tvm + - tw + - tsr + - uxl + - sxl + - gva + - mpv + - sd + - + - + - 2 + - + - 6 + - + - 9 + - 10 + - + - 23 + - 31 + - + - 36 + - 37 + - + - 40 + - 62 + uie: + implemented: false + description: Stores the state of the user mode interrupts. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + sie: + implemented: true + description: Stores the state of the supervisor mode interrupts. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + type: + wlrl: + - 0:1 + mie: + implemented: true + description: Stores the state of the machine mode interrupts. + shadow: + shadow_type: rw + msb: 3 + lsb: 3 + type: + wlrl: + - 0:1 + upie: + implemented: false + description: Stores the state of the user mode interrupts prior to + the trap. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + spie: + implemented: true + description: Stores the state of the supervisor mode interrupts prior + to the trap. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + type: + wlrl: + - 0:1 + mpie: + implemented: true + description: Stores the state of the machine mode interrupts prior + to the trap. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + type: + wlrl: + - 0:1 + spp: + implemented: true + description: Stores the previous priority mode for supervisor. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + type: {ro_constant: 0} + mpp: + implemented: true + description: Stores the previous priority mode for machine. + shadow: + shadow_type: rw + msb: 12 + lsb: 11 + type: {ro_constant: 0} + fs: + implemented: true + description: Encodes the status of the floating-point unit, including + the CSR fcsr and floating-point data registers. + shadow: + shadow_type: rw + msb: 14 + lsb: 13 + type: + warl: + dependency_fields: [] + legal: + - fs[1:0] in [0x0:0x3] + wr_illegal: + - unchanged + xs: + implemented: false + description: Encodes the status of additional user-mode extensions + and associated state. + shadow: + shadow_type: rw + msb: 16 + lsb: 15 + mprv: + implemented: true + description: Modifies the privilege level at which loads and stores + execute in all privilege modes. + shadow: + shadow_type: rw + msb: 17 + lsb: 17 + type: + warl: + dependency_fields: [] + legal: + - mprv[0] in [0x0] + wr_illegal: + - unchanged + sum: + implemented: true + description: Modifies the privilege with which S-mode loads and stores + access virtual memory. + shadow: + shadow_type: rw + msb: 18 + lsb: 18 + type: + warl: + dependency_fields: [] + legal: + - sum[0] in [0x0] + wr_illegal: + - unchanged + mxr: + implemented: true + description: Modifies the privilege with which loads access virtual + memory. + shadow: + shadow_type: rw + msb: 19 + lsb: 19 + type: + warl: + dependency_fields: [] + legal: + - mxr[0] in [0x0] + wr_illegal: + - unchanged + tvm: + implemented: true + description: Supports intercepting supervisor virtual-memory management + operations. + shadow: + shadow_type: rw + msb: 20 + lsb: 20 + type: + warl: + dependency_fields: [] + legal: + - tvm[0] in [0x0] + wr_illegal: + - unchanged + tw: + implemented: true + description: Supports intercepting the WFI instruction. + shadow: + shadow_type: rw + msb: 21 + lsb: 21 + type: {ro_constant: 0} + tsr: + implemented: true + description: Supports intercepting the supervisor exception return + instruction. + shadow: + shadow_type: rw + msb: 22 + lsb: 22 + type: + warl: + dependency_fields: [] + legal: + - tsr[0] in [0x0] + wr_illegal: + - unchanged + sxl: + implemented: true + description: Controls the value of xlen for Supervisor mode. + shadow: + shadow_type: rw + msb: 35 + lsb: 34 + type: {ro_constant: 2} + uxl: + implemented: true + description: Controls the xlen for User mode. + shadow: + shadow_type: rw + msb: 33 + lsb: 32 + type: {ro_constant: 2} + gva: + implemented: true + description: For any trap (access fault, page fault, or guest-page + fault) that writes a guest virtual address to mtval, GVA is set + to 1. + shadow: + shadow_type: rw + msb: 38 + lsb: 38 + type: {ro_constant: 0} + mpv: + implemented: true + description: Machine Previous Virtualization Mode is written by the + implementation whenever a trap is taken into M-mode. + shadow: + shadow_type: rw + msb: 39 + lsb: 39 + type: {ro_constant: 0} + sd: + implemented: true + description: Read-only bit that summarizes whether either the FS field + or XS field signals the presence of some dirty state. + shadow: + shadow_type: rw + msb: 63 + lsb: 63 + type: + wlrl: + - 0:1 + description: The mstatus register keeps track of and controls the hart’s current + operating state. + address: 768 + priv_mode: M + reset-val: 42949672960 + mstatush: + rv32: + accessible: false + rv64: + accessible: false + description: The mstatush register keeps track of and controls the hart’s + current operating state. + address: 768 + priv_mode: M + reset-val: 0 + mvendorid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + description: 32-bit read-only register providing the JEDEC manufacturer ID + of the provider of the core. + address: 3857 + priv_mode: M + reset-val: 0 + mhartid: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + ro_constant: 0 + description: MXLEN-bit read-only register containing the integer ID of the + hardware thread running the code. + address: 3860 + priv_mode: M + reset-val: 0 + mtvec: + rv32: + accessible: false + rv64: + accessible: true + fields: + - mode + - base + base: + implemented: true + description: Vector base address. + shadow: + shadow_type: rw + msb: 63 + lsb: 2 + type: + warl: + dependency_fields: [] + legal: + - base[61:0] bitmask [0x3FFFFFFFFFFFFFFF, 0x0000000000000000] + wr_illegal: + - Unchanged + mode: + implemented: true + description: Vector mode. + shadow: + shadow_type: rw + msb: 1 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mode[1:0] in [0x0:0x1] + wr_illegal: + - Unchanged + description: MXLEN-bit read/write register that holds trap vector configuration. + address: 773 + priv_mode: M + reset-val: 0 + mideleg: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mideleg[63:0] bitmask [0x000000000000F7FF,0x0000000000000000] + wr_illegal: + - Unchanged + description: Machine Interrupt delegation Register. + address: 771 + priv_mode: M + reset-val: 0 + medeleg: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - medeleg[63:0] bitmask [0x000000000000F7FF,0x0000000000000000] + wr_illegal: + - Unchanged + description: Machine Exception delegation Register. + address: 770 + priv_mode: M + reset-val: 0 + mip: + rv32: + accessible: false + rv64: + accessible: true + fields: + - usip + - ssip + - vssip + - msip + - utip + - stip + - vstip + - mtip + - ueip + - seip + - vseip + - meip + - sgeip + - + - + - 13 + - 63 + usip: + implemented: false + description: User Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + ssip: + implemented: true + description: Supervisor Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + type: + wlrl: + - 0:1 + vssip: + implemented: true + description: VS-level Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 2 + lsb: 2 + type: + warl: + dependency_fields: [] + legal: + - vssip[0] in [0x0, 0x1] + wr_illegal: + - unchanged + msip: + implemented: true + description: Machine Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 3 + lsb: 3 + type: + ro_variable: true + utip: + implemented: false + description: User Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + stip: + implemented: true + description: Supervisor Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + type: + wlrl: + - 0:1 + vstip: + implemented: true + description: VS-level Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 6 + lsb: 6 + type: + warl: + dependency_fields: [] + legal: + - vstip[0] in [0x0, 0x1] + wr_illegal: + - unchanged + mtip: + implemented: true + description: Machine Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + type: + ro_variable: true + ueip: + implemented: false + description: User External Interrupt Pending. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + seip: + implemented: true + description: Supervisor External Interrupt Pending. + shadow: + shadow_type: rw + msb: 9 + lsb: 9 + type: + wlrl: + - 0:1 + vseip: + implemented: true + description: VS-level External Interrupt Pending. + shadow: + shadow_type: rw + msb: 10 + lsb: 10 + type: + warl: + dependency_fields: [] + legal: + - vseip[0] in [0x0, 0x1] + wr_illegal: + - unchanged + meip: + implemented: true + description: Machine External Interrupt Pending. + shadow: + shadow_type: rw + msb: 11 + lsb: 11 + type: + ro_variable: true + sgeip: + implemented: true + description: HS-level External Interrupt Pending. + shadow: + shadow_type: rw + msb: 12 + lsb: 12 + type: + warl: + dependency_fields: [] + legal: + - sgeip[0] in [0x0, 0x1] + wr_illegal: + - unchanged + description: The mip register is an MXLEN-bit read/write register containing + information on pending interrupts. + address: 836 + priv_mode: M + reset-val: 0 + hie: + rv32: + accessible: false + rv64: + accessible: true + fields: + - vssie + - vstie + - vseie + - sgeie + - + - + - 0 + - 1 + - + - 3 + - 5 + - + - 7 + - 9 + - + - 11 + - + - 13 + - 63 + vssie: + implemented: false + description: VS-level Software Interrupt enable. + shadow: mie.vssie + shadow_type: rw + msb: 2 + lsb: 2 + vstie: + implemented: false + description: VS-level Timer Interrupt enable. + shadow: mie.vstie + shadow_type: rw + msb: 6 + lsb: 6 + vseie: + implemented: false + description: VS-level External Interrupt enable. + shadow: mie.vseie + shadow_type: rw + msb: 10 + lsb: 10 + sgeie: + implemented: true + description: HS-level External Interrupt enable. + shadow: mie.sgeie + shadow_type: rw + msb: 12 + lsb: 12 + type: + warl: + dependency_fields: [] + legal: + - sgeie[0] in [0x0, 0x1] + wr_illegal: + - unchanged + description: The hie register is an HSXLEN-bit read/write register containing + interrupt enable bits. + address: 0x604 + priv_mode: H + reset-val: 0 + mie: + rv32: + accessible: false + rv64: + accessible: true + fields: + - usie + - ssie + - vssie + - msie + - utie + - stie + - vstie + - mtie + - ueie + - seie + - vseie + - meie + - sgeie + - + - + - 13 + - 63 + usie: + implemented: false + description: User Software Interrupt enable. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + ssie: + implemented: true + description: Supervisor Software Interrupt enable. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + type: + wlrl: + - 0:1 + vssie: + implemented: true + description: VS-level Software Interrupt enable. + shadow: + shadow_type: rw + msb: 2 + lsb: 2 + type: + warl: + dependency_fields: [] + legal: + - vssie[0] in [0x0, 0x1] + wr_illegal: + - unchanged + msie: + implemented: true + description: Machine Software Interrupt enable. + shadow: + shadow_type: rw + msb: 3 + lsb: 3 + type: + wlrl: + - 0x0:0x1 + utie: + implemented: false + description: User Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + stie: + implemented: true + description: Supervisor Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + type: + wlrl: + - 0:1 + vstie: + implemented: true + description: VS-level Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 6 + lsb: 6 + type: + warl: + dependency_fields: [] + legal: + - vstie[0] in [0x0, 0x1] + wr_illegal: + - unchanged + mtie: + implemented: true + description: Machine Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + type: + wlrl: + - 0:1 + ueie: + implemented: false + description: User External Interrupt enable. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + seie: + implemented: true + description: Supervisor External Interrupt enable. + shadow: + shadow_type: rw + msb: 9 + lsb: 9 + type: + wlrl: + - 0:1 + vseie: + implemented: true + description: VS-level External Interrupt enable. + shadow: + shadow_type: rw + msb: 10 + lsb: 10 + type: + warl: + dependency_fields: [] + legal: + - vseie[0] in [0x0, 0x1] + wr_illegal: + - unchanged + meie: + implemented: true + description: Machine External Interrupt enable. + shadow: + shadow_type: rw + msb: 11 + lsb: 11 + type: + wlrl: + - 0:1 + sgeie: + implemented: true + description: HS-level External Interrupt enable. + shadow: + shadow_type: rw + msb: 12 + lsb: 12 + type: + warl: + dependency_fields: [] + legal: + - sgeie[0] in [0x0, 0x1] + wr_illegal: + - unchanged + description: The mie register is an MXLEN-bit read/write register containing + interrupt enable bits. + address: 772 + priv_mode: M + reset-val: 0 + mscratch: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + + description: The mscratch register is an MXLEN-bit read/write register dedicated + for use by machine mode. + address: 832 + priv_mode: M + reset-val: 0 + mepc: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The mepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x341 + priv_mode: M + reset-val: 0 + mtval: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mtval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The mtval is a warl register that holds the address of the instruction + which caused the exception. + address: 835 + priv_mode: M + reset-val: 0 + mcause: + rv32: + accessible: false + rv64: + accessible: true + fields: + - exception_code + - interrupt + interrupt: + implemented: true + description: Indicates whether the trap was due to an interrupt. + shadow: + shadow_type: rw + msb: 63 + lsb: 63 + type: + wlrl: + - 0:1 + exception_code: + implemented: true + description: Encodes the exception code. + shadow: + shadow_type: rw + msb: 62 + lsb: 0 + type: + wlrl: + - 0:15 + description: The mcause register stores the information regarding the trap. + address: 834 + priv_mode: M + reset-val: 0 + pmpcfg0: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A0 + priv_mode: M + reset-val: 0 + pmpcfg1: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A1 + priv_mode: M + reset-val: 0 + pmpcfg2: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A2 + priv_mode: M + reset-val: 0 + pmpcfg3: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A3 + priv_mode: M + reset-val: 0 + pmpcfg4: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A4 + priv_mode: M + reset-val: 0 + pmpcfg5: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A5 + priv_mode: M + reset-val: 0 + pmpcfg6: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A6 + priv_mode: M + reset-val: 0 + pmpcfg7: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A7 + priv_mode: M + reset-val: 0 + pmpcfg8: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A8 + priv_mode: M + reset-val: 0 + pmpcfg9: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A9 + priv_mode: M + reset-val: 0 + pmpcfg10: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AA + priv_mode: M + reset-val: 0 + pmpcfg11: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AB + priv_mode: M + reset-val: 0 + pmpcfg12: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AC + priv_mode: M + reset-val: 0 + pmpcfg13: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AD + priv_mode: M + reset-val: 0 + pmpcfg14: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AE + priv_mode: M + reset-val: 0 + pmpcfg15: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AF + priv_mode: M + reset-val: 0 + pmpaddr0: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B0 + priv_mode: M + reset-val: 0 + pmpaddr1: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B1 + priv_mode: M + reset-val: 0 + pmpaddr2: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B2 + priv_mode: M + reset-val: 0 + pmpaddr3: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B3 + priv_mode: M + reset-val: 0 + pmpaddr4: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B4 + priv_mode: M + reset-val: 0 + pmpaddr5: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B5 + priv_mode: M + reset-val: 0 + pmpaddr6: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B6 + priv_mode: M + reset-val: 0 + pmpaddr7: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B7 + priv_mode: M + reset-val: 0 + pmpaddr8: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B8 + priv_mode: M + reset-val: 0 + pmpaddr9: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B9 + priv_mode: M + reset-val: 0 + pmpaddr10: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BA + priv_mode: M + reset-val: 0 + pmpaddr11: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BB + priv_mode: M + reset-val: 0 + pmpaddr12: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BC + priv_mode: M + reset-val: 0 + pmpaddr13: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BD + priv_mode: M + reset-val: 0 + pmpaddr14: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BE + priv_mode: M + reset-val: 0 + pmpaddr15: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BF + priv_mode: M + reset-val: 0 + pmpaddr16: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C0 + priv_mode: M + reset-val: 0 + pmpaddr17: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C1 + priv_mode: M + reset-val: 0 + pmpaddr18: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C2 + priv_mode: M + reset-val: 0 + pmpaddr19: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C3 + priv_mode: M + reset-val: 0 + pmpaddr20: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C4 + priv_mode: M + reset-val: 0 + pmpaddr21: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C5 + priv_mode: M + reset-val: 0 + pmpaddr22: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C6 + priv_mode: M + reset-val: 0 + pmpaddr23: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C7 + priv_mode: M + reset-val: 0 + pmpaddr24: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C8 + priv_mode: M + reset-val: 0 + pmpaddr25: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C9 + priv_mode: M + reset-val: 0 + pmpaddr26: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CA + priv_mode: M + reset-val: 0 + pmpaddr27: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CB + priv_mode: M + reset-val: 0 + pmpaddr28: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CC + priv_mode: M + reset-val: 0 + pmpaddr29: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CD + priv_mode: M + reset-val: 0 + pmpaddr30: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CE + priv_mode: M + reset-val: 0 + pmpaddr31: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CF + priv_mode: M + reset-val: 0 + pmpaddr32: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D0 + priv_mode: M + reset-val: 0 + pmpaddr33: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D1 + priv_mode: M + reset-val: 0 + pmpaddr34: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D2 + priv_mode: M + reset-val: 0 + pmpaddr35: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D3 + priv_mode: M + reset-val: 0 + pmpaddr36: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D4 + priv_mode: M + reset-val: 0 + pmpaddr37: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D5 + priv_mode: M + reset-val: 0 + pmpaddr38: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D6 + priv_mode: M + reset-val: 0 + pmpaddr39: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D7 + priv_mode: M + reset-val: 0 + pmpaddr40: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D8 + priv_mode: M + reset-val: 0 + pmpaddr41: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D9 + priv_mode: M + reset-val: 0 + pmpaddr42: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DA + priv_mode: M + reset-val: 0 + pmpaddr43: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DB + priv_mode: M + reset-val: 0 + pmpaddr44: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DC + priv_mode: M + reset-val: 0 + pmpaddr45: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DD + priv_mode: M + reset-val: 0 + pmpaddr46: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DE + priv_mode: M + reset-val: 0 + pmpaddr47: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DF + priv_mode: M + reset-val: 0 + pmpaddr48: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E0 + priv_mode: M + reset-val: 0 + pmpaddr49: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E1 + priv_mode: M + reset-val: 0 + pmpaddr50: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E2 + priv_mode: M + reset-val: 0 + pmpaddr51: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E3 + priv_mode: M + reset-val: 0 + pmpaddr52: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E4 + priv_mode: M + reset-val: 0 + pmpaddr53: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E5 + priv_mode: M + reset-val: 0 + pmpaddr54: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E6 + priv_mode: M + reset-val: 0 + pmpaddr55: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E7 + priv_mode: M + reset-val: 0 + pmpaddr56: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E8 + priv_mode: M + reset-val: 0 + pmpaddr57: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E9 + priv_mode: M + reset-val: 0 + pmpaddr58: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EA + priv_mode: M + reset-val: 0 + pmpaddr59: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EB + priv_mode: M + reset-val: 0 + pmpaddr60: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EC + priv_mode: M + reset-val: 0 + pmpaddr61: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3ED + priv_mode: M + reset-val: 0 + pmpaddr62: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EE + priv_mode: M + reset-val: 0 + pmpaddr63: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EF + priv_mode: M + reset-val: 0 + mcounteren: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + description: The mcounteren is a 32-bit register that controls the availability + of the hardware performance-monitoring counters to the next-lowest privileged + mode. + address: 0x306 + priv_mode: M + reset-val: 0 + mcountinhibit: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + description: The mcountinhibit is a 32-bit WARL register that controls which + of the hardware performance-monitoring counters increment. + address: 0x320 + priv_mode: M + reset-val: 0 + mcycle: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mcycle[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + description: Counts the number of clock cycles executed from an arbitrary + point in time. + address: 0xB00 + priv_mode: M + reset-val: 0 + mcycleh: + rv32: + accessible: false + rv64: + accessible: false + description: upper 32 bits of mcycle + address: 0xB80 + priv_mode: M + reset-val: 0 + minstret: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - minstret[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + description: Counts the number of instructions completed from an arbitrary + point in time. + address: 0xB02 + priv_mode: M + reset-val: 0 + minstreth: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32 bits of minstret. + address: 0xB82 + priv_mode: M + reset-val: 0 + mhpmevent3: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: &id001 + ro_constant: 0 + description: The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3. + address: 0x323 + priv_mode: M + reset-val: 0 + mhpmcounter3: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in + RV32I mode. + address: 0xB03 + priv_mode: M + reset-val: 0 + mhpmcounter3h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter3h returns the upper half word in RV32I systems. + address: 0xB83 + priv_mode: M + reset-val: 0 + mhpmevent4: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4. + address: 0x324 + priv_mode: M + reset-val: 0 + mhpmcounter4: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in + RV42I mode. + address: 0xB04 + priv_mode: M + reset-val: 0 + mhpmcounter4h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter4h returns the upper half word in RV42I systems. + address: 0xB84 + priv_mode: M + reset-val: 0 + mhpmevent5: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5. + address: 0x325 + priv_mode: M + reset-val: 0 + mhpmcounter5: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in + RV52I mode. + address: 0xB05 + priv_mode: M + reset-val: 0 + mhpmcounter5h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter5h returns the upper half word in RV52I systems. + address: 0xB85 + priv_mode: M + reset-val: 0 + mhpmevent6: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6. + address: 0x326 + priv_mode: M + reset-val: 0 + mhpmcounter6: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in + RV62I mode. + address: 0xB06 + priv_mode: M + reset-val: 0 + mhpmcounter6h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter6h returns the upper half word in RV62I systems. + address: 0xB86 + priv_mode: M + reset-val: 0 + mhpmevent7: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7. + address: 0x327 + priv_mode: M + reset-val: 0 + mhpmcounter7: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in + RV72I mode. + address: 0xB07 + priv_mode: M + reset-val: 0 + mhpmcounter7h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter7h returns the upper half word in RV72I systems. + address: 0xB87 + priv_mode: M + reset-val: 0 + mhpmevent8: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8. + address: 0x328 + priv_mode: M + reset-val: 0 + mhpmcounter8: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in + RV82I mode. + address: 0xB08 + priv_mode: M + reset-val: 0 + mhpmcounter8h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter8h returns the upper half word in RV82I systems. + address: 0xB88 + priv_mode: M + reset-val: 0 + mhpmevent9: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9. + address: 0x329 + priv_mode: M + reset-val: 0 + mhpmcounter9: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in + RV32I mode. + address: 0xB09 + priv_mode: M + reset-val: 0 + mhpmcounter9h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter9h returns the upper half word in RV32I systems. + address: 0xB89 + priv_mode: M + reset-val: 0 + mhpmevent10: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent10 is a MXLEN-bit event register which controls + mhpmcounter10. + address: 0x32a + priv_mode: M + reset-val: 0 + mhpmcounter10: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits + in RV102I mode. + address: 0xB0A + priv_mode: M + reset-val: 0 + mhpmcounter10h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter10h returns the upper half word in RV102I systems. + address: 0xB8A + priv_mode: M + reset-val: 0 + mhpmevent11: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent11 is a MXLEN-bit event register which controls + mhpmcounter11. + address: 0x32b + priv_mode: M + reset-val: 0 + mhpmcounter11: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits + in RV112I mode. + address: 0xB0B + priv_mode: M + reset-val: 0 + mhpmcounter11h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter11h returns the upper half word in RV112I systems. + address: 0xB8B + priv_mode: M + reset-val: 0 + mhpmevent12: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent12 is a MXLEN-bit event register which controls + mhpmcounter12. + address: 0x32c + priv_mode: M + reset-val: 0 + mhpmcounter12: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits + in RV122I mode. + address: 0xB0C + priv_mode: M + reset-val: 0 + mhpmcounter12h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter12h returns the upper half word in RV122I systems. + address: 0xB8C + priv_mode: M + reset-val: 0 + mhpmevent13: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent13 is a MXLEN-bit event register which controls + mhpmcounter13. + address: 0x32d + priv_mode: M + reset-val: 0 + mhpmcounter13: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits + in RV132I mode. + address: 0xB0D + priv_mode: M + reset-val: 0 + mhpmcounter13h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter13h returns the upper half word in RV132I systems. + address: 0xB8D + priv_mode: M + reset-val: 0 + mhpmevent14: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent14 is a MXLEN-bit event register which controls + mhpmcounter14. + address: 0x32e + priv_mode: M + reset-val: 0 + mhpmcounter14: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits + in RV142I mode. + address: 0xB0E + priv_mode: M + reset-val: 0 + mhpmcounter14h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter14h returns the upper half word in RV142I systems. + address: 0xB8E + priv_mode: M + reset-val: 0 + mhpmevent15: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent15 is a MXLEN-bit event register which controls + mhpmcounter15. + address: 0x32f + priv_mode: M + reset-val: 0 + mhpmcounter15: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits + in RV152I mode. + address: 0xB0F + priv_mode: M + reset-val: 0 + mhpmcounter15h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter15h returns the upper half word in RV152I systems. + address: 0xB8F + priv_mode: M + reset-val: 0 + mhpmevent16: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent16 is a MXLEN-bit event register which controls + mhpmcounter16. + address: 0x330 + priv_mode: M + reset-val: 0 + mhpmcounter16: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits + in RV162I mode. + address: 0xB10 + priv_mode: M + reset-val: 0 + mhpmcounter16h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter16h returns the upper half word in RV162I systems. + address: 0xB90 + priv_mode: M + reset-val: 0 + mhpmevent17: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent17 is a MXLEN-bit event register which controls + mhpmcounter17. + address: 0x331 + priv_mode: M + reset-val: 0 + mhpmcounter17: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits + in RV172I mode. + address: 0xB11 + priv_mode: M + reset-val: 0 + mhpmcounter17h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter17h returns the upper half word in RV172I systems. + address: 0xB91 + priv_mode: M + reset-val: 0 + mhpmevent18: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent18 is a MXLEN-bit event register which controls + mhpmcounter18. + address: 0x332 + priv_mode: M + reset-val: 0 + mhpmcounter18: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits + in RV182I mode. + address: 0xB12 + priv_mode: M + reset-val: 0 + mhpmcounter18h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter18h returns the upper half word in RV182I systems. + address: 0xB92 + priv_mode: M + reset-val: 0 + mhpmevent19: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent19 is a MXLEN-bit event register which controls + mhpmcounter19. + address: 0x333 + priv_mode: M + reset-val: 0 + mhpmcounter19: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits + in RV32I mode. + address: 0xB13 + priv_mode: M + reset-val: 0 + mhpmcounter19h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter19h returns the upper half word in RV32I systems. + address: 0xB93 + priv_mode: M + reset-val: 0 + mhpmevent20: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent20 is a MXLEN-bit event register which controls + mhpmcounter20. + address: 0x334 + priv_mode: M + reset-val: 0 + mhpmcounter20: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits + in RV202I mode. + address: 0xB14 + priv_mode: M + reset-val: 0 + mhpmcounter20h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter20h returns the upper half word in RV202I systems. + address: 0xB94 + priv_mode: M + reset-val: 0 + mhpmevent21: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent21 is a MXLEN-bit event register which controls + mhpmcounter21. + address: 0x335 + priv_mode: M + reset-val: 0 + mhpmcounter21: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits + in RV212I mode. + address: 0xB15 + priv_mode: M + reset-val: 0 + mhpmcounter21h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter21h returns the upper half word in RV212I systems. + address: 0xB95 + priv_mode: M + reset-val: 0 + mhpmevent22: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent22 is a MXLEN-bit event register which controls + mhpmcounter22. + address: 0x336 + priv_mode: M + reset-val: 0 + mhpmcounter22: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits + in RV222I mode. + address: 0xB16 + priv_mode: M + reset-val: 0 + mhpmcounter22h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter22h returns the upper half word in RV222I systems. + address: 0xB96 + priv_mode: M + reset-val: 0 + mhpmevent23: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent23 is a MXLEN-bit event register which controls + mhpmcounter23. + address: 0x337 + priv_mode: M + reset-val: 0 + mhpmcounter23: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits + in RV232I mode. + address: 0xB17 + priv_mode: M + reset-val: 0 + mhpmcounter23h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter23h returns the upper half word in RV232I systems. + address: 0xB97 + priv_mode: M + reset-val: 0 + mhpmevent24: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent24 is a MXLEN-bit event register which controls + mhpmcounter24. + address: 0x338 + priv_mode: M + reset-val: 0 + mhpmcounter24: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits + in RV242I mode. + address: 0xB18 + priv_mode: M + reset-val: 0 + mhpmcounter24h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter24h returns the upper half word in RV242I systems. + address: 0xB98 + priv_mode: M + reset-val: 0 + mhpmevent25: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent25 is a MXLEN-bit event register which controls + mhpmcounter25. + address: 0x339 + priv_mode: M + reset-val: 0 + mhpmcounter25: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits + in RV252I mode. + address: 0xB19 + priv_mode: M + reset-val: 0 + mhpmcounter25h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter25h returns the upper half word in RV252I systems. + address: 0xB99 + priv_mode: M + reset-val: 0 + mhpmevent26: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent26 is a MXLEN-bit event register which controls + mhpmcounter26. + address: 0x33a + priv_mode: M + reset-val: 0 + mhpmcounter26: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits + in RV262I mode. + address: 0xB1A + priv_mode: M + reset-val: 0 + mhpmcounter26h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter26h returns the upper half word in RV262I systems. + address: 0xB9A + priv_mode: M + reset-val: 0 + mhpmevent27: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent27 is a MXLEN-bit event register which controls + mhpmcounter27. + address: 0x33b + priv_mode: M + reset-val: 0 + mhpmcounter27: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits + in RV272I mode. + address: 0xB1B + priv_mode: M + reset-val: 0 + mhpmcounter27h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter27h returns the upper half word in RV272I systems. + address: 0xB9B + priv_mode: M + reset-val: 0 + mhpmevent28: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent28 is a MXLEN-bit event register which controls + mhpmcounter28. + address: 0x33c + priv_mode: M + reset-val: 0 + mhpmcounter28: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits + in RV282I mode. + address: 0xB1C + priv_mode: M + reset-val: 0 + mhpmcounter28h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter28h returns the upper half word in RV282I systems. + address: 0xB9C + priv_mode: M + reset-val: 0 + mhpmevent29: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent29 is a MXLEN-bit event register which controls + mhpmcounter29. + address: 0x33d + priv_mode: M + reset-val: 0 + mhpmcounter29: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits + in RV32I mode. + address: 0xB1D + priv_mode: M + reset-val: 0 + mhpmcounter29h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter29h returns the upper half word in RV32I systems. + address: 0xB9D + priv_mode: M + reset-val: 0 + mhpmevent30: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent30 is a MXLEN-bit event register which controls + mhpmcounter30. + address: 0x33e + priv_mode: M + reset-val: 0 + mhpmcounter30: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits + in RV302I mode. + address: 0xB1E + priv_mode: M + reset-val: 0 + mhpmcounter30h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter30h returns the upper half word in RV302I systems. + address: 0xB9E + priv_mode: M + reset-val: 0 + mhpmevent31: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmevent31 is a MXLEN-bit event register which controls + mhpmcounter31. + address: 0x33f + priv_mode: M + reset-val: 0 + mhpmcounter31: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: *id001 + description: The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits + in RV312I mode. + address: 0xB1F + priv_mode: M + reset-val: 0 + mhpmcounter31h: + rv32: + accessible: false + rv64: + accessible: false + description: The mhpmcounter31h returns the upper half word in RV312I systems. + address: 0xB9F + priv_mode: M + reset-val: 0 + sedeleg: + rv32: + accessible: false + rv64: + accessible: false + description: sedeleg + address: 258 + priv_mode: S + reset-val: 0 + sideleg: + rv32: + accessible: false + rv64: + accessible: false + description: sideleg + priv_mode: S + address: 259 + reset-val: 0 + fflags: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: fcsr.fflags + shadow_type: rw + msb: 4 + lsb: 0 + description: 32-bit register to hold floating point accrued exceptions. + address: 001 + priv_mode: U + reset-val: 0 + frm: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: fcsr.frm + shadow_type: rw + msb: 2 + lsb: 0 + description: 32-bit register to hold Floating-Point Dynamic Rounding Mode. + address: 002 + priv_mode: U + reset-val: 0 + fcsr: + rv32: + accessible: false + rv64: + accessible: true + fields: + - fflags + - frm + - + - + - 8 + - 63 + frm: + implemented: true + description: Stores Floating-Point Dynamic Rounding Mode. + shadow: + shadow_type: rw + msb: 7 + lsb: 5 + type: + warl: + dependency_fields: [] + legal: + - frm[2:0] in [0x0:0x7] + wr_illegal: + - Unchanged + fflags: + implemented: true + description: Stores floating point accrued exceptions. + shadow: + shadow_type: rw + msb: 4 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - fflags[4:0] in [0x0:0x1F] + wr_illegal: + - Unchanged + description: 32-bit register to hold Floating-Point Control and Status Register. + address: 003 + priv_mode: U + reset-val: 0 + cycle: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mcycle + shadow_type: ro + msb: 63 + lsb: 0 + description: Captures the number of cycles executed from an arbitrary point + in time. + priv_mode: U + address: 0xC00 + reset-val: 0 + cycleh: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of the mcycle counter; only for rv32. + address: 0xC80 + priv_mode: U + reset-val: 0 + time: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: ro + msb: 63 + lsb: 0 + type: + ro_variable: true + description: Timer for RDTIME instruction and RTC in the processor. + priv_mode: U + address: 0xC01 + reset-val: 0 + timeh: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of the Timer for RDTIME instruction and RTC in + the processor; only for rv32. + address: 0xC81 + priv_mode: U + reset-val: 0 + instret: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: minstret + shadow_type: ro + msb: 63 + lsb: 0 + description: Captures the number of instructions executed from an arbitrary + point in time. + priv_mode: U + address: 0xC02 + reset-val: 0 + instreth: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of the minstret counter; only for rv32. + address: 0xC82 + priv_mode: U + reset-val: 0 + hpmcounter3: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter3 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC03 + hpmcounter4: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter4 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC04 + hpmcounter5: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter5 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC05 + hpmcounter6: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter6 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC06 + hpmcounter7: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter7 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC07 + hpmcounter8: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter8 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC08 + hpmcounter9: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter9 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC09 + hpmcounter10: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter10 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0A + hpmcounter11: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter11 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0B + hpmcounter12: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter12 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0C + hpmcounter13: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter13 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0D + hpmcounter14: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter14 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0E + hpmcounter15: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter15 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0F + hpmcounter16: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter16 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC10 + hpmcounter17: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter17 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC11 + hpmcounter18: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter18 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC12 + hpmcounter19: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter19 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC13 + hpmcounter20: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter20 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC14 + hpmcounter21: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter21 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC15 + hpmcounter22: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter22 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC16 + hpmcounter23: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter23 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC17 + hpmcounter24: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter24 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC18 + hpmcounter25: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter25 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC19 + hpmcounter26: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter26 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1A + hpmcounter27: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter27 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1B + hpmcounter28: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter28 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1C + hpmcounter29: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter29 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1D + hpmcounter30: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter30 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1E + hpmcounter31: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: mhpmcounter31 + shadow_type: ro + msb: 63 + lsb: 0 + priv_mode: U + reset-val: 0 + description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1F + hpmcounter3h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter3h returns the upper half word in RV32I systems. + address: 0xC83 + hpmcounter4h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter4h returns the upper half word in RV32I systems. + address: 0xC84 + hpmcounter5h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter5h returns the upper half word in RV32I systems. + address: 0xC85 + hpmcounter6h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter6h returns the upper half word in RV32I systems. + address: 0xC86 + hpmcounter7h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter7h returns the upper half word in RV32I systems. + address: 0xC87 + hpmcounter8h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter8h returns the upper half word in RV32I systems. + address: 0xC88 + hpmcounter9h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter9h returns the upper half word in RV32I systems. + address: 0xC89 + hpmcounter10h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter10h returns the upper half word in RV32I systems. + address: 0xC8A + hpmcounter11h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter11h returns the upper half word in RV32I systems. + address: 0xC8B + hpmcounter12h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter12h returns the upper half word in RV32I systems. + address: 0xC8C + hpmcounter13h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter13h returns the upper half word in RV32I systems. + address: 0xC8D + hpmcounter14h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter14h returns the upper half word in RV32I systems. + address: 0xC8E + hpmcounter15h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter15h returns the upper half word in RV32I systems. + address: 0xC8F + hpmcounter16h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter16h returns the upper half word in RV32I systems. + address: 0xC90 + hpmcounter17h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter17h returns the upper half word in RV32I systems. + address: 0xC91 + hpmcounter18h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter18h returns the upper half word in RV32I systems. + address: 0xC92 + hpmcounter19h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter19h returns the upper half word in RV32I systems. + address: 0xC93 + hpmcounter20h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter20h returns the upper half word in RV32I systems. + address: 0xC94 + hpmcounter21h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter21h returns the upper half word in RV32I systems. + address: 0xC95 + hpmcounter22h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter22h returns the upper half word in RV32I systems. + address: 0xC96 + hpmcounter23h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter23h returns the upper half word in RV32I systems. + address: 0xC97 + hpmcounter24h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter24h returns the upper half word in RV32I systems. + address: 0xC98 + hpmcounter25h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter25h returns the upper half word in RV32I systems. + address: 0xC99 + hpmcounter26h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter26h returns the upper half word in RV32I systems. + address: 0xC9A + hpmcounter27h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter27h returns the upper half word in RV32I systems. + address: 0xC9B + hpmcounter28h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter28h returns the upper half word in RV32I systems. + address: 0xC9C + hpmcounter29h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter29h returns the upper half word in RV32I systems. + address: 0xC9D + hpmcounter30h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter30h returns the upper half word in RV32I systems. + address: 0xC9E + hpmcounter31h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter31h returns the upper half word in RV32I systems. + address: 0xC9F + sstatus: + rv32: + accessible: false + rv64: + accessible: true + fields: + - uie + - sie + - upie + - spie + - spp + - fs + - xs + - sum + - mxr + - uxl + - sd + - + - + - 2 + - 3 + - + - 6 + - 7 + - + - 9 + - 12 + - + - 17 + - + - 20 + - 31 + - + - 34 + - 62 + uie: + implemented: false + description: Stores the state of the user mode interrupts. + shadow: mstatus.uie + shadow_type: rw + msb: 0 + lsb: 0 + sie: + implemented: true + description: Stores the state of the supervisor mode interrupts. + shadow: mstatus.sie + shadow_type: rw + msb: 1 + lsb: 1 + upie: + implemented: false + description: Stores the state of the user mode interrupts prior to + the trap. + shadow: mstatus.upie + shadow_type: rw + msb: 4 + lsb: 4 + spie: + implemented: true + description: Stores the state of the supervisor mode interrupts prior + to the trap. + shadow: mstatus.spie + shadow_type: rw + msb: 5 + lsb: 5 + spp: + implemented: true + description: Stores the previous priority mode for supervisor. + shadow: mstatus.spp + shadow_type: rw + msb: 8 + lsb: 8 + fs: + implemented: true + description: Encodes the status of the floating-point unit, including + the CSR fcsr and floating-point data registers. + shadow: mstatus.fs + shadow_type: rw + msb: 14 + lsb: 13 + xs: + implemented: false + description: Encodes the status of additional user-mode extensions + and associated state. + shadow: mstatus.xs + shadow_type: rw + msb: 16 + lsb: 15 + sum: + implemented: true + description: Modifies the privilege with which S-mode loads and stores + access virtual memory. + shadow: mstatus.sum + shadow_type: rw + msb: 18 + lsb: 18 + mxr: + implemented: true + description: Modifies the privilege with which loads access virtual + memory. + shadow: mstatus.mxr + shadow_type: rw + msb: 19 + lsb: 19 + uxl: + implemented: true + description: Controls the xlen for User mode. + shadow: mstatus.uxl + shadow_type: rw + msb: 33 + lsb: 32 + sd: + implemented: true + description: Read-only bit that summarizes whether either the FS field + or XS field signals the presence of some dirty state. + shadow: mstatus.sd + shadow_type: rw + msb: 63 + lsb: 63 + description: The sstatus register keeps track of the processor’s current operating + state. + address: 0x100 + priv_mode: S + reset-val: 0 + sie: + rv32: + accessible: false + rv64: + accessible: true + fields: + - usie + - ssie + - utie + - stie + - ueie + - seie + - + - + - 2 + - 3 + - + - 6 + - 7 + - + - 10 + - 63 + usie: + implemented: false + description: User Software Interrupt enable. + shadow: mie.usie + shadow_type: rw + msb: 0 + lsb: 0 + ssie: + implemented: true + description: Supervisor Software Interrupt enable. + shadow: mie.ssie + shadow_type: rw + msb: 1 + lsb: 1 + utie: + implemented: false + description: User Timer Interrupt enable. + shadow: mie.utie + shadow_type: rw + msb: 4 + lsb: 4 + stie: + implemented: true + description: Supervisor Timer Interrupt enable. + shadow: mie.stie + shadow_type: rw + msb: 5 + lsb: 5 + ueie: + implemented: false + description: User External Interrupt enable. + shadow: mie.ueie + shadow_type: rw + msb: 8 + lsb: 8 + seie: + implemented: true + description: Supervisor External Interrupt enable. + shadow: mie.seie + shadow_type: rw + msb: 9 + lsb: 9 + description: The sie register is an SXLEN-bit read/write register containing + interrupt enable bits. + address: 0x104 + priv_mode: S + reset-val: 0 + sip: + rv32: + accessible: false + rv64: + accessible: true + fields: + - usip + - ssip + - utip + - stip + - ueip + - seip + - + - + - 2 + - 3 + - + - 6 + - 7 + - + - 10 + - 63 + usip: + implemented: false + description: User Software Interrupt enable. + shadow: mip.usip + shadow_type: rw + msb: 0 + lsb: 0 + ssip: + implemented: true + description: Supervisor Software Interrupt enable. + shadow: mip.ssip + shadow_type: rw + msb: 1 + lsb: 1 + utip: + implemented: false + description: User Timer Interrupt enable. + shadow: mip.utip + shadow_type: rw + msb: 4 + lsb: 4 + stip: + implemented: true + description: Supervisor Timer Interrupt enable. + shadow: mip.stip + shadow_type: ro + msb: 5 + lsb: 5 + ueip: + implemented: false + description: User External Interrupt enable. + shadow: mip.ueip + shadow_type: rw + msb: 8 + lsb: 8 + seip: + implemented: true + description: Supervisor External Interrupt enable. + shadow: mip.seip + shadow_type: ro + msb: 9 + lsb: 9 + description: The sip register is an SXLEN-bit read/write register containing + interrupt pending bits. + address: 0x144 + priv_mode: S + reset-val: 0 + sscratch: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - sscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The sscratch register is an MXLEN-bit read/write register dedicated + for use by machine mode. + address: 0x140 + priv_mode: S + reset-val: 0 + sepc: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - sepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The sepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x141 + priv_mode: S + reset-val: 0 + stval: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - stval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The stval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x143 + priv_mode: S + reset-val: 0 + scause: + rv32: + accessible: false + rv64: + accessible: true + fields: + - exception_code + - interrupt + interrupt: + implemented: true + description: Indicates whether the trap was due to an interrupt. + shadow: + shadow_type: rw + msb: 63 + lsb: 63 + type: + wlrl: + - 0:1 + exception_code: + implemented: true + description: Encodes the exception code. + shadow: + shadow_type: rw + msb: 62 + lsb: 0 + type: + wlrl: + - 0:15 + description: The scause register stores the information regarding the trap. + address: 0x142 + priv_mode: S + reset-val: 0 + stvec: + rv32: + accessible: false + rv64: + accessible: true + fields: + - mode + - base + base: + implemented: true + description: Vector base address. + shadow: + shadow_type: rw + msb: 63 + lsb: 2 + type: + warl: + dependency_fields: [] + legal: + - base[61:0] bitmask [0x3FFFFFFFFFFFFFFF, 0x0000000000000000] + wr_illegal: + - Unchanged + mode: + implemented: true + description: Vector mode. + shadow: + shadow_type: rw + msb: 1 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mode[1:0] in [0x0:0x1] + wr_illegal: + - Unchanged + description: SXLEN-bit read/write register that holds trap vector configuration. + address: 0x105 + priv_mode: S + reset-val: 0 + satp: + rv32: + accessible: false + rv64: + accessible: true + fields: + - ppn + - asid + - mode + ppn: + implemented: true + description: Physical Page Number + shadow: + shadow_type: rw + msb: 43 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - ppn[43:0] in [0x0:0xFFFFFFFFFFF] + wr_illegal: + - Unchanged + asid: + implemented: true + description: Address Space identifier. + shadow: + shadow_type: rw + msb: 59 + lsb: 44 + type: + warl: + dependency_fields: [] + legal: + - asid[15:0] in [0x0:0xFFFF] + wr_illegal: + - Unchanged + mode: + implemented: true + description: Vector mode. + shadow: + shadow_type: rw + msb: 63 + lsb: 60 + type: + warl: + dependency_fields: [] + legal: + - mode[3:0] in [0, 8, 9, 10] + wr_illegal: + - Unchanged + description: SXLEN-bit register which controls supervisor-mode address translation + and protection + address: 0x180 + priv_mode: S + reset-val: 0 + ustatus: + rv32: + accessible: false + rv64: + accessible: false + description: The ustatus register keeps track of the processor’s current operating + state. + address: 0x000 + priv_mode: U + reset-val: 0 + uie: + rv32: + accessible: false + rv64: + accessible: false + description: The uie register is an UXLEN-bit read/write register containing + interrupt enable bits. + address: 0x004 + priv_mode: U + reset-val: 0 + uip: + rv32: + accessible: false + rv64: + accessible: false + description: The uip register is an UXLEN-bit read/write register containing + interrupt pending bits. + address: 0x044 + priv_mode: U + reset-val: 0 + uscratch: + rv32: + accessible: false + rv64: + accessible: false + description: The uscratch register is an UXLEN-bit read/write register dedicated + for use by machine mode. + address: 0x040 + priv_mode: U + reset-val: 0 + uepc: + rv32: + accessible: false + rv64: + accessible: false + description: The uepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x041 + priv_mode: U + reset-val: 0 + utval: + rv32: + accessible: false + rv64: + accessible: false + description: The utval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x043 + priv_mode: U + reset-val: 0 + ucause: + rv32: + accessible: false + rv64: + accessible: false + description: The ucause register stores the information regarding the trap. + address: 0x042 + priv_mode: U + reset-val: 0 + utvec: + rv32: + accessible: false + rv64: + accessible: false + description: UXLEN-bit read/write register that holds trap vector configuration. + address: 0x005 + priv_mode: U + reset-val: 0 + scounteren: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + description: The scounteren is a 32-bit register that controls the availability + of the hardware performance-monitoring counters to the next-lowest privileged + mode. + address: 0x106 + priv_mode: S + reset-val: 0 + hideleg: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - hideleg[63:0] bitmask [0x0000000000000444, 0x0000000000000000] + wr_illegal: + - unchanged + description: Hypervisor Interrupt delegation Register. + address: 1539 + priv_mode: H + reset-val: 0 + hedeleg: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - medeleg[63:0] bitmask [0x0000000000001BFE, 0x000000000000000] + wr_illegal: + - unchanged + description: Hypervisor Exception delegation Register. + address: 1538 + priv_mode: H + reset-val: 0 + hip: + rv32: + accessible: false + rv64: + accessible: true + fields: + - vssip + - vstip + - vseip + - sgeip + - + - + - 0 + - 1 + - + - 3 + - 5 + - + - 7 + - 9 + - + - 11 + - + - 13 + - 63 + vssip: + implemented: false + description: VS-level Software Interrupt Pending. + shadow: mip.vssip + shadow_type: rw + msb: 2 + lsb: 2 + vstip: + implemented: false + description: VS-level Timer Interrupt Pending. + shadow: mip.vstip + shadow_type: rw + msb: 6 + lsb: 6 + vseip: + implemented: false + description: VS-level External Interrupt Pending. + shadow: mip.vseip + shadow_type: rw + msb: 10 + lsb: 10 + sgeip: + implemented: true + description: HS-level External Interrupt Pending. + shadow: mip.sgeip + shadow_type: rw + msb: 12 + lsb: 12 + type: + ro_variable: true + description: The hip register is an HXLEN-bit read/write register containing + information on pending interrupts. + address: 1604 + priv_mode: H + reset-val: 0 + hvip: + rv32: + accessible: false + rv64: + accessible: true + fields: + - vssip + - vstip + - vseip + - + - + - 0 + - 1 + - + - 3 + - 5 + - + - 7 + - 9 + - + - 11 + - 63 + vssip: + implemented: false + description: VS-level Software Interrupt Pending. + shadow: mip.vssip + shadow_type: rw + msb: 2 + lsb: 2 + vstip: + implemented: false + description: VS-level Timer Interrupt Pending. + shadow: mip.vstip + shadow_type: rw + msb: 6 + lsb: 6 + vseip: + implemented: false + description: VS-level External Interrupt Pending. + shadow: mip.vseip + shadow_type: rw + msb: 10 + lsb: 10 + description: The hvip register is an HSXLEN-bit read/write register that a + hypervisor can write to indicate virtual interrupts intended for VS-mode. + address: 1605 + priv_mode: H + reset-val: 0 + hgeip: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: {ro_variable: true} + description: The hgeip register is an HSXLEN-bit read-only register that indicates + pending guest external interrupts for this hart. + address: 0xE12 + priv_mode: H + reset-val: 0 + hgeie: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - hgeie[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The hgeie register is an HSXLEN-bit read/write register that + contains enable bits for the guest external interrupts at this hart. + address: 0x607 + priv_mode: H + reset-val: 0 + htval: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - htval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The htval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x643 + priv_mode: H + reset-val: 0 + htinst: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - htinst[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The htinst is a warl register that need only be able to hold + the values that the implementation may automatically write to it on a + trap. + address: 0x64A + priv_mode: H + reset-val: 0 + mtval2: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mtval2[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: When a trap is taken into M-mode, mtval2 is written with additional + exception-specific information to assist software in handling the trap. + address: 0x34B + priv_mode: M + reset-val: 0 + mtinst: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mtinst[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The mtinst is a warl register that need only be able to hold + the values that the implementation may automatically write to it on a + trap. + address: 0x34A + priv_mode: M + reset-val: 0 + hgatp: + rv32: + accessible: false + rv64: + accessible: true + fields: + - ppn + - vmid + - mode + - + - + - 58 + - 59 + ppn: + implemented: false + description: Physical Page Number + shadow: + shadow_type: rw + msb: 43 + lsb: 0 + vmid: + implemented: false + description: Address Space identifier. + shadow: + shadow_type: rw + msb: 57 + lsb: 44 + mode: + implemented: false + description: Vector mode. + shadow: + shadow_type: rw + msb: 63 + lsb: 60 + description: HSXLEN-bit register which controls G-stage address translation + and protection + address: 0x680 + priv_mode: H + reset-val: 0 + hcounteren: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - hcounteren[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + description: The hcounteren is a 32-bit register that controls the availability + of the hardware performance-monitoring counters to the next-lowest privileged + mode. + address: 0x606 + priv_mode: H + reset-val: 0 + htimedelta: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - htimedelta[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The htimedelta CSR is a read/write register that contains the + delta between the value of the time CSR and the value returned in VS-mode + or VU-mode. + priv_mode: H + address: 0x605 + reset-val: 0 + htimedeltah: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of htimedelta + address: 0x615 + priv_mode: H + reset-val: 0 + vsstatus: + rv32: + accessible: false + rv64: + accessible: true + fields: + - uie + - sie + - upie + - spie + - spp + - fs + - xs + - sum + - mxr + - uxl + - sd + - + - + - 2 + - 3 + - + - 6 + - 7 + - + - 9 + - 12 + - + - 17 + - + - 20 + - 31 + - + - 34 + - 62 + uie: + implemented: false + description: Stores the state of the user mode interrupts. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + sie: + implemented: true + description: Stores the state of the supervisor mode interrupts. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + type: {ro_constant: 0} + upie: + implemented: false + description: Stores the state of the user mode interrupts prior to + the trap. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + spie: + implemented: true + description: Stores the state of the supervisor mode interrupts prior + to the trap. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + type: {ro_constant: 0} + spp: + implemented: true + description: Stores the previous priority mode for supervisor. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + type: {ro_constant: 0} + fs: + implemented: false + description: Encodes the status of the floating-point unit, including + the CSR fcsr and floating-point data registers. + shadow: + shadow_type: rw + msb: 14 + lsb: 13 + xs: + implemented: false + description: Encodes the status of additional user-mode extensions + and associated state. + shadow: + shadow_type: rw + msb: 16 + lsb: 15 + sum: + implemented: true + description: Modifies the privilege with which S-mode loads and stores + access virtual memory. + shadow: + shadow_type: rw + msb: 18 + lsb: 18 + type: {ro_constant: 0} + mxr: + implemented: true + description: Modifies the privilege with which loads access virtual + memory. + shadow: + shadow_type: rw + msb: 19 + lsb: 19 + type: {ro_constant: 0} + uxl: + implemented: true + description: Controls the xlen for User mode. + shadow: + shadow_type: rw + msb: 33 + lsb: 32 + type: {ro_constant: 2} + sd: + implemented: true + description: Read-only bit that summarizes whether either the FS field + or XS field signals the presence of some dirty state. + shadow: + shadow_type: rw + msb: 63 + lsb: 63 + type: {wlrl: [0:1]} + description: The vsstatus register keeps track of the processor’s current + operating state. + address: 0x200 + priv_mode: S + reset-val: 8589934592 + vsie: + rv32: + accessible: false + rv64: + accessible: true + fields: + - ssie + - stie + - seie + - + - + - 0 + - + - 2 + - 4 + - + - 6 + - 8 + - + - 10 + - 63 + ssie: + implemented: true + description: Supervisor Software Interrupt enable. + shadow: mie.vssie + shadow_type: rw + msb: 1 + lsb: 1 + stie: + implemented: true + description: Supervisor Timer Interrupt enable. + shadow: mie.vstie + shadow_type: rw + msb: 5 + lsb: 5 + seie: + implemented: true + description: Supervisor External Interrupt enable. + shadow: mie.vseie + shadow_type: rw + msb: 9 + lsb: 9 + description: The vsie register is an VSXLEN-bit read/write register containing + interrupt enable bits. + address: 0x204 + priv_mode: S + reset-val: 0 + vsip: + rv32: + accessible: false + rv64: + accessible: true + fields: + - ssip + - stip + - seip + - + - + - 0 + - + - 2 + - 4 + - + - 6 + - 8 + - + - 10 + - 63 + ssip: + implemented: true + description: Supervisor Software Interrupt enable. + shadow: mip.vssip + shadow_type: rw + msb: 1 + lsb: 1 + stip: + implemented: true + description: Supervisor Timer Interrupt enable. + shadow: mip.vstip + shadow_type: rw + msb: 5 + lsb: 5 + seip: + implemented: true + description: Supervisor External Interrupt enable. + shadow: mip.vseip + shadow_type: rw + msb: 9 + lsb: 9 + description: The vsip register is an VSXLEN-bit read/write register containing + interrupt pending bits. + address: 0x244 + priv_mode: S + reset-val: 0 + vsscratch: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - vsscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + + description: The vsscratch register is an VSXLEN-bit read/write register dedicated + for use by machine mode. + address: 0x240 + priv_mode: S + reset-val: 0 + vsepc: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - vsepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The vsepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x241 + priv_mode: S + reset-val: 0 + vstval: + rv32: + accessible: false + rv64: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 63 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - vstval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + description: The vstval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x243 + priv_mode: S + reset-val: 0 + vscause: + rv32: + accessible: false + rv64: + accessible: true + fields: + - exception_code + - interrupt + interrupt: + implemented: false + description: Indicates whether the trap was due to an interrupt. + shadow: + shadow_type: rw + msb: 63 + lsb: 63 + exception_code: + implemented: false + description: Encodes the exception code. + shadow: + shadow_type: rw + msb: 62 + lsb: 0 + description: The scause register stores the information regarding the trap. + address: 0x242 + priv_mode: S + reset-val: 0 + vstvec: + rv32: + accessible: false + rv64: + accessible: true + fields: + - mode + - base + base: + implemented: false + description: Vector base address. + shadow: + shadow_type: rw + msb: 63 + lsb: 2 + mode: + implemented: false + description: Vector mode. + shadow: + shadow_type: rw + msb: 1 + lsb: 0 + description: SXLEN-bit read/write register that holds trap vector configuration. + address: 0x205 + priv_mode: S + reset-val: 0 + vsatp: + rv32: + accessible: false + rv64: + accessible: true + fields: + - ppn + - asid + - mode + ppn: + implemented: false + description: Physical Page Number + shadow: + shadow_type: rw + msb: 43 + lsb: 0 + asid: + implemented: false + description: Address Space identifier. + shadow: + shadow_type: rw + msb: 59 + lsb: 44 + mode: + implemented: false + description: Vector mode. + shadow: + shadow_type: rw + msb: 63 + lsb: 60 + description: VSXLEN-bit register which controls supervisor-mode address translation + and protection + address: 0x280 + priv_mode: S + reset-val: 0 + vxsat: + rv32: + accessible: false + rv64: + accessible: false + description: The vxsat register records the overflow saturation condition + of P and V instructions. + address: 9 + priv_mode: U + reset-val: 0 diff --git a/StarFive/Dubhe-90-2023-12-14/Dubhe-90_platform_checked.yaml b/StarFive/Dubhe-90-2023-12-14/Dubhe-90_platform_checked.yaml new file mode 100755 index 0000000..becc615 --- /dev/null +++ b/StarFive/Dubhe-90-2023-12-14/Dubhe-90_platform_checked.yaml @@ -0,0 +1,16 @@ +mtime: + implemented: true +nmi: + label: nmi_vector +reset: + label: reset_vector +mtimecmp: + implemented: false +mtval_condition_writes: + implemented: false +scause_non_standard: + implemented: false +stval_condition_writes: + implemented: false +zicbo_cache_block_sz: + implemented: false diff --git a/StarFive/Dubhe-90-2023-12-14/report.html b/StarFive/Dubhe-90-2023-12-14/report.html new file mode 100755 index 0000000..83fe4ba --- /dev/null +++ b/StarFive/Dubhe-90-2023-12-14/report.html @@ -0,0 +1,12622 @@ + + +
+ +Report generated on 2023-12-14 06:03 GMT by riscof v
+Riscof Version | +1.25.3 |
Riscv-arch-test Version/Commit Id | +3.8.0 |
DUT | +Dubhe-90 |
Reference | +spike |
ISA | +RV64IMAFDCSHUZicsr_Zicntr_Zifencei_Zihintpause_Zba_Zbb_Zbc_Zbs |
User Spec Version | +2.2 |
Privilege Spec Version | +1.10 |
Name | +
---|
/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/Dubhe-90_isa_checked.yaml |
+ hart_ids: [0]
+hart0:
+ ISA: RV64IMAFDCSHUZicsr_Zicntr_Zifencei_Zihintpause_Zba_Zbb_Zbc_Zbs
+ physical_addr_sz: 56
+ User_Spec_Version: '2.2'
+ supported_xlen:
+ - 64
+ misa:
+ reset-val: 0x80000000001411AD
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - extensions
+ - mxl
+ -
+ -
+ - 26
+ - 61
+ mxl:
+ implemented: true
+ description: Encodes the native base integer ISA width.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 62
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mxl[1:0] in [0x2]
+ wr_illegal:
+ - unchanged
+ extensions:
+ implemented: true
+ description: Encodes the presence of the standard extensions, with
+ a single bit per letter of the alphabet.
+ shadow:
+ shadow_type: rw
+ msb: 25
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - extensions[25:0] bitmask [0x1411AD, 0x00000000]
+ wr_illegal:
+ - unchanged
+ description: misa is a read-write register reporting the ISA supported by
+ the hart.
+ address: 769
+ priv_mode: M
+ hstatus:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The hstatus register keeps track of and controls the hart’s current
+ operating state.
+ address: 1536
+ priv_mode: H
+ reset-val: 1
+ marchid:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ ro_constant: 0
+ address: 3858
+ priv_mode: M
+ reset-val: 0
+ description: MXLEN-bit read-only register encoding the base microarchitecture
+ of the hart.
+ mimpid:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ ro_constant: 0
+ address: 3859
+ priv_mode: M
+ reset-val: 0
+ description: Provides a unique encoding of the version of the processor implementation.
+ Privilege_Spec_Version: '1.10'
+ hw_data_misaligned_support: false
+ pmp_granularity: 0
+ custom_exceptions:
+ custom_interrupts:
+ pte_ad_hw_update: false
+ mtval_update: 0b11111111
+ mstatus:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - uie
+ - sie
+ - mie
+ - upie
+ - spie
+ - mpie
+ - spp
+ - mpp
+ - fs
+ - xs
+ - mprv
+ - sum
+ - mxr
+ - tvm
+ - tw
+ - tsr
+ - uxl
+ - sxl
+ - gva
+ - mpv
+ - sd
+ -
+ -
+ - 2
+ -
+ - 6
+ -
+ - 9
+ - 10
+ -
+ - 23
+ - 31
+ -
+ - 36
+ - 37
+ -
+ - 40
+ - 62
+ uie:
+ implemented: false
+ description: Stores the state of the user mode interrupts.
+ shadow:
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ sie:
+ implemented: true
+ description: Stores the state of the supervisor mode interrupts.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ type:
+ wlrl:
+ - 0:1
+ mie:
+ implemented: true
+ description: Stores the state of the machine mode interrupts.
+ shadow:
+ shadow_type: rw
+ msb: 3
+ lsb: 3
+ type:
+ wlrl:
+ - 0:1
+ upie:
+ implemented: false
+ description: Stores the state of the user mode interrupts prior to
+ the trap.
+ shadow:
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ spie:
+ implemented: true
+ description: Stores the state of the supervisor mode interrupts prior
+ to the trap.
+ shadow:
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ type:
+ wlrl:
+ - 0:1
+ mpie:
+ implemented: true
+ description: Stores the state of the machine mode interrupts prior
+ to the trap.
+ shadow:
+ shadow_type: rw
+ msb: 7
+ lsb: 7
+ type:
+ wlrl:
+ - 0:1
+ spp:
+ implemented: true
+ description: Stores the previous priority mode for supervisor.
+ shadow:
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ type: {ro_constant: 0}
+ mpp:
+ implemented: true
+ description: Stores the previous priority mode for machine.
+ shadow:
+ shadow_type: rw
+ msb: 12
+ lsb: 11
+ type: {ro_constant: 0}
+ fs:
+ implemented: true
+ description: Encodes the status of the floating-point unit, including
+ the CSR fcsr and floating-point data registers.
+ shadow:
+ shadow_type: rw
+ msb: 14
+ lsb: 13
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - fs[1:0] in [0x0:0x3]
+ wr_illegal:
+ - unchanged
+ xs:
+ implemented: false
+ description: Encodes the status of additional user-mode extensions
+ and associated state.
+ shadow:
+ shadow_type: rw
+ msb: 16
+ lsb: 15
+ mprv:
+ implemented: true
+ description: Modifies the privilege level at which loads and stores
+ execute in all privilege modes.
+ shadow:
+ shadow_type: rw
+ msb: 17
+ lsb: 17
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mprv[0] in [0x0]
+ wr_illegal:
+ - unchanged
+ sum:
+ implemented: true
+ description: Modifies the privilege with which S-mode loads and stores
+ access virtual memory.
+ shadow:
+ shadow_type: rw
+ msb: 18
+ lsb: 18
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - sum[0] in [0x0]
+ wr_illegal:
+ - unchanged
+ mxr:
+ implemented: true
+ description: Modifies the privilege with which loads access virtual
+ memory.
+ shadow:
+ shadow_type: rw
+ msb: 19
+ lsb: 19
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mxr[0] in [0x0]
+ wr_illegal:
+ - unchanged
+ tvm:
+ implemented: true
+ description: Supports intercepting supervisor virtual-memory management
+ operations.
+ shadow:
+ shadow_type: rw
+ msb: 20
+ lsb: 20
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - tvm[0] in [0x0]
+ wr_illegal:
+ - unchanged
+ tw:
+ implemented: true
+ description: Supports intercepting the WFI instruction.
+ shadow:
+ shadow_type: rw
+ msb: 21
+ lsb: 21
+ type: {ro_constant: 0}
+ tsr:
+ implemented: true
+ description: Supports intercepting the supervisor exception return
+ instruction.
+ shadow:
+ shadow_type: rw
+ msb: 22
+ lsb: 22
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - tsr[0] in [0x0]
+ wr_illegal:
+ - unchanged
+ sxl:
+ implemented: true
+ description: Controls the value of xlen for Supervisor mode.
+ shadow:
+ shadow_type: rw
+ msb: 35
+ lsb: 34
+ type: {ro_constant: 2}
+ uxl:
+ implemented: true
+ description: Controls the xlen for User mode.
+ shadow:
+ shadow_type: rw
+ msb: 33
+ lsb: 32
+ type: {ro_constant: 2}
+ gva:
+ implemented: true
+ description: For any trap (access fault, page fault, or guest-page
+ fault) that writes a guest virtual address to mtval, GVA is set
+ to 1.
+ shadow:
+ shadow_type: rw
+ msb: 38
+ lsb: 38
+ type: {ro_constant: 0}
+ mpv:
+ implemented: true
+ description: Machine Previous Virtualization Mode is written by the
+ implementation whenever a trap is taken into M-mode.
+ shadow:
+ shadow_type: rw
+ msb: 39
+ lsb: 39
+ type: {ro_constant: 0}
+ sd:
+ implemented: true
+ description: Read-only bit that summarizes whether either the FS field
+ or XS field signals the presence of some dirty state.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 63
+ type:
+ wlrl:
+ - 0:1
+ description: The mstatus register keeps track of and controls the hart’s current
+ operating state.
+ address: 768
+ priv_mode: M
+ reset-val: 42949672960
+ mstatush:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mstatush register keeps track of and controls the hart’s
+ current operating state.
+ address: 768
+ priv_mode: M
+ reset-val: 0
+ mvendorid:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 31
+ lsb: 0
+ type:
+ ro_constant: 0
+ description: 32-bit read-only register providing the JEDEC manufacturer ID
+ of the provider of the core.
+ address: 3857
+ priv_mode: M
+ reset-val: 0
+ mhartid:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ ro_constant: 0
+ description: MXLEN-bit read-only register containing the integer ID of the
+ hardware thread running the code.
+ address: 3860
+ priv_mode: M
+ reset-val: 0
+ mtvec:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - mode
+ - base
+ base:
+ implemented: true
+ description: Vector base address.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 2
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - base[61:0] bitmask [0x3FFFFFFFFFFFFFFF, 0x0000000000000000]
+ wr_illegal:
+ - Unchanged
+ mode:
+ implemented: true
+ description: Vector mode.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mode[1:0] in [0x0:0x1]
+ wr_illegal:
+ - Unchanged
+ description: MXLEN-bit read/write register that holds trap vector configuration.
+ address: 773
+ priv_mode: M
+ reset-val: 0
+ mideleg:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mideleg[63:0] bitmask [0x000000000000F7FF,0x0000000000000000]
+ wr_illegal:
+ - Unchanged
+ description: Machine Interrupt delegation Register.
+ address: 771
+ priv_mode: M
+ reset-val: 0
+ medeleg:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - medeleg[63:0] bitmask [0x000000000000F7FF,0x0000000000000000]
+ wr_illegal:
+ - Unchanged
+ description: Machine Exception delegation Register.
+ address: 770
+ priv_mode: M
+ reset-val: 0
+ mip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - usip
+ - ssip
+ - vssip
+ - msip
+ - utip
+ - stip
+ - vstip
+ - mtip
+ - ueip
+ - seip
+ - vseip
+ - meip
+ - sgeip
+ -
+ -
+ - 13
+ - 63
+ usip:
+ implemented: false
+ description: User Software Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ ssip:
+ implemented: true
+ description: Supervisor Software Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ type:
+ wlrl:
+ - 0:1
+ vssip:
+ implemented: true
+ description: VS-level Software Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 2
+ lsb: 2
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vssip[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ msip:
+ implemented: true
+ description: Machine Software Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 3
+ lsb: 3
+ type:
+ ro_variable: true
+ utip:
+ implemented: false
+ description: User Timer Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ stip:
+ implemented: true
+ description: Supervisor Timer Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ type:
+ wlrl:
+ - 0:1
+ vstip:
+ implemented: true
+ description: VS-level Timer Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 6
+ lsb: 6
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vstip[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ mtip:
+ implemented: true
+ description: Machine Timer Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 7
+ lsb: 7
+ type:
+ ro_variable: true
+ ueip:
+ implemented: false
+ description: User External Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ seip:
+ implemented: true
+ description: Supervisor External Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 9
+ lsb: 9
+ type:
+ wlrl:
+ - 0:1
+ vseip:
+ implemented: true
+ description: VS-level External Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 10
+ lsb: 10
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vseip[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ meip:
+ implemented: true
+ description: Machine External Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 11
+ lsb: 11
+ type:
+ ro_variable: true
+ sgeip:
+ implemented: true
+ description: HS-level External Interrupt Pending.
+ shadow:
+ shadow_type: rw
+ msb: 12
+ lsb: 12
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - sgeip[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ description: The mip register is an MXLEN-bit read/write register containing
+ information on pending interrupts.
+ address: 836
+ priv_mode: M
+ reset-val: 0
+ hie:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - vssie
+ - vstie
+ - vseie
+ - sgeie
+ -
+ -
+ - 0
+ - 1
+ -
+ - 3
+ - 5
+ -
+ - 7
+ - 9
+ -
+ - 11
+ -
+ - 13
+ - 63
+ vssie:
+ implemented: false
+ description: VS-level Software Interrupt enable.
+ shadow: mie.vssie
+ shadow_type: rw
+ msb: 2
+ lsb: 2
+ vstie:
+ implemented: false
+ description: VS-level Timer Interrupt enable.
+ shadow: mie.vstie
+ shadow_type: rw
+ msb: 6
+ lsb: 6
+ vseie:
+ implemented: false
+ description: VS-level External Interrupt enable.
+ shadow: mie.vseie
+ shadow_type: rw
+ msb: 10
+ lsb: 10
+ sgeie:
+ implemented: true
+ description: HS-level External Interrupt enable.
+ shadow: mie.sgeie
+ shadow_type: rw
+ msb: 12
+ lsb: 12
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - sgeie[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ description: The hie register is an HSXLEN-bit read/write register containing
+ interrupt enable bits.
+ address: 0x604
+ priv_mode: H
+ reset-val: 0
+ mie:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - usie
+ - ssie
+ - vssie
+ - msie
+ - utie
+ - stie
+ - vstie
+ - mtie
+ - ueie
+ - seie
+ - vseie
+ - meie
+ - sgeie
+ -
+ -
+ - 13
+ - 63
+ usie:
+ implemented: false
+ description: User Software Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ ssie:
+ implemented: true
+ description: Supervisor Software Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ type:
+ wlrl:
+ - 0:1
+ vssie:
+ implemented: true
+ description: VS-level Software Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 2
+ lsb: 2
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vssie[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ msie:
+ implemented: true
+ description: Machine Software Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 3
+ lsb: 3
+ type:
+ wlrl:
+ - 0x0:0x1
+ utie:
+ implemented: false
+ description: User Timer Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ stie:
+ implemented: true
+ description: Supervisor Timer Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ type:
+ wlrl:
+ - 0:1
+ vstie:
+ implemented: true
+ description: VS-level Timer Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 6
+ lsb: 6
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vstie[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ mtie:
+ implemented: true
+ description: Machine Timer Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 7
+ lsb: 7
+ type:
+ wlrl:
+ - 0:1
+ ueie:
+ implemented: false
+ description: User External Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ seie:
+ implemented: true
+ description: Supervisor External Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 9
+ lsb: 9
+ type:
+ wlrl:
+ - 0:1
+ vseie:
+ implemented: true
+ description: VS-level External Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 10
+ lsb: 10
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vseie[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ meie:
+ implemented: true
+ description: Machine External Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 11
+ lsb: 11
+ type:
+ wlrl:
+ - 0:1
+ sgeie:
+ implemented: true
+ description: HS-level External Interrupt enable.
+ shadow:
+ shadow_type: rw
+ msb: 12
+ lsb: 12
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - sgeie[0] in [0x0, 0x1]
+ wr_illegal:
+ - unchanged
+ description: The mie register is an MXLEN-bit read/write register containing
+ interrupt enable bits.
+ address: 772
+ priv_mode: M
+ reset-val: 0
+ mscratch:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+
+ description: The mscratch register is an MXLEN-bit read/write register dedicated
+ for use by machine mode.
+ address: 832
+ priv_mode: M
+ reset-val: 0
+ mepc:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The mepc is a warl register that must be able to hold all valid
+ physical and virtual addresses.
+ address: 0x341
+ priv_mode: M
+ reset-val: 0
+ mtval:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mtval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The mtval is a warl register that holds the address of the instruction
+ which caused the exception.
+ address: 835
+ priv_mode: M
+ reset-val: 0
+ mcause:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - exception_code
+ - interrupt
+ interrupt:
+ implemented: true
+ description: Indicates whether the trap was due to an interrupt.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 63
+ type:
+ wlrl:
+ - 0:1
+ exception_code:
+ implemented: true
+ description: Encodes the exception code.
+ shadow:
+ shadow_type: rw
+ msb: 62
+ lsb: 0
+ type:
+ wlrl:
+ - 0:15
+ description: The mcause register stores the information regarding the trap.
+ address: 834
+ priv_mode: M
+ reset-val: 0
+ pmpcfg0:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A0
+ priv_mode: M
+ reset-val: 0
+ pmpcfg1:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A1
+ priv_mode: M
+ reset-val: 0
+ pmpcfg2:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A2
+ priv_mode: M
+ reset-val: 0
+ pmpcfg3:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A3
+ priv_mode: M
+ reset-val: 0
+ pmpcfg4:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A4
+ priv_mode: M
+ reset-val: 0
+ pmpcfg5:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A5
+ priv_mode: M
+ reset-val: 0
+ pmpcfg6:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A6
+ priv_mode: M
+ reset-val: 0
+ pmpcfg7:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A7
+ priv_mode: M
+ reset-val: 0
+ pmpcfg8:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A8
+ priv_mode: M
+ reset-val: 0
+ pmpcfg9:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3A9
+ priv_mode: M
+ reset-val: 0
+ pmpcfg10:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3AA
+ priv_mode: M
+ reset-val: 0
+ pmpcfg11:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3AB
+ priv_mode: M
+ reset-val: 0
+ pmpcfg12:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3AC
+ priv_mode: M
+ reset-val: 0
+ pmpcfg13:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3AD
+ priv_mode: M
+ reset-val: 0
+ pmpcfg14:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3AE
+ priv_mode: M
+ reset-val: 0
+ pmpcfg15:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: PMP configuration register
+ address: 0x3AF
+ priv_mode: M
+ reset-val: 0
+ pmpaddr0:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B0
+ priv_mode: M
+ reset-val: 0
+ pmpaddr1:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B1
+ priv_mode: M
+ reset-val: 0
+ pmpaddr2:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B2
+ priv_mode: M
+ reset-val: 0
+ pmpaddr3:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B3
+ priv_mode: M
+ reset-val: 0
+ pmpaddr4:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B4
+ priv_mode: M
+ reset-val: 0
+ pmpaddr5:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B5
+ priv_mode: M
+ reset-val: 0
+ pmpaddr6:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B6
+ priv_mode: M
+ reset-val: 0
+ pmpaddr7:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B7
+ priv_mode: M
+ reset-val: 0
+ pmpaddr8:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B8
+ priv_mode: M
+ reset-val: 0
+ pmpaddr9:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3B9
+ priv_mode: M
+ reset-val: 0
+ pmpaddr10:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3BA
+ priv_mode: M
+ reset-val: 0
+ pmpaddr11:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3BB
+ priv_mode: M
+ reset-val: 0
+ pmpaddr12:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3BC
+ priv_mode: M
+ reset-val: 0
+ pmpaddr13:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3BD
+ priv_mode: M
+ reset-val: 0
+ pmpaddr14:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3BE
+ priv_mode: M
+ reset-val: 0
+ pmpaddr15:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3BF
+ priv_mode: M
+ reset-val: 0
+ pmpaddr16:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C0
+ priv_mode: M
+ reset-val: 0
+ pmpaddr17:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C1
+ priv_mode: M
+ reset-val: 0
+ pmpaddr18:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C2
+ priv_mode: M
+ reset-val: 0
+ pmpaddr19:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C3
+ priv_mode: M
+ reset-val: 0
+ pmpaddr20:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C4
+ priv_mode: M
+ reset-val: 0
+ pmpaddr21:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C5
+ priv_mode: M
+ reset-val: 0
+ pmpaddr22:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C6
+ priv_mode: M
+ reset-val: 0
+ pmpaddr23:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C7
+ priv_mode: M
+ reset-val: 0
+ pmpaddr24:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C8
+ priv_mode: M
+ reset-val: 0
+ pmpaddr25:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3C9
+ priv_mode: M
+ reset-val: 0
+ pmpaddr26:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3CA
+ priv_mode: M
+ reset-val: 0
+ pmpaddr27:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3CB
+ priv_mode: M
+ reset-val: 0
+ pmpaddr28:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3CC
+ priv_mode: M
+ reset-val: 0
+ pmpaddr29:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3CD
+ priv_mode: M
+ reset-val: 0
+ pmpaddr30:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3CE
+ priv_mode: M
+ reset-val: 0
+ pmpaddr31:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3CF
+ priv_mode: M
+ reset-val: 0
+ pmpaddr32:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D0
+ priv_mode: M
+ reset-val: 0
+ pmpaddr33:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D1
+ priv_mode: M
+ reset-val: 0
+ pmpaddr34:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D2
+ priv_mode: M
+ reset-val: 0
+ pmpaddr35:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D3
+ priv_mode: M
+ reset-val: 0
+ pmpaddr36:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D4
+ priv_mode: M
+ reset-val: 0
+ pmpaddr37:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D5
+ priv_mode: M
+ reset-val: 0
+ pmpaddr38:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D6
+ priv_mode: M
+ reset-val: 0
+ pmpaddr39:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D7
+ priv_mode: M
+ reset-val: 0
+ pmpaddr40:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D8
+ priv_mode: M
+ reset-val: 0
+ pmpaddr41:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3D9
+ priv_mode: M
+ reset-val: 0
+ pmpaddr42:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3DA
+ priv_mode: M
+ reset-val: 0
+ pmpaddr43:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3DB
+ priv_mode: M
+ reset-val: 0
+ pmpaddr44:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3DC
+ priv_mode: M
+ reset-val: 0
+ pmpaddr45:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3DD
+ priv_mode: M
+ reset-val: 0
+ pmpaddr46:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3DE
+ priv_mode: M
+ reset-val: 0
+ pmpaddr47:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3DF
+ priv_mode: M
+ reset-val: 0
+ pmpaddr48:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E0
+ priv_mode: M
+ reset-val: 0
+ pmpaddr49:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E1
+ priv_mode: M
+ reset-val: 0
+ pmpaddr50:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E2
+ priv_mode: M
+ reset-val: 0
+ pmpaddr51:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E3
+ priv_mode: M
+ reset-val: 0
+ pmpaddr52:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E4
+ priv_mode: M
+ reset-val: 0
+ pmpaddr53:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E5
+ priv_mode: M
+ reset-val: 0
+ pmpaddr54:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E6
+ priv_mode: M
+ reset-val: 0
+ pmpaddr55:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E7
+ priv_mode: M
+ reset-val: 0
+ pmpaddr56:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E8
+ priv_mode: M
+ reset-val: 0
+ pmpaddr57:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3E9
+ priv_mode: M
+ reset-val: 0
+ pmpaddr58:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3EA
+ priv_mode: M
+ reset-val: 0
+ pmpaddr59:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3EB
+ priv_mode: M
+ reset-val: 0
+ pmpaddr60:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3EC
+ priv_mode: M
+ reset-val: 0
+ pmpaddr61:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3ED
+ priv_mode: M
+ reset-val: 0
+ pmpaddr62:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3EE
+ priv_mode: M
+ reset-val: 0
+ pmpaddr63:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Physical memory protection address register
+ address: 0x3EF
+ priv_mode: M
+ reset-val: 0
+ mcounteren:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 31
+ lsb: 0
+ type:
+ ro_constant: 0
+ description: The mcounteren is a 32-bit register that controls the availability
+ of the hardware performance-monitoring counters to the next-lowest privileged
+ mode.
+ address: 0x306
+ priv_mode: M
+ reset-val: 0
+ mcountinhibit:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 31
+ lsb: 0
+ type:
+ ro_constant: 0
+ description: The mcountinhibit is a 32-bit WARL register that controls which
+ of the hardware performance-monitoring counters increment.
+ address: 0x320
+ priv_mode: M
+ reset-val: 0
+ mcycle:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mcycle[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - Unchanged
+ description: Counts the number of clock cycles executed from an arbitrary
+ point in time.
+ address: 0xB00
+ priv_mode: M
+ reset-val: 0
+ mcycleh:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: upper 32 bits of mcycle
+ address: 0xB80
+ priv_mode: M
+ reset-val: 0
+ minstret:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - minstret[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - Unchanged
+ description: Counts the number of instructions completed from an arbitrary
+ point in time.
+ address: 0xB02
+ priv_mode: M
+ reset-val: 0
+ minstreth:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Upper 32 bits of minstret.
+ address: 0xB82
+ priv_mode: M
+ reset-val: 0
+ mhpmevent3:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: &id001
+ ro_constant: 0
+ description: The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3.
+ address: 0x323
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter3:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in
+ RV32I mode.
+ address: 0xB03
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter3h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter3h returns the upper half word in RV32I systems.
+ address: 0xB83
+ priv_mode: M
+ reset-val: 0
+ mhpmevent4:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4.
+ address: 0x324
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter4:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in
+ RV42I mode.
+ address: 0xB04
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter4h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter4h returns the upper half word in RV42I systems.
+ address: 0xB84
+ priv_mode: M
+ reset-val: 0
+ mhpmevent5:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5.
+ address: 0x325
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter5:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in
+ RV52I mode.
+ address: 0xB05
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter5h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter5h returns the upper half word in RV52I systems.
+ address: 0xB85
+ priv_mode: M
+ reset-val: 0
+ mhpmevent6:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6.
+ address: 0x326
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter6:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in
+ RV62I mode.
+ address: 0xB06
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter6h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter6h returns the upper half word in RV62I systems.
+ address: 0xB86
+ priv_mode: M
+ reset-val: 0
+ mhpmevent7:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7.
+ address: 0x327
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter7:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in
+ RV72I mode.
+ address: 0xB07
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter7h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter7h returns the upper half word in RV72I systems.
+ address: 0xB87
+ priv_mode: M
+ reset-val: 0
+ mhpmevent8:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8.
+ address: 0x328
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter8:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in
+ RV82I mode.
+ address: 0xB08
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter8h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter8h returns the upper half word in RV82I systems.
+ address: 0xB88
+ priv_mode: M
+ reset-val: 0
+ mhpmevent9:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9.
+ address: 0x329
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter9:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in
+ RV32I mode.
+ address: 0xB09
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter9h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter9h returns the upper half word in RV32I systems.
+ address: 0xB89
+ priv_mode: M
+ reset-val: 0
+ mhpmevent10:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent10 is a MXLEN-bit event register which controls
+ mhpmcounter10.
+ address: 0x32a
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter10:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits
+ in RV102I mode.
+ address: 0xB0A
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter10h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter10h returns the upper half word in RV102I systems.
+ address: 0xB8A
+ priv_mode: M
+ reset-val: 0
+ mhpmevent11:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent11 is a MXLEN-bit event register which controls
+ mhpmcounter11.
+ address: 0x32b
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter11:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits
+ in RV112I mode.
+ address: 0xB0B
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter11h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter11h returns the upper half word in RV112I systems.
+ address: 0xB8B
+ priv_mode: M
+ reset-val: 0
+ mhpmevent12:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent12 is a MXLEN-bit event register which controls
+ mhpmcounter12.
+ address: 0x32c
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter12:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits
+ in RV122I mode.
+ address: 0xB0C
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter12h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter12h returns the upper half word in RV122I systems.
+ address: 0xB8C
+ priv_mode: M
+ reset-val: 0
+ mhpmevent13:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent13 is a MXLEN-bit event register which controls
+ mhpmcounter13.
+ address: 0x32d
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter13:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits
+ in RV132I mode.
+ address: 0xB0D
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter13h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter13h returns the upper half word in RV132I systems.
+ address: 0xB8D
+ priv_mode: M
+ reset-val: 0
+ mhpmevent14:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent14 is a MXLEN-bit event register which controls
+ mhpmcounter14.
+ address: 0x32e
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter14:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits
+ in RV142I mode.
+ address: 0xB0E
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter14h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter14h returns the upper half word in RV142I systems.
+ address: 0xB8E
+ priv_mode: M
+ reset-val: 0
+ mhpmevent15:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent15 is a MXLEN-bit event register which controls
+ mhpmcounter15.
+ address: 0x32f
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter15:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits
+ in RV152I mode.
+ address: 0xB0F
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter15h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter15h returns the upper half word in RV152I systems.
+ address: 0xB8F
+ priv_mode: M
+ reset-val: 0
+ mhpmevent16:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent16 is a MXLEN-bit event register which controls
+ mhpmcounter16.
+ address: 0x330
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter16:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits
+ in RV162I mode.
+ address: 0xB10
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter16h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter16h returns the upper half word in RV162I systems.
+ address: 0xB90
+ priv_mode: M
+ reset-val: 0
+ mhpmevent17:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent17 is a MXLEN-bit event register which controls
+ mhpmcounter17.
+ address: 0x331
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter17:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits
+ in RV172I mode.
+ address: 0xB11
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter17h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter17h returns the upper half word in RV172I systems.
+ address: 0xB91
+ priv_mode: M
+ reset-val: 0
+ mhpmevent18:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent18 is a MXLEN-bit event register which controls
+ mhpmcounter18.
+ address: 0x332
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter18:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits
+ in RV182I mode.
+ address: 0xB12
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter18h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter18h returns the upper half word in RV182I systems.
+ address: 0xB92
+ priv_mode: M
+ reset-val: 0
+ mhpmevent19:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent19 is a MXLEN-bit event register which controls
+ mhpmcounter19.
+ address: 0x333
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter19:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits
+ in RV32I mode.
+ address: 0xB13
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter19h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter19h returns the upper half word in RV32I systems.
+ address: 0xB93
+ priv_mode: M
+ reset-val: 0
+ mhpmevent20:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent20 is a MXLEN-bit event register which controls
+ mhpmcounter20.
+ address: 0x334
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter20:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits
+ in RV202I mode.
+ address: 0xB14
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter20h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter20h returns the upper half word in RV202I systems.
+ address: 0xB94
+ priv_mode: M
+ reset-val: 0
+ mhpmevent21:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent21 is a MXLEN-bit event register which controls
+ mhpmcounter21.
+ address: 0x335
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter21:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits
+ in RV212I mode.
+ address: 0xB15
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter21h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter21h returns the upper half word in RV212I systems.
+ address: 0xB95
+ priv_mode: M
+ reset-val: 0
+ mhpmevent22:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent22 is a MXLEN-bit event register which controls
+ mhpmcounter22.
+ address: 0x336
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter22:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits
+ in RV222I mode.
+ address: 0xB16
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter22h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter22h returns the upper half word in RV222I systems.
+ address: 0xB96
+ priv_mode: M
+ reset-val: 0
+ mhpmevent23:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent23 is a MXLEN-bit event register which controls
+ mhpmcounter23.
+ address: 0x337
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter23:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits
+ in RV232I mode.
+ address: 0xB17
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter23h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter23h returns the upper half word in RV232I systems.
+ address: 0xB97
+ priv_mode: M
+ reset-val: 0
+ mhpmevent24:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent24 is a MXLEN-bit event register which controls
+ mhpmcounter24.
+ address: 0x338
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter24:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits
+ in RV242I mode.
+ address: 0xB18
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter24h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter24h returns the upper half word in RV242I systems.
+ address: 0xB98
+ priv_mode: M
+ reset-val: 0
+ mhpmevent25:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent25 is a MXLEN-bit event register which controls
+ mhpmcounter25.
+ address: 0x339
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter25:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits
+ in RV252I mode.
+ address: 0xB19
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter25h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter25h returns the upper half word in RV252I systems.
+ address: 0xB99
+ priv_mode: M
+ reset-val: 0
+ mhpmevent26:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent26 is a MXLEN-bit event register which controls
+ mhpmcounter26.
+ address: 0x33a
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter26:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits
+ in RV262I mode.
+ address: 0xB1A
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter26h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter26h returns the upper half word in RV262I systems.
+ address: 0xB9A
+ priv_mode: M
+ reset-val: 0
+ mhpmevent27:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent27 is a MXLEN-bit event register which controls
+ mhpmcounter27.
+ address: 0x33b
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter27:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits
+ in RV272I mode.
+ address: 0xB1B
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter27h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter27h returns the upper half word in RV272I systems.
+ address: 0xB9B
+ priv_mode: M
+ reset-val: 0
+ mhpmevent28:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent28 is a MXLEN-bit event register which controls
+ mhpmcounter28.
+ address: 0x33c
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter28:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits
+ in RV282I mode.
+ address: 0xB1C
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter28h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter28h returns the upper half word in RV282I systems.
+ address: 0xB9C
+ priv_mode: M
+ reset-val: 0
+ mhpmevent29:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent29 is a MXLEN-bit event register which controls
+ mhpmcounter29.
+ address: 0x33d
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter29:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits
+ in RV32I mode.
+ address: 0xB1D
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter29h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter29h returns the upper half word in RV32I systems.
+ address: 0xB9D
+ priv_mode: M
+ reset-val: 0
+ mhpmevent30:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent30 is a MXLEN-bit event register which controls
+ mhpmcounter30.
+ address: 0x33e
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter30:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits
+ in RV302I mode.
+ address: 0xB1E
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter30h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter30h returns the upper half word in RV302I systems.
+ address: 0xB9E
+ priv_mode: M
+ reset-val: 0
+ mhpmevent31:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmevent31 is a MXLEN-bit event register which controls
+ mhpmcounter31.
+ address: 0x33f
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter31:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: *id001
+ description: The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits
+ in RV312I mode.
+ address: 0xB1F
+ priv_mode: M
+ reset-val: 0
+ mhpmcounter31h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The mhpmcounter31h returns the upper half word in RV312I systems.
+ address: 0xB9F
+ priv_mode: M
+ reset-val: 0
+ sedeleg:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: sedeleg
+ address: 258
+ priv_mode: S
+ reset-val: 0
+ sideleg:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: sideleg
+ priv_mode: S
+ address: 259
+ reset-val: 0
+ fflags:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: fcsr.fflags
+ shadow_type: rw
+ msb: 4
+ lsb: 0
+ description: 32-bit register to hold floating point accrued exceptions.
+ address: 001
+ priv_mode: U
+ reset-val: 0
+ frm:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: fcsr.frm
+ shadow_type: rw
+ msb: 2
+ lsb: 0
+ description: 32-bit register to hold Floating-Point Dynamic Rounding Mode.
+ address: 002
+ priv_mode: U
+ reset-val: 0
+ fcsr:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - fflags
+ - frm
+ -
+ -
+ - 8
+ - 63
+ frm:
+ implemented: true
+ description: Stores Floating-Point Dynamic Rounding Mode.
+ shadow:
+ shadow_type: rw
+ msb: 7
+ lsb: 5
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - frm[2:0] in [0x0:0x7]
+ wr_illegal:
+ - Unchanged
+ fflags:
+ implemented: true
+ description: Stores floating point accrued exceptions.
+ shadow:
+ shadow_type: rw
+ msb: 4
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - fflags[4:0] in [0x0:0x1F]
+ wr_illegal:
+ - Unchanged
+ description: 32-bit register to hold Floating-Point Control and Status Register.
+ address: 003
+ priv_mode: U
+ reset-val: 0
+ cycle:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mcycle
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ description: Captures the number of cycles executed from an arbitrary point
+ in time.
+ priv_mode: U
+ address: 0xC00
+ reset-val: 0
+ cycleh:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Upper 32-bits of the mcycle counter; only for rv32.
+ address: 0xC80
+ priv_mode: U
+ reset-val: 0
+ time:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ type:
+ ro_variable: true
+ description: Timer for RDTIME instruction and RTC in the processor.
+ priv_mode: U
+ address: 0xC01
+ reset-val: 0
+ timeh:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Upper 32-bits of the Timer for RDTIME instruction and RTC in
+ the processor; only for rv32.
+ address: 0xC81
+ priv_mode: U
+ reset-val: 0
+ instret:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: minstret
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ description: Captures the number of instructions executed from an arbitrary
+ point in time.
+ priv_mode: U
+ address: 0xC02
+ reset-val: 0
+ instreth:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Upper 32-bits of the minstret counter; only for rv32.
+ address: 0xC82
+ priv_mode: U
+ reset-val: 0
+ hpmcounter3:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter3
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC03
+ hpmcounter4:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter4
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC04
+ hpmcounter5:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter5
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC05
+ hpmcounter6:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter6
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC06
+ hpmcounter7:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter7
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC07
+ hpmcounter8:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter8
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC08
+ hpmcounter9:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter9
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC09
+ hpmcounter10:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter10
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC0A
+ hpmcounter11:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter11
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC0B
+ hpmcounter12:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter12
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC0C
+ hpmcounter13:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter13
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC0D
+ hpmcounter14:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter14
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC0E
+ hpmcounter15:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter15
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC0F
+ hpmcounter16:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter16
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC10
+ hpmcounter17:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter17
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC11
+ hpmcounter18:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter18
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC12
+ hpmcounter19:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter19
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC13
+ hpmcounter20:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter20
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC14
+ hpmcounter21:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter21
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC15
+ hpmcounter22:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter22
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC16
+ hpmcounter23:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter23
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC17
+ hpmcounter24:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter24
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC18
+ hpmcounter25:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter25
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC19
+ hpmcounter26:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter26
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC1A
+ hpmcounter27:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter27
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC1B
+ hpmcounter28:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter28
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC1C
+ hpmcounter29:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter29
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC1D
+ hpmcounter30:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter30
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC1E
+ hpmcounter31:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow: mhpmcounter31
+ shadow_type: ro
+ msb: 63
+ lsb: 0
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in
+ RV32UI mode.
+ address: 0xC1F
+ hpmcounter3h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter3h returns the upper half word in RV32I systems.
+ address: 0xC83
+ hpmcounter4h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter4h returns the upper half word in RV32I systems.
+ address: 0xC84
+ hpmcounter5h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter5h returns the upper half word in RV32I systems.
+ address: 0xC85
+ hpmcounter6h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter6h returns the upper half word in RV32I systems.
+ address: 0xC86
+ hpmcounter7h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter7h returns the upper half word in RV32I systems.
+ address: 0xC87
+ hpmcounter8h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter8h returns the upper half word in RV32I systems.
+ address: 0xC88
+ hpmcounter9h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter9h returns the upper half word in RV32I systems.
+ address: 0xC89
+ hpmcounter10h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter10h returns the upper half word in RV32I systems.
+ address: 0xC8A
+ hpmcounter11h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter11h returns the upper half word in RV32I systems.
+ address: 0xC8B
+ hpmcounter12h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter12h returns the upper half word in RV32I systems.
+ address: 0xC8C
+ hpmcounter13h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter13h returns the upper half word in RV32I systems.
+ address: 0xC8D
+ hpmcounter14h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter14h returns the upper half word in RV32I systems.
+ address: 0xC8E
+ hpmcounter15h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter15h returns the upper half word in RV32I systems.
+ address: 0xC8F
+ hpmcounter16h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter16h returns the upper half word in RV32I systems.
+ address: 0xC90
+ hpmcounter17h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter17h returns the upper half word in RV32I systems.
+ address: 0xC91
+ hpmcounter18h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter18h returns the upper half word in RV32I systems.
+ address: 0xC92
+ hpmcounter19h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter19h returns the upper half word in RV32I systems.
+ address: 0xC93
+ hpmcounter20h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter20h returns the upper half word in RV32I systems.
+ address: 0xC94
+ hpmcounter21h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter21h returns the upper half word in RV32I systems.
+ address: 0xC95
+ hpmcounter22h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter22h returns the upper half word in RV32I systems.
+ address: 0xC96
+ hpmcounter23h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter23h returns the upper half word in RV32I systems.
+ address: 0xC97
+ hpmcounter24h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter24h returns the upper half word in RV32I systems.
+ address: 0xC98
+ hpmcounter25h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter25h returns the upper half word in RV32I systems.
+ address: 0xC99
+ hpmcounter26h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter26h returns the upper half word in RV32I systems.
+ address: 0xC9A
+ hpmcounter27h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter27h returns the upper half word in RV32I systems.
+ address: 0xC9B
+ hpmcounter28h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter28h returns the upper half word in RV32I systems.
+ address: 0xC9C
+ hpmcounter29h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter29h returns the upper half word in RV32I systems.
+ address: 0xC9D
+ hpmcounter30h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter30h returns the upper half word in RV32I systems.
+ address: 0xC9E
+ hpmcounter31h:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ priv_mode: U
+ reset-val: 0
+ description: The hpmcounter31h returns the upper half word in RV32I systems.
+ address: 0xC9F
+ sstatus:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - uie
+ - sie
+ - upie
+ - spie
+ - spp
+ - fs
+ - xs
+ - sum
+ - mxr
+ - uxl
+ - sd
+ -
+ -
+ - 2
+ - 3
+ -
+ - 6
+ - 7
+ -
+ - 9
+ - 12
+ -
+ - 17
+ -
+ - 20
+ - 31
+ -
+ - 34
+ - 62
+ uie:
+ implemented: false
+ description: Stores the state of the user mode interrupts.
+ shadow: mstatus.uie
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ sie:
+ implemented: true
+ description: Stores the state of the supervisor mode interrupts.
+ shadow: mstatus.sie
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ upie:
+ implemented: false
+ description: Stores the state of the user mode interrupts prior to
+ the trap.
+ shadow: mstatus.upie
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ spie:
+ implemented: true
+ description: Stores the state of the supervisor mode interrupts prior
+ to the trap.
+ shadow: mstatus.spie
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ spp:
+ implemented: true
+ description: Stores the previous priority mode for supervisor.
+ shadow: mstatus.spp
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ fs:
+ implemented: true
+ description: Encodes the status of the floating-point unit, including
+ the CSR fcsr and floating-point data registers.
+ shadow: mstatus.fs
+ shadow_type: rw
+ msb: 14
+ lsb: 13
+ xs:
+ implemented: false
+ description: Encodes the status of additional user-mode extensions
+ and associated state.
+ shadow: mstatus.xs
+ shadow_type: rw
+ msb: 16
+ lsb: 15
+ sum:
+ implemented: true
+ description: Modifies the privilege with which S-mode loads and stores
+ access virtual memory.
+ shadow: mstatus.sum
+ shadow_type: rw
+ msb: 18
+ lsb: 18
+ mxr:
+ implemented: true
+ description: Modifies the privilege with which loads access virtual
+ memory.
+ shadow: mstatus.mxr
+ shadow_type: rw
+ msb: 19
+ lsb: 19
+ uxl:
+ implemented: true
+ description: Controls the xlen for User mode.
+ shadow: mstatus.uxl
+ shadow_type: rw
+ msb: 33
+ lsb: 32
+ sd:
+ implemented: true
+ description: Read-only bit that summarizes whether either the FS field
+ or XS field signals the presence of some dirty state.
+ shadow: mstatus.sd
+ shadow_type: rw
+ msb: 63
+ lsb: 63
+ description: The sstatus register keeps track of the processor’s current operating
+ state.
+ address: 0x100
+ priv_mode: S
+ reset-val: 0
+ sie:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - usie
+ - ssie
+ - utie
+ - stie
+ - ueie
+ - seie
+ -
+ -
+ - 2
+ - 3
+ -
+ - 6
+ - 7
+ -
+ - 10
+ - 63
+ usie:
+ implemented: false
+ description: User Software Interrupt enable.
+ shadow: mie.usie
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ ssie:
+ implemented: true
+ description: Supervisor Software Interrupt enable.
+ shadow: mie.ssie
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ utie:
+ implemented: false
+ description: User Timer Interrupt enable.
+ shadow: mie.utie
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ stie:
+ implemented: true
+ description: Supervisor Timer Interrupt enable.
+ shadow: mie.stie
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ ueie:
+ implemented: false
+ description: User External Interrupt enable.
+ shadow: mie.ueie
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ seie:
+ implemented: true
+ description: Supervisor External Interrupt enable.
+ shadow: mie.seie
+ shadow_type: rw
+ msb: 9
+ lsb: 9
+ description: The sie register is an SXLEN-bit read/write register containing
+ interrupt enable bits.
+ address: 0x104
+ priv_mode: S
+ reset-val: 0
+ sip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - usip
+ - ssip
+ - utip
+ - stip
+ - ueip
+ - seip
+ -
+ -
+ - 2
+ - 3
+ -
+ - 6
+ - 7
+ -
+ - 10
+ - 63
+ usip:
+ implemented: false
+ description: User Software Interrupt enable.
+ shadow: mip.usip
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ ssip:
+ implemented: true
+ description: Supervisor Software Interrupt enable.
+ shadow: mip.ssip
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ utip:
+ implemented: false
+ description: User Timer Interrupt enable.
+ shadow: mip.utip
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ stip:
+ implemented: true
+ description: Supervisor Timer Interrupt enable.
+ shadow: mip.stip
+ shadow_type: ro
+ msb: 5
+ lsb: 5
+ ueip:
+ implemented: false
+ description: User External Interrupt enable.
+ shadow: mip.ueip
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ seip:
+ implemented: true
+ description: Supervisor External Interrupt enable.
+ shadow: mip.seip
+ shadow_type: ro
+ msb: 9
+ lsb: 9
+ description: The sip register is an SXLEN-bit read/write register containing
+ interrupt pending bits.
+ address: 0x144
+ priv_mode: S
+ reset-val: 0
+ sscratch:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - sscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The sscratch register is an MXLEN-bit read/write register dedicated
+ for use by machine mode.
+ address: 0x140
+ priv_mode: S
+ reset-val: 0
+ sepc:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - sepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The sepc is a warl register that must be able to hold all valid
+ physical and virtual addresses.
+ address: 0x141
+ priv_mode: S
+ reset-val: 0
+ stval:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - stval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The stval is a warl register that holds the address of the instruction
+ which caused the exception.
+ address: 0x143
+ priv_mode: S
+ reset-val: 0
+ scause:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - exception_code
+ - interrupt
+ interrupt:
+ implemented: true
+ description: Indicates whether the trap was due to an interrupt.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 63
+ type:
+ wlrl:
+ - 0:1
+ exception_code:
+ implemented: true
+ description: Encodes the exception code.
+ shadow:
+ shadow_type: rw
+ msb: 62
+ lsb: 0
+ type:
+ wlrl:
+ - 0:15
+ description: The scause register stores the information regarding the trap.
+ address: 0x142
+ priv_mode: S
+ reset-val: 0
+ stvec:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - mode
+ - base
+ base:
+ implemented: true
+ description: Vector base address.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 2
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - base[61:0] bitmask [0x3FFFFFFFFFFFFFFF, 0x0000000000000000]
+ wr_illegal:
+ - Unchanged
+ mode:
+ implemented: true
+ description: Vector mode.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mode[1:0] in [0x0:0x1]
+ wr_illegal:
+ - Unchanged
+ description: SXLEN-bit read/write register that holds trap vector configuration.
+ address: 0x105
+ priv_mode: S
+ reset-val: 0
+ satp:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - ppn
+ - asid
+ - mode
+ ppn:
+ implemented: true
+ description: Physical Page Number
+ shadow:
+ shadow_type: rw
+ msb: 43
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - ppn[43:0] in [0x0:0xFFFFFFFFFFF]
+ wr_illegal:
+ - Unchanged
+ asid:
+ implemented: true
+ description: Address Space identifier.
+ shadow:
+ shadow_type: rw
+ msb: 59
+ lsb: 44
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - asid[15:0] in [0x0:0xFFFF]
+ wr_illegal:
+ - Unchanged
+ mode:
+ implemented: true
+ description: Vector mode.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 60
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mode[3:0] in [0, 8, 9, 10]
+ wr_illegal:
+ - Unchanged
+ description: SXLEN-bit register which controls supervisor-mode address translation
+ and protection
+ address: 0x180
+ priv_mode: S
+ reset-val: 0
+ ustatus:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The ustatus register keeps track of the processor’s current operating
+ state.
+ address: 0x000
+ priv_mode: U
+ reset-val: 0
+ uie:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The uie register is an UXLEN-bit read/write register containing
+ interrupt enable bits.
+ address: 0x004
+ priv_mode: U
+ reset-val: 0
+ uip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The uip register is an UXLEN-bit read/write register containing
+ interrupt pending bits.
+ address: 0x044
+ priv_mode: U
+ reset-val: 0
+ uscratch:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The uscratch register is an UXLEN-bit read/write register dedicated
+ for use by machine mode.
+ address: 0x040
+ priv_mode: U
+ reset-val: 0
+ uepc:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The uepc is a warl register that must be able to hold all valid
+ physical and virtual addresses.
+ address: 0x041
+ priv_mode: U
+ reset-val: 0
+ utval:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The utval is a warl register that holds the address of the instruction
+ which caused the exception.
+ address: 0x043
+ priv_mode: U
+ reset-val: 0
+ ucause:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The ucause register stores the information regarding the trap.
+ address: 0x042
+ priv_mode: U
+ reset-val: 0
+ utvec:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: UXLEN-bit read/write register that holds trap vector configuration.
+ address: 0x005
+ priv_mode: U
+ reset-val: 0
+ scounteren:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 31
+ lsb: 0
+ type:
+ ro_constant: 0
+ description: The scounteren is a 32-bit register that controls the availability
+ of the hardware performance-monitoring counters to the next-lowest privileged
+ mode.
+ address: 0x106
+ priv_mode: S
+ reset-val: 0
+ hideleg:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - hideleg[63:0] bitmask [0x0000000000000444, 0x0000000000000000]
+ wr_illegal:
+ - unchanged
+ description: Hypervisor Interrupt delegation Register.
+ address: 1539
+ priv_mode: H
+ reset-val: 0
+ hedeleg:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - medeleg[63:0] bitmask [0x0000000000001BFE, 0x000000000000000]
+ wr_illegal:
+ - unchanged
+ description: Hypervisor Exception delegation Register.
+ address: 1538
+ priv_mode: H
+ reset-val: 0
+ hip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - vssip
+ - vstip
+ - vseip
+ - sgeip
+ -
+ -
+ - 0
+ - 1
+ -
+ - 3
+ - 5
+ -
+ - 7
+ - 9
+ -
+ - 11
+ -
+ - 13
+ - 63
+ vssip:
+ implemented: false
+ description: VS-level Software Interrupt Pending.
+ shadow: mip.vssip
+ shadow_type: rw
+ msb: 2
+ lsb: 2
+ vstip:
+ implemented: false
+ description: VS-level Timer Interrupt Pending.
+ shadow: mip.vstip
+ shadow_type: rw
+ msb: 6
+ lsb: 6
+ vseip:
+ implemented: false
+ description: VS-level External Interrupt Pending.
+ shadow: mip.vseip
+ shadow_type: rw
+ msb: 10
+ lsb: 10
+ sgeip:
+ implemented: true
+ description: HS-level External Interrupt Pending.
+ shadow: mip.sgeip
+ shadow_type: rw
+ msb: 12
+ lsb: 12
+ type:
+ ro_variable: true
+ description: The hip register is an HXLEN-bit read/write register containing
+ information on pending interrupts.
+ address: 1604
+ priv_mode: H
+ reset-val: 0
+ hvip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - vssip
+ - vstip
+ - vseip
+ -
+ -
+ - 0
+ - 1
+ -
+ - 3
+ - 5
+ -
+ - 7
+ - 9
+ -
+ - 11
+ - 63
+ vssip:
+ implemented: false
+ description: VS-level Software Interrupt Pending.
+ shadow: mip.vssip
+ shadow_type: rw
+ msb: 2
+ lsb: 2
+ vstip:
+ implemented: false
+ description: VS-level Timer Interrupt Pending.
+ shadow: mip.vstip
+ shadow_type: rw
+ msb: 6
+ lsb: 6
+ vseip:
+ implemented: false
+ description: VS-level External Interrupt Pending.
+ shadow: mip.vseip
+ shadow_type: rw
+ msb: 10
+ lsb: 10
+ description: The hvip register is an HSXLEN-bit read/write register that a
+ hypervisor can write to indicate virtual interrupts intended for VS-mode.
+ address: 1605
+ priv_mode: H
+ reset-val: 0
+ hgeip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type: {ro_variable: true}
+ description: The hgeip register is an HSXLEN-bit read-only register that indicates
+ pending guest external interrupts for this hart.
+ address: 0xE12
+ priv_mode: H
+ reset-val: 0
+ hgeie:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - hgeie[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The hgeie register is an HSXLEN-bit read/write register that
+ contains enable bits for the guest external interrupts at this hart.
+ address: 0x607
+ priv_mode: H
+ reset-val: 0
+ htval:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - htval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The htval is a warl register that holds the address of the instruction
+ which caused the exception.
+ address: 0x643
+ priv_mode: H
+ reset-val: 0
+ htinst:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - htinst[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The htinst is a warl register that need only be able to hold
+ the values that the implementation may automatically write to it on a
+ trap.
+ address: 0x64A
+ priv_mode: H
+ reset-val: 0
+ mtval2:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mtval2[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: When a trap is taken into M-mode, mtval2 is written with additional
+ exception-specific information to assist software in handling the trap.
+ address: 0x34B
+ priv_mode: M
+ reset-val: 0
+ mtinst:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - mtinst[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The mtinst is a warl register that need only be able to hold
+ the values that the implementation may automatically write to it on a
+ trap.
+ address: 0x34A
+ priv_mode: M
+ reset-val: 0
+ hgatp:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - ppn
+ - vmid
+ - mode
+ -
+ -
+ - 58
+ - 59
+ ppn:
+ implemented: false
+ description: Physical Page Number
+ shadow:
+ shadow_type: rw
+ msb: 43
+ lsb: 0
+ vmid:
+ implemented: false
+ description: Address Space identifier.
+ shadow:
+ shadow_type: rw
+ msb: 57
+ lsb: 44
+ mode:
+ implemented: false
+ description: Vector mode.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 60
+ description: HSXLEN-bit register which controls G-stage address translation
+ and protection
+ address: 0x680
+ priv_mode: H
+ reset-val: 0
+ hcounteren:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 31
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - hcounteren[31:0] in [0x00000000:0xFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The hcounteren is a 32-bit register that controls the availability
+ of the hardware performance-monitoring counters to the next-lowest privileged
+ mode.
+ address: 0x606
+ priv_mode: H
+ reset-val: 0
+ htimedelta:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - htimedelta[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The htimedelta CSR is a read/write register that contains the
+ delta between the value of the time CSR and the value returned in VS-mode
+ or VU-mode.
+ priv_mode: H
+ address: 0x605
+ reset-val: 0
+ htimedeltah:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: Upper 32-bits of htimedelta
+ address: 0x615
+ priv_mode: H
+ reset-val: 0
+ vsstatus:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - uie
+ - sie
+ - upie
+ - spie
+ - spp
+ - fs
+ - xs
+ - sum
+ - mxr
+ - uxl
+ - sd
+ -
+ -
+ - 2
+ - 3
+ -
+ - 6
+ - 7
+ -
+ - 9
+ - 12
+ -
+ - 17
+ -
+ - 20
+ - 31
+ -
+ - 34
+ - 62
+ uie:
+ implemented: false
+ description: Stores the state of the user mode interrupts.
+ shadow:
+ shadow_type: rw
+ msb: 0
+ lsb: 0
+ sie:
+ implemented: true
+ description: Stores the state of the supervisor mode interrupts.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ type: {ro_constant: 0}
+ upie:
+ implemented: false
+ description: Stores the state of the user mode interrupts prior to
+ the trap.
+ shadow:
+ shadow_type: rw
+ msb: 4
+ lsb: 4
+ spie:
+ implemented: true
+ description: Stores the state of the supervisor mode interrupts prior
+ to the trap.
+ shadow:
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ type: {ro_constant: 0}
+ spp:
+ implemented: true
+ description: Stores the previous priority mode for supervisor.
+ shadow:
+ shadow_type: rw
+ msb: 8
+ lsb: 8
+ type: {ro_constant: 0}
+ fs:
+ implemented: false
+ description: Encodes the status of the floating-point unit, including
+ the CSR fcsr and floating-point data registers.
+ shadow:
+ shadow_type: rw
+ msb: 14
+ lsb: 13
+ xs:
+ implemented: false
+ description: Encodes the status of additional user-mode extensions
+ and associated state.
+ shadow:
+ shadow_type: rw
+ msb: 16
+ lsb: 15
+ sum:
+ implemented: true
+ description: Modifies the privilege with which S-mode loads and stores
+ access virtual memory.
+ shadow:
+ shadow_type: rw
+ msb: 18
+ lsb: 18
+ type: {ro_constant: 0}
+ mxr:
+ implemented: true
+ description: Modifies the privilege with which loads access virtual
+ memory.
+ shadow:
+ shadow_type: rw
+ msb: 19
+ lsb: 19
+ type: {ro_constant: 0}
+ uxl:
+ implemented: true
+ description: Controls the xlen for User mode.
+ shadow:
+ shadow_type: rw
+ msb: 33
+ lsb: 32
+ type: {ro_constant: 2}
+ sd:
+ implemented: true
+ description: Read-only bit that summarizes whether either the FS field
+ or XS field signals the presence of some dirty state.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 63
+ type: {wlrl: [0:1]}
+ description: The vsstatus register keeps track of the processor’s current
+ operating state.
+ address: 0x200
+ priv_mode: S
+ reset-val: 8589934592
+ vsie:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - ssie
+ - stie
+ - seie
+ -
+ -
+ - 0
+ -
+ - 2
+ - 4
+ -
+ - 6
+ - 8
+ -
+ - 10
+ - 63
+ ssie:
+ implemented: true
+ description: Supervisor Software Interrupt enable.
+ shadow: mie.vssie
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ stie:
+ implemented: true
+ description: Supervisor Timer Interrupt enable.
+ shadow: mie.vstie
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ seie:
+ implemented: true
+ description: Supervisor External Interrupt enable.
+ shadow: mie.vseie
+ shadow_type: rw
+ msb: 9
+ lsb: 9
+ description: The vsie register is an VSXLEN-bit read/write register containing
+ interrupt enable bits.
+ address: 0x204
+ priv_mode: S
+ reset-val: 0
+ vsip:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - ssip
+ - stip
+ - seip
+ -
+ -
+ - 0
+ -
+ - 2
+ - 4
+ -
+ - 6
+ - 8
+ -
+ - 10
+ - 63
+ ssip:
+ implemented: true
+ description: Supervisor Software Interrupt enable.
+ shadow: mip.vssip
+ shadow_type: rw
+ msb: 1
+ lsb: 1
+ stip:
+ implemented: true
+ description: Supervisor Timer Interrupt enable.
+ shadow: mip.vstip
+ shadow_type: rw
+ msb: 5
+ lsb: 5
+ seip:
+ implemented: true
+ description: Supervisor External Interrupt enable.
+ shadow: mip.vseip
+ shadow_type: rw
+ msb: 9
+ lsb: 9
+ description: The vsip register is an VSXLEN-bit read/write register containing
+ interrupt pending bits.
+ address: 0x244
+ priv_mode: S
+ reset-val: 0
+ vsscratch:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vsscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+
+ description: The vsscratch register is an VSXLEN-bit read/write register dedicated
+ for use by machine mode.
+ address: 0x240
+ priv_mode: S
+ reset-val: 0
+ vsepc:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vsepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The vsepc is a warl register that must be able to hold all valid
+ physical and virtual addresses.
+ address: 0x241
+ priv_mode: S
+ reset-val: 0
+ vstval:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields: []
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 0
+ type:
+ warl:
+ dependency_fields: []
+ legal:
+ - vstval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF]
+ wr_illegal:
+ - unchanged
+ description: The vstval is a warl register that holds the address of the instruction
+ which caused the exception.
+ address: 0x243
+ priv_mode: S
+ reset-val: 0
+ vscause:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - exception_code
+ - interrupt
+ interrupt:
+ implemented: false
+ description: Indicates whether the trap was due to an interrupt.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 63
+ exception_code:
+ implemented: false
+ description: Encodes the exception code.
+ shadow:
+ shadow_type: rw
+ msb: 62
+ lsb: 0
+ description: The scause register stores the information regarding the trap.
+ address: 0x242
+ priv_mode: S
+ reset-val: 0
+ vstvec:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - mode
+ - base
+ base:
+ implemented: false
+ description: Vector base address.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 2
+ mode:
+ implemented: false
+ description: Vector mode.
+ shadow:
+ shadow_type: rw
+ msb: 1
+ lsb: 0
+ description: SXLEN-bit read/write register that holds trap vector configuration.
+ address: 0x205
+ priv_mode: S
+ reset-val: 0
+ vsatp:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: true
+ fields:
+ - ppn
+ - asid
+ - mode
+ ppn:
+ implemented: false
+ description: Physical Page Number
+ shadow:
+ shadow_type: rw
+ msb: 43
+ lsb: 0
+ asid:
+ implemented: false
+ description: Address Space identifier.
+ shadow:
+ shadow_type: rw
+ msb: 59
+ lsb: 44
+ mode:
+ implemented: false
+ description: Vector mode.
+ shadow:
+ shadow_type: rw
+ msb: 63
+ lsb: 60
+ description: VSXLEN-bit register which controls supervisor-mode address translation
+ and protection
+ address: 0x280
+ priv_mode: S
+ reset-val: 0
+ vxsat:
+ rv32:
+ accessible: false
+ rv64:
+ accessible: false
+ description: The vxsat register records the overflow saturation condition
+ of P and V instructions.
+ address: 9
+ priv_mode: U
+ reset-val: 0
+ |
+
/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/Dubhe-90_platform_checked.yaml |
+ mtime:
+ implemented: true
+nmi:
+ label: nmi_vector
+reset:
+ label: reset_vector
+mtimecmp:
+ implemented: false
+mtval_condition_writes:
+ implemented: false
+scause_non_standard:
+ implemented: false
+stval_condition_writes:
+ implemented: false
+zicbo_cache_block_sz:
+ implemented: false
+ |
+
Please visit YAML specifications for more information.
+ +(Un)check the boxes to filter the results.
519Passed, 0Failed +Test | +Result | +Path | +|
---|---|---|---|
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b10-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b10-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b11-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b11-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b12-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b12-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b13-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b13-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fadd.d_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fclass.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fclass.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.s_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.w_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.w_b25-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.w_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.w_b26-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.wu_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.wu_b25-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.wu_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.d.wu_b26-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.s.d_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
+TEST_CASE_1=True
+XLEN=64
+FLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b28-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.w.d_b29-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fcvt.wu.d_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b20-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b20-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b21-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b21-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b9-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fdiv.d_b9-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/feq.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/feq.d_b1-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/feq.d_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/feq.d_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fld-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fld-align-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fle.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fle.d_b1-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fle.d_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fle.d_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/flt.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/flt.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/flt.d_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/flt.d_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b14-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b15-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b16-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b17-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b18-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmadd.d_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmax.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmax.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmax.d_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmax.d_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmin.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmin.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmin.d_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmin.d_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b14-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b15-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b16-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b17-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b18-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b2-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b3-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b4-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b5-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b7-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmsub.d_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b3-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b5-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b6-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b7-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b8-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b9-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fmul.d_b9-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b14-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b15-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b16-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b17-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b18-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b2-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmadd.d_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b14-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b15-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b16-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b17-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b18-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b2-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b3-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b5-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b6-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b7-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fnmsub.d_b8-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsd-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsd-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsgnj.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsgnj.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsgnjn.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsgnjn.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsgnjx.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsgnjx.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b2-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b20-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b20-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b3-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b4-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b5-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b7-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b8-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b9-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fsqrt.d_b9-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b10-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b10-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b11-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b11-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b12-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b12-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b13-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b13-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b2-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b3-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b4-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b5-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b7-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/D/src/fssub.d_b8-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b10-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b10-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b11-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b11-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b12-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b12-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b13-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b13-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fadd_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fclass_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fclass_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.w_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.s.w_b25-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.w_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.s.w_b26-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.wu_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.s.wu_b25-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.wu_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.s.wu_b26-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.w.s_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fcvt.wu.s_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b20-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b20-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b21-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b21-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b9-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fdiv_b9-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/feq_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/feq_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/feq_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/feq_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fle_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fle_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fle_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fle_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flt_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/flt_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flt_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/flt_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/flw-align-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b14-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b15-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b16-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b17-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b18-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+XLEN=64
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+FLEN=32 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmadd_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmax_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmax_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmax_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmax_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmin_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmin_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmin_b19-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmin_b19-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b14-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b15-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b16-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b17-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b18-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmsub_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b9-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmul_b9-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.w.x_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.w.x_b25-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.w.x_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.w.x_b26-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b1-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b22-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fmv.x.w_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b14-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b15-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b16-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b17-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b18-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+TEST_CASE_1=True
+XLEN=64
+FLEN=32 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmadd_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b14-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b14-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b15-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b15-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b16-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b16-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b17-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b17-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b18-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b18-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b6-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b6-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fnmsub_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsgnj_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsgnj_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsgnjn_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsgnjn_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsgnjx_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsgnjx_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b20-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b20-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b9-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsqrt_b9-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b10-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b10-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b11-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b11-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b12-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b12-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b13-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b13-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b2-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b2-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b3-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b3-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b4-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b4-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b5-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b5-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b7-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b7-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsub_b8-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsw-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv32i_m/F/src/fsw-align-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoadd.d-01.S | |
+ commit_id:522da8ce564e25d002952d91052b0e9dc242c028
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoadd.w-01.S | |
+ commit_id:522da8ce564e25d002952d91052b0e9dc242c028
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoand.d-01.S | |
+ commit_id:522da8ce564e25d002952d91052b0e9dc242c028
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoand.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amomax.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amomax.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amomaxu.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amomaxu.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amomin.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amomin.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amominu.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amominu.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoor.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoor.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoswap.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoswap.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoxor.d-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/A/src/amoxor.w-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/add.uw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/add.uw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/andn-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/andn-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/bclr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/bclr-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/bclri-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/bclri-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/bext-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/bext-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/bexti-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/bexti-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/binv-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/binv-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/binvi-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/binvi-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/bset-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/bset-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/bseti-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/bseti-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/clmul-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/clmul-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/clmulh-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/clmulh-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/clmulr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/clmulr-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/clz-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/clz-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/clzw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/clzw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/cpop-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/cpop-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/cpopw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/cpopw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/ctz-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/ctz-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/ctzw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/ctzw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/max-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/max-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/maxu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/maxu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/min-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/min-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/minu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/minu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/orcb_64-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/orcb_64-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/orn-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/orn-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/rev8-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/rev8-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/rol-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/rol-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/rolw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/rolw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/ror-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/ror-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/rori-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/rori-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/roriw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/roriw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/rorw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/rorw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sext.b-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sext.b-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sext.h-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sext.h-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sh1add-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sh1add-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sh1add.uw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sh1add.uw-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sh2add-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sh2add-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sh2add.uw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sh2add.uw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sh3add-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sh3add-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/sh3add.uw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/sh3add.uw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/slli.uw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/slli.uw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/xnor-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/xnor-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/zext.h_64-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/B/src/zext.h_64-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cadd-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cadd-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/caddi-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi16sp-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/caddi16sp-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi4spn-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/caddi4spn-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddiw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/caddiw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/caddw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cand-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cand-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/candi-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/candi-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbeqz-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cbeqz-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbnez-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cbnez-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cebreak-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cebreak-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cj-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cj-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjalr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cjalr-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cjr-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cld-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cld-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cldsp-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cldsp-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cli-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cli-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clui-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/clui-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/clw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clwsp-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/clwsp-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cmv-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cmv-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cnop-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cnop-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cor-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cor-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csd-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csd-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csdsp-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csdsp-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cslli-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cslli-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrai-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csrai-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrli-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csrli-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csub-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csub-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csubw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csubw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/csw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cswsp-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cswsp-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cxor-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/C/src/cxor-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.d.l_b25-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.d.l_b26-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.d.lu_b25-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.d.lu_b26-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b22-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b23-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b27-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b28-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.l.d_b29-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b22-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b23-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b24-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b27-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b28-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fcvt.lu.d_b29-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.d.x_b25-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.d.x_b26-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b1-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/D/src/fmv.x.d_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b24-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b27-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.l.s_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.l.s_b29-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b1-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b1-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b22-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b22-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b23-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b23-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b24-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b24-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b27-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b27-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b28-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b28-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.lu.s_b29-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.lu.s_b29-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.s.l_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.s.l_b25-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.s.l_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.s.l_b26-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.s.lu_b25-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.s.lu_b25-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/F/src/fcvt.s.lu_b26-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/F/src/fcvt.s.lu_b26-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/add-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/add-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addi-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/addi-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addiw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/addiw-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/addw-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/and-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/and-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/andi-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/andi-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/auipc-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/auipc-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/beq-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/beq-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bge-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/bge-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bgeu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/bgeu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/blt-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/blt-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bltu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/bltu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bne-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/bne-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/fence-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/fence-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jal-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/jal-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jalr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/jalr-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lb-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lbu-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lbu-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ld-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/ld-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lh-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lh-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lhu-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lhu-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lui-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lui-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lw-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lw-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lwu-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/lwu-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/misalign1-jalr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/misalign1-jalr-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/or-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/or-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ori-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/ori-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sb-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sb-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sd-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sd-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sh-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sh-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sll-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sll-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slli-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/slli-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slliw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/slliw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sllw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sllw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slt-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/slt-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slti-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/slti-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltiu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sltiu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sltu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sra-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sra-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srai-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/srai-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraiw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sraiw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sraw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srl-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/srl-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srli-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/srli-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srliw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/srliw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srlw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/srlw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sub-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sub-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/subw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/subw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sw-align-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/sw-align-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xor-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/xor-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xori-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/I/src/xori-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/div-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/divu-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/divuw-01.S | |
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/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/divw-01.S | |
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mul-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/mul-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
+MACROS:
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulh-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/mulh-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/mulhsu-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/mulhu-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/mulw-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/rem-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/rem-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/remu-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remuw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/remuw-01.S | |
+ commit_id:b91f98f3a0e908bad4680c2e3901fbc24b63a563
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/M/src/remw-01.S | |
+ commit_id:237ce8d5f2ce0330a2823b4ac60b05d5d8604d19
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/Zifencei/src/Fencei.S | |
+ commit_id:274b6cd787d4d5b0b6c41424b9b7dcca495a9d4b
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/ebreak.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/ebreak.S | |
+ commit_id:bb74a4aefaa8c89fb28b876484cfdf9ca020cec1
+MACROS:
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+XLEN=64 |
+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/ecall.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/ecall.S | |
+ commit_id:bb74a4aefaa8c89fb28b876484cfdf9ca020cec1
+MACROS:
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-beq-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-beq-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
+MACROS:
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bge-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-bge-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bgeu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-bgeu-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-blt-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-blt-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bltu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-bltu-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bne-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-bne-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-jal-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-jal-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-ld-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-ld-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lh-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-lh-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lhu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-lhu-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-lw-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lwu-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-lwu-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sd-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-sd-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sh-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-sh-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sw-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign-sw-01.S | |
+ commit_id:fa34ab09dc4314604ae644dfcf818babdb8ea44a
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+ |||
/home/starfive/work/riscv-arch-tests/riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign2-jalr-01.S | +Passed | +/home/starfive/work/riscv-arch-tests/Dubhe-90/riscof_work/rv64i_m/privilege/src/misalign2-jalr-01.S | |
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