From ff0cf7bca63092786d640820a18f3e746b02e172 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 7 Jan 2023 13:18:14 -0800 Subject: [PATCH] i2c: cadence: Remove unnecessary register reads In the `cdns_i2c_mrecv()` function the CTRL register of the Cadence I2C controller is written and read back multiple times. The register value does not change on its own. So it is possible to remember the just written value instead of reading it back from the hardware. Signed-off-by: Lars-Peter Clausen Acked-by: Michal Simek Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-cadence.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c index bec50bfe7aada2..93c6d082246835 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -613,7 +613,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) /* Determine hold_clear based on number of bytes to receive and hold flag */ if (!id->bus_hold_flag && id->recv_count <= CDNS_I2C_FIFO_DEPTH) { - if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) { + if (ctrl_reg & CDNS_I2C_CR_HOLD) { hold_clear = true; if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) irq_save = true; @@ -624,7 +624,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) addr &= CDNS_I2C_ADDR_MASK; if (hold_clear) { - ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD; + ctrl_reg &= ~CDNS_I2C_CR_HOLD; /* * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size * register reaches '0'. This is an IP bug which causes transfer size