From b667ded86b8aeb6f5a55a15665532e3b31d3c844 Mon Sep 17 00:00:00 2001 From: pgschuey Date: Thu, 23 Jan 2025 17:57:04 -0700 Subject: [PATCH] [XDP] First cut implementation of AIE Debug feature for all devices (#8701) --- src/runtime_src/core/common/config_reader.h | 9 +- .../core/edge/hw_emu/CMakeLists.txt | 3 + .../core/edge/user/plugin/xdp/aie_debug.cpp | 72 + .../core/edge/user/plugin/xdp/aie_debug.h | 37 + .../edge/user/plugin/xdp/plugin_loader.cpp | 5 + .../edge/user/plugin/xdp/shim_callbacks.h | 16 +- .../database/dynamic_event_database.cpp | 23 +- .../profile/database/dynamic_event_database.h | 10 +- .../profile/database/dynamic_info/aie_db.h | 15 +- .../profile/database/dynamic_info/device_db.h | 14 +- .../profile/database/dynamic_info/samples.h | 27 + .../xdp/profile/database/dynamic_info/types.h | 9 + .../xdp/profile/plugin/CMakeLists.txt | 2 + .../profile/plugin/aie_debug/CMakeLists.txt | 44 +- .../profile/plugin/aie_debug/aie_debug_cb.cpp | 17 +- .../profile/plugin/aie_debug/aie_debug_cb.h | 17 +- .../profile/plugin/aie_debug/aie_debug_impl.h | 54 + .../plugin/aie_debug/aie_debug_metadata.cpp | 212 + .../plugin/aie_debug/aie_debug_metadata.h | 8322 +++++++++++++++++ .../plugin/aie_debug/aie_debug_plugin.cpp | 406 +- .../plugin/aie_debug/aie_debug_plugin.h | 66 +- .../plugin/aie_debug/client/aie_debug.cpp | 203 + .../plugin/aie_debug/client/aie_debug.h | 73 + .../plugin/aie_debug/edge/aie_debug.cpp | 183 + .../profile/plugin/aie_debug/edge/aie_debug.h | 75 + .../aie_debug/generations/aie1_attributes.h | 287 + .../aie_debug/generations/aie1_registers.h | 1266 +++ .../aie_debug/generations/aie2_attributes.h | 387 + .../aie_debug/generations/aie2_registers.h | 2838 ++++++ .../aie_debug/generations/aie2ps_attributes.h | 510 + .../aie_debug/generations/aie2ps_registers.h | 3663 ++++++++ .../plugin/aie_debug/util/aie_debug_util.cpp | 0 .../plugin/aie_debug/util/aie_debug_util.h | 0 .../plugin/aie_debug/ve2/aie_debug.cpp | 184 + .../profile/plugin/aie_debug/ve2/aie_debug.h | 75 + .../profile/plugin/aie_profile/CMakeLists.txt | 2 +- .../writer/aie_debug/aie_debug_writer.cpp | 105 + .../writer/aie_debug/aie_debug_writer.h | 44 + .../aie_debug_writer_aie1_metadata.cpp | 1491 +++ .../aie_debug_writer_aie2_metadata.cpp | 2288 +++++ .../aie_debug_writer_aie2ps_metadata.cpp | 2577 +++++ .../aie_debug/aie_debug_writer_metadata.h | 106 + .../writer/aie_debug/register_interpreter.cpp | 60 + .../writer/aie_debug/register_interpreter.h | 50 + 44 files changed, 25545 insertions(+), 302 deletions(-) create mode 100644 src/runtime_src/core/edge/user/plugin/xdp/aie_debug.cpp create mode 100644 src/runtime_src/core/edge/user/plugin/xdp/aie_debug.h mode change 100755 => 100644 src/runtime_src/xdp/profile/database/dynamic_event_database.cpp mode change 100755 => 100644 src/runtime_src/xdp/profile/database/dynamic_event_database.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_impl.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.cpp create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.h create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.cpp create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.cpp create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.h create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_attributes.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_registers.h create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_attributes.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_registers.h create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_attributes.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/util/aie_debug_util.cpp create mode 100644 src/runtime_src/xdp/profile/plugin/aie_debug/util/aie_debug_util.h create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.cpp create mode 100755 src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.h create mode 100644 src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.cpp create mode 100644 src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.h create mode 100644 src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie1_metadata.cpp create mode 100644 src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2_metadata.cpp create mode 100644 src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2ps_metadata.cpp create mode 100755 src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h create mode 100755 src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.cpp create mode 100755 src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.h diff --git a/src/runtime_src/core/common/config_reader.h b/src/runtime_src/core/common/config_reader.h index 64a00f83664..9709402d3c6 100644 --- a/src/runtime_src/core/common/config_reader.h +++ b/src/runtime_src/core/common/config_reader.h @@ -769,32 +769,31 @@ get_device_offline_timer() return value; } -// Configurations under AIE_debug_settings section inline std::string get_aie_debug_settings_core_registers() { - static std::string value = detail::get_string_value("AIE_debug_settings.core_registers", ""); + static std::string value = detail::get_string_value("AIE_debug_settings.core_registers", "all"); return value; } inline std::string get_aie_debug_settings_memory_registers() { - static std::string value = detail::get_string_value("AIE_debug_settings.memory_registers", ""); + static std::string value = detail::get_string_value("AIE_debug_settings.memory_registers", "all"); return value; } inline std::string get_aie_debug_settings_interface_registers() { - static std::string value = detail::get_string_value("AIE_debug_settings.interface_registers", ""); + static std::string value = detail::get_string_value("AIE_debug_settings.interface_registers", "all"); return value; } inline std::string get_aie_debug_settings_memory_tile_registers() { - static std::string value = detail::get_string_value("AIE_debug_settings.memory_tile_registers", ""); + static std::string value = detail::get_string_value("AIE_debug_settings.memory_tile_registers", "all"); return value; } diff --git a/src/runtime_src/core/edge/hw_emu/CMakeLists.txt b/src/runtime_src/core/edge/hw_emu/CMakeLists.txt index 370c61c9e12..dd202f9d92b 100644 --- a/src/runtime_src/core/edge/hw_emu/CMakeLists.txt +++ b/src/runtime_src/core/edge/hw_emu/CMakeLists.txt @@ -40,6 +40,9 @@ file(GLOB XDP_PLUGIN_HW_EM_FILES "${XDP_PLUGIN_DIR}/aie_status.cpp" "${XDP_PLUGIN_DIR}/aie_profile.h" "${XDP_PLUGIN_DIR}/aie_profile.cpp" + "${XDP_PLUGIN_DIR}/aie_debug.h" + "${XDP_PLUGIN_DIR}/aie_debug.cpp" + ) if (DEFINED XRT_AIE_BUILD) diff --git a/src/runtime_src/core/edge/user/plugin/xdp/aie_debug.cpp b/src/runtime_src/core/edge/user/plugin/xdp/aie_debug.cpp new file mode 100644 index 00000000000..8aec9450c10 --- /dev/null +++ b/src/runtime_src/core/edge/user/plugin/xdp/aie_debug.cpp @@ -0,0 +1,72 @@ +/** + * Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#include "aie_debug.h" +#include "core/common/module_loader.h" +#include "core/common/dlfcn.h" +#include + +namespace xdp { +namespace aie { +namespace debug { + void load() + { +//#ifdef XRT_ENABLE_AIE + static xrt_core::module_loader xdp_aie_loader("xdp_aie_debug_plugin", + register_callbacks, + warning_callbacks); +//#endif + } + std::function update_device_cb; + std::function end_poll_cb; + + void register_callbacks(void* handle) + { + using ftype = void (*)(void*); // Device handle + + update_device_cb = reinterpret_cast(xrt_core::dlsym(handle, "updateAIEDebugDevice")); + if (xrt_core::dlerror() != nullptr) + update_device_cb = nullptr; + + end_poll_cb = reinterpret_cast(xrt_core::dlsym(handle, "endAIEDebugRead")); + if (xrt_core::dlerror() != nullptr) + end_poll_cb = nullptr; + } + + void warning_callbacks() + { + // No warnings for AIE debug plugin + } + +} // end namespace debug + +namespace dbg { + void update_device(void* handle) + { + if (debug::update_device_cb != nullptr) { + debug::update_device_cb(handle) ; + } + } + + void end_poll(void* handle) + { + if (debug::end_poll_cb != nullptr) { + debug::end_poll_cb(handle) ; + } + } +} // end namespace dbg +} // end namespace aie +} // end namespace xdp diff --git a/src/runtime_src/core/edge/user/plugin/xdp/aie_debug.h b/src/runtime_src/core/edge/user/plugin/xdp/aie_debug.h new file mode 100644 index 00000000000..e51377fbefb --- /dev/null +++ b/src/runtime_src/core/edge/user/plugin/xdp/aie_debug.h @@ -0,0 +1,37 @@ +/** + * Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_DOT_H +#define AIE_DEBUG_DOT_H + +namespace xdp { +namespace aie { + +namespace debug { + void load(); + void register_callbacks(void* handle); + void warning_callbacks(); +} // end namespace debug + +namespace dbg { + void update_device(void* handle); + void end_poll(void* handle); +} // end namespace dbg + +} // end namespace aie +} // end namespace xdp + +#endif diff --git a/src/runtime_src/core/edge/user/plugin/xdp/plugin_loader.cpp b/src/runtime_src/core/edge/user/plugin/xdp/plugin_loader.cpp index 4df1d7fcda8..2bcec392477 100644 --- a/src/runtime_src/core/edge/user/plugin/xdp/plugin_loader.cpp +++ b/src/runtime_src/core/edge/user/plugin/xdp/plugin_loader.cpp @@ -24,6 +24,7 @@ #include "aie_status.h" #include "aie_profile.h" +#include "aie_debug.h" #ifndef __HWEM__ #include "aie_trace.h" @@ -56,6 +57,8 @@ bool load() if (xrt_core::config::get_aie_profile()) xdp::aie::profile::load(); + if (xrt_core::config::get_aie_debug()) + xdp::aie::debug::load(); if (xrt_core::config::get_noc_profile()) xdp::noc::profile::load(); @@ -103,6 +106,8 @@ bool load() if (xrt_core::config::get_aie_profile()) xdp::aie::profile::load(); + if (xrt_core::config::get_aie_debug()) + xdp::aie::debug::load(); #endif return true ; } diff --git a/src/runtime_src/core/edge/user/plugin/xdp/shim_callbacks.h b/src/runtime_src/core/edge/user/plugin/xdp/shim_callbacks.h index 4e0dd9ce8d3..0a7f801e6f7 100644 --- a/src/runtime_src/core/edge/user/plugin/xdp/shim_callbacks.h +++ b/src/runtime_src/core/edge/user/plugin/xdp/shim_callbacks.h @@ -31,6 +31,7 @@ #include "aie_profile.h" #include "aie_status.h" #include "hal_device_offload.h" +#include "aie_debug.h" #ifdef __HWEM__ #include "hw_emu_device_offload.h" @@ -45,14 +46,15 @@ inline void update_device(void* handle) { #ifndef __HWEM__ - hal::update_device(handle); - aie::update_device(handle); + hal::update_device(handle); //PL device offload + aie::update_device(handle); //trace + //aie::dbg::update_device(handle); //debug #else - hal::hw_emu::update_device(handle); + hal::hw_emu::update_device(handle); //PL device offload #endif - - aie::ctr::update_device(handle); - aie::sts::update_device(handle); + aie::dbg::update_device(handle); //debug + aie::ctr::update_device(handle); //counters=profiling + aie::sts::update_device(handle); //status } // The flush_device callback should be called just before a new xclbin @@ -84,8 +86,10 @@ void finish_flush_device(void* handle) { #ifndef __HWEM__ aie::finish_flush_device(handle); + //aie::dbg::end_poll(handle); #endif aie::ctr::end_poll(handle); + aie::dbg::end_poll(handle); } } // end namespace xdp diff --git a/src/runtime_src/xdp/profile/database/dynamic_event_database.cpp b/src/runtime_src/xdp/profile/database/dynamic_event_database.cpp old mode 100755 new mode 100644 index 32826aba5ec..77fe45b9d97 --- a/src/runtime_src/xdp/profile/database/dynamic_event_database.cpp +++ b/src/runtime_src/xdp/profile/database/dynamic_event_database.cpp @@ -26,7 +26,7 @@ #include namespace xdp { - + VPDynamicDatabase::VPDynamicDatabase(VPDatabase* d) : db(d), eventId(1) { @@ -291,6 +291,27 @@ namespace xdp { return device_db->moveAIESamples(); } + void VPDynamicDatabase::addAIEDebugSample(uint64_t deviceId, uint8_t col, + uint8_t row, uint32_t value, uint64_t offset, std::string name) + { + auto device_db = getDeviceDB(deviceId); + device_db->addAIEDebugSample(col, row, value, offset, name); + } + + std::vector + VPDynamicDatabase::getAIEDebugSamples(uint64_t deviceId) + { + auto device_db = getDeviceDB(deviceId); + return device_db->getAIEDebugSamples(); + } + + std::vector + VPDynamicDatabase::moveAIEDebugSamples(uint64_t deviceId) + { + auto device_db = getDeviceDB(deviceId); + return device_db->moveAIEDebugSamples(); + } + void VPDynamicDatabase::addAIETimerSample(uint64_t deviceId, unsigned long timestamp1, unsigned long timestamp2, const std::vector& values) { diff --git a/src/runtime_src/xdp/profile/database/dynamic_event_database.h b/src/runtime_src/xdp/profile/database/dynamic_event_database.h old mode 100755 new mode 100644 index 38f459b78dd..6b979e88eda --- a/src/runtime_src/xdp/profile/database/dynamic_event_database.h +++ b/src/runtime_src/xdp/profile/database/dynamic_event_database.h @@ -163,7 +163,7 @@ namespace xdp { XDP_CORE_EXPORT void addDependency(uint64_t id, uint64_t dependency) ; XDP_CORE_EXPORT std::map> getDependencyMap() ; - // Add and get AIE Trace Data Buffer + // Add and get AIE Trace Data Buffer XDP_CORE_EXPORT void addAIETraceData(uint64_t deviceId, uint64_t strmIndex, void* buffer, uint64_t bufferSz, bool copy); XDP_CORE_EXPORT aie::TraceDataType* getAIETraceData(uint64_t deviceId, uint64_t strmIndex); @@ -173,7 +173,11 @@ namespace xdp { XDP_CORE_EXPORT std::vector getPowerSamples(uint64_t deviceId) ; XDP_CORE_EXPORT void addAIESample(uint64_t deviceId, double timestamp, - const std::vector& values) ; + const std::vector& values); + XDP_CORE_EXPORT void addAIEDebugSample(uint64_t deviceId, uint8_t col, + uint8_t row, uint32_t value, uint64_t offset, std::string name); + XDP_CORE_EXPORT std::vector moveAIEDebugSamples(uint64_t deviceId); + XDP_CORE_EXPORT std::vector getAIEDebugSamples(uint64_t deviceId); XDP_CORE_EXPORT std::vector getAIESamples(uint64_t deviceId) ; XDP_CORE_EXPORT std::vector moveAIESamples(uint64_t deviceId); XDP_CORE_EXPORT void addAIETimerSample(uint64_t deviceId, unsigned long timestamp1, @@ -188,7 +192,7 @@ namespace xdp { XDP_CORE_EXPORT void setPLDeadlockInfo(uint64_t deviceId, const std::string& str); XDP_CORE_EXPORT std::string getPLDeadlockInfo(); } ; - + } #endif diff --git a/src/runtime_src/xdp/profile/database/dynamic_info/aie_db.h b/src/runtime_src/xdp/profile/database/dynamic_info/aie_db.h index 68dd280ebee..c091a52d0e6 100644 --- a/src/runtime_src/xdp/profile/database/dynamic_info/aie_db.h +++ b/src/runtime_src/xdp/profile/database/dynamic_info/aie_db.h @@ -37,6 +37,7 @@ namespace xdp { SampleContainer samples; DoubleSampleContainer timerSamples; + AIEDebugContainer aieDebugSamples; std::mutex traceLock; // Protects "traceData" vector @@ -54,10 +55,14 @@ namespace xdp { void addAIESample(double timestamp, const std::vector& values); inline - void addAIETimerSample(unsigned long timestamp1, unsigned long timestamp2, + void addAIETimerSample(unsigned long timestamp1, unsigned long timestamp2, const std::vector& values) { timerSamples.addSample({timestamp1, timestamp2, values}); } + inline + void addAIEDebugSample(uint8_t col, uint8_t row, uint32_t value, uint64_t offset, std::string name) + { aieDebugSamples.addAIEDebugData({col, row, value, offset, name}); } + inline std::vector getAIESamples() { return samples.getSamples(); } @@ -69,6 +74,14 @@ namespace xdp { inline std::vector getAIETimerSamples() { return timerSamples.getSamples(); } + + inline + std::vector getAIEDebugSamples() + { return aieDebugSamples.getAIEDebugData(); } + + inline + std::vector moveAIEDebugSamples() + { return aieDebugSamples.moveAIEDebugData(); } }; } // end namespace xdp diff --git a/src/runtime_src/xdp/profile/database/dynamic_info/device_db.h b/src/runtime_src/xdp/profile/database/dynamic_info/device_db.h index d8f273d7981..27adf93e47a 100644 --- a/src/runtime_src/xdp/profile/database/dynamic_info/device_db.h +++ b/src/runtime_src/xdp/profile/database/dynamic_info/device_db.h @@ -107,10 +107,14 @@ namespace xdp { void addAIESample(double timestamp, const std::vector& values) { aie_db.addAIESample(timestamp, values); } - void addAIETimerSample(unsigned long timestamp1, unsigned long timestamp2, + void addAIETimerSample(unsigned long timestamp1, unsigned long timestamp2, const std::vector& values) { aie_db.addAIETimerSample(timestamp1, timestamp2, values); } + inline + void addAIEDebugSample(uint8_t col, uint8_t row, uint32_t value, uint64_t offset, std::string name) + { aie_db.addAIEDebugSample(col, row, value, offset, name); } + inline std::vector getAIESamples() { return aie_db.getAIESamples(); } @@ -126,6 +130,14 @@ namespace xdp { inline std::string& getPLDeadlockInfo() { return pl_db.getDeadlockInfo(); } + inline + std::vector getAIEDebugSamples() + { return aie_db.getAIEDebugSamples(); } + + inline std::vector moveAIEDebugSamples() + { return aie_db.moveAIEDebugSamples(); } + + }; } // end namespace xdp diff --git a/src/runtime_src/xdp/profile/database/dynamic_info/samples.h b/src/runtime_src/xdp/profile/database/dynamic_info/samples.h index a459af4c4ba..c834132600a 100644 --- a/src/runtime_src/xdp/profile/database/dynamic_info/samples.h +++ b/src/runtime_src/xdp/profile/database/dynamic_info/samples.h @@ -87,6 +87,33 @@ namespace xdp { } }; + + class AIEDebugContainer + { + private: + std::vector samples; + std::mutex containerLock; // Protects the "samples" vector + + public: + AIEDebugContainer() = default; + ~AIEDebugContainer() = default; + + inline void addAIEDebugData(const xdp::aie::AIEDebugDataType& s) + { + std::lock_guard lock(containerLock); + samples.push_back(s); + } + inline std::vector getAIEDebugData() + { + std::lock_guard lock(containerLock); + return samples; + } + inline std::vector moveAIEDebugData() + { + std::lock_guard lock(containerLock); + return std::move(samples); + } + }; } // end namespace xdp #endif diff --git a/src/runtime_src/xdp/profile/database/dynamic_info/types.h b/src/runtime_src/xdp/profile/database/dynamic_info/types.h index fc608fdfa5c..99be1bce52c 100644 --- a/src/runtime_src/xdp/profile/database/dynamic_info/types.h +++ b/src/runtime_src/xdp/profile/database/dynamic_info/types.h @@ -82,6 +82,15 @@ namespace xdp::aie { typedef std::vector TraceDataVector; + struct AIEDebugDataType + { + uint8_t col; + uint8_t row; + uint32_t value; + uint64_t offset; + std::string name; + }; + } // end namespace xdp::aie #endif diff --git a/src/runtime_src/xdp/profile/plugin/CMakeLists.txt b/src/runtime_src/xdp/profile/plugin/CMakeLists.txt index 47b69ea2991..2b8f4ec92c5 100644 --- a/src/runtime_src/xdp/profile/plugin/CMakeLists.txt +++ b/src/runtime_src/xdp/profile/plugin/CMakeLists.txt @@ -5,6 +5,7 @@ if(XDP_VE2_BUILD_CMAKE STREQUAL "yes") add_subdirectory(aie_profile) add_subdirectory(aie_trace) + add_subdirectory(aie_debug) add_subdirectory(ml_timeline) elseif (XDP_CLIENT_BUILD_CMAKE STREQUAL "yes") @@ -44,6 +45,7 @@ if (NOT WIN32) add_subdirectory(aie_status) add_subdirectory(aie_profile) add_subdirectory(aie_trace) +add_subdirectory(aie_debug) add_subdirectory(device_offload/hw_emu) add_subdirectory(noc) add_subdirectory(power) diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/CMakeLists.txt b/src/runtime_src/xdp/profile/plugin/aie_debug/CMakeLists.txt index 00b5747cda1..33ccbabeb34 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_debug/CMakeLists.txt +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/CMakeLists.txt @@ -1,15 +1,29 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. # # ==================================================================== -# This builds the AIE Profile plugin. It is currently built -# on both Edge and x86 platforms that support AIE. +# This builds the AIE Debug plugin. It is currently built +# on Edge, Client, and VE2 platforms that support AIE. +# Note it is not built or supported on x86. # ==================================================================== +if (XDP_VE2_BUILD_CMAKE STREQUAL "yes") + set(IMPL_DIR "${PROFILE_DIR}/plugin/aie_debug/ve2") +elseif (XDP_CLIENT_BUILD_CMAKE STREQUAL "yes") + set(IMPL_DIR "${PROFILE_DIR}/plugin/aie_debug/client") +elseif (DEFINED XRT_AIE_BUILD AND ${XRT_NATIVE_BUILD} STREQUAL "no") + set(IMPL_DIR "${PROFILE_DIR}/plugin/aie_debug/edge") +endif() + file(GLOB AIE_DEBUG_PLUGIN_FILES "${PROFILE_DIR}/plugin/aie_debug/*.h" "${PROFILE_DIR}/plugin/aie_debug/*.cpp" + "${PROFILE_DIR}/plugin/aie_debug/generations/*.h" + "${PROFILE_DIR}/writer/aie_debug/*.h" + "${PROFILE_DIR}/writer/aie_debug/*.cpp" + "${IMPL_DIR}/*.h" + "${IMPL_DIR}/*.cpp" ) file(GLOB AIE_DRIVER_COMMON_UTIL_FILES @@ -17,7 +31,17 @@ file(GLOB AIE_DRIVER_COMMON_UTIL_FILES "${PROFILE_DIR}/device/common/*.cpp" ) -if (XDP_CLIENT_BUILD_CMAKE STREQUAL "yes") +if (XDP_VE2_BUILD_CMAKE STREQUAL "yes") + add_library(xdp_aie_debug_plugin MODULE ${AIE_DEBUG_PLUGIN_FILES}) + add_dependencies(xdp_aie_debug_plugin xdp_core xrt_coreutil) + target_link_libraries(xdp_aie_debug_plugin PRIVATE xdp_core xrt_coreutil xaiengine) + target_compile_definitions(xdp_aie_debug_plugin PRIVATE FAL_LINUX="on" XDP_VE2_BUILD=1) + + install (TARGETS xdp_aie_debug_plugin + LIBRARY DESTINATION ${XDP_PLUGIN_INSTALL_DIR} + ) + +elseif (XDP_CLIENT_BUILD_CMAKE STREQUAL "yes") add_library(xdp_aie_debug_plugin MODULE ${AIE_DEBUG_PLUGIN_FILES} ${AIE_DRIVER_COMMON_UTIL_FILES}) add_dependencies(xdp_aie_debug_plugin xdp_core xrt_coreutil) target_link_libraries(xdp_aie_debug_plugin PRIVATE xdp_core xrt_coreutil xaiengine) @@ -29,7 +53,17 @@ if (XDP_CLIENT_BUILD_CMAKE STREQUAL "yes") LIBRARY DESTINATION ${XDP_PLUGIN_INSTALL_DIR} COMPONENT ${XRT_COMPONENT} ) +elseif (DEFINED XRT_AIE_BUILD AND ${XRT_NATIVE_BUILD} STREQUAL "no") + add_library(xdp_aie_debug_plugin MODULE ${AIE_DEBUG_PLUGIN_FILES}) + add_dependencies(xdp_aie_debug_plugin xdp_core xrt_coreutil) + target_link_libraries(xdp_aie_debug_plugin PRIVATE xdp_core xrt_coreutil xaiengine) + target_compile_definitions(xdp_aie_debug_plugin PRIVATE FAL_LINUX="on") + set_target_properties(xdp_aie_debug_plugin PROPERTIES VERSION ${XRT_VERSION_STRING} SOVERSION ${XRT_SOVERSION}) + + install (TARGETS xdp_aie_debug_plugin + LIBRARY DESTINATION ${XDP_PLUGIN_INSTALL_DIR} + ) # Else, on edge-aarch64 don't build at all -endif() +endif() \ No newline at end of file diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.cpp index 0862926f57b..4763487bcfc 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.cpp +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.cpp @@ -1,5 +1,18 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ #define XDP_PLUGIN_SOURCE diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.h b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.h index 78859e10d30..a1a38aecda6 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.h +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_cb.h @@ -1,5 +1,18 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ #ifndef XDP_PLUGIN_AIE_DEBUG_CB_H #define XDP_PLUGIN_AIE_DEBUG_CB_H diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_impl.h b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_impl.h new file mode 100644 index 00000000000..32359cd9885 --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_impl.h @@ -0,0 +1,54 @@ +/** + * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_IMPL_H +#define AIE_DEBUG_IMPL_H + +#include "aie_debug_metadata.h" +#include "xdp/profile/plugin/vp_base/vp_base_plugin.h" + +namespace xdp { + + // AIE debugging can be done in different ways depending on the platform. + class AieDebugImpl + { + + protected: + VPDatabase* db = nullptr; + std::shared_ptr metadata; + + public: + AieDebugImpl(VPDatabase* database, std::shared_ptr metadata) + : db(database), metadata(metadata) {} + + AieDebugImpl() = delete; + virtual ~AieDebugImpl() {}; + + virtual void updateDevice() = 0; + virtual void updateAIEDevice(void* handle)=0; + virtual void poll(const uint64_t index, void* handle) = 0; + + const std::map moduleTypes = { + {module_type::core, "AIE"}, + {module_type::dma, "DMA"}, + {module_type::shim, "Interface"}, + {module_type::mem_tile, "Memory Tile"} + }; + }; + +} // namespace xdp + +#endif \ No newline at end of file diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.cpp new file mode 100644 index 00000000000..001065a3d2f --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.cpp @@ -0,0 +1,212 @@ +/** + * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#define XDP_PLUGIN_SOURCE + +#include "aie_debug_metadata.h" + +#include +#include +#include + +#include "core/common/config_reader.h" +#include "core/common/device.h" +#include "core/common/message.h" +#include "xdp/profile/database/database.h" +#include "xdp/profile/plugin/vp_base/vp_base_plugin.h" + +namespace xdp { + using severity_level = xrt_core::message::severity_level; + namespace pt = boost::property_tree; + + /**************************************************************************** + * Constructor + ***************************************************************************/ + AieDebugMetadata::AieDebugMetadata(uint64_t deviceID, void* handle) : + deviceID(deviceID), handle(handle) + { + VPDatabase* db = VPDatabase::Instance(); + + metadataReader = (db->getStaticInfo()).getAIEmetadataReader(); + if (!metadataReader) + return; + + // Record all tiles for debugging + for (int module = 0; module < NUM_MODULES; ++module) { + auto type = moduleTypes[module]; + + std::vector tiles = (type == module_type::shim) + ? metadataReader->getInterfaceTiles("all", "all", "input_output") + : metadataReader->getTiles("all", type, "all"); + + std::map moduleMap; + for (auto& t : tiles) + moduleMap[t] = "aie_debug"; + configMetrics.push_back(std::move(moduleMap)); + } + + // Get generation-specific register locations + auto hwGen = getHardwareGen(); + if (hwGen == 1) { + usedRegisters = std::make_unique(); + } + else if (hwGen == 5) { + usedRegisters = std::make_unique(); + } + else if ((hwGen > 1) && (hwGen < 10)) { + usedRegisters = std::make_unique(); + } + } + + /**************************************************************************** + * Lookup register names and values given current AIE HW generation + ***************************************************************************/ + std::string AieDebugMetadata::lookupRegisterName(uint64_t regVal) + { + return usedRegisters->getRegisterName(regVal); + } + + uint64_t AieDebugMetadata::lookupRegisterAddr(std::string regName) + { + return usedRegisters->getRegisterAddr(regName); + } + + /**************************************************************************** + * Convert xrt.ini setting to vector + ***************************************************************************/ + std::vector + AieDebugMetadata::getSettingsVector(std::string settingsString) + { + if (settingsString.empty()) + return {}; + + // Each of the metrics can have ; separated multiple values. Process and save all + std::vector settingsVector; + boost::replace_all(settingsString, " ", ""); + boost::split(settingsVector, settingsString, boost::is_any_of(",")); + return settingsVector; + } + + /**************************************************************************** + * Convert each xrt.ini entry to actual list of registers + ***************************************************************************/ + std::vector + AieDebugMetadata::stringToRegList(std::string stringEntry, module_type mod) + { + std::vector listofRegisters; + + /**************************************************************************** + AIE debug settings metrics can be entered in the following 3 ways: + [AIE_debug_settings] + # Very flexible but need to know specific reg values + core_registers = 0x12345, 0x34567 + # Simplified but not flexible + core_registers = trace_config, profile_config, all + # Specific registers but hides gen-specific values + core_registers = cm_core_status, mm_trace_status + /************************************************************************* */ + if (stringEntry.rfind("0x", 0) == 0) { + // Specific register addresses start with "0x" + uint64_t val = stoul(stringEntry, nullptr, 16); + listofRegisters.push_back(val); + return listofRegisters; + } + else if (stringEntry == "trace_config") { + usedRegisters->populateTraceRegisters(); + } + else if (stringEntry == "profile_config") { + usedRegisters->populateProfileRegisters(); + } + else if (stringEntry == "all") { + usedRegisters->populateAllRegisters(); + } + else { + // Find specific register names + uint64_t tmpRedAddr = lookupRegisterAddr(stringEntry); + if (tmpRedAddr != -1) { + listofRegisters.push_back(tmpRedAddr); + } + else { + xrt_core::message::send(severity_level::warning, "XRT", "Unable to parse AIE debug metric settings. " + "Please enter register addresses, names, or trace_config|profile_config|all."); + } + return listofRegisters; + } + + if (mod == module_type::core) { + auto coreAddressList = usedRegisters->getCoreAddresses(); + listofRegisters.insert(listofRegisters.end(), coreAddressList.begin(), + coreAddressList.end() ); + } + else if (mod == module_type::dma) { + auto memoryAddressList = usedRegisters->getMemoryAddresses(); + listofRegisters.insert(listofRegisters.end(), memoryAddressList.begin(), + memoryAddressList.end() ); + } + else if (mod == module_type::shim) { + auto interfaceAddressList = usedRegisters->getInterfaceAddresses(); + listofRegisters.insert(listofRegisters.end(), interfaceAddressList.begin(), + interfaceAddressList.end() ); + } + else if (mod == module_type::mem_tile) { + auto memoryTileAddressList = usedRegisters->getMemoryTileAddresses(); + listofRegisters.insert(listofRegisters.end(), memoryTileAddressList.begin(), + memoryTileAddressList.end() ); + } + else if (mod == module_type::uc) { + xrt_core::message::send(severity_level::debug, "XRT", "Debugging microcontroller registers not supported yet"); + } + + return listofRegisters; + } + + /**************************************************************************** + * Parse AIE metrics + ***************************************************************************/ + void AieDebugMetadata::parseMetrics() + { + parsedRegValues = { + {module_type::core, {}}, + {module_type::dma, {}}, + {module_type::shim, {}}, + {module_type::mem_tile, {}} + }; + + unsigned int module = 0; + std::vector metricsConfig; + metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_core_registers()); + metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_memory_registers()); + metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_interface_registers()); + metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_memory_tile_registers()); + + // Parse metric settings from xrt.ini file + for (auto const type : moduleTypes) { + std::vector metricsSettings = getSettingsVector(metricsConfig[module++]); + + for (auto& setting : metricsSettings) { + try { + std::vector regValList = stringToRegList(setting, type); + for (auto val : regValList) + parsedRegValues[type].push_back(val); + } catch (...) { + xrt_core::message::send(severity_level::warning, "XRT", "Unable to parse: " + + setting + ". Debug setting will be ignored."); + } + } + } + } + +} // namespace xdp diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.h b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.h new file mode 100644 index 00000000000..aebf946e89f --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_metadata.h @@ -0,0 +1,8322 @@ +/** + * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_METADATA_H +#define AIE_DEBUG_METADATA_H + +#include +#include +#include +#include + +#include "core/common/device.h" +#include "core/common/message.h" +#include "core/include/xrt/xrt_hw_context.h" +#include "xdp/config.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/database/static_info/aie_util.h" +#include "xdp/profile/database/static_info/filetypes/base_filetype_impl.h" +#include "xdp/profile/plugin/aie_profile/aie_profile_defs.h" +#include "xdp/profile/plugin/aie_debug/generations/aie1_registers.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2_registers.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h" +#include "xdp/profile/plugin/vp_base/vp_base_plugin.h" + +extern "C" { +#include +#include +} + +namespace xdp { + +// Forward declarations +class BaseReadableTile; +class UsedRegisters; + +class AieDebugMetadata { + public: + AieDebugMetadata(uint64_t deviceID, void* handle); + + void parseMetrics(); + + module_type getModuleType(int mod) {return moduleTypes[mod];} + uint64_t getDeviceID() {return deviceID;} + void* getHandle() {return handle;} + + std::map getConfigMetrics(const int module) { + return configMetrics[module]; + } + std::vector> getConfigMetricsVec(const int module) { + return {configMetrics[module].begin(), configMetrics[module].end()}; + } + + std::map>& getRegisterValues() { + return parsedRegValues; + } + + bool aieMetadataEmpty() const {return (metadataReader == nullptr);} + xdp::aie::driver_config getAIEConfigMetadata() {return metadataReader->getDriverConfig();} + + uint8_t getAIETileRowOffset() const { + return (metadataReader == nullptr) ? 0 : metadataReader->getAIETileRowOffset(); + } + int getHardwareGen() const { + return (metadataReader == nullptr) ? 0 : metadataReader->getHardwareGeneration(); + } + + int getNumModules() {return NUM_MODULES;} + xrt::hw_context getHwContext() {return hwContext;} + void setHwContext(xrt::hw_context c) { + hwContext = std::move(c); + } + + std::string lookupRegisterName(uint64_t regVal); + uint64_t lookupRegisterAddr(std::string regName); + + private: + std::vector stringToRegList(std::string stringEntry, module_type t); + std::vector getSettingsVector(std::string settingsString); + + private: + // Currently supporting Core, Memory, Interface Tiles, and Memory Tiles + static constexpr int NUM_MODULES = 4; + const std::vector moduleNames = + {"aie", "aie_memory", "interface_tile", "memory_tile"}; + const module_type moduleTypes[NUM_MODULES] = + {module_type::core, module_type::dma, module_type::shim, module_type::mem_tile}; + + void* handle; + uint64_t deviceID; + xrt::hw_context hwContext; + std::vector> configMetrics; + std::map> parsedRegValues; + const aie::BaseFiletypeImpl* metadataReader = nullptr; + + // List of AIE HW generation-specific registers + std::unique_ptr usedRegisters; +}; + +/***************************************************************** +The BaseReadableTile is created to simplify the retrieving of value at +each tile. This class encapsulates all the data (row, col, list of registers +to read) pertaining to a particuar tile, for easy extraction of tile by tile data. +****************************************************************** */ +class BaseReadableTile { + public: + virtual void readValues(XAie_DevInst* aieDevInst)=0; + + void setTileOffset(uint64_t offset) {tileOffset = offset;} + void addOffsetName(uint64_t rel, std::string name) { + relativeOffsets.push_back(rel); + registerNames.push_back(name); + } + + void printValues(uint32_t deviceID, VPDatabase* db) { + int i = 0; + for (auto& offset : relativeOffsets) { + db->getDynamicInfo().addAIEDebugSample(deviceID, col, row, values[i], + offset, registerNames[i]); + i++; + } + } + + public: + uint8_t col; + uint8_t row; + uint64_t tileOffset; + std::vector values; + std::vector relativeOffsets; + std::vector registerNames; +}; + +/************************************************************************************* +The class UsedRegisters is what gives us AIE hw generation specific data. The base class +has virtual functions which populate the correct registers and their addresses according +to the AIE hw generation in the derived classes. Thus we can dynamically populate the +correct registers and their addresses at runtime. +**************************************************************************************/ +class UsedRegisters { + public: + UsedRegisters() { + populateRegNameToValueMap(); + populateRegValueToNameMap(); + } + virtual ~UsedRegisters() { + core_addresses.clear(); + memory_addresses.clear(); + interface_addresses.clear(); + memory_tile_addresses.clear(); + regNameToValues.clear(); + regValueToName.clear(); + } + + std::set getCoreAddresses() { + return core_addresses; + } + std::set getMemoryAddresses() { + return memory_addresses; + } + std::set getInterfaceAddresses() { + return interface_addresses; + } + std::set getMemoryTileAddresses() { + return memory_tile_addresses; + } + + std::string getRegisterName(uint64_t regVal) { + auto itr = regValueToName.find(regVal); + return (itr != regValueToName.end()) ? itr->second : ""; + } + uint64_t getRegisterAddr(std::string regName) { + auto itr = regNameToValues.find(regName); + return (itr != regNameToValues.end()) ? itr->second : 0; + } + + virtual void populateProfileRegisters() {}; + virtual void populateTraceRegisters() {}; + virtual void populateRegNameToValueMap() {}; + virtual void populateRegValueToNameMap() {}; + + void populateAllRegisters() { + populateProfileRegisters(); + populateTraceRegisters(); + } + + protected: + std::set core_addresses; + std::set memory_addresses; + std::set interface_addresses; + std::set memory_tile_addresses; + std::map regNameToValues; + std::map regValueToName; +}; + +/************************************************************************************* + AIE1 Registers + *************************************************************************************/ +class AIE1UsedRegisters : public UsedRegisters { +public: + AIE1UsedRegisters() { + populateRegNameToValueMap(); + populateRegValueToNameMap(); + } + ~AIE1UsedRegisters() = default; + + void populateProfileRegisters() { + // Core modules + core_addresses.emplace(aie1::cm_performance_control0); + core_addresses.emplace(aie1::cm_performance_control1); + core_addresses.emplace(aie1::cm_performance_control2); + core_addresses.emplace(aie1::cm_performance_counter0); + core_addresses.emplace(aie1::cm_performance_counter1); + core_addresses.emplace(aie1::cm_performance_counter2); + core_addresses.emplace(aie1::cm_performance_counter3); + core_addresses.emplace(aie1::cm_performance_counter0_event_value); + core_addresses.emplace(aie1::cm_performance_counter1_event_value); + core_addresses.emplace(aie1::cm_performance_counter2_event_value); + core_addresses.emplace(aie1::cm_performance_counter3_event_value); + + // Memory modules + memory_addresses.emplace(aie1::mm_performance_control0); + memory_addresses.emplace(aie1::mm_performance_control1); + memory_addresses.emplace(aie1::mm_performance_counter0); + memory_addresses.emplace(aie1::mm_performance_counter1); + memory_addresses.emplace(aie1::mm_performance_counter0_event_value); + memory_addresses.emplace(aie1::mm_performance_counter1_event_value); + + // Interface tiles + interface_addresses.emplace(aie1::shim_performance_control0); + interface_addresses.emplace(aie1::shim_performance_control1); + interface_addresses.emplace(aie1::shim_performance_counter0); + interface_addresses.emplace(aie1::shim_performance_counter1); + interface_addresses.emplace(aie1::shim_performance_counter0_event_value); + interface_addresses.emplace(aie1::shim_performance_counter1_event_value); + + // Memory tiles + // NOTE, not available on AIE1 + } + + void populateTraceRegisters() { + // Core modules + core_addresses.emplace(aie1::cm_core_status); + core_addresses.emplace(aie1::cm_trace_control0); + core_addresses.emplace(aie1::cm_trace_control1); + core_addresses.emplace(aie1::cm_trace_status); + core_addresses.emplace(aie1::cm_trace_event0); + core_addresses.emplace(aie1::cm_trace_event1); + core_addresses.emplace(aie1::cm_event_status0); + core_addresses.emplace(aie1::cm_event_status1); + core_addresses.emplace(aie1::cm_event_status2); + core_addresses.emplace(aie1::cm_event_status3); + core_addresses.emplace(aie1::cm_event_broadcast0); + core_addresses.emplace(aie1::cm_event_broadcast1); + core_addresses.emplace(aie1::cm_event_broadcast2); + core_addresses.emplace(aie1::cm_event_broadcast3); + core_addresses.emplace(aie1::cm_event_broadcast4); + core_addresses.emplace(aie1::cm_event_broadcast5); + core_addresses.emplace(aie1::cm_event_broadcast6); + core_addresses.emplace(aie1::cm_event_broadcast7); + core_addresses.emplace(aie1::cm_event_broadcast8); + core_addresses.emplace(aie1::cm_event_broadcast9); + core_addresses.emplace(aie1::cm_event_broadcast10); + core_addresses.emplace(aie1::cm_event_broadcast11); + core_addresses.emplace(aie1::cm_event_broadcast12); + core_addresses.emplace(aie1::cm_event_broadcast13); + core_addresses.emplace(aie1::cm_event_broadcast14); + core_addresses.emplace(aie1::cm_event_broadcast15); + core_addresses.emplace(aie1::cm_timer_trig_event_low_value); + core_addresses.emplace(aie1::cm_timer_trig_event_high_value); + core_addresses.emplace(aie1::cm_timer_low); + core_addresses.emplace(aie1::cm_timer_high); + core_addresses.emplace(aie1::cm_stream_switch_event_port_selection_0); + core_addresses.emplace(aie1::cm_stream_switch_event_port_selection_1); + + // Memory modules + memory_addresses.emplace(aie1::mm_trace_control0); + memory_addresses.emplace(aie1::mm_trace_control1); + memory_addresses.emplace(aie1::mm_trace_status); + memory_addresses.emplace(aie1::mm_trace_event0); + memory_addresses.emplace(aie1::mm_trace_event1); + memory_addresses.emplace(aie1::mm_event_status0); + memory_addresses.emplace(aie1::mm_event_status1); + memory_addresses.emplace(aie1::mm_event_status2); + memory_addresses.emplace(aie1::mm_event_status3); + memory_addresses.emplace(aie1::mm_event_broadcast0); + memory_addresses.emplace(aie1::mm_event_broadcast1); + memory_addresses.emplace(aie1::mm_event_broadcast2); + memory_addresses.emplace(aie1::mm_event_broadcast3); + memory_addresses.emplace(aie1::mm_event_broadcast4); + memory_addresses.emplace(aie1::mm_event_broadcast5); + memory_addresses.emplace(aie1::mm_event_broadcast6); + memory_addresses.emplace(aie1::mm_event_broadcast7); + memory_addresses.emplace(aie1::mm_event_broadcast8); + memory_addresses.emplace(aie1::mm_event_broadcast9); + memory_addresses.emplace(aie1::mm_event_broadcast10); + memory_addresses.emplace(aie1::mm_event_broadcast11); + memory_addresses.emplace(aie1::mm_event_broadcast12); + memory_addresses.emplace(aie1::mm_event_broadcast13); + memory_addresses.emplace(aie1::mm_event_broadcast14); + memory_addresses.emplace(aie1::mm_event_broadcast15); + + // Interface tiles + interface_addresses.emplace(aie1::shim_trace_control0); + interface_addresses.emplace(aie1::shim_trace_control1); + interface_addresses.emplace(aie1::shim_trace_status); + interface_addresses.emplace(aie1::shim_trace_event0); + interface_addresses.emplace(aie1::shim_trace_event1); + interface_addresses.emplace(aie1::shim_event_broadcast_a_0); + interface_addresses.emplace(aie1::shim_event_broadcast_a_1); + interface_addresses.emplace(aie1::shim_event_broadcast_a_2); + interface_addresses.emplace(aie1::shim_event_broadcast_a_3); + interface_addresses.emplace(aie1::shim_event_broadcast_a_4); + interface_addresses.emplace(aie1::shim_event_broadcast_a_5); + interface_addresses.emplace(aie1::shim_event_broadcast_a_6); + interface_addresses.emplace(aie1::shim_event_broadcast_a_7); + interface_addresses.emplace(aie1::shim_event_broadcast_a_8); + interface_addresses.emplace(aie1::shim_event_broadcast_a_9); + interface_addresses.emplace(aie1::shim_event_broadcast_a_10); + interface_addresses.emplace(aie1::shim_event_broadcast_a_11); + interface_addresses.emplace(aie1::shim_event_broadcast_a_12); + interface_addresses.emplace(aie1::shim_event_broadcast_a_13); + interface_addresses.emplace(aie1::shim_event_broadcast_a_14); + interface_addresses.emplace(aie1::shim_event_broadcast_a_15); + interface_addresses.emplace(aie1::shim_event_status0); + interface_addresses.emplace(aie1::shim_event_status1); + interface_addresses.emplace(aie1::shim_event_status2); + interface_addresses.emplace(aie1::shim_event_status3); + interface_addresses.emplace(aie1::shim_stream_switch_event_port_selection_0); + interface_addresses.emplace(aie1::shim_stream_switch_event_port_selection_1); + + // Memory tiles + // NOTE, not available on AIE1 + } + + void populateRegNameToValueMap() { + regNameToValues = { + {"cm_program_counter", aie1::cm_program_counter}, + {"cm_md0", aie1::cm_md0}, + {"cm_md1", aie1::cm_md1}, + {"cm_mc0", aie1::cm_mc0}, + {"cm_mc1", aie1::cm_mc1}, + {"cm_performance_control0", aie1::cm_performance_control0}, + {"cm_performance_control1", aie1::cm_performance_control1}, + {"cm_performance_control2", aie1::cm_performance_control2}, + {"cm_performance_counter0", aie1::cm_performance_counter0}, + {"cm_performance_counter1", aie1::cm_performance_counter1}, + {"cm_performance_counter2", aie1::cm_performance_counter2}, + {"cm_performance_counter3", aie1::cm_performance_counter3}, + {"cm_performance_counter0_event_value", aie1::cm_performance_counter0_event_value}, + {"cm_performance_counter1_event_value", aie1::cm_performance_counter1_event_value}, + {"cm_performance_counter2_event_value", aie1::cm_performance_counter2_event_value}, + {"cm_performance_counter3_event_value", aie1::cm_performance_counter3_event_value}, + {"cm_core_control", aie1::cm_core_control}, + {"cm_core_status", aie1::cm_core_status}, + {"cm_enable_events", aie1::cm_enable_events}, + {"cm_reset_event", aie1::cm_reset_event}, + {"cm_debug_control0", aie1::cm_debug_control0}, + {"cm_debug_control1", aie1::cm_debug_control1}, + {"cm_debug_control2", aie1::cm_debug_control2}, + {"cm_debug_status", aie1::cm_debug_status}, + {"cm_pc_event0", aie1::cm_pc_event0}, + {"cm_pc_event1", aie1::cm_pc_event1}, + {"cm_pc_event2", aie1::cm_pc_event2}, + {"cm_pc_event3", aie1::cm_pc_event3}, + {"cm_error_halt_control", aie1::cm_error_halt_control}, + {"cm_error_halt_event", aie1::cm_error_halt_event}, + {"cm_ecc_scrubbing_event", aie1::cm_ecc_scrubbing_event}, + {"cm_timer_control", aie1::cm_timer_control}, + {"cm_event_generate", aie1::cm_event_generate}, + {"cm_event_broadcast0", aie1::cm_event_broadcast0}, + {"cm_event_broadcast1", aie1::cm_event_broadcast1}, + {"cm_event_broadcast2", aie1::cm_event_broadcast2}, + {"cm_event_broadcast3", aie1::cm_event_broadcast3}, + {"cm_event_broadcast4", aie1::cm_event_broadcast4}, + {"cm_event_broadcast5", aie1::cm_event_broadcast5}, + {"cm_event_broadcast6", aie1::cm_event_broadcast6}, + {"cm_event_broadcast7", aie1::cm_event_broadcast7}, + {"cm_event_broadcast8", aie1::cm_event_broadcast8}, + {"cm_event_broadcast9", aie1::cm_event_broadcast9}, + {"cm_event_broadcast10", aie1::cm_event_broadcast10}, + {"cm_event_broadcast11", aie1::cm_event_broadcast11}, + {"cm_event_broadcast12", aie1::cm_event_broadcast12}, + {"cm_event_broadcast13", aie1::cm_event_broadcast13}, + {"cm_event_broadcast14", aie1::cm_event_broadcast14}, + {"cm_event_broadcast15", aie1::cm_event_broadcast15}, + {"cm_event_broadcast_block_south_set", aie1::cm_event_broadcast_block_south_set}, + {"cm_event_broadcast_block_south_clr", aie1::cm_event_broadcast_block_south_clr}, + {"cm_event_broadcast_block_south_value", aie1::cm_event_broadcast_block_south_value}, + {"cm_event_broadcast_block_west_set", aie1::cm_event_broadcast_block_west_set}, + {"cm_event_broadcast_block_west_clr", aie1::cm_event_broadcast_block_west_clr}, + {"cm_event_broadcast_block_west_value", aie1::cm_event_broadcast_block_west_value}, + {"cm_event_broadcast_block_north_set", aie1::cm_event_broadcast_block_north_set}, + {"cm_event_broadcast_block_north_clr", aie1::cm_event_broadcast_block_north_clr}, + {"cm_event_broadcast_block_north_value", aie1::cm_event_broadcast_block_north_value}, + {"cm_event_broadcast_block_east_set", aie1::cm_event_broadcast_block_east_set}, + {"cm_event_broadcast_block_east_clr", aie1::cm_event_broadcast_block_east_clr}, + {"cm_event_broadcast_block_east_value", aie1::cm_event_broadcast_block_east_value}, + {"cm_trace_control0", aie1::cm_trace_control0}, + {"cm_trace_control1", aie1::cm_trace_control1}, + {"cm_trace_status", aie1::cm_trace_status}, + {"cm_trace_event0", aie1::cm_trace_event0}, + {"cm_trace_event1", aie1::cm_trace_event1}, + {"cm_timer_trig_event_low_value", aie1::cm_timer_trig_event_low_value}, + {"cm_timer_trig_event_high_value", aie1::cm_timer_trig_event_high_value}, + {"cm_timer_low", aie1::cm_timer_low}, + {"cm_timer_high", aie1::cm_timer_high}, + {"cm_event_status0", aie1::cm_event_status0}, + {"cm_event_status1", aie1::cm_event_status1}, + {"cm_event_status2", aie1::cm_event_status2}, + {"cm_event_status3", aie1::cm_event_status3}, + {"cm_combo_event_inputs", aie1::cm_combo_event_inputs}, + {"cm_combo_event_control", aie1::cm_combo_event_control}, + {"cm_event_group_0_enable", aie1::cm_event_group_0_enable}, + {"cm_event_group_pc_enable", aie1::cm_event_group_pc_enable}, + {"cm_event_group_core_stall_enable", aie1::cm_event_group_core_stall_enable}, + {"cm_event_group_core_program_flow_enable", aie1::cm_event_group_core_program_flow_enable}, + {"cm_event_group_errors0_enable", aie1::cm_event_group_errors0_enable}, + {"cm_event_group_errors1_enable", aie1::cm_event_group_errors1_enable}, + {"cm_event_group_stream_switch_enable", aie1::cm_event_group_stream_switch_enable}, + {"cm_event_group_broadcast_enable", aie1::cm_event_group_broadcast_enable}, + {"cm_event_group_user_event_enable", aie1::cm_event_group_user_event_enable}, + {"cm_tile_control", aie1::cm_tile_control}, + {"cm_tile_control_packet_handler_status", aie1::cm_tile_control_packet_handler_status}, + {"cm_tile_clock_control", aie1::cm_tile_clock_control}, + {"cm_stream_switch_master_config_aie_core0", aie1::cm_stream_switch_master_config_aie_core0}, + {"cm_stream_switch_master_config_aie_core1", aie1::cm_stream_switch_master_config_aie_core1}, + {"cm_stream_switch_master_config_dma0", aie1::cm_stream_switch_master_config_dma0}, + {"cm_stream_switch_master_config_dma1", aie1::cm_stream_switch_master_config_dma1}, + {"cm_stream_switch_master_config_tile_ctrl", aie1::cm_stream_switch_master_config_tile_ctrl}, + {"cm_stream_switch_master_config_fifo0", aie1::cm_stream_switch_master_config_fifo0}, + {"cm_stream_switch_master_config_fifo1", aie1::cm_stream_switch_master_config_fifo1}, + {"cm_stream_switch_master_config_south0", aie1::cm_stream_switch_master_config_south0}, + {"cm_stream_switch_master_config_south1", aie1::cm_stream_switch_master_config_south1}, + {"cm_stream_switch_master_config_south2", aie1::cm_stream_switch_master_config_south2}, + {"cm_stream_switch_master_config_south3", aie1::cm_stream_switch_master_config_south3}, + {"cm_stream_switch_master_config_west0", aie1::cm_stream_switch_master_config_west0}, + {"cm_stream_switch_master_config_west1", aie1::cm_stream_switch_master_config_west1}, + {"cm_stream_switch_master_config_west2", aie1::cm_stream_switch_master_config_west2}, + {"cm_stream_switch_master_config_west3", aie1::cm_stream_switch_master_config_west3}, + {"cm_stream_switch_master_config_north0", aie1::cm_stream_switch_master_config_north0}, + {"cm_stream_switch_master_config_north1", aie1::cm_stream_switch_master_config_north1}, + {"cm_stream_switch_master_config_north2", aie1::cm_stream_switch_master_config_north2}, + {"cm_stream_switch_master_config_north3", aie1::cm_stream_switch_master_config_north3}, + {"cm_stream_switch_master_config_north4", aie1::cm_stream_switch_master_config_north4}, + {"cm_stream_switch_master_config_north5", aie1::cm_stream_switch_master_config_north5}, + {"cm_stream_switch_master_config_east0", aie1::cm_stream_switch_master_config_east0}, + {"cm_stream_switch_master_config_east1", aie1::cm_stream_switch_master_config_east1}, + {"cm_stream_switch_master_config_east2", aie1::cm_stream_switch_master_config_east2}, + {"cm_stream_switch_master_config_east3", aie1::cm_stream_switch_master_config_east3}, + {"cm_stream_switch_slave_config_aie_core0", aie1::cm_stream_switch_slave_config_aie_core0}, + {"cm_stream_switch_slave_config_aie_core1", aie1::cm_stream_switch_slave_config_aie_core1}, + {"cm_stream_switch_slave_config_dma_0", aie1::cm_stream_switch_slave_config_dma_0}, + {"cm_stream_switch_slave_config_dma_1", aie1::cm_stream_switch_slave_config_dma_1}, + {"cm_stream_switch_slave_config_tile_ctrl", aie1::cm_stream_switch_slave_config_tile_ctrl}, + {"cm_stream_switch_slave_config_fifo_0", aie1::cm_stream_switch_slave_config_fifo_0}, + {"cm_stream_switch_slave_config_fifo_1", aie1::cm_stream_switch_slave_config_fifo_1}, + {"cm_stream_switch_slave_config_south_0", aie1::cm_stream_switch_slave_config_south_0}, + {"cm_stream_switch_slave_config_south_1", aie1::cm_stream_switch_slave_config_south_1}, + {"cm_stream_switch_slave_config_south_2", aie1::cm_stream_switch_slave_config_south_2}, + {"cm_stream_switch_slave_config_south_3", aie1::cm_stream_switch_slave_config_south_3}, + {"cm_stream_switch_slave_config_south_4", aie1::cm_stream_switch_slave_config_south_4}, + {"cm_stream_switch_slave_config_south_5", aie1::cm_stream_switch_slave_config_south_5}, + {"cm_stream_switch_slave_config_west_0", aie1::cm_stream_switch_slave_config_west_0}, + {"cm_stream_switch_slave_config_west_1", aie1::cm_stream_switch_slave_config_west_1}, + {"cm_stream_switch_slave_config_west_2", aie1::cm_stream_switch_slave_config_west_2}, + {"cm_stream_switch_slave_config_west_3", aie1::cm_stream_switch_slave_config_west_3}, + {"cm_stream_switch_slave_config_north_0", aie1::cm_stream_switch_slave_config_north_0}, + {"cm_stream_switch_slave_config_north_1", aie1::cm_stream_switch_slave_config_north_1}, + {"cm_stream_switch_slave_config_north_2", aie1::cm_stream_switch_slave_config_north_2}, + {"cm_stream_switch_slave_config_north_3", aie1::cm_stream_switch_slave_config_north_3}, + {"cm_stream_switch_slave_config_east_0", aie1::cm_stream_switch_slave_config_east_0}, + {"cm_stream_switch_slave_config_east_1", aie1::cm_stream_switch_slave_config_east_1}, + {"cm_stream_switch_slave_config_east_2", aie1::cm_stream_switch_slave_config_east_2}, + {"cm_stream_switch_slave_config_east_3", aie1::cm_stream_switch_slave_config_east_3}, + {"cm_stream_switch_slave_config_aie_trace", aie1::cm_stream_switch_slave_config_aie_trace}, + {"cm_stream_switch_slave_config_mem_trace", aie1::cm_stream_switch_slave_config_mem_trace}, + {"cm_stream_switch_slave_aie_core0_slot0", aie1::cm_stream_switch_slave_aie_core0_slot0}, + {"cm_stream_switch_slave_aie_core0_slot1", aie1::cm_stream_switch_slave_aie_core0_slot1}, + {"cm_stream_switch_slave_aie_core0_slot2", aie1::cm_stream_switch_slave_aie_core0_slot2}, + {"cm_stream_switch_slave_aie_core0_slot3", aie1::cm_stream_switch_slave_aie_core0_slot3}, + {"cm_stream_switch_slave_aie_core1_slot0", aie1::cm_stream_switch_slave_aie_core1_slot0}, + {"cm_stream_switch_slave_aie_core1_slot1", aie1::cm_stream_switch_slave_aie_core1_slot1}, + {"cm_stream_switch_slave_aie_core1_slot2", aie1::cm_stream_switch_slave_aie_core1_slot2}, + {"cm_stream_switch_slave_aie_core1_slot3", aie1::cm_stream_switch_slave_aie_core1_slot3}, + {"cm_stream_switch_slave_dma_0_slot0", aie1::cm_stream_switch_slave_dma_0_slot0}, + {"cm_stream_switch_slave_dma_0_slot1", aie1::cm_stream_switch_slave_dma_0_slot1}, + {"cm_stream_switch_slave_dma_0_slot2", aie1::cm_stream_switch_slave_dma_0_slot2}, + {"cm_stream_switch_slave_dma_0_slot3", aie1::cm_stream_switch_slave_dma_0_slot3}, + {"cm_stream_switch_slave_dma_1_slot0", aie1::cm_stream_switch_slave_dma_1_slot0}, + {"cm_stream_switch_slave_dma_1_slot1", aie1::cm_stream_switch_slave_dma_1_slot1}, + {"cm_stream_switch_slave_dma_1_slot2", aie1::cm_stream_switch_slave_dma_1_slot2}, + {"cm_stream_switch_slave_dma_1_slot3", aie1::cm_stream_switch_slave_dma_1_slot3}, + {"cm_stream_switch_slave_tile_ctrl_slot0", aie1::cm_stream_switch_slave_tile_ctrl_slot0}, + {"cm_stream_switch_slave_tile_ctrl_slot1", aie1::cm_stream_switch_slave_tile_ctrl_slot1}, + {"cm_stream_switch_slave_tile_ctrl_slot2", aie1::cm_stream_switch_slave_tile_ctrl_slot2}, + {"cm_stream_switch_slave_tile_ctrl_slot3", aie1::cm_stream_switch_slave_tile_ctrl_slot3}, + {"cm_stream_switch_slave_fifo_0_slot0", aie1::cm_stream_switch_slave_fifo_0_slot0}, + {"cm_stream_switch_slave_fifo_0_slot1", aie1::cm_stream_switch_slave_fifo_0_slot1}, + {"cm_stream_switch_slave_fifo_0_slot2", aie1::cm_stream_switch_slave_fifo_0_slot2}, + {"cm_stream_switch_slave_fifo_0_slot3", aie1::cm_stream_switch_slave_fifo_0_slot3}, + {"cm_stream_switch_slave_fifo_1_slot0", aie1::cm_stream_switch_slave_fifo_1_slot0}, + {"cm_stream_switch_slave_fifo_1_slot1", aie1::cm_stream_switch_slave_fifo_1_slot1}, + {"cm_stream_switch_slave_fifo_1_slot2", aie1::cm_stream_switch_slave_fifo_1_slot2}, + {"cm_stream_switch_slave_fifo_1_slot3", aie1::cm_stream_switch_slave_fifo_1_slot3}, + {"cm_stream_switch_slave_south_0_slot0", aie1::cm_stream_switch_slave_south_0_slot0}, + {"cm_stream_switch_slave_south_0_slot1", aie1::cm_stream_switch_slave_south_0_slot1}, + {"cm_stream_switch_slave_south_0_slot2", aie1::cm_stream_switch_slave_south_0_slot2}, + {"cm_stream_switch_slave_south_0_slot3", aie1::cm_stream_switch_slave_south_0_slot3}, + {"cm_stream_switch_slave_south_1_slot0", aie1::cm_stream_switch_slave_south_1_slot0}, + {"cm_stream_switch_slave_south_1_slot1", aie1::cm_stream_switch_slave_south_1_slot1}, + {"cm_stream_switch_slave_south_1_slot2", aie1::cm_stream_switch_slave_south_1_slot2}, + {"cm_stream_switch_slave_south_1_slot3", aie1::cm_stream_switch_slave_south_1_slot3}, + {"cm_stream_switch_slave_south_2_slot0", aie1::cm_stream_switch_slave_south_2_slot0}, + {"cm_stream_switch_slave_south_2_slot1", aie1::cm_stream_switch_slave_south_2_slot1}, + {"cm_stream_switch_slave_south_2_slot2", aie1::cm_stream_switch_slave_south_2_slot2}, + {"cm_stream_switch_slave_south_2_slot3", aie1::cm_stream_switch_slave_south_2_slot3}, + {"cm_stream_switch_slave_south_3_slot0", aie1::cm_stream_switch_slave_south_3_slot0}, + {"cm_stream_switch_slave_south_3_slot1", aie1::cm_stream_switch_slave_south_3_slot1}, + {"cm_stream_switch_slave_south_3_slot2", aie1::cm_stream_switch_slave_south_3_slot2}, + {"cm_stream_switch_slave_south_3_slot3", aie1::cm_stream_switch_slave_south_3_slot3}, + {"cm_stream_switch_slave_south_4_slot0", aie1::cm_stream_switch_slave_south_4_slot0}, + {"cm_stream_switch_slave_south_4_slot1", aie1::cm_stream_switch_slave_south_4_slot1}, + {"cm_stream_switch_slave_south_4_slot2", aie1::cm_stream_switch_slave_south_4_slot2}, + {"cm_stream_switch_slave_south_4_slot3", aie1::cm_stream_switch_slave_south_4_slot3}, + {"cm_stream_switch_slave_south_5_slot0", aie1::cm_stream_switch_slave_south_5_slot0}, + {"cm_stream_switch_slave_south_5_slot1", aie1::cm_stream_switch_slave_south_5_slot1}, + {"cm_stream_switch_slave_south_5_slot2", aie1::cm_stream_switch_slave_south_5_slot2}, + {"cm_stream_switch_slave_south_5_slot3", aie1::cm_stream_switch_slave_south_5_slot3}, + {"cm_stream_switch_slave_west_0_slot0", aie1::cm_stream_switch_slave_west_0_slot0}, + {"cm_stream_switch_slave_west_0_slot1", aie1::cm_stream_switch_slave_west_0_slot1}, + {"cm_stream_switch_slave_west_0_slot2", aie1::cm_stream_switch_slave_west_0_slot2}, + {"cm_stream_switch_slave_west_0_slot3", aie1::cm_stream_switch_slave_west_0_slot3}, + {"cm_stream_switch_slave_west_1_slot0", aie1::cm_stream_switch_slave_west_1_slot0}, + {"cm_stream_switch_slave_west_1_slot1", aie1::cm_stream_switch_slave_west_1_slot1}, + {"cm_stream_switch_slave_west_1_slot2", aie1::cm_stream_switch_slave_west_1_slot2}, + {"cm_stream_switch_slave_west_1_slot3", aie1::cm_stream_switch_slave_west_1_slot3}, + {"cm_stream_switch_slave_west_2_slot0", aie1::cm_stream_switch_slave_west_2_slot0}, + {"cm_stream_switch_slave_west_2_slot1", aie1::cm_stream_switch_slave_west_2_slot1}, + {"cm_stream_switch_slave_west_2_slot2", aie1::cm_stream_switch_slave_west_2_slot2}, + {"cm_stream_switch_slave_west_2_slot3", aie1::cm_stream_switch_slave_west_2_slot3}, + {"cm_stream_switch_slave_west_3_slot0", aie1::cm_stream_switch_slave_west_3_slot0}, + {"cm_stream_switch_slave_west_3_slot1", aie1::cm_stream_switch_slave_west_3_slot1}, + {"cm_stream_switch_slave_west_3_slot2", aie1::cm_stream_switch_slave_west_3_slot2}, + {"cm_stream_switch_slave_west_3_slot3", aie1::cm_stream_switch_slave_west_3_slot3}, + {"cm_stream_switch_slave_north_0_slot0", aie1::cm_stream_switch_slave_north_0_slot0}, + {"cm_stream_switch_slave_north_0_slot1", aie1::cm_stream_switch_slave_north_0_slot1}, + {"cm_stream_switch_slave_north_0_slot2", aie1::cm_stream_switch_slave_north_0_slot2}, + {"cm_stream_switch_slave_north_0_slot3", aie1::cm_stream_switch_slave_north_0_slot3}, + {"cm_stream_switch_slave_north_1_slot0", aie1::cm_stream_switch_slave_north_1_slot0}, + {"cm_stream_switch_slave_north_1_slot1", aie1::cm_stream_switch_slave_north_1_slot1}, + {"cm_stream_switch_slave_north_1_slot2", aie1::cm_stream_switch_slave_north_1_slot2}, + {"cm_stream_switch_slave_north_1_slot3", aie1::cm_stream_switch_slave_north_1_slot3}, + {"cm_stream_switch_slave_north_2_slot0", aie1::cm_stream_switch_slave_north_2_slot0}, + {"cm_stream_switch_slave_north_2_slot1", aie1::cm_stream_switch_slave_north_2_slot1}, + {"cm_stream_switch_slave_north_2_slot2", aie1::cm_stream_switch_slave_north_2_slot2}, + {"cm_stream_switch_slave_north_2_slot3", aie1::cm_stream_switch_slave_north_2_slot3}, + {"cm_stream_switch_slave_north_3_slot0", aie1::cm_stream_switch_slave_north_3_slot0}, + {"cm_stream_switch_slave_north_3_slot1", aie1::cm_stream_switch_slave_north_3_slot1}, + {"cm_stream_switch_slave_north_3_slot2", aie1::cm_stream_switch_slave_north_3_slot2}, + {"cm_stream_switch_slave_north_3_slot3", aie1::cm_stream_switch_slave_north_3_slot3}, + {"cm_stream_switch_slave_east_0_slot0", aie1::cm_stream_switch_slave_east_0_slot0}, + {"cm_stream_switch_slave_east_0_slot1", aie1::cm_stream_switch_slave_east_0_slot1}, + {"cm_stream_switch_slave_east_0_slot2", aie1::cm_stream_switch_slave_east_0_slot2}, + {"cm_stream_switch_slave_east_0_slot3", aie1::cm_stream_switch_slave_east_0_slot3}, + {"cm_stream_switch_slave_east_1_slot0", aie1::cm_stream_switch_slave_east_1_slot0}, + {"cm_stream_switch_slave_east_1_slot1", aie1::cm_stream_switch_slave_east_1_slot1}, + {"cm_stream_switch_slave_east_1_slot2", aie1::cm_stream_switch_slave_east_1_slot2}, + {"cm_stream_switch_slave_east_1_slot3", aie1::cm_stream_switch_slave_east_1_slot3}, + {"cm_stream_switch_slave_east_2_slot0", aie1::cm_stream_switch_slave_east_2_slot0}, + {"cm_stream_switch_slave_east_2_slot1", aie1::cm_stream_switch_slave_east_2_slot1}, + {"cm_stream_switch_slave_east_2_slot2", aie1::cm_stream_switch_slave_east_2_slot2}, + {"cm_stream_switch_slave_east_2_slot3", aie1::cm_stream_switch_slave_east_2_slot3}, + {"cm_stream_switch_slave_east_3_slot0", aie1::cm_stream_switch_slave_east_3_slot0}, + {"cm_stream_switch_slave_east_3_slot1", aie1::cm_stream_switch_slave_east_3_slot1}, + {"cm_stream_switch_slave_east_3_slot2", aie1::cm_stream_switch_slave_east_3_slot2}, + {"cm_stream_switch_slave_east_3_slot3", aie1::cm_stream_switch_slave_east_3_slot3}, + {"cm_stream_switch_slave_aie_trace_slot0", aie1::cm_stream_switch_slave_aie_trace_slot0}, + {"cm_stream_switch_slave_aie_trace_slot1", aie1::cm_stream_switch_slave_aie_trace_slot1}, + {"cm_stream_switch_slave_aie_trace_slot2", aie1::cm_stream_switch_slave_aie_trace_slot2}, + {"cm_stream_switch_slave_aie_trace_slot3", aie1::cm_stream_switch_slave_aie_trace_slot3}, + {"cm_stream_switch_slave_mem_trace_slot0", aie1::cm_stream_switch_slave_mem_trace_slot0}, + {"cm_stream_switch_slave_mem_trace_slot1", aie1::cm_stream_switch_slave_mem_trace_slot1}, + {"cm_stream_switch_slave_mem_trace_slot2", aie1::cm_stream_switch_slave_mem_trace_slot2}, + {"cm_stream_switch_slave_mem_trace_slot3", aie1::cm_stream_switch_slave_mem_trace_slot3}, + {"cm_stream_switch_event_port_selection_0", aie1::cm_stream_switch_event_port_selection_0}, + {"cm_stream_switch_event_port_selection_1", aie1::cm_stream_switch_event_port_selection_1}, + {"mm_performance_control0", aie1::mm_performance_control0}, + {"mm_performance_control1", aie1::mm_performance_control1}, + {"mm_performance_counter0", aie1::mm_performance_counter0}, + {"mm_performance_counter1", aie1::mm_performance_counter1}, + {"mm_performance_counter0_event_value", aie1::mm_performance_counter0_event_value}, + {"mm_performance_counter1_event_value", aie1::mm_performance_counter1_event_value}, + {"mm_checkbit_error_generation", aie1::mm_checkbit_error_generation}, + {"mm_ecc_scrubbing_event", aie1::mm_ecc_scrubbing_event}, + {"mm_ecc_failing_address", aie1::mm_ecc_failing_address}, + {"mm_parity_failing_address", aie1::mm_parity_failing_address}, + {"mm_reset_control", aie1::mm_reset_control}, + {"mm_timer_control", aie1::mm_timer_control}, + {"mm_event_generate", aie1::mm_event_generate}, + {"mm_event_broadcast0", aie1::mm_event_broadcast0}, + {"mm_event_broadcast1", aie1::mm_event_broadcast1}, + {"mm_event_broadcast2", aie1::mm_event_broadcast2}, + {"mm_event_broadcast3", aie1::mm_event_broadcast3}, + {"mm_event_broadcast4", aie1::mm_event_broadcast4}, + {"mm_event_broadcast5", aie1::mm_event_broadcast5}, + {"mm_event_broadcast6", aie1::mm_event_broadcast6}, + {"mm_event_broadcast7", aie1::mm_event_broadcast7}, + {"mm_event_broadcast8", aie1::mm_event_broadcast8}, + {"mm_event_broadcast9", aie1::mm_event_broadcast9}, + {"mm_event_broadcast10", aie1::mm_event_broadcast10}, + {"mm_event_broadcast11", aie1::mm_event_broadcast11}, + {"mm_event_broadcast12", aie1::mm_event_broadcast12}, + {"mm_event_broadcast13", aie1::mm_event_broadcast13}, + {"mm_event_broadcast14", aie1::mm_event_broadcast14}, + {"mm_event_broadcast15", aie1::mm_event_broadcast15}, + {"mm_event_broadcast_block_south_set", aie1::mm_event_broadcast_block_south_set}, + {"mm_event_broadcast_block_south_clr", aie1::mm_event_broadcast_block_south_clr}, + {"mm_event_broadcast_block_south_value", aie1::mm_event_broadcast_block_south_value}, + {"mm_event_broadcast_block_west_set", aie1::mm_event_broadcast_block_west_set}, + {"mm_event_broadcast_block_west_clr", aie1::mm_event_broadcast_block_west_clr}, + {"mm_event_broadcast_block_west_value", aie1::mm_event_broadcast_block_west_value}, + {"mm_event_broadcast_block_north_set", aie1::mm_event_broadcast_block_north_set}, + {"mm_event_broadcast_block_north_clr", aie1::mm_event_broadcast_block_north_clr}, + {"mm_event_broadcast_block_north_value", aie1::mm_event_broadcast_block_north_value}, + {"mm_event_broadcast_block_east_set", aie1::mm_event_broadcast_block_east_set}, + {"mm_event_broadcast_block_east_clr", aie1::mm_event_broadcast_block_east_clr}, + {"mm_event_broadcast_block_east_value", aie1::mm_event_broadcast_block_east_value}, + {"mm_trace_control0", aie1::mm_trace_control0}, + {"mm_trace_control1", aie1::mm_trace_control1}, + {"mm_trace_status", aie1::mm_trace_status}, + {"mm_trace_event0", aie1::mm_trace_event0}, + {"mm_trace_event1", aie1::mm_trace_event1}, + {"mm_timer_trig_event_low_value", aie1::mm_timer_trig_event_low_value}, + {"mm_timer_trig_event_high_value", aie1::mm_timer_trig_event_high_value}, + {"mm_timer_low", aie1::mm_timer_low}, + {"mm_timer_high", aie1::mm_timer_high}, + {"mm_watchpoint0", aie1::mm_watchpoint0}, + {"mm_watchpoint1", aie1::mm_watchpoint1}, + {"mm_event_status0", aie1::mm_event_status0}, + {"mm_event_status1", aie1::mm_event_status1}, + {"mm_event_status2", aie1::mm_event_status2}, + {"mm_event_status3", aie1::mm_event_status3}, + {"mm_reserved0", aie1::mm_reserved0}, + {"mm_reserved1", aie1::mm_reserved1}, + {"mm_reserved2", aie1::mm_reserved2}, + {"mm_reserved3", aie1::mm_reserved3}, + {"mm_combo_event_inputs", aie1::mm_combo_event_inputs}, + {"mm_combo_event_control", aie1::mm_combo_event_control}, + {"mm_event_group_0_enable", aie1::mm_event_group_0_enable}, + {"mm_event_group_watchpoint_enable", aie1::mm_event_group_watchpoint_enable}, + {"mm_event_group_dma_enable", aie1::mm_event_group_dma_enable}, + {"mm_event_group_lock_enable", aie1::mm_event_group_lock_enable}, + {"mm_event_group_memory_conflict_enable", aie1::mm_event_group_memory_conflict_enable}, + {"mm_event_group_error_enable", aie1::mm_event_group_error_enable}, + {"mm_event_group_broadcast_enable", aie1::mm_event_group_broadcast_enable}, + {"mm_event_group_user_event_enable", aie1::mm_event_group_user_event_enable}, + {"mm_spare_reg", aie1::mm_spare_reg}, + {"mm_dma_bd0_addr_a", aie1::mm_dma_bd0_addr_a}, + {"mm_dma_bd0_addr_b", aie1::mm_dma_bd0_addr_b}, + {"mm_dma_bd0_2d_x", aie1::mm_dma_bd0_2d_x}, + {"mm_dma_bd0_2d_y", aie1::mm_dma_bd0_2d_y}, + {"mm_dma_bd0_packet", aie1::mm_dma_bd0_packet}, + {"mm_dma_bd0_interleaved_state", aie1::mm_dma_bd0_interleaved_state}, + {"mm_dma_bd0_control", aie1::mm_dma_bd0_control}, + {"mm_dma_bd1_addr_a", aie1::mm_dma_bd1_addr_a}, + {"mm_dma_bd1_addr_b", aie1::mm_dma_bd1_addr_b}, + {"mm_dma_bd1_2d_x", aie1::mm_dma_bd1_2d_x}, + {"mm_dma_bd1_2d_y", aie1::mm_dma_bd1_2d_y}, + {"mm_dma_bd1_packet", aie1::mm_dma_bd1_packet}, + {"mm_dma_bd1_interleaved_state", aie1::mm_dma_bd1_interleaved_state}, + {"mm_dma_bd1_control", aie1::mm_dma_bd1_control}, + {"mm_dma_bd2_addr_a", aie1::mm_dma_bd2_addr_a}, + {"mm_dma_bd2_addr_b", aie1::mm_dma_bd2_addr_b}, + {"mm_dma_bd2_2d_x", aie1::mm_dma_bd2_2d_x}, + {"mm_dma_bd2_2d_y", aie1::mm_dma_bd2_2d_y}, + {"mm_dma_bd2_packet", aie1::mm_dma_bd2_packet}, + {"mm_dma_bd2_interleaved_state", aie1::mm_dma_bd2_interleaved_state}, + {"mm_dma_bd2_control", aie1::mm_dma_bd2_control}, + {"mm_dma_bd3_addr_a", aie1::mm_dma_bd3_addr_a}, + {"mm_dma_bd3_addr_b", aie1::mm_dma_bd3_addr_b}, + {"mm_dma_bd3_2d_x", aie1::mm_dma_bd3_2d_x}, + {"mm_dma_bd3_2d_y", aie1::mm_dma_bd3_2d_y}, + {"mm_dma_bd3_packet", aie1::mm_dma_bd3_packet}, + {"mm_dma_bd3_interleaved_state", aie1::mm_dma_bd3_interleaved_state}, + {"mm_dma_bd3_control", aie1::mm_dma_bd3_control}, + {"mm_dma_bd4_addr_a", aie1::mm_dma_bd4_addr_a}, + {"mm_dma_bd4_addr_b", aie1::mm_dma_bd4_addr_b}, + {"mm_dma_bd4_2d_x", aie1::mm_dma_bd4_2d_x}, + {"mm_dma_bd4_2d_y", aie1::mm_dma_bd4_2d_y}, + {"mm_dma_bd4_packet", aie1::mm_dma_bd4_packet}, + {"mm_dma_bd4_interleaved_state", aie1::mm_dma_bd4_interleaved_state}, + {"mm_dma_bd4_control", aie1::mm_dma_bd4_control}, + {"mm_dma_bd5_addr_a", aie1::mm_dma_bd5_addr_a}, + {"mm_dma_bd5_addr_b", aie1::mm_dma_bd5_addr_b}, + {"mm_dma_bd5_2d_x", aie1::mm_dma_bd5_2d_x}, + {"mm_dma_bd5_2d_y", aie1::mm_dma_bd5_2d_y}, + {"mm_dma_bd5_packet", aie1::mm_dma_bd5_packet}, + {"mm_dma_bd5_interleaved_state", aie1::mm_dma_bd5_interleaved_state}, + {"mm_dma_bd5_control", aie1::mm_dma_bd5_control}, + {"mm_dma_bd6_addr_a", aie1::mm_dma_bd6_addr_a}, + {"mm_dma_bd6_addr_b", aie1::mm_dma_bd6_addr_b}, + {"mm_dma_bd6_2d_x", aie1::mm_dma_bd6_2d_x}, + {"mm_dma_bd6_2d_y", aie1::mm_dma_bd6_2d_y}, + {"mm_dma_bd6_packet", aie1::mm_dma_bd6_packet}, + {"mm_dma_bd6_interleaved_state", aie1::mm_dma_bd6_interleaved_state}, + {"mm_dma_bd6_control", aie1::mm_dma_bd6_control}, + {"mm_dma_bd7_addr_a", aie1::mm_dma_bd7_addr_a}, + {"mm_dma_bd7_addr_b", aie1::mm_dma_bd7_addr_b}, + {"mm_dma_bd7_2d_x", aie1::mm_dma_bd7_2d_x}, + {"mm_dma_bd7_2d_y", aie1::mm_dma_bd7_2d_y}, + {"mm_dma_bd7_packet", aie1::mm_dma_bd7_packet}, + {"mm_dma_bd7_interleaved_state", aie1::mm_dma_bd7_interleaved_state}, + {"mm_dma_bd7_control", aie1::mm_dma_bd7_control}, + {"mm_dma_bd8_addr_a", aie1::mm_dma_bd8_addr_a}, + {"mm_dma_bd8_addr_b", aie1::mm_dma_bd8_addr_b}, + {"mm_dma_bd8_2d_x", aie1::mm_dma_bd8_2d_x}, + {"mm_dma_bd8_2d_y", aie1::mm_dma_bd8_2d_y}, + {"mm_dma_bd8_packet", aie1::mm_dma_bd8_packet}, + {"mm_dma_bd8_interleaved_state", aie1::mm_dma_bd8_interleaved_state}, + {"mm_dma_bd8_control", aie1::mm_dma_bd8_control}, + {"mm_dma_bd9_addr_a", aie1::mm_dma_bd9_addr_a}, + {"mm_dma_bd9_addr_b", aie1::mm_dma_bd9_addr_b}, + {"mm_dma_bd9_2d_x", aie1::mm_dma_bd9_2d_x}, + {"mm_dma_bd9_2d_y", aie1::mm_dma_bd9_2d_y}, + {"mm_dma_bd9_packet", aie1::mm_dma_bd9_packet}, + {"mm_dma_bd9_interleaved_state", aie1::mm_dma_bd9_interleaved_state}, + {"mm_dma_bd9_control", aie1::mm_dma_bd9_control}, + {"mm_dma_bd10_addr_a", aie1::mm_dma_bd10_addr_a}, + {"mm_dma_bd10_addr_b", aie1::mm_dma_bd10_addr_b}, + {"mm_dma_bd10_2d_x", aie1::mm_dma_bd10_2d_x}, + {"mm_dma_bd10_2d_y", aie1::mm_dma_bd10_2d_y}, + {"mm_dma_bd10_packet", aie1::mm_dma_bd10_packet}, + {"mm_dma_bd10_interleaved_state", aie1::mm_dma_bd10_interleaved_state}, + {"mm_dma_bd10_control", aie1::mm_dma_bd10_control}, + {"mm_dma_bd11_addr_a", aie1::mm_dma_bd11_addr_a}, + {"mm_dma_bd11_addr_b", aie1::mm_dma_bd11_addr_b}, + {"mm_dma_bd11_2d_x", aie1::mm_dma_bd11_2d_x}, + {"mm_dma_bd11_2d_y", aie1::mm_dma_bd11_2d_y}, + {"mm_dma_bd11_packet", aie1::mm_dma_bd11_packet}, + {"mm_dma_bd11_interleaved_state", aie1::mm_dma_bd11_interleaved_state}, + {"mm_dma_bd11_control", aie1::mm_dma_bd11_control}, + {"mm_dma_bd12_addr_a", aie1::mm_dma_bd12_addr_a}, + {"mm_dma_bd12_addr_b", aie1::mm_dma_bd12_addr_b}, + {"mm_dma_bd12_2d_x", aie1::mm_dma_bd12_2d_x}, + {"mm_dma_bd12_2d_y", aie1::mm_dma_bd12_2d_y}, + {"mm_dma_bd12_packet", aie1::mm_dma_bd12_packet}, + {"mm_dma_bd12_interleaved_state", aie1::mm_dma_bd12_interleaved_state}, + {"mm_dma_bd12_control", aie1::mm_dma_bd12_control}, + {"mm_dma_bd13_addr_a", aie1::mm_dma_bd13_addr_a}, + {"mm_dma_bd13_addr_b", aie1::mm_dma_bd13_addr_b}, + {"mm_dma_bd13_2d_x", aie1::mm_dma_bd13_2d_x}, + {"mm_dma_bd13_2d_y", aie1::mm_dma_bd13_2d_y}, + {"mm_dma_bd13_packet", aie1::mm_dma_bd13_packet}, + {"mm_dma_bd13_interleaved_state", aie1::mm_dma_bd13_interleaved_state}, + {"mm_dma_bd13_control", aie1::mm_dma_bd13_control}, + {"mm_dma_bd14_addr_a", aie1::mm_dma_bd14_addr_a}, + {"mm_dma_bd14_addr_b", aie1::mm_dma_bd14_addr_b}, + {"mm_dma_bd14_2d_x", aie1::mm_dma_bd14_2d_x}, + {"mm_dma_bd14_2d_y", aie1::mm_dma_bd14_2d_y}, + {"mm_dma_bd14_packet", aie1::mm_dma_bd14_packet}, + {"mm_dma_bd14_interleaved_state", aie1::mm_dma_bd14_interleaved_state}, + {"mm_dma_bd14_control", aie1::mm_dma_bd14_control}, + {"mm_dma_bd15_addr_a", aie1::mm_dma_bd15_addr_a}, + {"mm_dma_bd15_addr_b", aie1::mm_dma_bd15_addr_b}, + {"mm_dma_bd15_2d_x", aie1::mm_dma_bd15_2d_x}, + {"mm_dma_bd15_2d_y", aie1::mm_dma_bd15_2d_y}, + {"mm_dma_bd15_packet", aie1::mm_dma_bd15_packet}, + {"mm_dma_bd15_interleaved_state", aie1::mm_dma_bd15_interleaved_state}, + {"mm_dma_bd15_control", aie1::mm_dma_bd15_control}, + {"mm_dma_s2mm_0_ctrl", aie1::mm_dma_s2mm_0_ctrl}, + {"mm_dma_s2mm_0_start_queue", aie1::mm_dma_s2mm_0_start_queue}, + {"mm_dma_s2mm_1_ctrl", aie1::mm_dma_s2mm_1_ctrl}, + {"mm_dma_s2mm_1_start_queue", aie1::mm_dma_s2mm_1_start_queue}, + {"mm_dma_mm2s_0_ctrl", aie1::mm_dma_mm2s_0_ctrl}, + {"mm_dma_mm2s_0_start_queue", aie1::mm_dma_mm2s_0_start_queue}, + {"mm_dma_mm2s_1_ctrl", aie1::mm_dma_mm2s_1_ctrl}, + {"mm_dma_mm2s_1_start_queue", aie1::mm_dma_mm2s_1_start_queue}, + {"mm_dma_s2mm_status", aie1::mm_dma_s2mm_status}, + {"mm_dma_mm2s_status", aie1::mm_dma_mm2s_status}, + {"mm_dma_fifo_counter", aie1::mm_dma_fifo_counter}, + {"mm_lock0_release_nv", aie1::mm_lock0_release_nv}, + {"mm_lock0_release_v0", aie1::mm_lock0_release_v0}, + {"mm_lock0_release_v1", aie1::mm_lock0_release_v1}, + {"mm_lock0_acquire_nv", aie1::mm_lock0_acquire_nv}, + {"mm_lock0_acquire_v0", aie1::mm_lock0_acquire_v0}, + {"mm_lock0_acquire_v1", aie1::mm_lock0_acquire_v1}, + {"mm_lock1_release_nv", aie1::mm_lock1_release_nv}, + {"mm_lock1_release_v0", aie1::mm_lock1_release_v0}, + {"mm_lock1_release_v1", aie1::mm_lock1_release_v1}, + {"mm_lock1_acquire_nv", aie1::mm_lock1_acquire_nv}, + {"mm_lock1_acquire_v0", aie1::mm_lock1_acquire_v0}, + {"mm_lock1_acquire_v1", aie1::mm_lock1_acquire_v1}, + {"mm_lock2_release_nv", aie1::mm_lock2_release_nv}, + {"mm_lock2_release_v0", aie1::mm_lock2_release_v0}, + {"mm_lock2_release_v1", aie1::mm_lock2_release_v1}, + {"mm_lock2_acquire_nv", aie1::mm_lock2_acquire_nv}, + {"mm_lock2_acquire_v0", aie1::mm_lock2_acquire_v0}, + {"mm_lock2_acquire_v1", aie1::mm_lock2_acquire_v1}, + {"mm_lock3_release_nv", aie1::mm_lock3_release_nv}, + {"mm_lock3_release_v0", aie1::mm_lock3_release_v0}, + {"mm_lock3_release_v1", aie1::mm_lock3_release_v1}, + {"mm_lock3_acquire_nv", aie1::mm_lock3_acquire_nv}, + {"mm_lock3_acquire_v0", aie1::mm_lock3_acquire_v0}, + {"mm_lock3_acquire_v1", aie1::mm_lock3_acquire_v1}, + {"mm_lock4_release_nv", aie1::mm_lock4_release_nv}, + {"mm_lock4_release_v0", aie1::mm_lock4_release_v0}, + {"mm_lock4_release_v1", aie1::mm_lock4_release_v1}, + {"mm_lock4_acquire_nv", aie1::mm_lock4_acquire_nv}, + {"mm_lock4_acquire_v0", aie1::mm_lock4_acquire_v0}, + {"mm_lock4_acquire_v1", aie1::mm_lock4_acquire_v1}, + {"mm_lock5_release_nv", aie1::mm_lock5_release_nv}, + {"mm_lock5_release_v0", aie1::mm_lock5_release_v0}, + {"mm_lock5_release_v1", aie1::mm_lock5_release_v1}, + {"mm_lock5_acquire_nv", aie1::mm_lock5_acquire_nv}, + {"mm_lock5_acquire_v0", aie1::mm_lock5_acquire_v0}, + {"mm_lock5_acquire_v1", aie1::mm_lock5_acquire_v1}, + {"mm_lock6_release_nv", aie1::mm_lock6_release_nv}, + {"mm_lock6_release_v0", aie1::mm_lock6_release_v0}, + {"mm_lock6_release_v1", aie1::mm_lock6_release_v1}, + {"mm_lock6_acquire_nv", aie1::mm_lock6_acquire_nv}, + {"mm_lock6_acquire_v0", aie1::mm_lock6_acquire_v0}, + {"mm_lock6_acquire_v1", aie1::mm_lock6_acquire_v1}, + {"mm_lock7_release_nv", aie1::mm_lock7_release_nv}, + {"mm_lock7_release_v0", aie1::mm_lock7_release_v0}, + {"mm_lock7_release_v1", aie1::mm_lock7_release_v1}, + {"mm_lock7_acquire_nv", aie1::mm_lock7_acquire_nv}, + {"mm_lock7_acquire_v0", aie1::mm_lock7_acquire_v0}, + {"mm_lock7_acquire_v1", aie1::mm_lock7_acquire_v1}, + {"mm_lock8_release_nv", aie1::mm_lock8_release_nv}, + {"mm_lock8_release_v0", aie1::mm_lock8_release_v0}, + {"mm_lock8_release_v1", aie1::mm_lock8_release_v1}, + {"mm_lock8_acquire_nv", aie1::mm_lock8_acquire_nv}, + {"mm_lock8_acquire_v0", aie1::mm_lock8_acquire_v0}, + {"mm_lock8_acquire_v1", aie1::mm_lock8_acquire_v1}, + {"mm_lock9_release_nv", aie1::mm_lock9_release_nv}, + {"mm_lock9_release_v0", aie1::mm_lock9_release_v0}, + {"mm_lock9_release_v1", aie1::mm_lock9_release_v1}, + {"mm_lock9_acquire_nv", aie1::mm_lock9_acquire_nv}, + {"mm_lock9_acquire_v0", aie1::mm_lock9_acquire_v0}, + {"mm_lock9_acquire_v1", aie1::mm_lock9_acquire_v1}, + {"mm_lock10_release_nv", aie1::mm_lock10_release_nv}, + {"mm_lock10_release_v0", aie1::mm_lock10_release_v0}, + {"mm_lock10_release_v1", aie1::mm_lock10_release_v1}, + {"mm_lock10_acquire_nv", aie1::mm_lock10_acquire_nv}, + {"mm_lock10_acquire_v0", aie1::mm_lock10_acquire_v0}, + {"mm_lock10_acquire_v1", aie1::mm_lock10_acquire_v1}, + {"mm_lock11_release_nv", aie1::mm_lock11_release_nv}, + {"mm_lock11_release_v0", aie1::mm_lock11_release_v0}, + {"mm_lock11_release_v1", aie1::mm_lock11_release_v1}, + {"mm_lock11_acquire_nv", aie1::mm_lock11_acquire_nv}, + {"mm_lock11_acquire_v0", aie1::mm_lock11_acquire_v0}, + {"mm_lock11_acquire_v1", aie1::mm_lock11_acquire_v1}, + {"mm_lock12_release_nv", aie1::mm_lock12_release_nv}, + {"mm_lock12_release_v0", aie1::mm_lock12_release_v0}, + {"mm_lock12_release_v1", aie1::mm_lock12_release_v1}, + {"mm_lock12_acquire_nv", aie1::mm_lock12_acquire_nv}, + {"mm_lock12_acquire_v0", aie1::mm_lock12_acquire_v0}, + {"mm_lock12_acquire_v1", aie1::mm_lock12_acquire_v1}, + {"mm_lock13_release_nv", aie1::mm_lock13_release_nv}, + {"mm_lock13_release_v0", aie1::mm_lock13_release_v0}, + {"mm_lock13_release_v1", aie1::mm_lock13_release_v1}, + {"mm_lock13_acquire_nv", aie1::mm_lock13_acquire_nv}, + {"mm_lock13_acquire_v0", aie1::mm_lock13_acquire_v0}, + {"mm_lock13_acquire_v1", aie1::mm_lock13_acquire_v1}, + {"mm_lock14_release_nv", aie1::mm_lock14_release_nv}, + {"mm_lock14_release_v0", aie1::mm_lock14_release_v0}, + {"mm_lock14_release_v1", aie1::mm_lock14_release_v1}, + {"mm_lock14_acquire_nv", aie1::mm_lock14_acquire_nv}, + {"mm_lock14_acquire_v0", aie1::mm_lock14_acquire_v0}, + {"mm_lock14_acquire_v1", aie1::mm_lock14_acquire_v1}, + {"mm_lock15_release_nv", aie1::mm_lock15_release_nv}, + {"mm_lock15_release_v0", aie1::mm_lock15_release_v0}, + {"mm_lock15_release_v1", aie1::mm_lock15_release_v1}, + {"mm_lock15_acquire_nv", aie1::mm_lock15_acquire_nv}, + {"mm_lock15_acquire_v0", aie1::mm_lock15_acquire_v0}, + {"mm_lock15_acquire_v1", aie1::mm_lock15_acquire_v1}, + {"mm_all_lock_state_value", aie1::mm_all_lock_state_value}, + {"mm_lock_event_value_control_0", aie1::mm_lock_event_value_control_0}, + {"mm_lock_event_value_control_1", aie1::mm_lock_event_value_control_1}, + {"shim_dma_bd_step_size", aie1::shim_dma_bd_step_size}, + {"shim_dma_s2mm_step_size", aie1::shim_dma_s2mm_step_size}, + {"shim_all_lock_state_value", aie1::shim_all_lock_state_value}, + {"shim_dma_bd0_addr_low", aie1::shim_dma_bd0_addr_low}, + {"shim_dma_bd0_buffer_length", aie1::shim_dma_bd0_buffer_length}, + {"shim_dma_bd0_control", aie1::shim_dma_bd0_control}, + {"shim_dma_bd0_axi_config", aie1::shim_dma_bd0_axi_config}, + {"shim_dma_bd0_packet", aie1::shim_dma_bd0_packet}, + {"shim_dma_s2mm_0_ctrl", aie1::shim_dma_s2mm_0_ctrl}, + {"shim_dma_s2mm_0_start_queue", aie1::shim_dma_s2mm_0_start_queue}, + {"shim_performance_control0", aie1::shim_performance_control0}, + {"shim_performance_control1", aie1::shim_performance_control1}, + {"shim_performance_counter0", aie1::shim_performance_counter0}, + {"shim_performance_counter1", aie1::shim_performance_counter1}, + {"shim_performance_counter0_event_value", aie1::shim_performance_counter0_event_value}, + {"shim_performance_counter1_event_value", aie1::shim_performance_counter1_event_value}, + {"shim_event_generate", aie1::shim_event_generate}, + {"shim_event_broadcast_a_0", aie1::shim_event_broadcast_a_0}, + {"shim_event_broadcast_a_1", aie1::shim_event_broadcast_a_1}, + {"shim_event_broadcast_a_2", aie1::shim_event_broadcast_a_2}, + {"shim_event_broadcast_a_3", aie1::shim_event_broadcast_a_3}, + {"shim_event_broadcast_a_4", aie1::shim_event_broadcast_a_4}, + {"shim_event_broadcast_a_5", aie1::shim_event_broadcast_a_5}, + {"shim_event_broadcast_a_6", aie1::shim_event_broadcast_a_6}, + {"shim_event_broadcast_a_7", aie1::shim_event_broadcast_a_7}, + {"shim_event_broadcast_a_8", aie1::shim_event_broadcast_a_8}, + {"shim_event_broadcast_a_9", aie1::shim_event_broadcast_a_9}, + {"shim_event_broadcast_a_10", aie1::shim_event_broadcast_a_10}, + {"shim_event_broadcast_a_11", aie1::shim_event_broadcast_a_11}, + {"shim_event_broadcast_a_12", aie1::shim_event_broadcast_a_12}, + {"shim_event_broadcast_a_13", aie1::shim_event_broadcast_a_13}, + {"shim_event_broadcast_a_14", aie1::shim_event_broadcast_a_14}, + {"shim_event_broadcast_a_15", aie1::shim_event_broadcast_a_15}, + {"shim_event_broadcast_a_block_south_set", aie1::shim_event_broadcast_a_block_south_set}, + {"shim_event_broadcast_a_block_south_clr", aie1::shim_event_broadcast_a_block_south_clr}, + {"shim_event_broadcast_a_block_south_value", aie1::shim_event_broadcast_a_block_south_value}, + {"shim_event_broadcast_a_block_west_set", aie1::shim_event_broadcast_a_block_west_set}, + {"shim_event_broadcast_a_block_west_clr", aie1::shim_event_broadcast_a_block_west_clr}, + {"shim_event_broadcast_a_block_west_value", aie1::shim_event_broadcast_a_block_west_value}, + {"shim_event_broadcast_a_block_north_set", aie1::shim_event_broadcast_a_block_north_set}, + {"shim_event_broadcast_a_block_north_clr", aie1::shim_event_broadcast_a_block_north_clr}, + {"shim_event_broadcast_a_block_north_value", aie1::shim_event_broadcast_a_block_north_value}, + {"shim_event_broadcast_a_block_east_set", aie1::shim_event_broadcast_a_block_east_set}, + {"shim_event_broadcast_a_block_east_clr", aie1::shim_event_broadcast_a_block_east_clr}, + {"shim_event_broadcast_a_block_east_value", aie1::shim_event_broadcast_a_block_east_value}, + {"shim_trace_control0", aie1::shim_trace_control0}, + {"shim_trace_control1", aie1::shim_trace_control1}, + {"shim_trace_status", aie1::shim_trace_status}, + {"shim_trace_event0", aie1::shim_trace_event0}, + {"shim_trace_event1", aie1::shim_trace_event1}, + {"shim_timer_trig_event_low_value", aie1::shim_timer_trig_event_low_value}, + {"shim_timer_trig_event_high_value", aie1::shim_timer_trig_event_high_value}, + {"shim_timer_low", aie1::shim_timer_low}, + {"shim_timer_high", aie1::shim_timer_high}, + {"shim_event_status0", aie1::shim_event_status0}, + {"shim_event_status1", aie1::shim_event_status1}, + {"shim_event_status2", aie1::shim_event_status2}, + {"shim_event_status3", aie1::shim_event_status3}, + {"shim_event_group_dma_enable", aie1::shim_event_group_dma_enable}, + {"shim_stream_switch_event_port_selection_0", aie1::shim_stream_switch_event_port_selection_0}, + {"shim_stream_switch_event_port_selection_1", aie1::shim_stream_switch_event_port_selection_1}, + {"mem_performance_counter0", aie1::mem_performance_counter0} + }; + } + + void populateRegValueToNameMap() { + regValueToName= { + {0x0003f054, "cm_stream_switch_master_config_east0"}, + {0x0003f058, "cm_stream_switch_master_config_east1"}, + {0x0003f05c, "cm_stream_switch_master_config_east2"}, + {0x0003f060, "cm_stream_switch_master_config_east3"}, + {0x0001ef20, "mm_lock_event_value_control_0"}, + {0x0001d110, "mm_dma_bd8_packet"}, + {0x00034208, "cm_event_status2"}, + {0x0003420c, "cm_event_status3"}, + {0x00034200, "cm_event_status0"}, + {0x00034204, "cm_event_status1"}, + {0x00034048, "cm_event_broadcast14"}, + {0x0003404c, "cm_event_broadcast15"}, + {0x00034040, "cm_event_broadcast12"}, + {0x00034044, "cm_event_broadcast13"}, + {0x00034038, "cm_event_broadcast10"}, + {0x0003403c, "cm_event_broadcast11"}, + {0x00034080, "cm_event_broadcast_block_east_set"}, + {0x0001d174, "mm_dma_bd11_interleaved_state"}, + {0x0001d1b4, "mm_dma_bd13_interleaved_state"}, + {0x0001d1d4, "mm_dma_bd14_interleaved_state"}, + {0x0001d1cc, "mm_dma_bd14_2d_y"}, + {0x0001d1c8, "mm_dma_bd14_2d_x"}, + {0x0001e070, "mm_lock0_acquire_v1"}, + {0x0001e060, "mm_lock0_acquire_v0"}, + {0x0001e4b0, "mm_lock9_release_v1"}, + {0x0001e4a0, "mm_lock9_release_v0"}, + {0x000340f4, "shim_timer_trig_event_high_value"}, + {0x0001d150, "mm_dma_bd10_packet"}, + {0x00034068, "shim_event_broadcast_a_block_west_value"}, + {0x00034504, "shim_event_group_dma_enable"}, + {0x0001d060, "mm_dma_bd3_addr_a"}, + {0x0001d064, "mm_dma_bd3_addr_b"}, + {0x0003450c, "cm_event_group_core_program_flow_enable"}, + {0x00014074, "mm_event_broadcast_block_north_clr"}, + {0x00014050, "mm_event_broadcast_block_south_set"}, + {0x0001e100, "mm_lock2_release_nv"}, + {0x0001e2b0, "mm_lock5_release_v1"}, + {0x0001e2a0, "mm_lock5_release_v0"}, + {0x0003f154, "cm_stream_switch_slave_config_east_0"}, + {0x0001d1c0, "mm_dma_bd14_addr_a"}, + {0x00014008, "mm_event_generate"}, + {0x0003f2f4, "cm_stream_switch_slave_west_2_slot1"}, + {0x0003f2f0, "cm_stream_switch_slave_west_2_slot0"}, + {0x0003f2fc, "cm_stream_switch_slave_west_2_slot3"}, + {0x0003f2f8, "cm_stream_switch_slave_west_2_slot2"}, + {0x00034014, "shim_event_broadcast_a_1"}, + {0x0001e320, "mm_lock6_release_v0"}, + {0x00034500, "cm_event_group_0_enable"}, + {0x0001d00c, "shim_dma_bd0_axi_config"}, + {0x00016000, "mm_spare_reg"}, + {0x0003f150, "cm_stream_switch_slave_config_north_3"}, + {0x0003f14c, "cm_stream_switch_slave_config_north_2"}, + {0x0003f148, "cm_stream_switch_slave_config_north_1"}, + {0x0003f144, "cm_stream_switch_slave_config_north_0"}, + {0x0001de14, "mm_dma_mm2s_0_start_queue"}, + {0x0001e420, "mm_lock8_release_v0"}, + {0x0001e430, "mm_lock8_release_v1"}, + {0x000140d8, "mm_trace_status"}, + {0x0001d190, "mm_dma_bd12_packet"}, + {0x0003f204, "cm_stream_switch_slave_aie_core0_slot1"}, + {0x0003f200, "cm_stream_switch_slave_aie_core0_slot0"}, + {0x0003f20c, "cm_stream_switch_slave_aie_core0_slot3"}, + {0x0003f208, "cm_stream_switch_slave_aie_core0_slot2"}, + {0x0001d08c, "mm_dma_bd4_2d_y"}, + {0x0001d088, "mm_dma_bd4_2d_x"}, + {0x0001451c, "mm_event_group_user_event_enable"}, + {0x00014000, "mm_timer_control"}, + {0x00031000, "shim_performance_control0"}, + {0x0003f388, "cm_stream_switch_slave_east_3_slot2"}, + {0x0001e560, "mm_lock10_acquire_v0"}, + {0x00034024, "cm_event_broadcast5"}, + {0x0003f380, "cm_stream_switch_slave_east_3_slot0"}, + {0x0003f384, "cm_stream_switch_slave_east_3_slot1"}, + {0x0001d168, "mm_dma_bd11_2d_x"}, + {0x0001d16c, "mm_dma_bd11_2d_y"}, + {0x00031080, "shim_performance_counter0_event_value"}, + {0x0001d114, "mm_dma_bd8_interleaved_state"}, + {0x0001de0c, "mm_dma_s2mm_1_start_queue"}, + {0x0001d0d0, "mm_dma_bd6_packet"}, + {0x00034508, "cm_event_group_core_stall_enable"}, + {0x0001d158, "mm_dma_bd10_control"}, + {0x00034510, "cm_event_group_errors0_enable"}, + {0x00034058, "shim_event_broadcast_a_block_south_value"}, + {0x0001e770, "mm_lock14_acquire_v1"}, + {0x0001e760, "mm_lock14_acquire_v0"}, + {0x00032030, "cm_error_halt_control"}, + {0x0001e6b0, "mm_lock13_release_v1"}, + {0x0001e6c0, "mm_lock13_acquire_nv"}, + {0x0001e0b0, "mm_lock1_release_v1"}, + {0x0001e0a0, "mm_lock1_release_v0"}, + {0x0001d004, "shim_dma_bd0_buffer_length"}, + {0x0003f110, "cm_stream_switch_slave_config_tile_ctrl"}, + {0x0001d0b0, "mm_dma_bd5_packet"}, + {0x00014404, "mm_combo_event_control"}, + {0x0003f334, "cm_stream_switch_slave_north_2_slot1"}, + {0x0003f338, "cm_stream_switch_slave_north_2_slot2"}, + {0x0003f33c, "cm_stream_switch_slave_north_2_slot3"}, + {0x0001d134, "mm_dma_bd9_interleaved_state"}, + {0x00031020, "shim_performance_counter0"}, + {0x00031024, "shim_performance_counter1"}, + {0x00014514, "mm_event_group_error_enable"}, + {0x00014508, "mm_event_group_dma_enable"}, + {0x000340f4, "cm_timer_trig_event_high_value"}, + {0x0001d140, "shim_dma_s2mm_0_ctrl"}, + {0x00031008, "shim_performance_control1"}, + {0x0001e780, "mm_lock15_release_nv"}, + {0x0003ff00, "cm_stream_switch_event_port_selection_0"}, + {0x0001d038, "mm_dma_bd1_control"}, + {0x0001e680, "mm_lock13_release_nv"}, + {0x00034050, "cm_event_broadcast_block_south_set"}, + {0x0001e330, "mm_lock6_release_v1"}, + {0x0001d080, "mm_dma_bd4_addr_a"}, + {0x0001d084, "mm_dma_bd4_addr_b"}, + {0x000340f0, "cm_timer_trig_event_low_value"}, + {0x00014058, "mm_event_broadcast_block_south_value"}, + {0x0003f354, "cm_stream_switch_slave_east_0_slot1"}, + {0x0003f350, "cm_stream_switch_slave_east_0_slot0"}, + {0x0003f35c, "cm_stream_switch_slave_east_0_slot3"}, + {0x0003f358, "cm_stream_switch_slave_east_0_slot2"}, + {0x0003f018, "cm_stream_switch_master_config_fifo1"}, + {0x0003f014, "cm_stream_switch_master_config_fifo0"}, + {0x0003f298, "cm_stream_switch_slave_south_2_slot2"}, + {0x0003f29c, "cm_stream_switch_slave_south_2_slot3"}, + {0x0003f290, "cm_stream_switch_slave_south_2_slot0"}, + {0x0003f294, "cm_stream_switch_slave_south_2_slot1"}, + {0x00014200, "mm_event_status0"}, + {0x00014204, "mm_event_status1"}, + {0x00014208, "mm_event_status2"}, + {0x0001420c, "mm_event_status3"}, + {0x00034088, "cm_event_broadcast_block_east_value"}, + {0x00011084, "mm_performance_counter1_event_value"}, + {0x00034058, "cm_event_broadcast_block_south_value"}, + {0x0003202c, "cm_pc_event3"}, + {0x0001d0d4, "mm_dma_bd6_interleaved_state"}, + {0x0003ff04, "cm_stream_switch_event_port_selection_1"}, + {0x0003f360, "cm_stream_switch_slave_east_1_slot0"}, + {0x0003f364, "cm_stream_switch_slave_east_1_slot1"}, + {0x0003f368, "cm_stream_switch_slave_east_1_slot2"}, + {0x0003f36c, "cm_stream_switch_slave_east_1_slot3"}, + {0x0001d070, "mm_dma_bd3_packet"}, + {0x0001d14c, "mm_dma_bd10_2d_y"}, + {0x0001d148, "mm_dma_bd10_2d_x"}, + {0x0001d1a4, "mm_dma_bd13_addr_b"}, + {0x0001d1a0, "mm_dma_bd13_addr_a"}, + {0x0001ef24, "mm_lock_event_value_control_1"}, + {0x0001d068, "mm_dma_bd3_2d_x"}, + {0x0001d06c, "mm_dma_bd3_2d_y"}, + {0x0001e340, "mm_lock6_acquire_nv"}, + {0x0001d058, "mm_dma_bd2_control"}, + {0x00031088, "cm_performance_counter2_event_value"}, + {0x000340f0, "shim_timer_trig_event_low_value"}, + {0x000140f4, "mm_timer_trig_event_high_value"}, + {0x0001d0d8, "mm_dma_bd6_control"}, + {0x00032034, "cm_error_halt_event"}, + {0x00034074, "shim_event_broadcast_a_block_north_clr"}, + {0x00014400, "mm_combo_event_inputs"}, + {0x0001e5b0, "mm_lock11_release_v1"}, + {0x0001e5a0, "mm_lock11_release_v0"}, + {0x0, "mem_performance_counter0"}, + {0x0003f100, "cm_stream_switch_slave_config_aie_core0"}, + {0x0003f040, "cm_stream_switch_master_config_north1"}, + {0x0003f03c, "cm_stream_switch_master_config_north0"}, + {0x0003f048, "cm_stream_switch_master_config_north3"}, + {0x0003f044, "cm_stream_switch_master_config_north2"}, + {0x0003f050, "cm_stream_switch_master_config_north5"}, + {0x0003f04c, "cm_stream_switch_master_config_north4"}, + {0x0001d1c4, "mm_dma_bd14_addr_b"}, + {0x8, "shim_dma_s2mm_step_size"}, + {0x0003f37c, "cm_stream_switch_slave_east_2_slot3"}, + {0x0003f378, "cm_stream_switch_slave_east_2_slot2"}, + {0x0003f374, "cm_stream_switch_slave_east_2_slot1"}, + {0x0003f370, "cm_stream_switch_slave_east_2_slot0"}, + {0x00014070, "mm_event_broadcast_block_north_set"}, + {0x0001de10, "mm_dma_mm2s_0_ctrl"}, + {0x0001d180, "mm_dma_bd12_addr_a"}, + {0x0001d0f0, "mm_dma_bd7_packet"}, + {0x0001e280, "mm_lock5_release_nv"}, + {0x0001e170, "mm_lock2_acquire_v1"}, + {0x0001e160, "mm_lock2_acquire_v0"}, + {0x0001e4c0, "mm_lock9_acquire_nv"}, + {0x0003f284, "cm_stream_switch_slave_south_1_slot1"}, + {0x0003f280, "cm_stream_switch_slave_south_1_slot0"}, + {0x0003f28c, "cm_stream_switch_slave_south_1_slot3"}, + {0x0003f288, "cm_stream_switch_slave_south_1_slot2"}, + {0x000140e0, "mm_trace_event0"}, + {0x000140e4, "mm_trace_event1"}, + {0x0003f21c, "cm_stream_switch_slave_aie_core1_slot3"}, + {0x0001df00, "mm_dma_s2mm_status"}, + {0x00034078, "cm_event_broadcast_block_north_value"}, + {0x00014060, "mm_event_broadcast_block_west_set"}, + {0x00034400, "cm_combo_event_inputs"}, + {0x0001e180, "mm_lock3_release_nv"}, + {0x0001450c, "mm_event_group_lock_enable"}, + {0x0003f164, "cm_stream_switch_slave_config_aie_trace"}, + {0x0001e7f0, "mm_lock15_acquire_v1"}, + {0x0001d078, "mm_dma_bd3_control"}, + {0x0003f240, "cm_stream_switch_slave_tile_ctrl_slot0"}, + {0x0003f244, "cm_stream_switch_slave_tile_ctrl_slot1"}, + {0x0003f248, "cm_stream_switch_slave_tile_ctrl_slot2"}, + {0x0003f24c, "cm_stream_switch_slave_tile_ctrl_slot3"}, + {0x00034070, "cm_event_broadcast_block_north_set"}, + {0x0003f158, "cm_stream_switch_slave_config_east_1"}, + {0x0003f15c, "cm_stream_switch_slave_config_east_2"}, + {0x0003f160, "cm_stream_switch_slave_config_east_3"}, + {0x00034008, "shim_event_generate"}, + {0x0001e400, "mm_lock8_release_nv"}, + {0x0001e3c0, "mm_lock7_acquire_nv"}, + {0x0001d18c, "mm_dma_bd12_2d_y"}, + {0x0001d188, "mm_dma_bd12_2d_x"}, + {0x0001d1f0, "mm_dma_bd15_packet"}, + {0x0001e040, "mm_lock0_acquire_nv"}, + {0x0001e540, "mm_lock10_acquire_nv"}, + {0x000140fc, "mm_timer_high"}, + {0x0003f3a4, "cm_stream_switch_slave_mem_trace_slot1"}, + {0x0003f12c, "cm_stream_switch_slave_config_south_4"}, + {0x0003f2c4, "cm_stream_switch_slave_south_5_slot1"}, + {0x0003f2c0, "cm_stream_switch_slave_south_5_slot0"}, + {0x0003f2cc, "cm_stream_switch_slave_south_5_slot3"}, + {0x0003f2c8, "cm_stream_switch_slave_south_5_slot2"}, + {0x0001d04c, "mm_dma_bd2_2d_y"}, + {0x000340d4, "cm_trace_control1"}, + {0x000340d0, "cm_trace_control0"}, + {0x0001d048, "mm_dma_bd2_2d_x"}, + {0x0003f210, "cm_stream_switch_slave_aie_core1_slot0"}, + {0x0003f214, "cm_stream_switch_slave_aie_core1_slot1"}, + {0x0003f218, "cm_stream_switch_slave_aie_core1_slot2"}, + {0x00014500, "mm_event_group_0_enable"}, + {0x0003f394, "cm_stream_switch_slave_aie_trace_slot1"}, + {0x0003f390, "cm_stream_switch_slave_aie_trace_slot0"}, + {0x0003f39c, "cm_stream_switch_slave_aie_trace_slot3"}, + {0x0003f398, "cm_stream_switch_slave_aie_trace_slot2"}, + {0x0001d10c, "mm_dma_bd8_2d_y"}, + {0x0001d108, "mm_dma_bd8_2d_x"}, + {0x0001d144, "shim_dma_s2mm_0_start_queue"}, + {0x0001e6e0, "mm_lock13_acquire_v0"}, + {0x0001e6f0, "mm_lock13_acquire_v1"}, + {0x0003f010, "cm_stream_switch_master_config_tile_ctrl"}, + {0x0001e7b0, "mm_lock15_release_v1"}, + {0x0001e7a0, "mm_lock15_release_v0"}, + {0x0001d024, "mm_dma_bd1_addr_b"}, + {0x0001d020, "mm_dma_bd1_addr_a"}, + {0x0001e360, "mm_lock6_acquire_v0"}, + {0x0001d028, "mm_dma_bd1_2d_x"}, + {0x0001d02c, "mm_dma_bd1_2d_y"}, + {0x0001d124, "mm_dma_bd9_addr_b"}, + {0x0001d120, "mm_dma_bd9_addr_a"}, + {0x0001e240, "mm_lock4_acquire_nv"}, + {0x00031024, "cm_performance_counter1"}, + {0x00031020, "cm_performance_counter0"}, + {0x0003102c, "cm_performance_counter3"}, + {0x00031028, "cm_performance_counter2"}, + {0x000340e0, "cm_trace_event0"}, + {0x000340e4, "cm_trace_event1"}, + {0x0001e080, "mm_lock1_release_nv"}, + {0x0001e1a0, "mm_lock3_release_v0"}, + {0x0003f2dc, "cm_stream_switch_slave_west_0_slot3"}, + {0x0003f2d8, "cm_stream_switch_slave_west_0_slot2"}, + {0x0003f2d4, "cm_stream_switch_slave_west_0_slot1"}, + {0x0003f2d0, "cm_stream_switch_slave_west_0_slot0"}, + {0x0001e300, "mm_lock6_release_nv"}, + {0x00034060, "cm_event_broadcast_block_west_set"}, + {0x00034080, "shim_event_broadcast_a_block_east_set"}, + {0x0001d094, "mm_dma_bd4_interleaved_state"}, + {0x0001e7e0, "mm_lock15_acquire_v0"}, + {0x00034084, "cm_event_broadcast_block_east_clr"}, + {0x0001e370, "mm_lock6_acquire_v1"}, + {0x00034064, "shim_event_broadcast_a_block_west_clr"}, + {0x0001e0e0, "mm_lock1_acquire_v0"}, + {0x0001e0f0, "mm_lock1_acquire_v1"}, + {0x0003f318, "cm_stream_switch_slave_north_0_slot2"}, + {0x0003f31c, "cm_stream_switch_slave_north_0_slot3"}, + {0x0003f310, "cm_stream_switch_slave_north_0_slot0"}, + {0x0003f314, "cm_stream_switch_slave_north_0_slot1"}, + {0x0003f2e8, "cm_stream_switch_slave_west_1_slot2"}, + {0x00011024, "mm_performance_counter1"}, + {0x00011020, "mm_performance_counter0"}, + {0x0003f2ec, "cm_stream_switch_slave_west_1_slot3"}, + {0x0003f2e0, "cm_stream_switch_slave_west_1_slot0"}, + {0x0001d000, "shim_dma_bd0_addr_low"}, + {0x0003f348, "cm_stream_switch_slave_north_3_slot2"}, + {0x0001d118, "mm_dma_bd8_control"}, + {0x00014068, "mm_event_broadcast_block_west_value"}, + {0x0001d100, "mm_dma_bd8_addr_a"}, + {0x0001d104, "mm_dma_bd8_addr_b"}, + {0x0001d0cc, "mm_dma_bd6_2d_y"}, + {0x0001d010, "mm_dma_bd0_packet"}, + {0x0001d0c8, "mm_dma_bd6_2d_x"}, + {0x0001e000, "mm_lock0_release_nv"}, + {0x0001d0ec, "mm_dma_bd7_2d_y"}, + {0x00014088, "mm_event_broadcast_block_east_value"}, + {0x0001d0b8, "mm_dma_bd5_control"}, + {0x00034000, "cm_timer_control"}, + {0x00032000, "cm_core_control"}, + {0x0001d130, "mm_dma_bd9_packet"}, + {0x0001e2e0, "mm_lock5_acquire_v0"}, + {0x0001e4e0, "mm_lock9_acquire_v0"}, + {0x0001e4f0, "mm_lock9_acquire_v1"}, + {0x00014054, "mm_event_broadcast_block_south_clr"}, + {0x00034084, "shim_event_broadcast_a_block_east_clr"}, + {0x0001e5f0, "mm_lock11_acquire_v1"}, + {0x00031084, "cm_performance_counter1_event_value"}, + {0x0001d1b0, "mm_dma_bd13_packet"}, + {0x0001df20, "mm_dma_fifo_counter"}, + {0x0001e7c0, "mm_lock15_acquire_nv"}, + {0x00036034, "cm_tile_control_packet_handler_status"}, + {0x00034030, "cm_event_broadcast8"}, + {0x00034034, "cm_event_broadcast9"}, + {0x0001e580, "mm_lock11_release_nv"}, + {0x00034020, "cm_event_broadcast4"}, + {0x0003f38c, "cm_stream_switch_slave_east_3_slot3"}, + {0x00034028, "cm_event_broadcast6"}, + {0x0003402c, "cm_event_broadcast7"}, + {0x00034010, "cm_event_broadcast0"}, + {0x00034014, "cm_event_broadcast1"}, + {0x00034018, "cm_event_broadcast2"}, + {0x0003401c, "cm_event_broadcast3"}, + {0x0001d0f4, "mm_dma_bd7_interleaved_state"}, + {0x0001e2c0, "mm_lock5_acquire_nv"}, + {0x0003f008, "cm_stream_switch_master_config_dma0"}, + {0x0003f00c, "cm_stream_switch_master_config_dma1"}, + {0x0001d1d0, "mm_dma_bd14_packet"}, + {0x0001d194, "mm_dma_bd12_interleaved_state"}, + {0x00034504, "cm_event_group_pc_enable"}, + {0x00034054, "cm_event_broadcast_block_south_clr"}, + {0x0003f034, "cm_stream_switch_master_config_west2"}, + {0x0003f038, "cm_stream_switch_master_config_west3"}, + {0x0003f02c, "cm_stream_switch_master_config_west0"}, + {0x0003f030, "cm_stream_switch_master_config_west1"}, + {0x0003f264, "cm_stream_switch_slave_fifo_1_slot1"}, + {0x0003f260, "cm_stream_switch_slave_fifo_1_slot0"}, + {0x0003f26c, "cm_stream_switch_slave_fifo_1_slot3"}, + {0x0003f268, "cm_stream_switch_slave_fifo_1_slot2"}, + {0x0001d184, "mm_dma_bd12_addr_b"}, + {0x0003420c, "shim_event_status3"}, + {0x00034208, "shim_event_status2"}, + {0x00034204, "shim_event_status1"}, + {0x00034200, "shim_event_status0"}, + {0x0001e140, "mm_lock2_acquire_nv"}, + {0x0001d1a8, "mm_dma_bd13_2d_x"}, + {0x0001d1ac, "mm_dma_bd13_2d_y"}, + {0x0003f130, "cm_stream_switch_slave_config_south_5"}, + {0x0003f3a0, "cm_stream_switch_slave_mem_trace_slot0"}, + {0x0003f3ac, "cm_stream_switch_slave_mem_trace_slot3"}, + {0x0003f3a8, "cm_stream_switch_slave_mem_trace_slot2"}, + {0x0003f120, "cm_stream_switch_slave_config_south_1"}, + {0x0003f11c, "cm_stream_switch_slave_config_south_0"}, + {0x0003f128, "cm_stream_switch_slave_config_south_3"}, + {0x0003f124, "cm_stream_switch_slave_config_south_2"}, + {0x0001d1f4, "mm_dma_bd15_interleaved_state"}, + {0x0001d160, "mm_dma_bd11_addr_a"}, + {0x0001e1b0, "mm_lock3_release_v1"}, + {0x00012110, "mm_ecc_scrubbing_event"}, + {0x0003f028, "cm_stream_switch_master_config_south3"}, + {0x0003f024, "cm_stream_switch_master_config_south2"}, + {0x0003f020, "cm_stream_switch_master_config_south1"}, + {0x0003f01c, "cm_stream_switch_master_config_south0"}, + {0x0001d074, "mm_dma_bd3_interleaved_state"}, + {0x00031084, "shim_performance_counter1_event_value"}, + {0x000340e4, "shim_trace_event1"}, + {0x0001d138, "mm_dma_bd9_control"}, + {0x000340e0, "shim_trace_event0"}, + {0x00013000, "mm_reset_control"}, + {0x00014100, "mm_watchpoint0"}, + {0x00014104, "mm_watchpoint1"}, + {0x0001421c, "mm_reserved3"}, + {0x00014218, "mm_reserved2"}, + {0x00014214, "mm_reserved1"}, + {0x00014210, "mm_reserved0"}, + {0x0001e270, "mm_lock4_acquire_v1"}, + {0x0001e260, "mm_lock4_acquire_v0"}, + {0x0001d144, "mm_dma_bd10_addr_b"}, + {0x0001d140, "mm_dma_bd10_addr_a"}, + {0x0001d0b4, "mm_dma_bd5_interleaved_state"}, + {0x00014038, "mm_event_broadcast10"}, + {0x0001403c, "mm_event_broadcast11"}, + {0x00014040, "mm_event_broadcast12"}, + {0x00014044, "mm_event_broadcast13"}, + {0x00014048, "mm_event_broadcast14"}, + {0x0001404c, "mm_event_broadcast15"}, + {0x0001d00c, "mm_dma_bd0_2d_y"}, + {0x0001d008, "mm_dma_bd0_2d_x"}, + {0x0003f168, "cm_stream_switch_slave_config_mem_trace"}, + {0x00034514, "cm_event_group_errors1_enable"}, + {0x0001e1c0, "mm_lock3_acquire_nv"}, + {0x0001d044, "mm_dma_bd2_addr_b"}, + {0x0001df10, "mm_dma_mm2s_status"}, + {0x0001d040, "mm_dma_bd2_addr_a"}, + {0x00031008, "cm_performance_control2"}, + {0x0001d054, "mm_dma_bd2_interleaved_state"}, + {0x0003f2ac, "cm_stream_switch_slave_south_3_slot3"}, + {0x0003f2a8, "cm_stream_switch_slave_south_3_slot2"}, + {0x0003f2a4, "cm_stream_switch_slave_south_3_slot1"}, + {0x0003f2a0, "cm_stream_switch_slave_south_3_slot0"}, + {0x0001e5c0, "mm_lock11_acquire_nv"}, + {0x0001e460, "mm_lock8_acquire_v0"}, + {0x000140d4, "mm_trace_control1"}, + {0x000140d0, "mm_trace_control0"}, + {0x0001e0c0, "mm_lock1_acquire_nv"}, + {0x0001e3e0, "mm_lock7_acquire_v0"}, + {0x0001e3b0, "mm_lock7_release_v1"}, + {0x0001e3a0, "mm_lock7_release_v0"}, + {0x00034050, "shim_event_broadcast_a_block_south_set"}, + {0x00034078, "shim_event_broadcast_a_block_north_value"}, + {0x00034064, "cm_event_broadcast_block_west_clr"}, + {0x00034054, "shim_event_broadcast_a_block_south_clr"}, + {0x0001e3f0, "mm_lock7_acquire_v1"}, + {0x0001d0e0, "mm_dma_bd7_addr_a"}, + {0x0001d0a4, "mm_dma_bd5_addr_b"}, + {0x0001d0a0, "mm_dma_bd5_addr_a"}, + {0x0001d0e4, "mm_dma_bd7_addr_b"}, + {0x000140f0, "mm_timer_trig_event_low_value"}, + {0x0001d1b8, "mm_dma_bd13_control"}, + {0x0003451c, "cm_event_group_broadcast_enable"}, + {0x00014084, "mm_event_broadcast_block_east_clr"}, + {0x00014064, "mm_event_broadcast_block_west_clr"}, + {0x0001e520, "mm_lock10_release_v0"}, + {0x0001e530, "mm_lock10_release_v1"}, + {0x0001e440, "mm_lock8_acquire_nv"}, + {0x0001d090, "mm_dma_bd4_packet"}, + {0x0001d000, "mm_dma_bd0_addr_a"}, + {0x0001d004, "mm_dma_bd0_addr_b"}, + {0x0003404c, "shim_event_broadcast_a_15"}, + {0x0003108c, "cm_performance_counter3_event_value"}, + {0x00011080, "mm_performance_counter0_event_value"}, + {0x0001ef00, "mm_all_lock_state_value"}, + {0x0003f108, "cm_stream_switch_slave_config_dma_0"}, + {0x0003f10c, "cm_stream_switch_slave_config_dma_1"}, + {0x00014510, "mm_event_group_memory_conflict_enable"}, + {0x00034068, "cm_event_broadcast_block_west_value"}, + {0x00034034, "shim_event_broadcast_a_9"}, + {0x00034030, "shim_event_broadcast_a_8"}, + {0x0003402c, "shim_event_broadcast_a_7"}, + {0x00034028, "shim_event_broadcast_a_6"}, + {0x00034024, "shim_event_broadcast_a_5"}, + {0x00034020, "shim_event_broadcast_a_4"}, + {0x0003401c, "shim_event_broadcast_a_3"}, + {0x00034018, "shim_event_broadcast_a_2"}, + {0x0001d198, "mm_dma_bd12_control"}, + {0x00034010, "shim_event_broadcast_a_0"}, + {0x0001d170, "mm_dma_bd11_packet"}, + {0x0001d008, "shim_dma_bd0_control"}, + {0x00036040, "cm_tile_clock_control"}, + {0x0001e220, "mm_lock4_release_v0"}, + {0x0001e230, "mm_lock4_release_v1"}, + {0x0001d014, "mm_dma_bd0_interleaved_state"}, + {0x0003f104, "cm_stream_switch_slave_config_aie_core1"}, + {0x0001d0c0, "mm_dma_bd6_addr_a"}, + {0x000340d8, "shim_trace_status"}, + {0x000340d8, "cm_trace_status"}, + {0x00012120, "mm_ecc_failing_address"}, + {0x0003f250, "cm_stream_switch_slave_fifo_0_slot0"}, + {0x0003f254, "cm_stream_switch_slave_fifo_0_slot1"}, + {0x0003f258, "cm_stream_switch_slave_fifo_0_slot2"}, + {0x0003f25c, "cm_stream_switch_slave_fifo_0_slot3"}, + {0x0003200c, "cm_reset_event"}, + {0x0001e700, "mm_lock14_release_nv"}, + {0x000140f8, "mm_timer_low"}, + {0x0001e020, "mm_lock0_release_v0"}, + {0x0001e030, "mm_lock0_release_v1"}, + {0x00014030, "mm_event_broadcast8"}, + {0x00014034, "mm_event_broadcast9"}, + {0x00014028, "mm_event_broadcast6"}, + {0x0001402c, "mm_event_broadcast7"}, + {0x00014020, "mm_event_broadcast4"}, + {0x00014024, "mm_event_broadcast5"}, + {0x00014018, "mm_event_broadcast2"}, + {0x0001401c, "mm_event_broadcast3"}, + {0x00014010, "mm_event_broadcast0"}, + {0x00014014, "mm_event_broadcast1"}, + {0x0001e470, "mm_lock8_acquire_v1"}, + {0x00012124, "mm_parity_failing_address"}, + {0x0003f2b0, "cm_stream_switch_slave_south_4_slot0"}, + {0x0003f2b4, "cm_stream_switch_slave_south_4_slot1"}, + {0x0003f2b8, "cm_stream_switch_slave_south_4_slot2"}, + {0x0003f2bc, "cm_stream_switch_slave_south_4_slot3"}, + {0x0003f238, "cm_stream_switch_slave_dma_1_slot2"}, + {0x0003f23c, "cm_stream_switch_slave_dma_1_slot3"}, + {0x0003f230, "cm_stream_switch_slave_dma_1_slot0"}, + {0x0003f234, "cm_stream_switch_slave_dma_1_slot1"}, + {0x0001d034, "mm_dma_bd1_interleaved_state"}, + {0x0001d164, "mm_dma_bd11_addr_b"}, + {0x00034008, "cm_event_generate"}, + {0x0001de18, "mm_dma_mm2s_1_ctrl"}, + {0x0001d178, "mm_dma_bd11_control"}, + {0x00031000, "cm_performance_control0"}, + {0x00031004, "cm_performance_control1"}, + {0x00030470, "cm_mc1"}, + {0x00030460, "cm_mc0"}, + {0x0001d0a8, "mm_dma_bd5_2d_x"}, + {0x0001d0ac, "mm_dma_bd5_2d_y"}, + {0x00034044, "shim_event_broadcast_a_13"}, + {0x00034040, "shim_event_broadcast_a_12"}, + {0x0003403c, "shim_event_broadcast_a_11"}, + {0x00034038, "shim_event_broadcast_a_10"}, + {0x0001e480, "mm_lock9_release_nv"}, + {0x0001de00, "mm_dma_s2mm_0_ctrl"}, + {0x00034048, "shim_event_broadcast_a_14"}, + {0x00012000, "mm_checkbit_error_generation"}, + {0x0001d1f8, "mm_dma_bd15_control"}, + {0x00034404, "cm_combo_event_control"}, + {0x0001e640, "mm_lock12_acquire_nv"}, + {0x00011000, "mm_performance_control0"}, + {0x00011008, "mm_performance_control1"}, + {0x00032018, "cm_debug_control2"}, + {0x00032014, "cm_debug_control1"}, + {0x00032010, "cm_debug_control0"}, + {0x0003f13c, "cm_stream_switch_slave_config_west_2"}, + {0x0003f140, "cm_stream_switch_slave_config_west_3"}, + {0x0003f134, "cm_stream_switch_slave_config_west_0"}, + {0x0003f138, "cm_stream_switch_slave_config_west_1"}, + {0x00014518, "mm_event_group_broadcast_enable"}, + {0x00034070, "shim_event_broadcast_a_block_north_set"}, + {0x0001e600, "mm_lock12_release_nv"}, + {0x00030440, "cm_md0"}, + {0x00030450, "cm_md1"}, + {0x0001e2f0, "mm_lock5_acquire_v1"}, + {0x0003ff04, "shim_stream_switch_event_port_selection_1"}, + {0x0001e1e0, "mm_lock3_acquire_v0"}, + {0x0001d050, "mm_dma_bd2_packet"}, + {0x0001e1f0, "mm_lock3_acquire_v1"}, + {0x0001d0c4, "mm_dma_bd6_addr_b"}, + {0x000340f8, "shim_timer_low"}, + {0x0001e200, "mm_lock4_release_nv"}, + {0x0003f32c, "cm_stream_switch_slave_north_1_slot3"}, + {0x0003f328, "cm_stream_switch_slave_north_1_slot2"}, + {0x0003f324, "cm_stream_switch_slave_north_1_slot1"}, + {0x0003f320, "cm_stream_switch_slave_north_1_slot0"}, + {0x00034088, "shim_event_broadcast_a_block_east_value"}, + {0x00014078, "mm_event_broadcast_block_north_value"}, + {0x00014080, "mm_event_broadcast_block_east_set"}, + {0x00034518, "cm_event_group_stream_switch_enable"}, + {0x0003f300, "cm_stream_switch_slave_west_3_slot0"}, + {0x0003f304, "cm_stream_switch_slave_west_3_slot1"}, + {0x0003f308, "cm_stream_switch_slave_west_3_slot2"}, + {0x0003f30c, "cm_stream_switch_slave_west_3_slot3"}, + {0x0003201c, "cm_debug_status"}, + {0x0001e6a0, "mm_lock13_release_v0"}, + {0x0001d154, "mm_dma_bd10_interleaved_state"}, + {0x000340fc, "cm_timer_high"}, + {0x00032028, "cm_pc_event2"}, + {0x00032024, "cm_pc_event1"}, + {0x00032020, "cm_pc_event0"}, + {0x0003f000, "cm_stream_switch_master_config_aie_core0"}, + {0x0003f004, "cm_stream_switch_master_config_aie_core1"}, + {0x0001e120, "mm_lock2_release_v0"}, + {0x0001e130, "mm_lock2_release_v1"}, + {0x0001d018, "mm_dma_bd0_control"}, + {0x0001d030, "mm_dma_bd1_packet"}, + {0x14, "shim_dma_bd_step_size"}, + {0x0001e740, "mm_lock14_acquire_nv"}, + {0x0001e380, "mm_lock7_release_nv"}, + {0x0003ff00, "shim_stream_switch_event_port_selection_0"}, + {0x0001de1c, "mm_dma_mm2s_1_start_queue"}, + {0x00034060, "shim_event_broadcast_a_block_west_set"}, + {0x00032110, "cm_ecc_scrubbing_event"}, + {0x0001e720, "mm_lock14_release_v0"}, + {0x0001e730, "mm_lock14_release_v1"}, + {0x0003f344, "cm_stream_switch_slave_north_3_slot1"}, + {0x0003f340, "cm_stream_switch_slave_north_3_slot0"}, + {0x0003f34c, "cm_stream_switch_slave_north_3_slot3"}, + {0x0003f2e4, "cm_stream_switch_slave_west_1_slot1"}, + {0x0001e500, "mm_lock10_release_nv"}, + {0x0003f118, "cm_stream_switch_slave_config_fifo_1"}, + {0x0003f114, "cm_stream_switch_slave_config_fifo_0"}, + {0x000340d0, "shim_trace_control0"}, + {0x000340d4, "shim_trace_control1"}, + {0x0001e5e0, "mm_lock11_acquire_v0"}, + {0x0001d1d8, "mm_dma_bd14_control"}, + {0x00036030, "cm_tile_control"}, + {0x00031080, "cm_performance_counter0_event_value"}, + {0x00034074, "cm_event_broadcast_block_north_clr"}, + {0x00032008, "cm_enable_events"}, + {0x00030280, "cm_program_counter"}, + {0x0001d1e0, "mm_dma_bd15_addr_a"}, + {0x0001d1e4, "mm_dma_bd15_addr_b"}, + {0x0001d128, "mm_dma_bd9_2d_x"}, + {0x0001d12c, "mm_dma_bd9_2d_y"}, + {0x000340f8, "cm_timer_low"}, + {0x0003f270, "cm_stream_switch_slave_south_0_slot0"}, + {0x0003f274, "cm_stream_switch_slave_south_0_slot1"}, + {0x0003f278, "cm_stream_switch_slave_south_0_slot2"}, + {0x0003f27c, "cm_stream_switch_slave_south_0_slot3"}, + {0x0001e670, "mm_lock12_acquire_v1"}, + {0x0001e660, "mm_lock12_acquire_v0"}, + {0x00014504, "mm_event_group_watchpoint_enable"}, + {0x0001e570, "mm_lock10_acquire_v1"}, + {0x0003f330, "cm_stream_switch_slave_north_2_slot0"}, + {0x0001d098, "mm_dma_bd4_control"}, + {0x00032004, "cm_core_status"}, + {0x00014f00, "shim_all_lock_state_value"}, + {0x0001d0e8, "mm_dma_bd7_2d_x"}, + {0x0001de08, "mm_dma_s2mm_1_ctrl"}, + {0x0001d0f8, "mm_dma_bd7_control"}, + {0x0001d010, "shim_dma_bd0_packet"}, + {0x0001d1e8, "mm_dma_bd15_2d_x"}, + {0x0001d1ec, "mm_dma_bd15_2d_y"}, + {0x0001de04, "mm_dma_s2mm_0_start_queue"}, + {0x0001e620, "mm_lock12_release_v0"}, + {0x0001e630, "mm_lock12_release_v1"}, + {0x000340fc, "shim_timer_high"}, + {0x00034520, "cm_event_group_user_event_enable"}, + {0x0003f22c, "cm_stream_switch_slave_dma_0_slot3"}, + {0x0003f228, "cm_stream_switch_slave_dma_0_slot2"}, + {0x0003f224, "cm_stream_switch_slave_dma_0_slot1"}, + {0x0003f220, "cm_stream_switch_slave_dma_0_slot0"} + }; + } +}; + +/************************************************************************************* + AIE2 Registers + *************************************************************************************/ +class AIE2UsedRegisters : public UsedRegisters { +public: + AIE2UsedRegisters() { + populateRegNameToValueMap(); + populateRegValueToNameMap(); + } + ~AIE2UsedRegisters() = default; + + void populateProfileRegisters() { + // Core modules + core_addresses.emplace(aie2::cm_performance_control0); + core_addresses.emplace(aie2::cm_performance_control1); + core_addresses.emplace(aie2::cm_performance_control2); + core_addresses.emplace(aie2::cm_performance_counter0); + core_addresses.emplace(aie2::cm_performance_counter1); + core_addresses.emplace(aie2::cm_performance_counter2); + core_addresses.emplace(aie2::cm_performance_counter3); + core_addresses.emplace(aie2::cm_performance_counter0_event_value); + core_addresses.emplace(aie2::cm_performance_counter1_event_value); + core_addresses.emplace(aie2::cm_performance_counter2_event_value); + core_addresses.emplace(aie2::cm_performance_counter3_event_value); + + // Memory modules + memory_addresses.emplace(aie2::mm_performance_control0); + memory_addresses.emplace(aie2::mm_performance_control1); + memory_addresses.emplace(aie2::mm_performance_counter0); + memory_addresses.emplace(aie2::mm_performance_counter1); + memory_addresses.emplace(aie2::mm_performance_counter0_event_value); + memory_addresses.emplace(aie2::mm_performance_counter1_event_value); + + // Interface tiles + interface_addresses.emplace(aie2::shim_performance_control0); + interface_addresses.emplace(aie2::shim_performance_control1); + interface_addresses.emplace(aie2::shim_performance_counter0); + interface_addresses.emplace(aie2::shim_performance_counter1); + interface_addresses.emplace(aie2::shim_performance_counter0_event_value); + interface_addresses.emplace(aie2::shim_performance_counter1_event_value); + + // Memory tiles + memory_tile_addresses.emplace(aie2::mem_performance_control0); + memory_tile_addresses.emplace(aie2::mem_performance_control1); + memory_tile_addresses.emplace(aie2::mem_performance_control2); + memory_tile_addresses.emplace(aie2::mem_performance_counter0); + memory_tile_addresses.emplace(aie2::mem_performance_counter1); + memory_tile_addresses.emplace(aie2::mem_performance_counter2); + memory_tile_addresses.emplace(aie2::mem_performance_counter3); + memory_tile_addresses.emplace(aie2::mem_performance_counter0_event_value); + memory_tile_addresses.emplace(aie2::mem_performance_counter1_event_value); + memory_tile_addresses.emplace(aie2::mem_performance_counter2_event_value); + memory_tile_addresses.emplace(aie2::mem_performance_counter3_event_value); + } + + void populateTraceRegisters() { + // Core modules + core_addresses.emplace(aie2::cm_core_status); + core_addresses.emplace(aie2::cm_trace_control0); + core_addresses.emplace(aie2::cm_trace_control1); + core_addresses.emplace(aie2::cm_trace_status); + core_addresses.emplace(aie2::cm_trace_event0); + core_addresses.emplace(aie2::cm_trace_event1); + core_addresses.emplace(aie2::cm_event_status0); + core_addresses.emplace(aie2::cm_event_status1); + core_addresses.emplace(aie2::cm_event_status2); + core_addresses.emplace(aie2::cm_event_status3); + core_addresses.emplace(aie2::cm_event_broadcast0); + core_addresses.emplace(aie2::cm_event_broadcast1); + core_addresses.emplace(aie2::cm_event_broadcast2); + core_addresses.emplace(aie2::cm_event_broadcast3); + core_addresses.emplace(aie2::cm_event_broadcast4); + core_addresses.emplace(aie2::cm_event_broadcast5); + core_addresses.emplace(aie2::cm_event_broadcast6); + core_addresses.emplace(aie2::cm_event_broadcast7); + core_addresses.emplace(aie2::cm_event_broadcast8); + core_addresses.emplace(aie2::cm_event_broadcast9); + core_addresses.emplace(aie2::cm_event_broadcast10); + core_addresses.emplace(aie2::cm_event_broadcast11); + core_addresses.emplace(aie2::cm_event_broadcast12); + core_addresses.emplace(aie2::cm_event_broadcast13); + core_addresses.emplace(aie2::cm_event_broadcast14); + core_addresses.emplace(aie2::cm_event_broadcast15); + core_addresses.emplace(aie2::cm_timer_trig_event_low_value); + core_addresses.emplace(aie2::cm_timer_trig_event_high_value); + core_addresses.emplace(aie2::cm_timer_low); + core_addresses.emplace(aie2::cm_timer_high); + core_addresses.emplace(aie2::cm_edge_detection_event_control); + core_addresses.emplace(aie2::cm_stream_switch_event_port_selection_0); + core_addresses.emplace(aie2::cm_stream_switch_event_port_selection_1); + + // Memory modules + memory_addresses.emplace(aie2::mm_trace_control0); + memory_addresses.emplace(aie2::mm_trace_control1); + memory_addresses.emplace(aie2::mm_trace_status); + memory_addresses.emplace(aie2::mm_trace_event0); + memory_addresses.emplace(aie2::mm_trace_event1); + memory_addresses.emplace(aie2::mm_event_status0); + memory_addresses.emplace(aie2::mm_event_status1); + memory_addresses.emplace(aie2::mm_event_status2); + memory_addresses.emplace(aie2::mm_event_status3); + memory_addresses.emplace(aie2::mm_event_broadcast0); + memory_addresses.emplace(aie2::mm_event_broadcast1); + memory_addresses.emplace(aie2::mm_event_broadcast2); + memory_addresses.emplace(aie2::mm_event_broadcast3); + memory_addresses.emplace(aie2::mm_event_broadcast4); + memory_addresses.emplace(aie2::mm_event_broadcast5); + memory_addresses.emplace(aie2::mm_event_broadcast6); + memory_addresses.emplace(aie2::mm_event_broadcast7); + memory_addresses.emplace(aie2::mm_event_broadcast8); + memory_addresses.emplace(aie2::mm_event_broadcast9); + memory_addresses.emplace(aie2::mm_event_broadcast10); + memory_addresses.emplace(aie2::mm_event_broadcast11); + memory_addresses.emplace(aie2::mm_event_broadcast12); + memory_addresses.emplace(aie2::mm_event_broadcast13); + memory_addresses.emplace(aie2::mm_event_broadcast14); + memory_addresses.emplace(aie2::mm_event_broadcast15); + + // Interface tiles + interface_addresses.emplace(aie2::shim_trace_control0); + interface_addresses.emplace(aie2::shim_trace_control1); + interface_addresses.emplace(aie2::shim_trace_status); + interface_addresses.emplace(aie2::shim_trace_event0); + interface_addresses.emplace(aie2::shim_trace_event1); + interface_addresses.emplace(aie2::shim_event_broadcast_a_0); + interface_addresses.emplace(aie2::shim_event_broadcast_a_1); + interface_addresses.emplace(aie2::shim_event_broadcast_a_2); + interface_addresses.emplace(aie2::shim_event_broadcast_a_3); + interface_addresses.emplace(aie2::shim_event_broadcast_a_4); + interface_addresses.emplace(aie2::shim_event_broadcast_a_5); + interface_addresses.emplace(aie2::shim_event_broadcast_a_6); + interface_addresses.emplace(aie2::shim_event_broadcast_a_7); + interface_addresses.emplace(aie2::shim_event_broadcast_a_8); + interface_addresses.emplace(aie2::shim_event_broadcast_a_9); + interface_addresses.emplace(aie2::shim_event_broadcast_a_10); + interface_addresses.emplace(aie2::shim_event_broadcast_a_11); + interface_addresses.emplace(aie2::shim_event_broadcast_a_12); + interface_addresses.emplace(aie2::shim_event_broadcast_a_13); + interface_addresses.emplace(aie2::shim_event_broadcast_a_14); + interface_addresses.emplace(aie2::shim_event_broadcast_a_15); + interface_addresses.emplace(aie2::shim_event_status0); + interface_addresses.emplace(aie2::shim_event_status1); + interface_addresses.emplace(aie2::shim_event_status2); + interface_addresses.emplace(aie2::shim_event_status3); + interface_addresses.emplace(aie2::shim_stream_switch_event_port_selection_0); + interface_addresses.emplace(aie2::shim_stream_switch_event_port_selection_1); + + // Memory tiles + memory_tile_addresses.emplace(aie2::mem_trace_control0); + memory_tile_addresses.emplace(aie2::mem_trace_control1); + memory_tile_addresses.emplace(aie2::mem_trace_status); + memory_tile_addresses.emplace(aie2::mem_trace_event0); + memory_tile_addresses.emplace(aie2::mem_trace_event1); + memory_tile_addresses.emplace(aie2::mem_dma_event_channel_selection); + memory_tile_addresses.emplace(aie2::mem_edge_detection_event_control); + memory_tile_addresses.emplace(aie2::mem_stream_switch_event_port_selection_0); + memory_tile_addresses.emplace(aie2::mem_stream_switch_event_port_selection_1); + memory_tile_addresses.emplace(aie2::mem_event_broadcast0); + memory_tile_addresses.emplace(aie2::mem_event_status0); + memory_tile_addresses.emplace(aie2::mem_event_status1); + memory_tile_addresses.emplace(aie2::mem_event_status2); + memory_tile_addresses.emplace(aie2::mem_event_status3); + memory_tile_addresses.emplace(aie2::mem_event_status4); + memory_tile_addresses.emplace(aie2::mem_event_status5); + } + + void populateRegNameToValueMap() { + regNameToValues = { + {"cm_program_counter", aie2::cm_program_counter}, + {"cm_performance_control0", aie2::cm_performance_control0}, + {"cm_performance_control1", aie2::cm_performance_control1}, + {"cm_performance_control2", aie2::cm_performance_control2}, + {"cm_performance_counter0", aie2::cm_performance_counter0}, + {"cm_performance_counter1", aie2::cm_performance_counter1}, + {"cm_performance_counter2", aie2::cm_performance_counter2}, + {"cm_performance_counter3", aie2::cm_performance_counter3}, + {"cm_performance_counter0_event_value", aie2::cm_performance_counter0_event_value}, + {"cm_performance_counter1_event_value", aie2::cm_performance_counter1_event_value}, + {"cm_performance_counter2_event_value", aie2::cm_performance_counter2_event_value}, + {"cm_performance_counter3_event_value", aie2::cm_performance_counter3_event_value}, + {"cm_core_control", aie2::cm_core_control}, + {"cm_core_status", aie2::cm_core_status}, + {"cm_enable_events", aie2::cm_enable_events}, + {"cm_reset_event", aie2::cm_reset_event}, + {"cm_debug_control0", aie2::cm_debug_control0}, + {"cm_debug_control1", aie2::cm_debug_control1}, + {"cm_debug_control2", aie2::cm_debug_control2}, + {"cm_debug_status", aie2::cm_debug_status}, + {"cm_pc_event0", aie2::cm_pc_event0}, + {"cm_pc_event1", aie2::cm_pc_event1}, + {"cm_pc_event2", aie2::cm_pc_event2}, + {"cm_pc_event3", aie2::cm_pc_event3}, + {"cm_error_halt_control", aie2::cm_error_halt_control}, + {"cm_error_halt_event", aie2::cm_error_halt_event}, + {"cm_core_processor_bus", aie2::cm_core_processor_bus}, + {"cm_ecc_scrubbing_event", aie2::cm_ecc_scrubbing_event}, + {"cm_timer_control", aie2::cm_timer_control}, + {"cm_event_generate", aie2::cm_event_generate}, + {"cm_event_broadcast0", aie2::cm_event_broadcast0}, + {"cm_event_broadcast1", aie2::cm_event_broadcast1}, + {"cm_event_broadcast2", aie2::cm_event_broadcast2}, + {"cm_event_broadcast3", aie2::cm_event_broadcast3}, + {"cm_event_broadcast4", aie2::cm_event_broadcast4}, + {"cm_event_broadcast5", aie2::cm_event_broadcast5}, + {"cm_event_broadcast6", aie2::cm_event_broadcast6}, + {"cm_event_broadcast7", aie2::cm_event_broadcast7}, + {"cm_event_broadcast8", aie2::cm_event_broadcast8}, + {"cm_event_broadcast9", aie2::cm_event_broadcast9}, + {"cm_event_broadcast10", aie2::cm_event_broadcast10}, + {"cm_event_broadcast11", aie2::cm_event_broadcast11}, + {"cm_event_broadcast12", aie2::cm_event_broadcast12}, + {"cm_event_broadcast13", aie2::cm_event_broadcast13}, + {"cm_event_broadcast14", aie2::cm_event_broadcast14}, + {"cm_event_broadcast15", aie2::cm_event_broadcast15}, + {"cm_event_broadcast_block_south_set", aie2::cm_event_broadcast_block_south_set}, + {"cm_event_broadcast_block_south_clr", aie2::cm_event_broadcast_block_south_clr}, + {"cm_event_broadcast_block_south_value", aie2::cm_event_broadcast_block_south_value}, + {"cm_event_broadcast_block_west_set", aie2::cm_event_broadcast_block_west_set}, + {"cm_event_broadcast_block_west_clr", aie2::cm_event_broadcast_block_west_clr}, + {"cm_event_broadcast_block_west_value", aie2::cm_event_broadcast_block_west_value}, + {"cm_event_broadcast_block_north_set", aie2::cm_event_broadcast_block_north_set}, + {"cm_event_broadcast_block_north_clr", aie2::cm_event_broadcast_block_north_clr}, + {"cm_event_broadcast_block_north_value", aie2::cm_event_broadcast_block_north_value}, + {"cm_event_broadcast_block_east_set", aie2::cm_event_broadcast_block_east_set}, + {"cm_event_broadcast_block_east_clr", aie2::cm_event_broadcast_block_east_clr}, + {"cm_event_broadcast_block_east_value", aie2::cm_event_broadcast_block_east_value}, + {"cm_trace_control0", aie2::cm_trace_control0}, + {"cm_trace_control1", aie2::cm_trace_control1}, + {"cm_trace_status", aie2::cm_trace_status}, + {"cm_trace_event0", aie2::cm_trace_event0}, + {"cm_trace_event1", aie2::cm_trace_event1}, + {"cm_timer_trig_event_low_value", aie2::cm_timer_trig_event_low_value}, + {"cm_timer_trig_event_high_value", aie2::cm_timer_trig_event_high_value}, + {"cm_timer_low", aie2::cm_timer_low}, + {"cm_timer_high", aie2::cm_timer_high}, + {"cm_event_status0", aie2::cm_event_status0}, + {"cm_event_status1", aie2::cm_event_status1}, + {"cm_event_status2", aie2::cm_event_status2}, + {"cm_event_status3", aie2::cm_event_status3}, + {"cm_combo_event_inputs", aie2::cm_combo_event_inputs}, + {"cm_combo_event_control", aie2::cm_combo_event_control}, + {"cm_edge_detection_event_control", aie2::cm_edge_detection_event_control}, + {"cm_event_group_0_enable", aie2::cm_event_group_0_enable}, + {"cm_event_group_pc_enable", aie2::cm_event_group_pc_enable}, + {"cm_event_group_core_stall_enable", aie2::cm_event_group_core_stall_enable}, + {"cm_event_group_core_program_flow_enable", aie2::cm_event_group_core_program_flow_enable}, + {"cm_event_group_errors0_enable", aie2::cm_event_group_errors0_enable}, + {"cm_event_group_errors1_enable", aie2::cm_event_group_errors1_enable}, + {"cm_event_group_stream_switch_enable", aie2::cm_event_group_stream_switch_enable}, + {"cm_event_group_broadcast_enable", aie2::cm_event_group_broadcast_enable}, + {"cm_event_group_user_event_enable", aie2::cm_event_group_user_event_enable}, + {"cm_tile_control", aie2::cm_tile_control}, + {"cm_accumulator_control", aie2::cm_accumulator_control}, + {"cm_memory_control", aie2::cm_memory_control}, + {"cm_stream_switch_master_config_aie_core0", aie2::cm_stream_switch_master_config_aie_core0}, + {"cm_stream_switch_master_config_dma0", aie2::cm_stream_switch_master_config_dma0}, + {"cm_stream_switch_master_config_dma1", aie2::cm_stream_switch_master_config_dma1}, + {"cm_stream_switch_master_config_tile_ctrl", aie2::cm_stream_switch_master_config_tile_ctrl}, + {"cm_stream_switch_master_config_fifo0", aie2::cm_stream_switch_master_config_fifo0}, + {"cm_stream_switch_master_config_south0", aie2::cm_stream_switch_master_config_south0}, + {"cm_stream_switch_master_config_south1", aie2::cm_stream_switch_master_config_south1}, + {"cm_stream_switch_master_config_south2", aie2::cm_stream_switch_master_config_south2}, + {"cm_stream_switch_master_config_south3", aie2::cm_stream_switch_master_config_south3}, + {"cm_stream_switch_master_config_west0", aie2::cm_stream_switch_master_config_west0}, + {"cm_stream_switch_master_config_west1", aie2::cm_stream_switch_master_config_west1}, + {"cm_stream_switch_master_config_west2", aie2::cm_stream_switch_master_config_west2}, + {"cm_stream_switch_master_config_west3", aie2::cm_stream_switch_master_config_west3}, + {"cm_stream_switch_master_config_north0", aie2::cm_stream_switch_master_config_north0}, + {"cm_stream_switch_master_config_north1", aie2::cm_stream_switch_master_config_north1}, + {"cm_stream_switch_master_config_north2", aie2::cm_stream_switch_master_config_north2}, + {"cm_stream_switch_master_config_north3", aie2::cm_stream_switch_master_config_north3}, + {"cm_stream_switch_master_config_north4", aie2::cm_stream_switch_master_config_north4}, + {"cm_stream_switch_master_config_north5", aie2::cm_stream_switch_master_config_north5}, + {"cm_stream_switch_master_config_east0", aie2::cm_stream_switch_master_config_east0}, + {"cm_stream_switch_master_config_east1", aie2::cm_stream_switch_master_config_east1}, + {"cm_stream_switch_master_config_east2", aie2::cm_stream_switch_master_config_east2}, + {"cm_stream_switch_master_config_east3", aie2::cm_stream_switch_master_config_east3}, + {"cm_stream_switch_slave_config_aie_core0", aie2::cm_stream_switch_slave_config_aie_core0}, + {"cm_stream_switch_slave_config_dma_0", aie2::cm_stream_switch_slave_config_dma_0}, + {"cm_stream_switch_slave_config_dma_1", aie2::cm_stream_switch_slave_config_dma_1}, + {"cm_stream_switch_slave_config_tile_ctrl", aie2::cm_stream_switch_slave_config_tile_ctrl}, + {"cm_stream_switch_slave_config_fifo_0", aie2::cm_stream_switch_slave_config_fifo_0}, + {"cm_stream_switch_slave_config_south_0", aie2::cm_stream_switch_slave_config_south_0}, + {"cm_stream_switch_slave_config_south_1", aie2::cm_stream_switch_slave_config_south_1}, + {"cm_stream_switch_slave_config_south_2", aie2::cm_stream_switch_slave_config_south_2}, + {"cm_stream_switch_slave_config_south_3", aie2::cm_stream_switch_slave_config_south_3}, + {"cm_stream_switch_slave_config_south_4", aie2::cm_stream_switch_slave_config_south_4}, + {"cm_stream_switch_slave_config_south_5", aie2::cm_stream_switch_slave_config_south_5}, + {"cm_stream_switch_slave_config_west_0", aie2::cm_stream_switch_slave_config_west_0}, + {"cm_stream_switch_slave_config_west_1", aie2::cm_stream_switch_slave_config_west_1}, + {"cm_stream_switch_slave_config_west_2", aie2::cm_stream_switch_slave_config_west_2}, + {"cm_stream_switch_slave_config_west_3", aie2::cm_stream_switch_slave_config_west_3}, + {"cm_stream_switch_slave_config_north_0", aie2::cm_stream_switch_slave_config_north_0}, + {"cm_stream_switch_slave_config_north_1", aie2::cm_stream_switch_slave_config_north_1}, + {"cm_stream_switch_slave_config_north_2", aie2::cm_stream_switch_slave_config_north_2}, + {"cm_stream_switch_slave_config_north_3", aie2::cm_stream_switch_slave_config_north_3}, + {"cm_stream_switch_slave_config_east_0", aie2::cm_stream_switch_slave_config_east_0}, + {"cm_stream_switch_slave_config_east_1", aie2::cm_stream_switch_slave_config_east_1}, + {"cm_stream_switch_slave_config_east_2", aie2::cm_stream_switch_slave_config_east_2}, + {"cm_stream_switch_slave_config_east_3", aie2::cm_stream_switch_slave_config_east_3}, + {"cm_stream_switch_slave_config_aie_trace", aie2::cm_stream_switch_slave_config_aie_trace}, + {"cm_stream_switch_slave_config_mem_trace", aie2::cm_stream_switch_slave_config_mem_trace}, + {"cm_stream_switch_slave_aie_core0_slot0", aie2::cm_stream_switch_slave_aie_core0_slot0}, + {"cm_stream_switch_slave_aie_core0_slot1", aie2::cm_stream_switch_slave_aie_core0_slot1}, + {"cm_stream_switch_slave_aie_core0_slot2", aie2::cm_stream_switch_slave_aie_core0_slot2}, + {"cm_stream_switch_slave_aie_core0_slot3", aie2::cm_stream_switch_slave_aie_core0_slot3}, + {"cm_stream_switch_slave_dma_0_slot0", aie2::cm_stream_switch_slave_dma_0_slot0}, + {"cm_stream_switch_slave_dma_0_slot1", aie2::cm_stream_switch_slave_dma_0_slot1}, + {"cm_stream_switch_slave_dma_0_slot2", aie2::cm_stream_switch_slave_dma_0_slot2}, + {"cm_stream_switch_slave_dma_0_slot3", aie2::cm_stream_switch_slave_dma_0_slot3}, + {"cm_stream_switch_slave_dma_1_slot0", aie2::cm_stream_switch_slave_dma_1_slot0}, + {"cm_stream_switch_slave_dma_1_slot1", aie2::cm_stream_switch_slave_dma_1_slot1}, + {"cm_stream_switch_slave_dma_1_slot2", aie2::cm_stream_switch_slave_dma_1_slot2}, + {"cm_stream_switch_slave_dma_1_slot3", aie2::cm_stream_switch_slave_dma_1_slot3}, + {"cm_stream_switch_slave_tile_ctrl_slot0", aie2::cm_stream_switch_slave_tile_ctrl_slot0}, + {"cm_stream_switch_slave_tile_ctrl_slot1", aie2::cm_stream_switch_slave_tile_ctrl_slot1}, + {"cm_stream_switch_slave_tile_ctrl_slot2", aie2::cm_stream_switch_slave_tile_ctrl_slot2}, + {"cm_stream_switch_slave_tile_ctrl_slot3", aie2::cm_stream_switch_slave_tile_ctrl_slot3}, + {"cm_stream_switch_slave_fifo_0_slot0", aie2::cm_stream_switch_slave_fifo_0_slot0}, + {"cm_stream_switch_slave_fifo_0_slot1", aie2::cm_stream_switch_slave_fifo_0_slot1}, + {"cm_stream_switch_slave_fifo_0_slot2", aie2::cm_stream_switch_slave_fifo_0_slot2}, + {"cm_stream_switch_slave_fifo_0_slot3", aie2::cm_stream_switch_slave_fifo_0_slot3}, + {"cm_stream_switch_slave_south_0_slot0", aie2::cm_stream_switch_slave_south_0_slot0}, + {"cm_stream_switch_slave_south_0_slot1", aie2::cm_stream_switch_slave_south_0_slot1}, + {"cm_stream_switch_slave_south_0_slot2", aie2::cm_stream_switch_slave_south_0_slot2}, + {"cm_stream_switch_slave_south_0_slot3", aie2::cm_stream_switch_slave_south_0_slot3}, + {"cm_stream_switch_slave_south_1_slot0", aie2::cm_stream_switch_slave_south_1_slot0}, + {"cm_stream_switch_slave_south_1_slot1", aie2::cm_stream_switch_slave_south_1_slot1}, + {"cm_stream_switch_slave_south_1_slot2", aie2::cm_stream_switch_slave_south_1_slot2}, + {"cm_stream_switch_slave_south_1_slot3", aie2::cm_stream_switch_slave_south_1_slot3}, + {"cm_stream_switch_slave_south_2_slot0", aie2::cm_stream_switch_slave_south_2_slot0}, + {"cm_stream_switch_slave_south_2_slot1", aie2::cm_stream_switch_slave_south_2_slot1}, + {"cm_stream_switch_slave_south_2_slot2", aie2::cm_stream_switch_slave_south_2_slot2}, + {"cm_stream_switch_slave_south_2_slot3", aie2::cm_stream_switch_slave_south_2_slot3}, + {"cm_stream_switch_slave_south_3_slot0", aie2::cm_stream_switch_slave_south_3_slot0}, + {"cm_stream_switch_slave_south_3_slot1", aie2::cm_stream_switch_slave_south_3_slot1}, + {"cm_stream_switch_slave_south_3_slot2", aie2::cm_stream_switch_slave_south_3_slot2}, + {"cm_stream_switch_slave_south_3_slot3", aie2::cm_stream_switch_slave_south_3_slot3}, + {"cm_stream_switch_slave_south_4_slot0", aie2::cm_stream_switch_slave_south_4_slot0}, + {"cm_stream_switch_slave_south_4_slot1", aie2::cm_stream_switch_slave_south_4_slot1}, + {"cm_stream_switch_slave_south_4_slot2", aie2::cm_stream_switch_slave_south_4_slot2}, + {"cm_stream_switch_slave_south_4_slot3", aie2::cm_stream_switch_slave_south_4_slot3}, + {"cm_stream_switch_slave_south_5_slot0", aie2::cm_stream_switch_slave_south_5_slot0}, + {"cm_stream_switch_slave_south_5_slot1", aie2::cm_stream_switch_slave_south_5_slot1}, + {"cm_stream_switch_slave_south_5_slot2", aie2::cm_stream_switch_slave_south_5_slot2}, + {"cm_stream_switch_slave_south_5_slot3", aie2::cm_stream_switch_slave_south_5_slot3}, + {"cm_stream_switch_slave_west_0_slot0", aie2::cm_stream_switch_slave_west_0_slot0}, + {"cm_stream_switch_slave_west_0_slot1", aie2::cm_stream_switch_slave_west_0_slot1}, + {"cm_stream_switch_slave_west_0_slot2", aie2::cm_stream_switch_slave_west_0_slot2}, + {"cm_stream_switch_slave_west_0_slot3", aie2::cm_stream_switch_slave_west_0_slot3}, + {"cm_stream_switch_slave_west_1_slot0", aie2::cm_stream_switch_slave_west_1_slot0}, + {"cm_stream_switch_slave_west_1_slot1", aie2::cm_stream_switch_slave_west_1_slot1}, + {"cm_stream_switch_slave_west_1_slot2", aie2::cm_stream_switch_slave_west_1_slot2}, + {"cm_stream_switch_slave_west_1_slot3", aie2::cm_stream_switch_slave_west_1_slot3}, + {"cm_stream_switch_slave_west_2_slot0", aie2::cm_stream_switch_slave_west_2_slot0}, + {"cm_stream_switch_slave_west_2_slot1", aie2::cm_stream_switch_slave_west_2_slot1}, + {"cm_stream_switch_slave_west_2_slot2", aie2::cm_stream_switch_slave_west_2_slot2}, + {"cm_stream_switch_slave_west_2_slot3", aie2::cm_stream_switch_slave_west_2_slot3}, + {"cm_stream_switch_slave_west_3_slot0", aie2::cm_stream_switch_slave_west_3_slot0}, + {"cm_stream_switch_slave_west_3_slot1", aie2::cm_stream_switch_slave_west_3_slot1}, + {"cm_stream_switch_slave_west_3_slot2", aie2::cm_stream_switch_slave_west_3_slot2}, + {"cm_stream_switch_slave_west_3_slot3", aie2::cm_stream_switch_slave_west_3_slot3}, + {"cm_stream_switch_slave_north_0_slot0", aie2::cm_stream_switch_slave_north_0_slot0}, + {"cm_stream_switch_slave_north_0_slot1", aie2::cm_stream_switch_slave_north_0_slot1}, + {"cm_stream_switch_slave_north_0_slot2", aie2::cm_stream_switch_slave_north_0_slot2}, + {"cm_stream_switch_slave_north_0_slot3", aie2::cm_stream_switch_slave_north_0_slot3}, + {"cm_stream_switch_slave_north_1_slot0", aie2::cm_stream_switch_slave_north_1_slot0}, + {"cm_stream_switch_slave_north_1_slot1", aie2::cm_stream_switch_slave_north_1_slot1}, + {"cm_stream_switch_slave_north_1_slot2", aie2::cm_stream_switch_slave_north_1_slot2}, + {"cm_stream_switch_slave_north_1_slot3", aie2::cm_stream_switch_slave_north_1_slot3}, + {"cm_stream_switch_slave_north_2_slot0", aie2::cm_stream_switch_slave_north_2_slot0}, + {"cm_stream_switch_slave_north_2_slot1", aie2::cm_stream_switch_slave_north_2_slot1}, + {"cm_stream_switch_slave_north_2_slot2", aie2::cm_stream_switch_slave_north_2_slot2}, + {"cm_stream_switch_slave_north_2_slot3", aie2::cm_stream_switch_slave_north_2_slot3}, + {"cm_stream_switch_slave_north_3_slot0", aie2::cm_stream_switch_slave_north_3_slot0}, + {"cm_stream_switch_slave_north_3_slot1", aie2::cm_stream_switch_slave_north_3_slot1}, + {"cm_stream_switch_slave_north_3_slot2", aie2::cm_stream_switch_slave_north_3_slot2}, + {"cm_stream_switch_slave_north_3_slot3", aie2::cm_stream_switch_slave_north_3_slot3}, + {"cm_stream_switch_slave_east_0_slot0", aie2::cm_stream_switch_slave_east_0_slot0}, + {"cm_stream_switch_slave_east_0_slot1", aie2::cm_stream_switch_slave_east_0_slot1}, + {"cm_stream_switch_slave_east_0_slot2", aie2::cm_stream_switch_slave_east_0_slot2}, + {"cm_stream_switch_slave_east_0_slot3", aie2::cm_stream_switch_slave_east_0_slot3}, + {"cm_stream_switch_slave_east_1_slot0", aie2::cm_stream_switch_slave_east_1_slot0}, + {"cm_stream_switch_slave_east_1_slot1", aie2::cm_stream_switch_slave_east_1_slot1}, + {"cm_stream_switch_slave_east_1_slot2", aie2::cm_stream_switch_slave_east_1_slot2}, + {"cm_stream_switch_slave_east_1_slot3", aie2::cm_stream_switch_slave_east_1_slot3}, + {"cm_stream_switch_slave_east_2_slot0", aie2::cm_stream_switch_slave_east_2_slot0}, + {"cm_stream_switch_slave_east_2_slot1", aie2::cm_stream_switch_slave_east_2_slot1}, + {"cm_stream_switch_slave_east_2_slot2", aie2::cm_stream_switch_slave_east_2_slot2}, + {"cm_stream_switch_slave_east_2_slot3", aie2::cm_stream_switch_slave_east_2_slot3}, + {"cm_stream_switch_slave_east_3_slot0", aie2::cm_stream_switch_slave_east_3_slot0}, + {"cm_stream_switch_slave_east_3_slot1", aie2::cm_stream_switch_slave_east_3_slot1}, + {"cm_stream_switch_slave_east_3_slot2", aie2::cm_stream_switch_slave_east_3_slot2}, + {"cm_stream_switch_slave_east_3_slot3", aie2::cm_stream_switch_slave_east_3_slot3}, + {"cm_stream_switch_slave_aie_trace_slot0", aie2::cm_stream_switch_slave_aie_trace_slot0}, + {"cm_stream_switch_slave_aie_trace_slot1", aie2::cm_stream_switch_slave_aie_trace_slot1}, + {"cm_stream_switch_slave_aie_trace_slot2", aie2::cm_stream_switch_slave_aie_trace_slot2}, + {"cm_stream_switch_slave_aie_trace_slot3", aie2::cm_stream_switch_slave_aie_trace_slot3}, + {"cm_stream_switch_slave_mem_trace_slot0", aie2::cm_stream_switch_slave_mem_trace_slot0}, + {"cm_stream_switch_slave_mem_trace_slot1", aie2::cm_stream_switch_slave_mem_trace_slot1}, + {"cm_stream_switch_slave_mem_trace_slot2", aie2::cm_stream_switch_slave_mem_trace_slot2}, + {"cm_stream_switch_slave_mem_trace_slot3", aie2::cm_stream_switch_slave_mem_trace_slot3}, + {"cm_stream_switch_deterministic_merge_arb0_slave0_1", aie2::cm_stream_switch_deterministic_merge_arb0_slave0_1}, + {"cm_stream_switch_deterministic_merge_arb0_slave2_3", aie2::cm_stream_switch_deterministic_merge_arb0_slave2_3}, + {"cm_stream_switch_deterministic_merge_arb0_ctrl", aie2::cm_stream_switch_deterministic_merge_arb0_ctrl}, + {"cm_stream_switch_deterministic_merge_arb1_slave0_1", aie2::cm_stream_switch_deterministic_merge_arb1_slave0_1}, + {"cm_stream_switch_deterministic_merge_arb1_slave2_3", aie2::cm_stream_switch_deterministic_merge_arb1_slave2_3}, + {"cm_stream_switch_deterministic_merge_arb1_ctrl", aie2::cm_stream_switch_deterministic_merge_arb1_ctrl}, + {"cm_stream_switch_event_port_selection_0", aie2::cm_stream_switch_event_port_selection_0}, + {"cm_stream_switch_event_port_selection_1", aie2::cm_stream_switch_event_port_selection_1}, + {"cm_stream_switch_parity_status", aie2::cm_stream_switch_parity_status}, + {"cm_stream_switch_parity_injection", aie2::cm_stream_switch_parity_injection}, + {"cm_tile_control_packet_handler_status", aie2::cm_tile_control_packet_handler_status}, + {"cm_stream_switch_adaptive_clock_gate_status", aie2::cm_stream_switch_adaptive_clock_gate_status}, + {"cm_stream_switch_adaptive_clock_gate_abort_period", aie2::cm_stream_switch_adaptive_clock_gate_abort_period}, + {"cm_module_clock_control", aie2::cm_module_clock_control}, + {"cm_module_reset_control", aie2::cm_module_reset_control}, + {"mm_performance_control0", aie2::mm_performance_control0}, + {"mm_performance_control1", aie2::mm_performance_control1}, + {"mm_performance_counter0", aie2::mm_performance_counter0}, + {"mm_performance_counter1", aie2::mm_performance_counter1}, + {"mm_performance_counter0_event_value", aie2::mm_performance_counter0_event_value}, + {"mm_performance_counter1_event_value", aie2::mm_performance_counter1_event_value}, + {"mm_checkbit_error_generation", aie2::mm_checkbit_error_generation}, + {"mm_ecc_scrubbing_event", aie2::mm_ecc_scrubbing_event}, + {"mm_ecc_failing_address", aie2::mm_ecc_failing_address}, + {"mm_parity_failing_address", aie2::mm_parity_failing_address}, + {"mm_timer_control", aie2::mm_timer_control}, + {"mm_event_generate", aie2::mm_event_generate}, + {"mm_event_broadcast0", aie2::mm_event_broadcast0}, + {"mm_event_broadcast1", aie2::mm_event_broadcast1}, + {"mm_event_broadcast2", aie2::mm_event_broadcast2}, + {"mm_event_broadcast3", aie2::mm_event_broadcast3}, + {"mm_event_broadcast4", aie2::mm_event_broadcast4}, + {"mm_event_broadcast5", aie2::mm_event_broadcast5}, + {"mm_event_broadcast6", aie2::mm_event_broadcast6}, + {"mm_event_broadcast7", aie2::mm_event_broadcast7}, + {"mm_event_broadcast8", aie2::mm_event_broadcast8}, + {"mm_event_broadcast9", aie2::mm_event_broadcast9}, + {"mm_event_broadcast10", aie2::mm_event_broadcast10}, + {"mm_event_broadcast11", aie2::mm_event_broadcast11}, + {"mm_event_broadcast12", aie2::mm_event_broadcast12}, + {"mm_event_broadcast13", aie2::mm_event_broadcast13}, + {"mm_event_broadcast14", aie2::mm_event_broadcast14}, + {"mm_event_broadcast15", aie2::mm_event_broadcast15}, + {"mm_event_broadcast_block_south_set", aie2::mm_event_broadcast_block_south_set}, + {"mm_event_broadcast_block_south_clr", aie2::mm_event_broadcast_block_south_clr}, + {"mm_event_broadcast_block_south_value", aie2::mm_event_broadcast_block_south_value}, + {"mm_event_broadcast_block_west_set", aie2::mm_event_broadcast_block_west_set}, + {"mm_event_broadcast_block_west_clr", aie2::mm_event_broadcast_block_west_clr}, + {"mm_event_broadcast_block_west_value", aie2::mm_event_broadcast_block_west_value}, + {"mm_event_broadcast_block_north_set", aie2::mm_event_broadcast_block_north_set}, + {"mm_event_broadcast_block_north_clr", aie2::mm_event_broadcast_block_north_clr}, + {"mm_event_broadcast_block_north_value", aie2::mm_event_broadcast_block_north_value}, + {"mm_event_broadcast_block_east_set", aie2::mm_event_broadcast_block_east_set}, + {"mm_event_broadcast_block_east_clr", aie2::mm_event_broadcast_block_east_clr}, + {"mm_event_broadcast_block_east_value", aie2::mm_event_broadcast_block_east_value}, + {"mm_trace_control0", aie2::mm_trace_control0}, + {"mm_trace_control1", aie2::mm_trace_control1}, + {"mm_trace_status", aie2::mm_trace_status}, + {"mm_trace_event0", aie2::mm_trace_event0}, + {"mm_trace_event1", aie2::mm_trace_event1}, + {"mm_timer_trig_event_low_value", aie2::mm_timer_trig_event_low_value}, + {"mm_timer_trig_event_high_value", aie2::mm_timer_trig_event_high_value}, + {"mm_timer_low", aie2::mm_timer_low}, + {"mm_timer_high", aie2::mm_timer_high}, + {"mm_watchpoint0", aie2::mm_watchpoint0}, + {"mm_watchpoint1", aie2::mm_watchpoint1}, + {"mm_event_status0", aie2::mm_event_status0}, + {"mm_event_status1", aie2::mm_event_status1}, + {"mm_event_status2", aie2::mm_event_status2}, + {"mm_event_status3", aie2::mm_event_status3}, + {"mm_reserved0", aie2::mm_reserved0}, + {"mm_reserved1", aie2::mm_reserved1}, + {"mm_reserved2", aie2::mm_reserved2}, + {"mm_reserved3", aie2::mm_reserved3}, + {"mm_combo_event_inputs", aie2::mm_combo_event_inputs}, + {"mm_combo_event_control", aie2::mm_combo_event_control}, + {"mm_edge_detection_event_control", aie2::mm_edge_detection_event_control}, + {"mm_event_group_0_enable", aie2::mm_event_group_0_enable}, + {"mm_event_group_watchpoint_enable", aie2::mm_event_group_watchpoint_enable}, + {"mm_event_group_dma_enable", aie2::mm_event_group_dma_enable}, + {"mm_event_group_lock_enable", aie2::mm_event_group_lock_enable}, + {"mm_event_group_memory_conflict_enable", aie2::mm_event_group_memory_conflict_enable}, + {"mm_event_group_error_enable", aie2::mm_event_group_error_enable}, + {"mm_event_group_broadcast_enable", aie2::mm_event_group_broadcast_enable}, + {"mm_event_group_user_event_enable", aie2::mm_event_group_user_event_enable}, + {"mm_spare_reg", aie2::mm_spare_reg}, + {"mm_memory_control", aie2::mm_memory_control}, + {"mm_dma_bd0_0", aie2::mm_dma_bd0_0}, + {"mm_dma_bd0_1", aie2::mm_dma_bd0_1}, + {"mm_dma_bd0_2", aie2::mm_dma_bd0_2}, + {"mm_dma_bd0_3", aie2::mm_dma_bd0_3}, + {"mm_dma_bd0_4", aie2::mm_dma_bd0_4}, + {"mm_dma_bd0_5", aie2::mm_dma_bd0_5}, + {"mm_dma_bd1_0", aie2::mm_dma_bd1_0}, + {"mm_dma_bd1_1", aie2::mm_dma_bd1_1}, + {"mm_dma_bd1_2", aie2::mm_dma_bd1_2}, + {"mm_dma_bd1_3", aie2::mm_dma_bd1_3}, + {"mm_dma_bd1_4", aie2::mm_dma_bd1_4}, + {"mm_dma_bd1_5", aie2::mm_dma_bd1_5}, + {"mm_dma_bd2_0", aie2::mm_dma_bd2_0}, + {"mm_dma_bd2_1", aie2::mm_dma_bd2_1}, + {"mm_dma_bd2_2", aie2::mm_dma_bd2_2}, + {"mm_dma_bd2_3", aie2::mm_dma_bd2_3}, + {"mm_dma_bd2_4", aie2::mm_dma_bd2_4}, + {"mm_dma_bd2_5", aie2::mm_dma_bd2_5}, + {"mm_dma_bd3_0", aie2::mm_dma_bd3_0}, + {"mm_dma_bd3_1", aie2::mm_dma_bd3_1}, + {"mm_dma_bd3_2", aie2::mm_dma_bd3_2}, + {"mm_dma_bd3_3", aie2::mm_dma_bd3_3}, + {"mm_dma_bd3_4", aie2::mm_dma_bd3_4}, + {"mm_dma_bd3_5", aie2::mm_dma_bd3_5}, + {"mm_dma_bd4_0", aie2::mm_dma_bd4_0}, + {"mm_dma_bd4_1", aie2::mm_dma_bd4_1}, + {"mm_dma_bd4_2", aie2::mm_dma_bd4_2}, + {"mm_dma_bd4_3", aie2::mm_dma_bd4_3}, + {"mm_dma_bd4_4", aie2::mm_dma_bd4_4}, + {"mm_dma_bd4_5", aie2::mm_dma_bd4_5}, + {"mm_dma_bd5_0", aie2::mm_dma_bd5_0}, + {"mm_dma_bd5_1", aie2::mm_dma_bd5_1}, + {"mm_dma_bd5_2", aie2::mm_dma_bd5_2}, + {"mm_dma_bd5_3", aie2::mm_dma_bd5_3}, + {"mm_dma_bd5_4", aie2::mm_dma_bd5_4}, + {"mm_dma_bd5_5", aie2::mm_dma_bd5_5}, + {"mm_dma_bd6_0", aie2::mm_dma_bd6_0}, + {"mm_dma_bd6_1", aie2::mm_dma_bd6_1}, + {"mm_dma_bd6_2", aie2::mm_dma_bd6_2}, + {"mm_dma_bd6_3", aie2::mm_dma_bd6_3}, + {"mm_dma_bd6_4", aie2::mm_dma_bd6_4}, + {"mm_dma_bd6_5", aie2::mm_dma_bd6_5}, + {"mm_dma_bd7_0", aie2::mm_dma_bd7_0}, + {"mm_dma_bd7_1", aie2::mm_dma_bd7_1}, + {"mm_dma_bd7_2", aie2::mm_dma_bd7_2}, + {"mm_dma_bd7_3", aie2::mm_dma_bd7_3}, + {"mm_dma_bd7_4", aie2::mm_dma_bd7_4}, + {"mm_dma_bd7_5", aie2::mm_dma_bd7_5}, + {"mm_dma_bd8_0", aie2::mm_dma_bd8_0}, + {"mm_dma_bd8_1", aie2::mm_dma_bd8_1}, + {"mm_dma_bd8_2", aie2::mm_dma_bd8_2}, + {"mm_dma_bd8_3", aie2::mm_dma_bd8_3}, + {"mm_dma_bd8_4", aie2::mm_dma_bd8_4}, + {"mm_dma_bd8_5", aie2::mm_dma_bd8_5}, + {"mm_dma_bd9_0", aie2::mm_dma_bd9_0}, + {"mm_dma_bd9_1", aie2::mm_dma_bd9_1}, + {"mm_dma_bd9_2", aie2::mm_dma_bd9_2}, + {"mm_dma_bd9_3", aie2::mm_dma_bd9_3}, + {"mm_dma_bd9_4", aie2::mm_dma_bd9_4}, + {"mm_dma_bd9_5", aie2::mm_dma_bd9_5}, + {"mm_dma_bd10_0", aie2::mm_dma_bd10_0}, + {"mm_dma_bd10_1", aie2::mm_dma_bd10_1}, + {"mm_dma_bd10_2", aie2::mm_dma_bd10_2}, + {"mm_dma_bd10_3", aie2::mm_dma_bd10_3}, + {"mm_dma_bd10_4", aie2::mm_dma_bd10_4}, + {"mm_dma_bd10_5", aie2::mm_dma_bd10_5}, + {"mm_dma_bd11_0", aie2::mm_dma_bd11_0}, + {"mm_dma_bd11_1", aie2::mm_dma_bd11_1}, + {"mm_dma_bd11_2", aie2::mm_dma_bd11_2}, + {"mm_dma_bd11_3", aie2::mm_dma_bd11_3}, + {"mm_dma_bd11_4", aie2::mm_dma_bd11_4}, + {"mm_dma_bd11_5", aie2::mm_dma_bd11_5}, + {"mm_dma_bd12_0", aie2::mm_dma_bd12_0}, + {"mm_dma_bd12_1", aie2::mm_dma_bd12_1}, + {"mm_dma_bd12_2", aie2::mm_dma_bd12_2}, + {"mm_dma_bd12_3", aie2::mm_dma_bd12_3}, + {"mm_dma_bd12_4", aie2::mm_dma_bd12_4}, + {"mm_dma_bd12_5", aie2::mm_dma_bd12_5}, + {"mm_dma_bd13_0", aie2::mm_dma_bd13_0}, + {"mm_dma_bd13_1", aie2::mm_dma_bd13_1}, + {"mm_dma_bd13_2", aie2::mm_dma_bd13_2}, + {"mm_dma_bd13_3", aie2::mm_dma_bd13_3}, + {"mm_dma_bd13_4", aie2::mm_dma_bd13_4}, + {"mm_dma_bd13_5", aie2::mm_dma_bd13_5}, + {"mm_dma_bd14_0", aie2::mm_dma_bd14_0}, + {"mm_dma_bd14_1", aie2::mm_dma_bd14_1}, + {"mm_dma_bd14_2", aie2::mm_dma_bd14_2}, + {"mm_dma_bd14_3", aie2::mm_dma_bd14_3}, + {"mm_dma_bd14_4", aie2::mm_dma_bd14_4}, + {"mm_dma_bd14_5", aie2::mm_dma_bd14_5}, + {"mm_dma_bd15_0", aie2::mm_dma_bd15_0}, + {"mm_dma_bd15_1", aie2::mm_dma_bd15_1}, + {"mm_dma_bd15_2", aie2::mm_dma_bd15_2}, + {"mm_dma_bd15_3", aie2::mm_dma_bd15_3}, + {"mm_dma_bd15_4", aie2::mm_dma_bd15_4}, + {"mm_dma_bd15_5", aie2::mm_dma_bd15_5}, + {"mm_dma_s2mm_0_ctrl", aie2::mm_dma_s2mm_0_ctrl}, + {"mm_dma_s2mm_0_start_queue", aie2::mm_dma_s2mm_0_start_queue}, + {"mm_dma_s2mm_1_ctrl", aie2::mm_dma_s2mm_1_ctrl}, + {"mm_dma_s2mm_1_start_queue", aie2::mm_dma_s2mm_1_start_queue}, + {"mm_dma_mm2s_0_ctrl", aie2::mm_dma_mm2s_0_ctrl}, + {"mm_dma_mm2s_0_start_queue", aie2::mm_dma_mm2s_0_start_queue}, + {"mm_dma_mm2s_1_ctrl", aie2::mm_dma_mm2s_1_ctrl}, + {"mm_dma_mm2s_1_start_queue", aie2::mm_dma_mm2s_1_start_queue}, + {"mm_dma_s2mm_status_0", aie2::mm_dma_s2mm_status_0}, + {"mm_dma_s2mm_status_1", aie2::mm_dma_s2mm_status_1}, + {"mm_dma_mm2s_status_0", aie2::mm_dma_mm2s_status_0}, + {"mm_dma_mm2s_status_1", aie2::mm_dma_mm2s_status_1}, + {"mm_dma_s2mm_current_write_count_0", aie2::mm_dma_s2mm_current_write_count_0}, + {"mm_dma_s2mm_current_write_count_1", aie2::mm_dma_s2mm_current_write_count_1}, + {"mm_dma_s2mm_fot_count_fifo_pop_0", aie2::mm_dma_s2mm_fot_count_fifo_pop_0}, + {"mm_dma_s2mm_fot_count_fifo_pop_1", aie2::mm_dma_s2mm_fot_count_fifo_pop_1}, + {"mm_lock0_value", aie2::mm_lock0_value}, + {"mm_lock1_value", aie2::mm_lock1_value}, + {"mm_lock2_value", aie2::mm_lock2_value}, + {"mm_lock3_value", aie2::mm_lock3_value}, + {"mm_lock4_value", aie2::mm_lock4_value}, + {"mm_lock5_value", aie2::mm_lock5_value}, + {"mm_lock6_value", aie2::mm_lock6_value}, + {"mm_lock7_value", aie2::mm_lock7_value}, + {"mm_lock8_value", aie2::mm_lock8_value}, + {"mm_lock9_value", aie2::mm_lock9_value}, + {"mm_lock10_value", aie2::mm_lock10_value}, + {"mm_lock11_value", aie2::mm_lock11_value}, + {"mm_lock12_value", aie2::mm_lock12_value}, + {"mm_lock13_value", aie2::mm_lock13_value}, + {"mm_lock14_value", aie2::mm_lock14_value}, + {"mm_lock15_value", aie2::mm_lock15_value}, + {"mm_locks_event_selection_0", aie2::mm_locks_event_selection_0}, + {"mm_locks_event_selection_1", aie2::mm_locks_event_selection_1}, + {"mm_locks_event_selection_2", aie2::mm_locks_event_selection_2}, + {"mm_locks_event_selection_3", aie2::mm_locks_event_selection_3}, + {"mm_locks_event_selection_4", aie2::mm_locks_event_selection_4}, + {"mm_locks_event_selection_5", aie2::mm_locks_event_selection_5}, + {"mm_locks_event_selection_6", aie2::mm_locks_event_selection_6}, + {"mm_locks_event_selection_7", aie2::mm_locks_event_selection_7}, + {"mm_locks_overflow", aie2::mm_locks_overflow}, + {"mm_locks_underflow", aie2::mm_locks_underflow}, + {"mm_lock_request", aie2::mm_lock_request}, + {"mem_performance_control0", aie2::mem_performance_control0}, + {"mem_performance_control1", aie2::mem_performance_control1}, + {"mem_performance_control2", aie2::mem_performance_control2}, + {"mem_performance_counter0", aie2::mem_performance_counter0}, + {"mem_performance_counter1", aie2::mem_performance_counter1}, + {"mem_performance_counter2", aie2::mem_performance_counter2}, + {"mem_performance_counter3", aie2::mem_performance_counter3}, + {"mem_performance_counter0_event_value", aie2::mem_performance_counter0_event_value}, + {"mem_performance_counter1_event_value", aie2::mem_performance_counter1_event_value}, + {"mem_performance_counter2_event_value", aie2::mem_performance_counter2_event_value}, + {"mem_performance_counter3_event_value", aie2::mem_performance_counter3_event_value}, + {"mem_checkbit_error_generation", aie2::mem_checkbit_error_generation}, + {"mem_ecc_scrubbing_event", aie2::mem_ecc_scrubbing_event}, + {"mem_ecc_failing_address", aie2::mem_ecc_failing_address}, + {"mem_timer_control", aie2::mem_timer_control}, + {"mem_event_generate", aie2::mem_event_generate}, + {"mem_event_broadcast0", aie2::mem_event_broadcast0}, + {"mem_event_broadcast1", aie2::mem_event_broadcast1}, + {"mem_event_broadcast2", aie2::mem_event_broadcast2}, + {"mem_event_broadcast3", aie2::mem_event_broadcast3}, + {"mem_event_broadcast4", aie2::mem_event_broadcast4}, + {"mem_event_broadcast5", aie2::mem_event_broadcast5}, + {"mem_event_broadcast6", aie2::mem_event_broadcast6}, + {"mem_event_broadcast7", aie2::mem_event_broadcast7}, + {"mem_event_broadcast8", aie2::mem_event_broadcast8}, + {"mem_event_broadcast9", aie2::mem_event_broadcast9}, + {"mem_event_broadcast10", aie2::mem_event_broadcast10}, + {"mem_event_broadcast11", aie2::mem_event_broadcast11}, + {"mem_event_broadcast12", aie2::mem_event_broadcast12}, + {"mem_event_broadcast13", aie2::mem_event_broadcast13}, + {"mem_event_broadcast14", aie2::mem_event_broadcast14}, + {"mem_event_broadcast15", aie2::mem_event_broadcast15}, + {"mem_event_broadcast_a_block_south_set", aie2::mem_event_broadcast_a_block_south_set}, + {"mem_event_broadcast_a_block_south_clr", aie2::mem_event_broadcast_a_block_south_clr}, + {"mem_event_broadcast_a_block_south_value", aie2::mem_event_broadcast_a_block_south_value}, + {"mem_event_broadcast_a_block_west_set", aie2::mem_event_broadcast_a_block_west_set}, + {"mem_event_broadcast_a_block_west_clr", aie2::mem_event_broadcast_a_block_west_clr}, + {"mem_event_broadcast_a_block_west_value", aie2::mem_event_broadcast_a_block_west_value}, + {"mem_event_broadcast_a_block_north_set", aie2::mem_event_broadcast_a_block_north_set}, + {"mem_event_broadcast_a_block_north_clr", aie2::mem_event_broadcast_a_block_north_clr}, + {"mem_event_broadcast_a_block_north_value", aie2::mem_event_broadcast_a_block_north_value}, + {"mem_event_broadcast_a_block_east_set", aie2::mem_event_broadcast_a_block_east_set}, + {"mem_event_broadcast_a_block_east_clr", aie2::mem_event_broadcast_a_block_east_clr}, + {"mem_event_broadcast_a_block_east_value", aie2::mem_event_broadcast_a_block_east_value}, + {"mem_event_broadcast_b_block_south_set", aie2::mem_event_broadcast_b_block_south_set}, + {"mem_event_broadcast_b_block_south_clr", aie2::mem_event_broadcast_b_block_south_clr}, + {"mem_event_broadcast_b_block_south_value", aie2::mem_event_broadcast_b_block_south_value}, + {"mem_event_broadcast_b_block_west_set", aie2::mem_event_broadcast_b_block_west_set}, + {"mem_event_broadcast_b_block_west_clr", aie2::mem_event_broadcast_b_block_west_clr}, + {"mem_event_broadcast_b_block_west_value", aie2::mem_event_broadcast_b_block_west_value}, + {"mem_event_broadcast_b_block_north_set", aie2::mem_event_broadcast_b_block_north_set}, + {"mem_event_broadcast_b_block_north_clr", aie2::mem_event_broadcast_b_block_north_clr}, + {"mem_event_broadcast_b_block_north_value", aie2::mem_event_broadcast_b_block_north_value}, + {"mem_event_broadcast_b_block_east_set", aie2::mem_event_broadcast_b_block_east_set}, + {"mem_event_broadcast_b_block_east_clr", aie2::mem_event_broadcast_b_block_east_clr}, + {"mem_event_broadcast_b_block_east_value", aie2::mem_event_broadcast_b_block_east_value}, + {"mem_trace_control0", aie2::mem_trace_control0}, + {"mem_trace_control1", aie2::mem_trace_control1}, + {"mem_trace_status", aie2::mem_trace_status}, + {"mem_trace_event0", aie2::mem_trace_event0}, + {"mem_trace_event1", aie2::mem_trace_event1}, + {"mem_timer_trig_event_low_value", aie2::mem_timer_trig_event_low_value}, + {"mem_timer_trig_event_high_value", aie2::mem_timer_trig_event_high_value}, + {"mem_timer_low", aie2::mem_timer_low}, + {"mem_timer_high", aie2::mem_timer_high}, + {"mem_watchpoint0", aie2::mem_watchpoint0}, + {"mem_watchpoint1", aie2::mem_watchpoint1}, + {"mem_watchpoint2", aie2::mem_watchpoint2}, + {"mem_watchpoint3", aie2::mem_watchpoint3}, + {"mem_event_status0", aie2::mem_event_status0}, + {"mem_event_status1", aie2::mem_event_status1}, + {"mem_event_status2", aie2::mem_event_status2}, + {"mem_event_status3", aie2::mem_event_status3}, + {"mem_event_status4", aie2::mem_event_status4}, + {"mem_event_status5", aie2::mem_event_status5}, + {"mem_reserved0", aie2::mem_reserved0}, + {"mem_reserved1", aie2::mem_reserved1}, + {"mem_reserved2", aie2::mem_reserved2}, + {"mem_reserved3", aie2::mem_reserved3}, + {"mem_combo_event_inputs", aie2::mem_combo_event_inputs}, + {"mem_combo_event_control", aie2::mem_combo_event_control}, + {"mem_edge_detection_event_control", aie2::mem_edge_detection_event_control}, + {"mem_event_group_0_enable", aie2::mem_event_group_0_enable}, + {"mem_event_group_watchpoint_enable", aie2::mem_event_group_watchpoint_enable}, + {"mem_event_group_dma_enable", aie2::mem_event_group_dma_enable}, + {"mem_event_group_lock_enable", aie2::mem_event_group_lock_enable}, + {"mem_event_group_stream_switch_enable", aie2::mem_event_group_stream_switch_enable}, + {"mem_event_group_memory_conflict_enable", aie2::mem_event_group_memory_conflict_enable}, + {"mem_event_group_error_enable", aie2::mem_event_group_error_enable}, + {"mem_event_group_broadcast_enable", aie2::mem_event_group_broadcast_enable}, + {"mem_event_group_user_event_enable", aie2::mem_event_group_user_event_enable}, + {"mem_spare_reg", aie2::mem_spare_reg}, + {"mem_tile_control", aie2::mem_tile_control}, + {"mem_cssd_trigger", aie2::mem_cssd_trigger}, + {"mem_memory_control", aie2::mem_memory_control}, + {"mem_dma_bd0_0", aie2::mem_dma_bd0_0}, + {"mem_dma_bd0_1", aie2::mem_dma_bd0_1}, + {"mem_dma_bd0_2", aie2::mem_dma_bd0_2}, + {"mem_dma_bd0_3", aie2::mem_dma_bd0_3}, + {"mem_dma_bd0_4", aie2::mem_dma_bd0_4}, + {"mem_dma_bd0_5", aie2::mem_dma_bd0_5}, + {"mem_dma_bd0_6", aie2::mem_dma_bd0_6}, + {"mem_dma_bd0_7", aie2::mem_dma_bd0_7}, + {"mem_dma_bd1_0", aie2::mem_dma_bd1_0}, + {"mem_dma_bd1_1", aie2::mem_dma_bd1_1}, + {"mem_dma_bd1_2", aie2::mem_dma_bd1_2}, + {"mem_dma_bd1_3", aie2::mem_dma_bd1_3}, + {"mem_dma_bd1_4", aie2::mem_dma_bd1_4}, + {"mem_dma_bd1_5", aie2::mem_dma_bd1_5}, + {"mem_dma_bd1_6", aie2::mem_dma_bd1_6}, + {"mem_dma_bd1_7", aie2::mem_dma_bd1_7}, + {"mem_dma_bd2_0", aie2::mem_dma_bd2_0}, + {"mem_dma_bd2_1", aie2::mem_dma_bd2_1}, + {"mem_dma_bd2_2", aie2::mem_dma_bd2_2}, + {"mem_dma_bd2_3", aie2::mem_dma_bd2_3}, + {"mem_dma_bd2_4", aie2::mem_dma_bd2_4}, + {"mem_dma_bd2_5", aie2::mem_dma_bd2_5}, + {"mem_dma_bd2_6", aie2::mem_dma_bd2_6}, + {"mem_dma_bd2_7", aie2::mem_dma_bd2_7}, + {"mem_dma_bd3_0", aie2::mem_dma_bd3_0}, + {"mem_dma_bd3_1", aie2::mem_dma_bd3_1}, + {"mem_dma_bd3_2", aie2::mem_dma_bd3_2}, + {"mem_dma_bd3_3", aie2::mem_dma_bd3_3}, + {"mem_dma_bd3_4", aie2::mem_dma_bd3_4}, + {"mem_dma_bd3_5", aie2::mem_dma_bd3_5}, + {"mem_dma_bd3_6", aie2::mem_dma_bd3_6}, + {"mem_dma_bd3_7", aie2::mem_dma_bd3_7}, + {"mem_dma_bd4_0", aie2::mem_dma_bd4_0}, + {"mem_dma_bd4_1", aie2::mem_dma_bd4_1}, + {"mem_dma_bd4_2", aie2::mem_dma_bd4_2}, + {"mem_dma_bd4_3", aie2::mem_dma_bd4_3}, + {"mem_dma_bd4_4", aie2::mem_dma_bd4_4}, + {"mem_dma_bd4_5", aie2::mem_dma_bd4_5}, + {"mem_dma_bd4_6", aie2::mem_dma_bd4_6}, + {"mem_dma_bd4_7", aie2::mem_dma_bd4_7}, + {"mem_dma_bd5_0", aie2::mem_dma_bd5_0}, + {"mem_dma_bd5_1", aie2::mem_dma_bd5_1}, + {"mem_dma_bd5_2", aie2::mem_dma_bd5_2}, + {"mem_dma_bd5_3", aie2::mem_dma_bd5_3}, + {"mem_dma_bd5_4", aie2::mem_dma_bd5_4}, + {"mem_dma_bd5_5", aie2::mem_dma_bd5_5}, + {"mem_dma_bd5_6", aie2::mem_dma_bd5_6}, + {"mem_dma_bd5_7", aie2::mem_dma_bd5_7}, + {"mem_dma_bd6_0", aie2::mem_dma_bd6_0}, + {"mem_dma_bd6_1", aie2::mem_dma_bd6_1}, + {"mem_dma_bd6_2", aie2::mem_dma_bd6_2}, + {"mem_dma_bd6_3", aie2::mem_dma_bd6_3}, + {"mem_dma_bd6_4", aie2::mem_dma_bd6_4}, + {"mem_dma_bd6_5", aie2::mem_dma_bd6_5}, + {"mem_dma_bd6_6", aie2::mem_dma_bd6_6}, + {"mem_dma_bd6_7", aie2::mem_dma_bd6_7}, + {"mem_dma_bd7_0", aie2::mem_dma_bd7_0}, + {"mem_dma_bd7_1", aie2::mem_dma_bd7_1}, + {"mem_dma_bd7_2", aie2::mem_dma_bd7_2}, + {"mem_dma_bd7_3", aie2::mem_dma_bd7_3}, + {"mem_dma_bd7_4", aie2::mem_dma_bd7_4}, + {"mem_dma_bd7_5", aie2::mem_dma_bd7_5}, + {"mem_dma_bd7_6", aie2::mem_dma_bd7_6}, + {"mem_dma_bd7_7", aie2::mem_dma_bd7_7}, + {"mem_dma_bd8_0", aie2::mem_dma_bd8_0}, + {"mem_dma_bd8_1", aie2::mem_dma_bd8_1}, + {"mem_dma_bd8_2", aie2::mem_dma_bd8_2}, + {"mem_dma_bd8_3", aie2::mem_dma_bd8_3}, + {"mem_dma_bd8_4", aie2::mem_dma_bd8_4}, + {"mem_dma_bd8_5", aie2::mem_dma_bd8_5}, + {"mem_dma_bd8_6", aie2::mem_dma_bd8_6}, + {"mem_dma_bd8_7", aie2::mem_dma_bd8_7}, + {"mem_dma_bd9_0", aie2::mem_dma_bd9_0}, + {"mem_dma_bd9_1", aie2::mem_dma_bd9_1}, + {"mem_dma_bd9_2", aie2::mem_dma_bd9_2}, + {"mem_dma_bd9_3", aie2::mem_dma_bd9_3}, + {"mem_dma_bd9_4", aie2::mem_dma_bd9_4}, + {"mem_dma_bd9_5", aie2::mem_dma_bd9_5}, + {"mem_dma_bd9_6", aie2::mem_dma_bd9_6}, + {"mem_dma_bd9_7", aie2::mem_dma_bd9_7}, + {"mem_dma_bd10_0", aie2::mem_dma_bd10_0}, + {"mem_dma_bd10_1", aie2::mem_dma_bd10_1}, + {"mem_dma_bd10_2", aie2::mem_dma_bd10_2}, + {"mem_dma_bd10_3", aie2::mem_dma_bd10_3}, + {"mem_dma_bd10_4", aie2::mem_dma_bd10_4}, + {"mem_dma_bd10_5", aie2::mem_dma_bd10_5}, + {"mem_dma_bd10_6", aie2::mem_dma_bd10_6}, + {"mem_dma_bd10_7", aie2::mem_dma_bd10_7}, + {"mem_dma_bd11_0", aie2::mem_dma_bd11_0}, + {"mem_dma_bd11_1", aie2::mem_dma_bd11_1}, + {"mem_dma_bd11_2", aie2::mem_dma_bd11_2}, + {"mem_dma_bd11_3", aie2::mem_dma_bd11_3}, + {"mem_dma_bd11_4", aie2::mem_dma_bd11_4}, + {"mem_dma_bd11_5", aie2::mem_dma_bd11_5}, + {"mem_dma_bd11_6", aie2::mem_dma_bd11_6}, + {"mem_dma_bd11_7", aie2::mem_dma_bd11_7}, + {"mem_dma_bd12_0", aie2::mem_dma_bd12_0}, + {"mem_dma_bd12_1", aie2::mem_dma_bd12_1}, + {"mem_dma_bd12_2", aie2::mem_dma_bd12_2}, + {"mem_dma_bd12_3", aie2::mem_dma_bd12_3}, + {"mem_dma_bd12_4", aie2::mem_dma_bd12_4}, + {"mem_dma_bd12_5", aie2::mem_dma_bd12_5}, + {"mem_dma_bd12_6", aie2::mem_dma_bd12_6}, + {"mem_dma_bd12_7", aie2::mem_dma_bd12_7}, + {"mem_dma_bd13_0", aie2::mem_dma_bd13_0}, + {"mem_dma_bd13_1", aie2::mem_dma_bd13_1}, + {"mem_dma_bd13_2", aie2::mem_dma_bd13_2}, + {"mem_dma_bd13_3", aie2::mem_dma_bd13_3}, + {"mem_dma_bd13_4", aie2::mem_dma_bd13_4}, + {"mem_dma_bd13_5", aie2::mem_dma_bd13_5}, + {"mem_dma_bd13_6", aie2::mem_dma_bd13_6}, + {"mem_dma_bd13_7", aie2::mem_dma_bd13_7}, + {"mem_dma_bd14_0", aie2::mem_dma_bd14_0}, + {"mem_dma_bd14_1", aie2::mem_dma_bd14_1}, + {"mem_dma_bd14_2", aie2::mem_dma_bd14_2}, + {"mem_dma_bd14_3", aie2::mem_dma_bd14_3}, + {"mem_dma_bd14_4", aie2::mem_dma_bd14_4}, + {"mem_dma_bd14_5", aie2::mem_dma_bd14_5}, + {"mem_dma_bd14_6", aie2::mem_dma_bd14_6}, + {"mem_dma_bd14_7", aie2::mem_dma_bd14_7}, + {"mem_dma_bd15_0", aie2::mem_dma_bd15_0}, + {"mem_dma_bd15_1", aie2::mem_dma_bd15_1}, + {"mem_dma_bd15_2", aie2::mem_dma_bd15_2}, + {"mem_dma_bd15_3", aie2::mem_dma_bd15_3}, + {"mem_dma_bd15_4", aie2::mem_dma_bd15_4}, + {"mem_dma_bd15_5", aie2::mem_dma_bd15_5}, + {"mem_dma_bd15_6", aie2::mem_dma_bd15_6}, + {"mem_dma_bd15_7", aie2::mem_dma_bd15_7}, + {"mem_dma_bd16_0", aie2::mem_dma_bd16_0}, + {"mem_dma_bd16_1", aie2::mem_dma_bd16_1}, + {"mem_dma_bd16_2", aie2::mem_dma_bd16_2}, + {"mem_dma_bd16_3", aie2::mem_dma_bd16_3}, + {"mem_dma_bd16_4", aie2::mem_dma_bd16_4}, + {"mem_dma_bd16_5", aie2::mem_dma_bd16_5}, + {"mem_dma_bd16_6", aie2::mem_dma_bd16_6}, + {"mem_dma_bd16_7", aie2::mem_dma_bd16_7}, + {"mem_dma_bd17_0", aie2::mem_dma_bd17_0}, + {"mem_dma_bd17_1", aie2::mem_dma_bd17_1}, + {"mem_dma_bd17_2", aie2::mem_dma_bd17_2}, + {"mem_dma_bd17_3", aie2::mem_dma_bd17_3}, + {"mem_dma_bd17_4", aie2::mem_dma_bd17_4}, + {"mem_dma_bd17_5", aie2::mem_dma_bd17_5}, + {"mem_dma_bd17_6", aie2::mem_dma_bd17_6}, + {"mem_dma_bd17_7", aie2::mem_dma_bd17_7}, + {"mem_dma_bd18_0", aie2::mem_dma_bd18_0}, + {"mem_dma_bd18_1", aie2::mem_dma_bd18_1}, + {"mem_dma_bd18_2", aie2::mem_dma_bd18_2}, + {"mem_dma_bd18_3", aie2::mem_dma_bd18_3}, + {"mem_dma_bd18_4", aie2::mem_dma_bd18_4}, + {"mem_dma_bd18_5", aie2::mem_dma_bd18_5}, + {"mem_dma_bd18_6", aie2::mem_dma_bd18_6}, + {"mem_dma_bd18_7", aie2::mem_dma_bd18_7}, + {"mem_dma_bd19_0", aie2::mem_dma_bd19_0}, + {"mem_dma_bd19_1", aie2::mem_dma_bd19_1}, + {"mem_dma_bd19_2", aie2::mem_dma_bd19_2}, + {"mem_dma_bd19_3", aie2::mem_dma_bd19_3}, + {"mem_dma_bd19_4", aie2::mem_dma_bd19_4}, + {"mem_dma_bd19_5", aie2::mem_dma_bd19_5}, + {"mem_dma_bd19_6", aie2::mem_dma_bd19_6}, + {"mem_dma_bd19_7", aie2::mem_dma_bd19_7}, + {"mem_dma_bd20_0", aie2::mem_dma_bd20_0}, + {"mem_dma_bd20_1", aie2::mem_dma_bd20_1}, + {"mem_dma_bd20_2", aie2::mem_dma_bd20_2}, + {"mem_dma_bd20_3", aie2::mem_dma_bd20_3}, + {"mem_dma_bd20_4", aie2::mem_dma_bd20_4}, + {"mem_dma_bd20_5", aie2::mem_dma_bd20_5}, + {"mem_dma_bd20_6", aie2::mem_dma_bd20_6}, + {"mem_dma_bd20_7", aie2::mem_dma_bd20_7}, + {"mem_dma_bd21_0", aie2::mem_dma_bd21_0}, + {"mem_dma_bd21_1", aie2::mem_dma_bd21_1}, + {"mem_dma_bd21_2", aie2::mem_dma_bd21_2}, + {"mem_dma_bd21_3", aie2::mem_dma_bd21_3}, + {"mem_dma_bd21_4", aie2::mem_dma_bd21_4}, + {"mem_dma_bd21_5", aie2::mem_dma_bd21_5}, + {"mem_dma_bd21_6", aie2::mem_dma_bd21_6}, + {"mem_dma_bd21_7", aie2::mem_dma_bd21_7}, + {"mem_dma_bd22_0", aie2::mem_dma_bd22_0}, + {"mem_dma_bd22_1", aie2::mem_dma_bd22_1}, + {"mem_dma_bd22_2", aie2::mem_dma_bd22_2}, + {"mem_dma_bd22_3", aie2::mem_dma_bd22_3}, + {"mem_dma_bd22_4", aie2::mem_dma_bd22_4}, + {"mem_dma_bd22_5", aie2::mem_dma_bd22_5}, + {"mem_dma_bd22_6", aie2::mem_dma_bd22_6}, + {"mem_dma_bd22_7", aie2::mem_dma_bd22_7}, + {"mem_dma_bd23_0", aie2::mem_dma_bd23_0}, + {"mem_dma_bd23_1", aie2::mem_dma_bd23_1}, + {"mem_dma_bd23_2", aie2::mem_dma_bd23_2}, + {"mem_dma_bd23_3", aie2::mem_dma_bd23_3}, + {"mem_dma_bd23_4", aie2::mem_dma_bd23_4}, + {"mem_dma_bd23_5", aie2::mem_dma_bd23_5}, + {"mem_dma_bd23_6", aie2::mem_dma_bd23_6}, + {"mem_dma_bd23_7", aie2::mem_dma_bd23_7}, + {"mem_dma_bd24_0", aie2::mem_dma_bd24_0}, + {"mem_dma_bd24_1", aie2::mem_dma_bd24_1}, + {"mem_dma_bd24_2", aie2::mem_dma_bd24_2}, + {"mem_dma_bd24_3", aie2::mem_dma_bd24_3}, + {"mem_dma_bd24_4", aie2::mem_dma_bd24_4}, + {"mem_dma_bd24_5", aie2::mem_dma_bd24_5}, + {"mem_dma_bd24_6", aie2::mem_dma_bd24_6}, + {"mem_dma_bd24_7", aie2::mem_dma_bd24_7}, + {"mem_dma_bd25_0", aie2::mem_dma_bd25_0}, + {"mem_dma_bd25_1", aie2::mem_dma_bd25_1}, + {"mem_dma_bd25_2", aie2::mem_dma_bd25_2}, + {"mem_dma_bd25_3", aie2::mem_dma_bd25_3}, + {"mem_dma_bd25_4", aie2::mem_dma_bd25_4}, + {"mem_dma_bd25_5", aie2::mem_dma_bd25_5}, + {"mem_dma_bd25_6", aie2::mem_dma_bd25_6}, + {"mem_dma_bd25_7", aie2::mem_dma_bd25_7}, + {"mem_dma_bd26_0", aie2::mem_dma_bd26_0}, + {"mem_dma_bd26_1", aie2::mem_dma_bd26_1}, + {"mem_dma_bd26_2", aie2::mem_dma_bd26_2}, + {"mem_dma_bd26_3", aie2::mem_dma_bd26_3}, + {"mem_dma_bd26_4", aie2::mem_dma_bd26_4}, + {"mem_dma_bd26_5", aie2::mem_dma_bd26_5}, + {"mem_dma_bd26_6", aie2::mem_dma_bd26_6}, + {"mem_dma_bd26_7", aie2::mem_dma_bd26_7}, + {"mem_dma_bd27_0", aie2::mem_dma_bd27_0}, + {"mem_dma_bd27_1", aie2::mem_dma_bd27_1}, + {"mem_dma_bd27_2", aie2::mem_dma_bd27_2}, + {"mem_dma_bd27_3", aie2::mem_dma_bd27_3}, + {"mem_dma_bd27_4", aie2::mem_dma_bd27_4}, + {"mem_dma_bd27_5", aie2::mem_dma_bd27_5}, + {"mem_dma_bd27_6", aie2::mem_dma_bd27_6}, + {"mem_dma_bd27_7", aie2::mem_dma_bd27_7}, + {"mem_dma_bd28_0", aie2::mem_dma_bd28_0}, + {"mem_dma_bd28_1", aie2::mem_dma_bd28_1}, + {"mem_dma_bd28_2", aie2::mem_dma_bd28_2}, + {"mem_dma_bd28_3", aie2::mem_dma_bd28_3}, + {"mem_dma_bd28_4", aie2::mem_dma_bd28_4}, + {"mem_dma_bd28_5", aie2::mem_dma_bd28_5}, + {"mem_dma_bd28_6", aie2::mem_dma_bd28_6}, + {"mem_dma_bd28_7", aie2::mem_dma_bd28_7}, + {"mem_dma_bd29_0", aie2::mem_dma_bd29_0}, + {"mem_dma_bd29_1", aie2::mem_dma_bd29_1}, + {"mem_dma_bd29_2", aie2::mem_dma_bd29_2}, + {"mem_dma_bd29_3", aie2::mem_dma_bd29_3}, + {"mem_dma_bd29_4", aie2::mem_dma_bd29_4}, + {"mem_dma_bd29_5", aie2::mem_dma_bd29_5}, + {"mem_dma_bd29_6", aie2::mem_dma_bd29_6}, + {"mem_dma_bd29_7", aie2::mem_dma_bd29_7}, + {"mem_dma_bd30_0", aie2::mem_dma_bd30_0}, + {"mem_dma_bd30_1", aie2::mem_dma_bd30_1}, + {"mem_dma_bd30_2", aie2::mem_dma_bd30_2}, + {"mem_dma_bd30_3", aie2::mem_dma_bd30_3}, + {"mem_dma_bd30_4", aie2::mem_dma_bd30_4}, + {"mem_dma_bd30_5", aie2::mem_dma_bd30_5}, + {"mem_dma_bd30_6", aie2::mem_dma_bd30_6}, + {"mem_dma_bd30_7", aie2::mem_dma_bd30_7}, + {"mem_dma_bd31_0", aie2::mem_dma_bd31_0}, + {"mem_dma_bd31_1", aie2::mem_dma_bd31_1}, + {"mem_dma_bd31_2", aie2::mem_dma_bd31_2}, + {"mem_dma_bd31_3", aie2::mem_dma_bd31_3}, + {"mem_dma_bd31_4", aie2::mem_dma_bd31_4}, + {"mem_dma_bd31_5", aie2::mem_dma_bd31_5}, + {"mem_dma_bd31_6", aie2::mem_dma_bd31_6}, + {"mem_dma_bd31_7", aie2::mem_dma_bd31_7}, + {"mem_dma_bd32_0", aie2::mem_dma_bd32_0}, + {"mem_dma_bd32_1", aie2::mem_dma_bd32_1}, + {"mem_dma_bd32_2", aie2::mem_dma_bd32_2}, + {"mem_dma_bd32_3", aie2::mem_dma_bd32_3}, + {"mem_dma_bd32_4", aie2::mem_dma_bd32_4}, + {"mem_dma_bd32_5", aie2::mem_dma_bd32_5}, + {"mem_dma_bd32_6", aie2::mem_dma_bd32_6}, + {"mem_dma_bd32_7", aie2::mem_dma_bd32_7}, + {"mem_dma_bd33_0", aie2::mem_dma_bd33_0}, + {"mem_dma_bd33_1", aie2::mem_dma_bd33_1}, + {"mem_dma_bd33_2", aie2::mem_dma_bd33_2}, + {"mem_dma_bd33_3", aie2::mem_dma_bd33_3}, + {"mem_dma_bd33_4", aie2::mem_dma_bd33_4}, + {"mem_dma_bd33_5", aie2::mem_dma_bd33_5}, + {"mem_dma_bd33_6", aie2::mem_dma_bd33_6}, + {"mem_dma_bd33_7", aie2::mem_dma_bd33_7}, + {"mem_dma_bd34_0", aie2::mem_dma_bd34_0}, + {"mem_dma_bd34_1", aie2::mem_dma_bd34_1}, + {"mem_dma_bd34_2", aie2::mem_dma_bd34_2}, + {"mem_dma_bd34_3", aie2::mem_dma_bd34_3}, + {"mem_dma_bd34_4", aie2::mem_dma_bd34_4}, + {"mem_dma_bd34_5", aie2::mem_dma_bd34_5}, + {"mem_dma_bd34_6", aie2::mem_dma_bd34_6}, + {"mem_dma_bd34_7", aie2::mem_dma_bd34_7}, + {"mem_dma_bd35_0", aie2::mem_dma_bd35_0}, + {"mem_dma_bd35_1", aie2::mem_dma_bd35_1}, + {"mem_dma_bd35_2", aie2::mem_dma_bd35_2}, + {"mem_dma_bd35_3", aie2::mem_dma_bd35_3}, + {"mem_dma_bd35_4", aie2::mem_dma_bd35_4}, + {"mem_dma_bd35_5", aie2::mem_dma_bd35_5}, + {"mem_dma_bd35_6", aie2::mem_dma_bd35_6}, + {"mem_dma_bd35_7", aie2::mem_dma_bd35_7}, + {"mem_dma_bd36_0", aie2::mem_dma_bd36_0}, + {"mem_dma_bd36_1", aie2::mem_dma_bd36_1}, + {"mem_dma_bd36_2", aie2::mem_dma_bd36_2}, + {"mem_dma_bd36_3", aie2::mem_dma_bd36_3}, + {"mem_dma_bd36_4", aie2::mem_dma_bd36_4}, + {"mem_dma_bd36_5", aie2::mem_dma_bd36_5}, + {"mem_dma_bd36_6", aie2::mem_dma_bd36_6}, + {"mem_dma_bd36_7", aie2::mem_dma_bd36_7}, + {"mem_dma_bd37_0", aie2::mem_dma_bd37_0}, + {"mem_dma_bd37_1", aie2::mem_dma_bd37_1}, + {"mem_dma_bd37_2", aie2::mem_dma_bd37_2}, + {"mem_dma_bd37_3", aie2::mem_dma_bd37_3}, + {"mem_dma_bd37_4", aie2::mem_dma_bd37_4}, + {"mem_dma_bd37_5", aie2::mem_dma_bd37_5}, + {"mem_dma_bd37_6", aie2::mem_dma_bd37_6}, + {"mem_dma_bd37_7", aie2::mem_dma_bd37_7}, + {"mem_dma_bd38_0", aie2::mem_dma_bd38_0}, + {"mem_dma_bd38_1", aie2::mem_dma_bd38_1}, + {"mem_dma_bd38_2", aie2::mem_dma_bd38_2}, + {"mem_dma_bd38_3", aie2::mem_dma_bd38_3}, + {"mem_dma_bd38_4", aie2::mem_dma_bd38_4}, + {"mem_dma_bd38_5", aie2::mem_dma_bd38_5}, + {"mem_dma_bd38_6", aie2::mem_dma_bd38_6}, + {"mem_dma_bd38_7", aie2::mem_dma_bd38_7}, + {"mem_dma_bd39_0", aie2::mem_dma_bd39_0}, + {"mem_dma_bd39_1", aie2::mem_dma_bd39_1}, + {"mem_dma_bd39_2", aie2::mem_dma_bd39_2}, + {"mem_dma_bd39_3", aie2::mem_dma_bd39_3}, + {"mem_dma_bd39_4", aie2::mem_dma_bd39_4}, + {"mem_dma_bd39_5", aie2::mem_dma_bd39_5}, + {"mem_dma_bd39_6", aie2::mem_dma_bd39_6}, + {"mem_dma_bd39_7", aie2::mem_dma_bd39_7}, + {"mem_dma_bd40_0", aie2::mem_dma_bd40_0}, + {"mem_dma_bd40_1", aie2::mem_dma_bd40_1}, + {"mem_dma_bd40_2", aie2::mem_dma_bd40_2}, + {"mem_dma_bd40_3", aie2::mem_dma_bd40_3}, + {"mem_dma_bd40_4", aie2::mem_dma_bd40_4}, + {"mem_dma_bd40_5", aie2::mem_dma_bd40_5}, + {"mem_dma_bd40_6", aie2::mem_dma_bd40_6}, + {"mem_dma_bd40_7", aie2::mem_dma_bd40_7}, + {"mem_dma_bd41_0", aie2::mem_dma_bd41_0}, + {"mem_dma_bd41_1", aie2::mem_dma_bd41_1}, + {"mem_dma_bd41_2", aie2::mem_dma_bd41_2}, + {"mem_dma_bd41_3", aie2::mem_dma_bd41_3}, + {"mem_dma_bd41_4", aie2::mem_dma_bd41_4}, + {"mem_dma_bd41_5", aie2::mem_dma_bd41_5}, + {"mem_dma_bd41_6", aie2::mem_dma_bd41_6}, + {"mem_dma_bd41_7", aie2::mem_dma_bd41_7}, + {"mem_dma_bd42_0", aie2::mem_dma_bd42_0}, + {"mem_dma_bd42_1", aie2::mem_dma_bd42_1}, + {"mem_dma_bd42_2", aie2::mem_dma_bd42_2}, + {"mem_dma_bd42_3", aie2::mem_dma_bd42_3}, + {"mem_dma_bd42_4", aie2::mem_dma_bd42_4}, + {"mem_dma_bd42_5", aie2::mem_dma_bd42_5}, + {"mem_dma_bd42_6", aie2::mem_dma_bd42_6}, + {"mem_dma_bd42_7", aie2::mem_dma_bd42_7}, + {"mem_dma_bd43_0", aie2::mem_dma_bd43_0}, + {"mem_dma_bd43_1", aie2::mem_dma_bd43_1}, + {"mem_dma_bd43_2", aie2::mem_dma_bd43_2}, + {"mem_dma_bd43_3", aie2::mem_dma_bd43_3}, + {"mem_dma_bd43_4", aie2::mem_dma_bd43_4}, + {"mem_dma_bd43_5", aie2::mem_dma_bd43_5}, + {"mem_dma_bd43_6", aie2::mem_dma_bd43_6}, + {"mem_dma_bd43_7", aie2::mem_dma_bd43_7}, + {"mem_dma_bd44_0", aie2::mem_dma_bd44_0}, + {"mem_dma_bd44_1", aie2::mem_dma_bd44_1}, + {"mem_dma_bd44_2", aie2::mem_dma_bd44_2}, + {"mem_dma_bd44_3", aie2::mem_dma_bd44_3}, + {"mem_dma_bd44_4", aie2::mem_dma_bd44_4}, + {"mem_dma_bd44_5", aie2::mem_dma_bd44_5}, + {"mem_dma_bd44_6", aie2::mem_dma_bd44_6}, + {"mem_dma_bd44_7", aie2::mem_dma_bd44_7}, + {"mem_dma_bd45_0", aie2::mem_dma_bd45_0}, + {"mem_dma_bd45_1", aie2::mem_dma_bd45_1}, + {"mem_dma_bd45_2", aie2::mem_dma_bd45_2}, + {"mem_dma_bd45_3", aie2::mem_dma_bd45_3}, + {"mem_dma_bd45_4", aie2::mem_dma_bd45_4}, + {"mem_dma_bd45_5", aie2::mem_dma_bd45_5}, + {"mem_dma_bd45_6", aie2::mem_dma_bd45_6}, + {"mem_dma_bd45_7", aie2::mem_dma_bd45_7}, + {"mem_dma_bd46_0", aie2::mem_dma_bd46_0}, + {"mem_dma_bd46_1", aie2::mem_dma_bd46_1}, + {"mem_dma_bd46_2", aie2::mem_dma_bd46_2}, + {"mem_dma_bd46_3", aie2::mem_dma_bd46_3}, + {"mem_dma_bd46_4", aie2::mem_dma_bd46_4}, + {"mem_dma_bd46_5", aie2::mem_dma_bd46_5}, + {"mem_dma_bd46_6", aie2::mem_dma_bd46_6}, + {"mem_dma_bd46_7", aie2::mem_dma_bd46_7}, + {"mem_dma_bd47_0", aie2::mem_dma_bd47_0}, + {"mem_dma_bd47_1", aie2::mem_dma_bd47_1}, + {"mem_dma_bd47_2", aie2::mem_dma_bd47_2}, + {"mem_dma_bd47_3", aie2::mem_dma_bd47_3}, + {"mem_dma_bd47_4", aie2::mem_dma_bd47_4}, + {"mem_dma_bd47_5", aie2::mem_dma_bd47_5}, + {"mem_dma_bd47_6", aie2::mem_dma_bd47_6}, + {"mem_dma_bd47_7", aie2::mem_dma_bd47_7}, + {"mem_dma_s2mm_0_ctrl", aie2::mem_dma_s2mm_0_ctrl}, + {"mem_dma_s2mm_0_start_queue", aie2::mem_dma_s2mm_0_start_queue}, + {"mem_dma_s2mm_1_ctrl", aie2::mem_dma_s2mm_1_ctrl}, + {"mem_dma_s2mm_1_start_queue", aie2::mem_dma_s2mm_1_start_queue}, + {"mem_dma_s2mm_2_ctrl", aie2::mem_dma_s2mm_2_ctrl}, + {"mem_dma_s2mm_2_start_queue", aie2::mem_dma_s2mm_2_start_queue}, + {"mem_dma_s2mm_3_ctrl", aie2::mem_dma_s2mm_3_ctrl}, + {"mem_dma_s2mm_3_start_queue", aie2::mem_dma_s2mm_3_start_queue}, + {"mem_dma_s2mm_4_ctrl", aie2::mem_dma_s2mm_4_ctrl}, + {"mem_dma_s2mm_4_start_queue", aie2::mem_dma_s2mm_4_start_queue}, + {"mem_dma_s2mm_5_ctrl", aie2::mem_dma_s2mm_5_ctrl}, + {"mem_dma_s2mm_5_start_queue", aie2::mem_dma_s2mm_5_start_queue}, + {"mem_dma_mm2s_0_ctrl", aie2::mem_dma_mm2s_0_ctrl}, + {"mem_dma_mm2s_0_start_queue", aie2::mem_dma_mm2s_0_start_queue}, + {"mem_dma_mm2s_1_ctrl", aie2::mem_dma_mm2s_1_ctrl}, + {"mem_dma_mm2s_1_start_queue", aie2::mem_dma_mm2s_1_start_queue}, + {"mem_dma_mm2s_2_ctrl", aie2::mem_dma_mm2s_2_ctrl}, + {"mem_dma_mm2s_2_start_queue", aie2::mem_dma_mm2s_2_start_queue}, + {"mem_dma_mm2s_3_ctrl", aie2::mem_dma_mm2s_3_ctrl}, + {"mem_dma_mm2s_3_start_queue", aie2::mem_dma_mm2s_3_start_queue}, + {"mem_dma_mm2s_4_ctrl", aie2::mem_dma_mm2s_4_ctrl}, + {"mem_dma_mm2s_4_start_queue", aie2::mem_dma_mm2s_4_start_queue}, + {"mem_dma_mm2s_5_ctrl", aie2::mem_dma_mm2s_5_ctrl}, + {"mem_dma_mm2s_5_start_queue", aie2::mem_dma_mm2s_5_start_queue}, + {"mem_dma_s2mm_status_0", aie2::mem_dma_s2mm_status_0}, + {"mem_dma_s2mm_status_1", aie2::mem_dma_s2mm_status_1}, + {"mem_dma_s2mm_status_2", aie2::mem_dma_s2mm_status_2}, + {"mem_dma_s2mm_status_3", aie2::mem_dma_s2mm_status_3}, + {"mem_dma_s2mm_status_4", aie2::mem_dma_s2mm_status_4}, + {"mem_dma_s2mm_status_5", aie2::mem_dma_s2mm_status_5}, + {"mem_dma_mm2s_status_0", aie2::mem_dma_mm2s_status_0}, + {"mem_dma_mm2s_status_1", aie2::mem_dma_mm2s_status_1}, + {"mem_dma_mm2s_status_2", aie2::mem_dma_mm2s_status_2}, + {"mem_dma_mm2s_status_3", aie2::mem_dma_mm2s_status_3}, + {"mem_dma_mm2s_status_4", aie2::mem_dma_mm2s_status_4}, + {"mem_dma_mm2s_status_5", aie2::mem_dma_mm2s_status_5}, + {"mem_dma_event_channel_selection", aie2::mem_dma_event_channel_selection}, + {"mem_dma_s2mm_current_write_count_0", aie2::mem_dma_s2mm_current_write_count_0}, + {"mem_dma_s2mm_current_write_count_1", aie2::mem_dma_s2mm_current_write_count_1}, + {"mem_dma_s2mm_current_write_count_2", aie2::mem_dma_s2mm_current_write_count_2}, + {"mem_dma_s2mm_current_write_count_3", aie2::mem_dma_s2mm_current_write_count_3}, + {"mem_dma_s2mm_current_write_count_4", aie2::mem_dma_s2mm_current_write_count_4}, + {"mem_dma_s2mm_current_write_count_5", aie2::mem_dma_s2mm_current_write_count_5}, + {"mem_dma_s2mm_fot_count_fifo_pop_0", aie2::mem_dma_s2mm_fot_count_fifo_pop_0}, + {"mem_dma_s2mm_fot_count_fifo_pop_1", aie2::mem_dma_s2mm_fot_count_fifo_pop_1}, + {"mem_dma_s2mm_fot_count_fifo_pop_2", aie2::mem_dma_s2mm_fot_count_fifo_pop_2}, + {"mem_dma_s2mm_fot_count_fifo_pop_3", aie2::mem_dma_s2mm_fot_count_fifo_pop_3}, + {"mem_dma_s2mm_fot_count_fifo_pop_4", aie2::mem_dma_s2mm_fot_count_fifo_pop_4}, + {"mem_dma_s2mm_fot_count_fifo_pop_5", aie2::mem_dma_s2mm_fot_count_fifo_pop_5}, + {"mem_stream_switch_master_config_dma0", aie2::mem_stream_switch_master_config_dma0}, + {"mem_stream_switch_master_config_dma1", aie2::mem_stream_switch_master_config_dma1}, + {"mem_stream_switch_master_config_dma2", aie2::mem_stream_switch_master_config_dma2}, + {"mem_stream_switch_master_config_dma3", aie2::mem_stream_switch_master_config_dma3}, + {"mem_stream_switch_master_config_dma4", aie2::mem_stream_switch_master_config_dma4}, + {"mem_stream_switch_master_config_dma5", aie2::mem_stream_switch_master_config_dma5}, + {"mem_stream_switch_master_config_tile_ctrl", aie2::mem_stream_switch_master_config_tile_ctrl}, + {"mem_stream_switch_master_config_south0", aie2::mem_stream_switch_master_config_south0}, + {"mem_stream_switch_master_config_south1", aie2::mem_stream_switch_master_config_south1}, + {"mem_stream_switch_master_config_south2", aie2::mem_stream_switch_master_config_south2}, + {"mem_stream_switch_master_config_south3", aie2::mem_stream_switch_master_config_south3}, + {"mem_stream_switch_master_config_north0", aie2::mem_stream_switch_master_config_north0}, + {"mem_stream_switch_master_config_north1", aie2::mem_stream_switch_master_config_north1}, + {"mem_stream_switch_master_config_north2", aie2::mem_stream_switch_master_config_north2}, + {"mem_stream_switch_master_config_north3", aie2::mem_stream_switch_master_config_north3}, + {"mem_stream_switch_master_config_north4", aie2::mem_stream_switch_master_config_north4}, + {"mem_stream_switch_master_config_north5", aie2::mem_stream_switch_master_config_north5}, + {"mem_stream_switch_slave_config_dma_0", aie2::mem_stream_switch_slave_config_dma_0}, + {"mem_stream_switch_slave_config_dma_1", aie2::mem_stream_switch_slave_config_dma_1}, + {"mem_stream_switch_slave_config_dma_2", aie2::mem_stream_switch_slave_config_dma_2}, + {"mem_stream_switch_slave_config_dma_3", aie2::mem_stream_switch_slave_config_dma_3}, + {"mem_stream_switch_slave_config_dma_4", aie2::mem_stream_switch_slave_config_dma_4}, + {"mem_stream_switch_slave_config_dma_5", aie2::mem_stream_switch_slave_config_dma_5}, + {"mem_stream_switch_slave_config_tile_ctrl", aie2::mem_stream_switch_slave_config_tile_ctrl}, + {"mem_stream_switch_slave_config_south_0", aie2::mem_stream_switch_slave_config_south_0}, + {"mem_stream_switch_slave_config_south_1", aie2::mem_stream_switch_slave_config_south_1}, + {"mem_stream_switch_slave_config_south_2", aie2::mem_stream_switch_slave_config_south_2}, + {"mem_stream_switch_slave_config_south_3", aie2::mem_stream_switch_slave_config_south_3}, + {"mem_stream_switch_slave_config_south_4", aie2::mem_stream_switch_slave_config_south_4}, + {"mem_stream_switch_slave_config_south_5", aie2::mem_stream_switch_slave_config_south_5}, + {"mem_stream_switch_slave_config_north_0", aie2::mem_stream_switch_slave_config_north_0}, + {"mem_stream_switch_slave_config_north_1", aie2::mem_stream_switch_slave_config_north_1}, + {"mem_stream_switch_slave_config_north_2", aie2::mem_stream_switch_slave_config_north_2}, + {"mem_stream_switch_slave_config_north_3", aie2::mem_stream_switch_slave_config_north_3}, + {"mem_stream_switch_slave_config_trace", aie2::mem_stream_switch_slave_config_trace}, + {"mem_stream_switch_slave_dma_0_slot0", aie2::mem_stream_switch_slave_dma_0_slot0}, + {"mem_stream_switch_slave_dma_0_slot1", aie2::mem_stream_switch_slave_dma_0_slot1}, + {"mem_stream_switch_slave_dma_0_slot2", aie2::mem_stream_switch_slave_dma_0_slot2}, + {"mem_stream_switch_slave_dma_0_slot3", aie2::mem_stream_switch_slave_dma_0_slot3}, + {"mem_stream_switch_slave_dma_1_slot0", aie2::mem_stream_switch_slave_dma_1_slot0}, + {"mem_stream_switch_slave_dma_1_slot1", aie2::mem_stream_switch_slave_dma_1_slot1}, + {"mem_stream_switch_slave_dma_1_slot2", aie2::mem_stream_switch_slave_dma_1_slot2}, + {"mem_stream_switch_slave_dma_1_slot3", aie2::mem_stream_switch_slave_dma_1_slot3}, + {"mem_stream_switch_slave_dma_2_slot0", aie2::mem_stream_switch_slave_dma_2_slot0}, + {"mem_stream_switch_slave_dma_2_slot1", aie2::mem_stream_switch_slave_dma_2_slot1}, + {"mem_stream_switch_slave_dma_2_slot2", aie2::mem_stream_switch_slave_dma_2_slot2}, + {"mem_stream_switch_slave_dma_2_slot3", aie2::mem_stream_switch_slave_dma_2_slot3}, + {"mem_stream_switch_slave_dma_3_slot0", aie2::mem_stream_switch_slave_dma_3_slot0}, + {"mem_stream_switch_slave_dma_3_slot1", aie2::mem_stream_switch_slave_dma_3_slot1}, + {"mem_stream_switch_slave_dma_3_slot2", aie2::mem_stream_switch_slave_dma_3_slot2}, + {"mem_stream_switch_slave_dma_3_slot3", aie2::mem_stream_switch_slave_dma_3_slot3}, + {"mem_stream_switch_slave_dma_4_slot0", aie2::mem_stream_switch_slave_dma_4_slot0}, + {"mem_stream_switch_slave_dma_4_slot1", aie2::mem_stream_switch_slave_dma_4_slot1}, + {"mem_stream_switch_slave_dma_4_slot2", aie2::mem_stream_switch_slave_dma_4_slot2}, + {"mem_stream_switch_slave_dma_4_slot3", aie2::mem_stream_switch_slave_dma_4_slot3}, + {"mem_stream_switch_slave_dma_5_slot0", aie2::mem_stream_switch_slave_dma_5_slot0}, + {"mem_stream_switch_slave_dma_5_slot1", aie2::mem_stream_switch_slave_dma_5_slot1}, + {"mem_stream_switch_slave_dma_5_slot2", aie2::mem_stream_switch_slave_dma_5_slot2}, + {"mem_stream_switch_slave_dma_5_slot3", aie2::mem_stream_switch_slave_dma_5_slot3}, + {"mem_stream_switch_slave_tile_ctrl_slot0", aie2::mem_stream_switch_slave_tile_ctrl_slot0}, + {"mem_stream_switch_slave_tile_ctrl_slot1", aie2::mem_stream_switch_slave_tile_ctrl_slot1}, + {"mem_stream_switch_slave_tile_ctrl_slot2", aie2::mem_stream_switch_slave_tile_ctrl_slot2}, + {"mem_stream_switch_slave_tile_ctrl_slot3", aie2::mem_stream_switch_slave_tile_ctrl_slot3}, + {"mem_stream_switch_slave_south_0_slot0", aie2::mem_stream_switch_slave_south_0_slot0}, + {"mem_stream_switch_slave_south_0_slot1", aie2::mem_stream_switch_slave_south_0_slot1}, + {"mem_stream_switch_slave_south_0_slot2", aie2::mem_stream_switch_slave_south_0_slot2}, + {"mem_stream_switch_slave_south_0_slot3", aie2::mem_stream_switch_slave_south_0_slot3}, + {"mem_stream_switch_slave_south_1_slot0", aie2::mem_stream_switch_slave_south_1_slot0}, + {"mem_stream_switch_slave_south_1_slot1", aie2::mem_stream_switch_slave_south_1_slot1}, + {"mem_stream_switch_slave_south_1_slot2", aie2::mem_stream_switch_slave_south_1_slot2}, + {"mem_stream_switch_slave_south_1_slot3", aie2::mem_stream_switch_slave_south_1_slot3}, + {"mem_stream_switch_slave_south_2_slot0", aie2::mem_stream_switch_slave_south_2_slot0}, + {"mem_stream_switch_slave_south_2_slot1", aie2::mem_stream_switch_slave_south_2_slot1}, + {"mem_stream_switch_slave_south_2_slot2", aie2::mem_stream_switch_slave_south_2_slot2}, + {"mem_stream_switch_slave_south_2_slot3", aie2::mem_stream_switch_slave_south_2_slot3}, + {"mem_stream_switch_slave_south_3_slot0", aie2::mem_stream_switch_slave_south_3_slot0}, + {"mem_stream_switch_slave_south_3_slot1", aie2::mem_stream_switch_slave_south_3_slot1}, + {"mem_stream_switch_slave_south_3_slot2", aie2::mem_stream_switch_slave_south_3_slot2}, + {"mem_stream_switch_slave_south_3_slot3", aie2::mem_stream_switch_slave_south_3_slot3}, + {"mem_stream_switch_slave_south_4_slot0", aie2::mem_stream_switch_slave_south_4_slot0}, + {"mem_stream_switch_slave_south_4_slot1", aie2::mem_stream_switch_slave_south_4_slot1}, + {"mem_stream_switch_slave_south_4_slot2", aie2::mem_stream_switch_slave_south_4_slot2}, + {"mem_stream_switch_slave_south_4_slot3", aie2::mem_stream_switch_slave_south_4_slot3}, + {"mem_stream_switch_slave_south_5_slot0", aie2::mem_stream_switch_slave_south_5_slot0}, + {"mem_stream_switch_slave_south_5_slot1", aie2::mem_stream_switch_slave_south_5_slot1}, + {"mem_stream_switch_slave_south_5_slot2", aie2::mem_stream_switch_slave_south_5_slot2}, + {"mem_stream_switch_slave_south_5_slot3", aie2::mem_stream_switch_slave_south_5_slot3}, + {"mem_stream_switch_slave_north_0_slot0", aie2::mem_stream_switch_slave_north_0_slot0}, + {"mem_stream_switch_slave_north_0_slot1", aie2::mem_stream_switch_slave_north_0_slot1}, + {"mem_stream_switch_slave_north_0_slot2", aie2::mem_stream_switch_slave_north_0_slot2}, + {"mem_stream_switch_slave_north_0_slot3", aie2::mem_stream_switch_slave_north_0_slot3}, + {"mem_stream_switch_slave_north_1_slot0", aie2::mem_stream_switch_slave_north_1_slot0}, + {"mem_stream_switch_slave_north_1_slot1", aie2::mem_stream_switch_slave_north_1_slot1}, + {"mem_stream_switch_slave_north_1_slot2", aie2::mem_stream_switch_slave_north_1_slot2}, + {"mem_stream_switch_slave_north_1_slot3", aie2::mem_stream_switch_slave_north_1_slot3}, + {"mem_stream_switch_slave_north_2_slot0", aie2::mem_stream_switch_slave_north_2_slot0}, + {"mem_stream_switch_slave_north_2_slot1", aie2::mem_stream_switch_slave_north_2_slot1}, + {"mem_stream_switch_slave_north_2_slot2", aie2::mem_stream_switch_slave_north_2_slot2}, + {"mem_stream_switch_slave_north_2_slot3", aie2::mem_stream_switch_slave_north_2_slot3}, + {"mem_stream_switch_slave_north_3_slot0", aie2::mem_stream_switch_slave_north_3_slot0}, + {"mem_stream_switch_slave_north_3_slot1", aie2::mem_stream_switch_slave_north_3_slot1}, + {"mem_stream_switch_slave_north_3_slot2", aie2::mem_stream_switch_slave_north_3_slot2}, + {"mem_stream_switch_slave_north_3_slot3", aie2::mem_stream_switch_slave_north_3_slot3}, + {"mem_stream_switch_slave_trace_slot0", aie2::mem_stream_switch_slave_trace_slot0}, + {"mem_stream_switch_slave_trace_slot1", aie2::mem_stream_switch_slave_trace_slot1}, + {"mem_stream_switch_slave_trace_slot2", aie2::mem_stream_switch_slave_trace_slot2}, + {"mem_stream_switch_slave_trace_slot3", aie2::mem_stream_switch_slave_trace_slot3}, + {"mem_stream_switch_deterministic_merge_arb0_slave0_1", aie2::mem_stream_switch_deterministic_merge_arb0_slave0_1}, + {"mem_stream_switch_deterministic_merge_arb0_slave2_3", aie2::mem_stream_switch_deterministic_merge_arb0_slave2_3}, + {"mem_stream_switch_deterministic_merge_arb0_ctrl", aie2::mem_stream_switch_deterministic_merge_arb0_ctrl}, + {"mem_stream_switch_deterministic_merge_arb1_slave0_1", aie2::mem_stream_switch_deterministic_merge_arb1_slave0_1}, + {"mem_stream_switch_deterministic_merge_arb1_slave2_3", aie2::mem_stream_switch_deterministic_merge_arb1_slave2_3}, + {"mem_stream_switch_deterministic_merge_arb1_ctrl", aie2::mem_stream_switch_deterministic_merge_arb1_ctrl}, + {"mem_stream_switch_event_port_selection_0", aie2::mem_stream_switch_event_port_selection_0}, + {"mem_stream_switch_event_port_selection_1", aie2::mem_stream_switch_event_port_selection_1}, + {"mem_stream_switch_parity_status", aie2::mem_stream_switch_parity_status}, + {"mem_stream_switch_parity_injection", aie2::mem_stream_switch_parity_injection}, + {"mem_tile_control_packet_handler_status", aie2::mem_tile_control_packet_handler_status}, + {"mem_stream_switch_adaptive_clock_gate_status", aie2::mem_stream_switch_adaptive_clock_gate_status}, + {"mem_stream_switch_adaptive_clock_gate_abort_period", aie2::mem_stream_switch_adaptive_clock_gate_abort_period}, + {"mem_lock0_value", aie2::mem_lock0_value}, + {"mem_lock1_value", aie2::mem_lock1_value}, + {"mem_lock2_value", aie2::mem_lock2_value}, + {"mem_lock3_value", aie2::mem_lock3_value}, + {"mem_lock4_value", aie2::mem_lock4_value}, + {"mem_lock5_value", aie2::mem_lock5_value}, + {"mem_lock6_value", aie2::mem_lock6_value}, + {"mem_lock7_value", aie2::mem_lock7_value}, + {"mem_lock8_value", aie2::mem_lock8_value}, + {"mem_lock9_value", aie2::mem_lock9_value}, + {"mem_lock10_value", aie2::mem_lock10_value}, + {"mem_lock11_value", aie2::mem_lock11_value}, + {"mem_lock12_value", aie2::mem_lock12_value}, + {"mem_lock13_value", aie2::mem_lock13_value}, + {"mem_lock14_value", aie2::mem_lock14_value}, + {"mem_lock15_value", aie2::mem_lock15_value}, + {"mem_lock16_value", aie2::mem_lock16_value}, + {"mem_lock17_value", aie2::mem_lock17_value}, + {"mem_lock18_value", aie2::mem_lock18_value}, + {"mem_lock19_value", aie2::mem_lock19_value}, + {"mem_lock20_value", aie2::mem_lock20_value}, + {"mem_lock21_value", aie2::mem_lock21_value}, + {"mem_lock22_value", aie2::mem_lock22_value}, + {"mem_lock23_value", aie2::mem_lock23_value}, + {"mem_lock24_value", aie2::mem_lock24_value}, + {"mem_lock25_value", aie2::mem_lock25_value}, + {"mem_lock26_value", aie2::mem_lock26_value}, + {"mem_lock27_value", aie2::mem_lock27_value}, + {"mem_lock28_value", aie2::mem_lock28_value}, + {"mem_lock29_value", aie2::mem_lock29_value}, + {"mem_lock30_value", aie2::mem_lock30_value}, + {"mem_lock31_value", aie2::mem_lock31_value}, + {"mem_lock32_value", aie2::mem_lock32_value}, + {"mem_lock33_value", aie2::mem_lock33_value}, + {"mem_lock34_value", aie2::mem_lock34_value}, + {"mem_lock35_value", aie2::mem_lock35_value}, + {"mem_lock36_value", aie2::mem_lock36_value}, + {"mem_lock37_value", aie2::mem_lock37_value}, + {"mem_lock38_value", aie2::mem_lock38_value}, + {"mem_lock39_value", aie2::mem_lock39_value}, + {"mem_lock40_value", aie2::mem_lock40_value}, + {"mem_lock41_value", aie2::mem_lock41_value}, + {"mem_lock42_value", aie2::mem_lock42_value}, + {"mem_lock43_value", aie2::mem_lock43_value}, + {"mem_lock44_value", aie2::mem_lock44_value}, + {"mem_lock45_value", aie2::mem_lock45_value}, + {"mem_lock46_value", aie2::mem_lock46_value}, + {"mem_lock47_value", aie2::mem_lock47_value}, + {"mem_lock48_value", aie2::mem_lock48_value}, + {"mem_lock49_value", aie2::mem_lock49_value}, + {"mem_lock50_value", aie2::mem_lock50_value}, + {"mem_lock51_value", aie2::mem_lock51_value}, + {"mem_lock52_value", aie2::mem_lock52_value}, + {"mem_lock53_value", aie2::mem_lock53_value}, + {"mem_lock54_value", aie2::mem_lock54_value}, + {"mem_lock55_value", aie2::mem_lock55_value}, + {"mem_lock56_value", aie2::mem_lock56_value}, + {"mem_lock57_value", aie2::mem_lock57_value}, + {"mem_lock58_value", aie2::mem_lock58_value}, + {"mem_lock59_value", aie2::mem_lock59_value}, + {"mem_lock60_value", aie2::mem_lock60_value}, + {"mem_lock61_value", aie2::mem_lock61_value}, + {"mem_lock62_value", aie2::mem_lock62_value}, + {"mem_lock63_value", aie2::mem_lock63_value}, + {"mem_locks_event_selection_0", aie2::mem_locks_event_selection_0}, + {"mem_locks_event_selection_1", aie2::mem_locks_event_selection_1}, + {"mem_locks_event_selection_2", aie2::mem_locks_event_selection_2}, + {"mem_locks_event_selection_3", aie2::mem_locks_event_selection_3}, + {"mem_locks_event_selection_4", aie2::mem_locks_event_selection_4}, + {"mem_locks_event_selection_5", aie2::mem_locks_event_selection_5}, + {"mem_locks_event_selection_6", aie2::mem_locks_event_selection_6}, + {"mem_locks_event_selection_7", aie2::mem_locks_event_selection_7}, + {"mem_locks_overflow_0", aie2::mem_locks_overflow_0}, + {"mem_locks_overflow_1", aie2::mem_locks_overflow_1}, + {"mem_locks_underflow_0", aie2::mem_locks_underflow_0}, + {"mem_locks_underflow_1", aie2::mem_locks_underflow_1}, + {"mem_lock_request", aie2::mem_lock_request}, + {"mem_module_clock_control", aie2::mem_module_clock_control}, + {"mem_module_reset_control", aie2::mem_module_reset_control}, + {"shim_lock_step_size", aie2::shim_lock_step_size}, + {"shim_dma_bd_step_size", aie2::shim_dma_bd_step_size}, + {"shim_dma_s2mm_step_size", aie2::shim_dma_s2mm_step_size}, + {"shim_lock0_value", aie2::shim_lock0_value}, + {"shim_lock1_value", aie2::shim_lock1_value}, + {"shim_lock2_value", aie2::shim_lock2_value}, + {"shim_lock3_value", aie2::shim_lock3_value}, + {"shim_lock4_value", aie2::shim_lock4_value}, + {"shim_lock5_value", aie2::shim_lock5_value}, + {"shim_lock6_value", aie2::shim_lock6_value}, + {"shim_lock7_value", aie2::shim_lock7_value}, + {"shim_lock8_value", aie2::shim_lock8_value}, + {"shim_lock9_value", aie2::shim_lock9_value}, + {"shim_lock10_value", aie2::shim_lock10_value}, + {"shim_lock11_value", aie2::shim_lock11_value}, + {"shim_lock12_value", aie2::shim_lock12_value}, + {"shim_lock13_value", aie2::shim_lock13_value}, + {"shim_lock14_value", aie2::shim_lock14_value}, + {"shim_lock15_value", aie2::shim_lock15_value}, + {"shim_dma_bd0_0", aie2::shim_dma_bd0_0}, + {"shim_dma_bd0_1", aie2::shim_dma_bd0_1}, + {"shim_dma_bd0_2", aie2::shim_dma_bd0_2}, + {"shim_dma_bd0_3", aie2::shim_dma_bd0_3}, + {"shim_dma_bd0_4", aie2::shim_dma_bd0_4}, + {"shim_dma_bd0_5", aie2::shim_dma_bd0_5}, + {"shim_dma_bd0_6", aie2::shim_dma_bd0_6}, + {"shim_dma_bd0_7", aie2::shim_dma_bd0_7}, + {"shim_dma_bd1_0", aie2::shim_dma_bd1_0}, + {"shim_dma_bd1_1", aie2::shim_dma_bd1_1}, + {"shim_dma_bd1_2", aie2::shim_dma_bd1_2}, + {"shim_dma_bd1_3", aie2::shim_dma_bd1_3}, + {"shim_dma_bd1_4", aie2::shim_dma_bd1_4}, + {"shim_dma_bd1_5", aie2::shim_dma_bd1_5}, + {"shim_dma_bd1_6", aie2::shim_dma_bd1_6}, + {"shim_dma_bd1_7", aie2::shim_dma_bd1_7}, + {"shim_dma_bd2_0", aie2::shim_dma_bd2_0}, + {"shim_dma_bd2_1", aie2::shim_dma_bd2_1}, + {"shim_dma_bd2_2", aie2::shim_dma_bd2_2}, + {"shim_dma_bd2_3", aie2::shim_dma_bd2_3}, + {"shim_dma_bd2_4", aie2::shim_dma_bd2_4}, + {"shim_dma_bd2_5", aie2::shim_dma_bd2_5}, + {"shim_dma_bd2_6", aie2::shim_dma_bd2_6}, + {"shim_dma_bd2_7", aie2::shim_dma_bd2_7}, + {"shim_dma_bd3_0", aie2::shim_dma_bd3_0}, + {"shim_dma_bd3_1", aie2::shim_dma_bd3_1}, + {"shim_dma_bd3_2", aie2::shim_dma_bd3_2}, + {"shim_dma_bd3_3", aie2::shim_dma_bd3_3}, + {"shim_dma_bd3_4", aie2::shim_dma_bd3_4}, + {"shim_dma_bd3_5", aie2::shim_dma_bd3_5}, + {"shim_dma_bd3_6", aie2::shim_dma_bd3_6}, + {"shim_dma_bd3_7", aie2::shim_dma_bd3_7}, + {"shim_dma_bd4_0", aie2::shim_dma_bd4_0}, + {"shim_dma_bd4_1", aie2::shim_dma_bd4_1}, + {"shim_dma_bd4_2", aie2::shim_dma_bd4_2}, + {"shim_dma_bd4_3", aie2::shim_dma_bd4_3}, + {"shim_dma_bd4_4", aie2::shim_dma_bd4_4}, + {"shim_dma_bd4_5", aie2::shim_dma_bd4_5}, + {"shim_dma_bd4_6", aie2::shim_dma_bd4_6}, + {"shim_dma_bd4_7", aie2::shim_dma_bd4_7}, + {"shim_dma_bd5_0", aie2::shim_dma_bd5_0}, + {"shim_dma_bd5_1", aie2::shim_dma_bd5_1}, + {"shim_dma_bd5_2", aie2::shim_dma_bd5_2}, + {"shim_dma_bd5_3", aie2::shim_dma_bd5_3}, + {"shim_dma_bd5_4", aie2::shim_dma_bd5_4}, + {"shim_dma_bd5_5", aie2::shim_dma_bd5_5}, + {"shim_dma_bd5_6", aie2::shim_dma_bd5_6}, + {"shim_dma_bd5_7", aie2::shim_dma_bd5_7}, + {"shim_dma_bd6_0", aie2::shim_dma_bd6_0}, + {"shim_dma_bd6_1", aie2::shim_dma_bd6_1}, + {"shim_dma_bd6_2", aie2::shim_dma_bd6_2}, + {"shim_dma_bd6_3", aie2::shim_dma_bd6_3}, + {"shim_dma_bd6_4", aie2::shim_dma_bd6_4}, + {"shim_dma_bd6_5", aie2::shim_dma_bd6_5}, + {"shim_dma_bd6_6", aie2::shim_dma_bd6_6}, + {"shim_dma_bd6_7", aie2::shim_dma_bd6_7}, + {"shim_dma_bd7_0", aie2::shim_dma_bd7_0}, + {"shim_dma_bd7_1", aie2::shim_dma_bd7_1}, + {"shim_dma_bd7_2", aie2::shim_dma_bd7_2}, + {"shim_dma_bd7_3", aie2::shim_dma_bd7_3}, + {"shim_dma_bd7_4", aie2::shim_dma_bd7_4}, + {"shim_dma_bd7_5", aie2::shim_dma_bd7_5}, + {"shim_dma_bd7_6", aie2::shim_dma_bd7_6}, + {"shim_dma_bd7_7", aie2::shim_dma_bd7_7}, + {"shim_dma_bd8_0", aie2::shim_dma_bd8_0}, + {"shim_dma_bd8_1", aie2::shim_dma_bd8_1}, + {"shim_dma_bd8_2", aie2::shim_dma_bd8_2}, + {"shim_dma_bd8_3", aie2::shim_dma_bd8_3}, + {"shim_dma_bd8_4", aie2::shim_dma_bd8_4}, + {"shim_dma_bd8_5", aie2::shim_dma_bd8_5}, + {"shim_dma_bd8_6", aie2::shim_dma_bd8_6}, + {"shim_dma_bd8_7", aie2::shim_dma_bd8_7}, + {"shim_dma_bd9_0", aie2::shim_dma_bd9_0}, + {"shim_dma_bd9_1", aie2::shim_dma_bd9_1}, + {"shim_dma_bd9_2", aie2::shim_dma_bd9_2}, + {"shim_dma_bd9_3", aie2::shim_dma_bd9_3}, + {"shim_dma_bd9_4", aie2::shim_dma_bd9_4}, + {"shim_dma_bd9_5", aie2::shim_dma_bd9_5}, + {"shim_dma_bd9_6", aie2::shim_dma_bd9_6}, + {"shim_dma_bd9_7", aie2::shim_dma_bd9_7}, + {"shim_dma_bd10_0", aie2::shim_dma_bd10_0}, + {"shim_dma_bd10_1", aie2::shim_dma_bd10_1}, + {"shim_dma_bd10_2", aie2::shim_dma_bd10_2}, + {"shim_dma_bd10_3", aie2::shim_dma_bd10_3}, + {"shim_dma_bd10_4", aie2::shim_dma_bd10_4}, + {"shim_dma_bd10_5", aie2::shim_dma_bd10_5}, + {"shim_dma_bd10_6", aie2::shim_dma_bd10_6}, + {"shim_dma_bd10_7", aie2::shim_dma_bd10_7}, + {"shim_dma_bd11_0", aie2::shim_dma_bd11_0}, + {"shim_dma_bd11_1", aie2::shim_dma_bd11_1}, + {"shim_dma_bd11_2", aie2::shim_dma_bd11_2}, + {"shim_dma_bd11_3", aie2::shim_dma_bd11_3}, + {"shim_dma_bd11_4", aie2::shim_dma_bd11_4}, + {"shim_dma_bd11_5", aie2::shim_dma_bd11_5}, + {"shim_dma_bd11_6", aie2::shim_dma_bd11_6}, + {"shim_dma_bd11_7", aie2::shim_dma_bd11_7}, + {"shim_dma_bd12_0", aie2::shim_dma_bd12_0}, + {"shim_dma_bd12_1", aie2::shim_dma_bd12_1}, + {"shim_dma_bd12_2", aie2::shim_dma_bd12_2}, + {"shim_dma_bd12_3", aie2::shim_dma_bd12_3}, + {"shim_dma_bd12_4", aie2::shim_dma_bd12_4}, + {"shim_dma_bd12_5", aie2::shim_dma_bd12_5}, + {"shim_dma_bd12_6", aie2::shim_dma_bd12_6}, + {"shim_dma_bd12_7", aie2::shim_dma_bd12_7}, + {"shim_dma_bd13_0", aie2::shim_dma_bd13_0}, + {"shim_dma_bd13_1", aie2::shim_dma_bd13_1}, + {"shim_dma_bd13_2", aie2::shim_dma_bd13_2}, + {"shim_dma_bd13_3", aie2::shim_dma_bd13_3}, + {"shim_dma_bd13_4", aie2::shim_dma_bd13_4}, + {"shim_dma_bd13_5", aie2::shim_dma_bd13_5}, + {"shim_dma_bd13_6", aie2::shim_dma_bd13_6}, + {"shim_dma_bd13_7", aie2::shim_dma_bd13_7}, + {"shim_dma_bd14_0", aie2::shim_dma_bd14_0}, + {"shim_dma_bd14_1", aie2::shim_dma_bd14_1}, + {"shim_dma_bd14_2", aie2::shim_dma_bd14_2}, + {"shim_dma_bd14_3", aie2::shim_dma_bd14_3}, + {"shim_dma_bd14_4", aie2::shim_dma_bd14_4}, + {"shim_dma_bd14_5", aie2::shim_dma_bd14_5}, + {"shim_dma_bd14_6", aie2::shim_dma_bd14_6}, + {"shim_dma_bd14_7", aie2::shim_dma_bd14_7}, + {"shim_dma_bd15_0", aie2::shim_dma_bd15_0}, + {"shim_dma_bd15_1", aie2::shim_dma_bd15_1}, + {"shim_dma_bd15_2", aie2::shim_dma_bd15_2}, + {"shim_dma_bd15_3", aie2::shim_dma_bd15_3}, + {"shim_dma_bd15_4", aie2::shim_dma_bd15_4}, + {"shim_dma_bd15_5", aie2::shim_dma_bd15_5}, + {"shim_dma_bd15_6", aie2::shim_dma_bd15_6}, + {"shim_dma_bd15_7", aie2::shim_dma_bd15_7}, + {"shim_dma_s2mm_0_ctrl", aie2::shim_dma_s2mm_0_ctrl}, + {"shim_dma_s2mm_0_task_queue", aie2::shim_dma_s2mm_0_task_queue}, + {"shim_dma_s2mm_status_0", aie2::shim_dma_s2mm_status_0}, + {"shim_dma_s2mm_status_1", aie2::shim_dma_s2mm_status_1}, + {"shim_dma_mm2s_status_0", aie2::shim_dma_mm2s_status_0}, + {"shim_dma_mm2s_status_1", aie2::shim_dma_mm2s_status_1}, + {"shim_performance_control0", aie2::shim_performance_control0}, + {"shim_performance_control1", aie2::shim_performance_control1}, + {"shim_performance_counter0", aie2::shim_performance_counter0}, + {"shim_performance_counter1", aie2::shim_performance_counter1}, + {"shim_performance_counter0_event_value", aie2::shim_performance_counter0_event_value}, + {"shim_performance_counter1_event_value", aie2::shim_performance_counter1_event_value}, + {"shim_event_generate", aie2::shim_event_generate}, + {"shim_event_broadcast_a_0", aie2::shim_event_broadcast_a_0}, + {"shim_event_broadcast_a_1", aie2::shim_event_broadcast_a_1}, + {"shim_event_broadcast_a_2", aie2::shim_event_broadcast_a_2}, + {"shim_event_broadcast_a_3", aie2::shim_event_broadcast_a_3}, + {"shim_event_broadcast_a_4", aie2::shim_event_broadcast_a_4}, + {"shim_event_broadcast_a_5", aie2::shim_event_broadcast_a_5}, + {"shim_event_broadcast_a_6", aie2::shim_event_broadcast_a_6}, + {"shim_event_broadcast_a_7", aie2::shim_event_broadcast_a_7}, + {"shim_event_broadcast_a_8", aie2::shim_event_broadcast_a_8}, + {"shim_event_broadcast_a_9", aie2::shim_event_broadcast_a_9}, + {"shim_event_broadcast_a_10", aie2::shim_event_broadcast_a_10}, + {"shim_event_broadcast_a_11", aie2::shim_event_broadcast_a_11}, + {"shim_event_broadcast_a_12", aie2::shim_event_broadcast_a_12}, + {"shim_event_broadcast_a_13", aie2::shim_event_broadcast_a_13}, + {"shim_event_broadcast_a_14", aie2::shim_event_broadcast_a_14}, + {"shim_event_broadcast_a_15", aie2::shim_event_broadcast_a_15}, + {"shim_event_broadcast_a_block_south_set", aie2::shim_event_broadcast_a_block_south_set}, + {"shim_event_broadcast_a_block_south_clr", aie2::shim_event_broadcast_a_block_south_clr}, + {"shim_event_broadcast_a_block_south_value", aie2::shim_event_broadcast_a_block_south_value}, + {"shim_event_broadcast_a_block_west_set", aie2::shim_event_broadcast_a_block_west_set}, + {"shim_event_broadcast_a_block_west_clr", aie2::shim_event_broadcast_a_block_west_clr}, + {"shim_event_broadcast_a_block_west_value", aie2::shim_event_broadcast_a_block_west_value}, + {"shim_event_broadcast_a_block_north_set", aie2::shim_event_broadcast_a_block_north_set}, + {"shim_event_broadcast_a_block_north_clr", aie2::shim_event_broadcast_a_block_north_clr}, + {"shim_event_broadcast_a_block_north_value", aie2::shim_event_broadcast_a_block_north_value}, + {"shim_event_broadcast_a_block_east_set", aie2::shim_event_broadcast_a_block_east_set}, + {"shim_event_broadcast_a_block_east_clr", aie2::shim_event_broadcast_a_block_east_clr}, + {"shim_event_broadcast_a_block_east_value", aie2::shim_event_broadcast_a_block_east_value}, + {"shim_trace_control0", aie2::shim_trace_control0}, + {"shim_trace_control1", aie2::shim_trace_control1}, + {"shim_trace_status", aie2::shim_trace_status}, + {"shim_trace_event0", aie2::shim_trace_event0}, + {"shim_trace_event1", aie2::shim_trace_event1}, + {"shim_timer_trig_event_low_value", aie2::shim_timer_trig_event_low_value}, + {"shim_timer_trig_event_high_value", aie2::shim_timer_trig_event_high_value}, + {"shim_timer_low", aie2::shim_timer_low}, + {"shim_timer_high", aie2::shim_timer_high}, + {"shim_event_status0", aie2::shim_event_status0}, + {"shim_event_status1", aie2::shim_event_status1}, + {"shim_event_status2", aie2::shim_event_status2}, + {"shim_event_status3", aie2::shim_event_status3}, + {"shim_event_group_dma_enable", aie2::shim_event_group_dma_enable}, + {"shim_stream_switch_event_port_selection_0", aie2::shim_stream_switch_event_port_selection_0}, + {"shim_stream_switch_event_port_selection_1", aie2::shim_stream_switch_event_port_selection_1} + }; + } + + void populateRegValueToNameMap() { + regValueToName= { + {0x000940a0, "mem_event_broadcast_b_block_west_set"}, + {0x0001d220, "shim_dma_s2mm_status_0"}, + {0x0001d224, "shim_dma_s2mm_status_1"}, + {0x000a061c, "mem_dma_s2mm_3_start_queue"}, + {0x000c0230, "mem_lock35_value"}, + {0x000a0614, "mem_dma_s2mm_2_start_queue"}, + {0x000340f4, "shim_timer_trig_event_high_value"}, + {0x00034068, "shim_event_broadcast_a_block_west_value"}, + {0x0001d10c, "mm_dma_bd8_3"}, + {0x000b0228, "mem_stream_switch_slave_dma_2_slot2"}, + {0x0001d104, "mm_dma_bd8_1"}, + {0x000140e0, "shim_lock14_value"}, + {0x0001d100, "mm_dma_bd8_0"}, + {0x0003f2d4, "cm_stream_switch_slave_west_2_slot1"}, + {0x0003f2d0, "cm_stream_switch_slave_west_2_slot0"}, + {0x0003f2dc, "cm_stream_switch_slave_west_2_slot3"}, + {0x0003f2d8, "cm_stream_switch_slave_west_2_slot2"}, + {0x000c0000, "mem_lock0_value"}, + {0x000c0130, "mem_lock19_value"}, + {0x000a0254, "mem_dma_bd18_5"}, + {0x000a0250, "mem_dma_bd18_4"}, + {0x000a025c, "mem_dma_bd18_7"}, + {0x000a0258, "mem_dma_bd18_6"}, + {0x000a0244, "mem_dma_bd18_1"}, + {0x000a0240, "mem_dma_bd18_0"}, + {0x000a024c, "mem_dma_bd18_3"}, + {0x000a0248, "mem_dma_bd18_2"}, + {0x000c02c0, "mem_lock44_value"}, + {0x0001de0c, "mm_dma_s2mm_1_start_queue"}, + {0x00034508, "cm_event_group_core_stall_enable"}, + {0x00094214, "mem_event_status5"}, + {0x00094200, "mem_event_status0"}, + {0x00094204, "mem_event_status1"}, + {0x00094208, "mem_event_status2"}, + {0x0009420c, "mem_event_status3"}, + {0x0003ff38, "cm_stream_switch_adaptive_clock_gate_abort_period"}, + {0x00094500, "mem_event_group_0_enable"}, + {0x0003f104, "cm_stream_switch_slave_config_dma_0"}, + {0x000c01c0, "mem_lock28_value"}, + {0x000a0624, "mem_dma_s2mm_4_start_queue"}, + {0x00014514, "mm_event_group_error_enable"}, + {0x0001f0b0, "mm_lock11_value"}, + {0x000c00c0, "mem_lock12_value"}, + {0x0001d200, "shim_dma_s2mm_0_ctrl"}, + {0x00014074, "mm_event_broadcast_block_north_clr"}, + {0x0001d084, "mm_dma_bd4_1"}, + {0x000340f0, "cm_timer_trig_event_low_value"}, + {0x00031080, "shim_performance_counter0_event_value"}, + {0x000b02d0, "mem_stream_switch_slave_north_0_slot0"}, + {0x000b02d4, "mem_stream_switch_slave_north_0_slot1"}, + {0x000b02d8, "mem_stream_switch_slave_north_0_slot2"}, + {0x000b02dc, "mem_stream_switch_slave_north_0_slot3"}, + {0x0003f278, "cm_stream_switch_slave_south_2_slot2"}, + {0x0003f27c, "cm_stream_switch_slave_south_2_slot3"}, + {0x0003f270, "cm_stream_switch_slave_south_2_slot0"}, + {0x0003f274, "cm_stream_switch_slave_south_2_slot1"}, + {0x0001f050, "mm_lock5_value"}, + {0x00060010, "cm_module_reset_control"}, + {0x000940f8, "mem_timer_low"}, + {0x0001d1f0, "mm_dma_bd15_4"}, + {0x0001d1f4, "mm_dma_bd15_5"}, + {0x000a063c, "mem_dma_mm2s_1_start_queue"}, + {0x0001d1e0, "mm_dma_bd15_0"}, + {0x0001d1e4, "mm_dma_bd15_1"}, + {0x0001d1e8, "mm_dma_bd15_2"}, + {0x0001d1ec, "mm_dma_bd15_3"}, + {0x00094400, "mem_combo_event_inputs"}, + {0x0003f100, "cm_stream_switch_slave_config_aie_core0"}, + {0x000c0200, "mem_lock32_value"}, + {0x000340d8, "shim_trace_status"}, + {0x00014070, "mm_event_broadcast_block_north_set"}, + {0x0001d160, "mm_dma_bd11_0"}, + {0x0001d164, "mm_dma_bd11_1"}, + {0x0001d168, "mm_dma_bd11_2"}, + {0x0001d16c, "mm_dma_bd11_3"}, + {0x0001d170, "mm_dma_bd11_4"}, + {0x0001d174, "mm_dma_bd11_5"}, + {0x0001d1b0, "mm_dma_bd13_4"}, + {0x0001d1b4, "mm_dma_bd13_5"}, + {0x0001d1a8, "mm_dma_bd13_2"}, + {0x0001d1ac, "mm_dma_bd13_3"}, + {0x0001d1a0, "mm_dma_bd13_0"}, + {0x0001d1a4, "mm_dma_bd13_1"}, + {0x0009422c, "mem_reserved3"}, + {0x00094228, "mem_reserved2"}, + {0x00094224, "mem_reserved1"}, + {0x00094220, "mem_reserved0"}, + {0x000140e0, "mm_trace_event0"}, + {0x000140e4, "mm_trace_event1"}, + {0x000a0230, "mem_dma_bd17_4"}, + {0x000a0234, "mem_dma_bd17_5"}, + {0x000a0228, "mem_dma_bd17_2"}, + {0x000a022c, "mem_dma_bd17_3"}, + {0x000a0220, "mem_dma_bd17_0"}, + {0x000a0224, "mem_dma_bd17_1"}, + {0x000a01e0, "mem_dma_bd15_0"}, + {0x000a01e4, "mem_dma_bd15_1"}, + {0x000a01e8, "mem_dma_bd15_2"}, + {0x000a01ec, "mem_dma_bd15_3"}, + {0x000a01f0, "mem_dma_bd15_4"}, + {0x000a01f4, "mem_dma_bd15_5"}, + {0x000a01f8, "mem_dma_bd15_6"}, + {0x000a01fc, "mem_dma_bd15_7"}, + {0x000a06dc, "mem_dma_s2mm_fot_count_fifo_pop_5"}, + {0x000a06d8, "mem_dma_s2mm_fot_count_fifo_pop_4"}, + {0x000a06cc, "mem_dma_s2mm_fot_count_fifo_pop_1"}, + {0x0001f0d0, "mm_lock13_value"}, + {0x000a06d4, "mem_dma_s2mm_fot_count_fifo_pop_3"}, + {0x000a06d0, "mem_dma_s2mm_fot_count_fifo_pop_2"}, + {0x000b0800, "mem_stream_switch_deterministic_merge_arb0_slave0_1"}, + {0x0003f234, "cm_stream_switch_slave_tile_ctrl_slot1"}, + {0x0003f238, "cm_stream_switch_slave_tile_ctrl_slot2"}, + {0x0003f23c, "cm_stream_switch_slave_tile_ctrl_slot3"}, + {0x0003f14c, "cm_stream_switch_slave_config_east_0"}, + {0x0003f150, "cm_stream_switch_slave_config_east_1"}, + {0x0003f154, "cm_stream_switch_slave_config_east_2"}, + {0x0003f158, "cm_stream_switch_slave_config_east_3"}, + {0x000a01a8, "mem_dma_bd13_2"}, + {0x000a01ac, "mem_dma_bd13_3"}, + {0x000a01a0, "mem_dma_bd13_0"}, + {0x000a01a4, "mem_dma_bd13_1"}, + {0x000a01b8, "mem_dma_bd13_6"}, + {0x000a01bc, "mem_dma_bd13_7"}, + {0x000a01b0, "mem_dma_bd13_4"}, + {0x000a01b4, "mem_dma_bd13_5"}, + {0x000a0170, "mem_dma_bd11_4"}, + {0x000a0174, "mem_dma_bd11_5"}, + {0x000a0178, "mem_dma_bd11_6"}, + {0x000a017c, "mem_dma_bd11_7"}, + {0x000a0160, "mem_dma_bd11_0"}, + {0x000a0164, "mem_dma_bd11_1"}, + {0x000a0168, "mem_dma_bd11_2"}, + {0x000a016c, "mem_dma_bd11_3"}, + {0x000940fc, "mem_timer_high"}, + {0x0003f374, "cm_stream_switch_slave_aie_trace_slot1"}, + {0x0003f370, "cm_stream_switch_slave_aie_trace_slot0"}, + {0x0003f37c, "cm_stream_switch_slave_aie_trace_slot3"}, + {0x0003f378, "cm_stream_switch_slave_aie_trace_slot2"}, + {0x00031524, "cm_performance_counter1"}, + {0x00031520, "cm_performance_counter0"}, + {0x0003152c, "cm_performance_counter3"}, + {0x00031528, "cm_performance_counter2"}, + {0x000b0018, "mem_stream_switch_master_config_tile_ctrl"}, + {0x000940c8, "mem_event_broadcast_b_block_east_value"}, + {0x0003f2bc, "cm_stream_switch_slave_west_0_slot3"}, + {0x0003f2b8, "cm_stream_switch_slave_west_0_slot2"}, + {0x0003f2b4, "cm_stream_switch_slave_west_0_slot1"}, + {0x0003f2b0, "cm_stream_switch_slave_west_0_slot0"}, + {0x000940d4, "mem_trace_control1"}, + {0x000940d0, "mem_trace_control0"}, + {0x0001f030, "mm_lock3_value"}, + {0x00014028, "mm_event_broadcast6"}, + {0x0001402c, "mm_event_broadcast7"}, + {0x00034000, "cm_timer_control"}, + {0x00014018, "mm_event_broadcast2"}, + {0x00014040, "shim_lock4_value"}, + {0x0001401c, "mm_event_broadcast3"}, + {0x0001d0cc, "mm_dma_bd6_3"}, + {0x00014014, "mm_event_broadcast1"}, + {0x00014090, "shim_lock9_value"}, + {0x0003ff30, "cm_tile_control_packet_handler_status"}, + {0x00034030, "cm_event_broadcast8"}, + {0x00034034, "cm_event_broadcast9"}, + {0x0003f368, "cm_stream_switch_slave_east_3_slot2"}, + {0x00034024, "cm_event_broadcast5"}, + {0x0003f360, "cm_stream_switch_slave_east_3_slot0"}, + {0x0003f364, "cm_stream_switch_slave_east_3_slot1"}, + {0x00034010, "cm_event_broadcast0"}, + {0x00034014, "cm_event_broadcast1"}, + {0x00034018, "cm_event_broadcast2"}, + {0x0003401c, "cm_event_broadcast3"}, + {0x00091084, "mem_performance_counter1_event_value"}, + {0x000b0268, "mem_stream_switch_slave_tile_ctrl_slot2"}, + {0x000b026c, "mem_stream_switch_slave_tile_ctrl_slot3"}, + {0x0001d158, "shim_dma_bd10_6"}, + {0x0003f02c, "cm_stream_switch_master_config_west2"}, + {0x0003f030, "cm_stream_switch_master_config_west3"}, + {0x0003f024, "cm_stream_switch_master_config_west0"}, + {0x0003f028, "cm_stream_switch_master_config_west1"}, + {0x0003f144, "cm_stream_switch_slave_config_north_2"}, + {0x000a05c0, "mem_dma_bd46_0"}, + {0x000a05c4, "mem_dma_bd46_1"}, + {0x000a05c8, "mem_dma_bd46_2"}, + {0x000a05cc, "mem_dma_bd46_3"}, + {0x000a05d0, "mem_dma_bd46_4"}, + {0x000a05d4, "mem_dma_bd46_5"}, + {0x000a05d8, "mem_dma_bd46_6"}, + {0x000a05dc, "mem_dma_bd46_7"}, + {0x00014100, "mm_watchpoint0"}, + {0x00014104, "mm_watchpoint1"}, + {0x00094068, "mem_event_broadcast_a_block_west_value"}, + {0x0001de18, "mm_dma_mm2s_1_ctrl"}, + {0x000140f0, "mm_timer_trig_event_low_value"}, + {0x000b0808, "mem_stream_switch_deterministic_merge_arb0_ctrl"}, + {0x0003f28c, "cm_stream_switch_slave_south_3_slot3"}, + {0x0003f288, "cm_stream_switch_slave_south_3_slot2"}, + {0x000b0030, "mem_stream_switch_master_config_north1"}, + {0x000b002c, "mem_stream_switch_master_config_north0"}, + {0x000b0040, "mem_stream_switch_master_config_north5"}, + {0x000b003c, "mem_stream_switch_master_config_north4"}, + {0x000140d4, "mm_trace_control1"}, + {0x000140d0, "mm_trace_control0"}, + {0x00034078, "shim_event_broadcast_a_block_north_value"}, + {0x00034054, "shim_event_broadcast_a_block_south_clr"}, + {0x00094074, "mem_event_broadcast_a_block_north_clr"}, + {0x00014064, "mm_event_broadcast_block_west_clr"}, + {0x000c02e0, "mem_lock46_value"}, + {0x0001d114, "mm_dma_bd8_5"}, + {0x0001d110, "mm_dma_bd8_4"}, + {0x000b022c, "mem_stream_switch_slave_dma_2_slot3"}, + {0x0001d108, "mm_dma_bd8_2"}, + {0x000b0224, "mem_stream_switch_slave_dma_2_slot1"}, + {0x000b0220, "mem_stream_switch_slave_dma_2_slot0"}, + {0x0001de00, "mm_dma_s2mm_0_ctrl"}, + {0x0003158c, "cm_performance_counter3_event_value"}, + {0x00091088, "mem_performance_counter2_event_value"}, + {0x0003f108, "cm_stream_switch_slave_config_dma_1"}, + {0x000a052c, "mem_dma_bd41_3"}, + {0x000a0528, "mem_dma_bd41_2"}, + {0x000a0524, "mem_dma_bd41_1"}, + {0x000a0520, "mem_dma_bd41_0"}, + {0x000a053c, "mem_dma_bd41_7"}, + {0x000a0538, "mem_dma_bd41_6"}, + {0x000a0534, "mem_dma_bd41_5"}, + {0x000a0530, "mem_dma_bd41_4"}, + {0x000a0574, "mem_dma_bd43_5"}, + {0x000a0570, "mem_dma_bd43_4"}, + {0x000a057c, "mem_dma_bd43_7"}, + {0x000a0578, "mem_dma_bd43_6"}, + {0x000a0564, "mem_dma_bd43_1"}, + {0x000a0560, "mem_dma_bd43_0"}, + {0x000a056c, "mem_dma_bd43_3"}, + {0x000a0568, "mem_dma_bd43_2"}, + {0x000c0350, "mem_lock53_value"}, + {0x000140b0, "shim_lock11_value"}, + {0x000b0244, "mem_stream_switch_slave_dma_4_slot1"}, + {0x000b0240, "mem_stream_switch_slave_dma_4_slot0"}, + {0x000b024c, "mem_stream_switch_slave_dma_4_slot3"}, + {0x000b0248, "mem_stream_switch_slave_dma_4_slot2"}, + {0x000a05bc, "mem_dma_bd45_7"}, + {0x000a05b8, "mem_dma_bd45_6"}, + {0x000a05b4, "mem_dma_bd45_5"}, + {0x000a05b0, "mem_dma_bd45_4"}, + {0x000a05ac, "mem_dma_bd45_3"}, + {0x000a05a8, "mem_dma_bd45_2"}, + {0x000a05a4, "mem_dma_bd45_1"}, + {0x000a05a0, "mem_dma_bd45_0"}, + {0x00014050, "shim_lock5_value"}, + {0x00092110, "mem_ecc_scrubbing_event"}, + {0x00034084, "shim_event_broadcast_a_block_east_clr"}, + {0x0003f290, "cm_stream_switch_slave_south_4_slot0"}, + {0x0003f294, "cm_stream_switch_slave_south_4_slot1"}, + {0x0003f298, "cm_stream_switch_slave_south_4_slot2"}, + {0x0003f29c, "cm_stream_switch_slave_south_4_slot3"}, + {0x00094520, "mem_event_group_user_event_enable"}, + {0x00014000, "shim_lock0_value"}, + {0x00092000, "mem_checkbit_error_generation"}, + {0x00011000, "mm_performance_control0"}, + {0x00011008, "mm_performance_control1"}, + {0x0003f134, "cm_stream_switch_slave_config_west_2"}, + {0x0003f138, "cm_stream_switch_slave_config_west_3"}, + {0x0003f12c, "cm_stream_switch_slave_config_west_0"}, + {0x0003f130, "cm_stream_switch_slave_config_west_1"}, + {0x00014518, "mm_event_group_broadcast_enable"}, + {0x00034070, "shim_event_broadcast_a_block_north_set"}, + {0x00094210, "mem_event_status4"}, + {0x0001d1c4, "shim_dma_bd14_1"}, + {0x000a010c, "mem_dma_bd8_3"}, + {0x000a0108, "mem_dma_bd8_2"}, + {0x000a0104, "mem_dma_bd8_1"}, + {0x000a0100, "mem_dma_bd8_0"}, + {0x000a011c, "mem_dma_bd8_7"}, + {0x000a0118, "mem_dma_bd8_6"}, + {0x000a0114, "mem_dma_bd8_5"}, + {0x000a0110, "mem_dma_bd8_4"}, + {0x000a00c4, "mem_dma_bd6_1"}, + {0x000a00c0, "mem_dma_bd6_0"}, + {0x000a00cc, "mem_dma_bd6_3"}, + {0x000a00c8, "mem_dma_bd6_2"}, + {0x000a00d4, "mem_dma_bd6_5"}, + {0x000a00d0, "mem_dma_bd6_4"}, + {0x000a00dc, "mem_dma_bd6_7"}, + {0x000a00d8, "mem_dma_bd6_6"}, + {0x000940b0, "mem_event_broadcast_b_block_north_set"}, + {0x00096040, "mem_cssd_trigger"}, + {0x0001d0f0, "mm_dma_bd7_4"}, + {0x0001d0f4, "mm_dma_bd7_5"}, + {0x0001d0e0, "mm_dma_bd7_0"}, + {0x0001d0e4, "mm_dma_bd7_1"}, + {0x0001d0e8, "mm_dma_bd7_2"}, + {0x0001d0ec, "mm_dma_bd7_3"}, + {0x000b02f8, "mem_stream_switch_slave_north_2_slot2"}, + {0x000b02fc, "mem_stream_switch_slave_north_2_slot3"}, + {0x000b02f0, "mem_stream_switch_slave_north_2_slot0"}, + {0x000b02f4, "mem_stream_switch_slave_north_2_slot1"}, + {0x0001d0a8, "mm_dma_bd5_2"}, + {0x0001d0ac, "mm_dma_bd5_3"}, + {0x0001d0a0, "mm_dma_bd5_0"}, + {0x0001d0a4, "mm_dma_bd5_1"}, + {0x0001d0b0, "mm_dma_bd5_4"}, + {0x0001d0b4, "mm_dma_bd5_5"}, + {0x00094518, "mem_event_group_error_enable"}, + {0x0001f020, "mm_lock2_value"}, + {0x00034060, "shim_event_broadcast_a_block_west_set"}, + {0x000a0028, "mem_dma_bd1_2"}, + {0x000a002c, "mem_dma_bd1_3"}, + {0x000a0020, "mem_dma_bd1_0"}, + {0x000a0024, "mem_dma_bd1_1"}, + {0x000a0038, "mem_dma_bd1_6"}, + {0x000a003c, "mem_dma_bd1_7"}, + {0x000a0030, "mem_dma_bd1_4"}, + {0x000a0034, "mem_dma_bd1_5"}, + {0x000340d0, "shim_trace_control0"}, + {0x000340d4, "shim_trace_control1"}, + {0x000b0f00, "mem_stream_switch_event_port_selection_0"}, + {0x000b0f04, "mem_stream_switch_event_port_selection_1"}, + {0x0001d068, "mm_dma_bd3_2"}, + {0x0001d06c, "mm_dma_bd3_3"}, + {0x0001d070, "mm_dma_bd3_4"}, + {0x0001d074, "mm_dma_bd3_5"}, + {0x00034074, "cm_event_broadcast_block_north_clr"}, + {0x0001d030, "mm_dma_bd1_4"}, + {0x0001d034, "mm_dma_bd1_5"}, + {0x0001d028, "mm_dma_bd1_2"}, + {0x0001d02c, "mm_dma_bd1_3"}, + {0x00032008, "cm_enable_events"}, + {0x0001d024, "mm_dma_bd1_1"}, + {0x000c0250, "mem_lock37_value"}, + {0x000b0110, "mem_stream_switch_slave_config_dma_4"}, + {0x000b0114, "mem_stream_switch_slave_config_dma_5"}, + {0x000b0100, "mem_stream_switch_slave_config_dma_0"}, + {0x000b0104, "mem_stream_switch_slave_config_dma_1"}, + {0x000b0108, "mem_stream_switch_slave_config_dma_2"}, + {0x00094508, "mem_event_group_dma_enable"}, + {0x00094028, "mem_event_broadcast6"}, + {0x0009402c, "mem_event_broadcast7"}, + {0x00094020, "mem_event_broadcast4"}, + {0x00094024, "mem_event_broadcast5"}, + {0x00094018, "mem_event_broadcast2"}, + {0x0009401c, "mem_event_broadcast3"}, + {0x00094010, "mem_event_broadcast0"}, + {0x00094014, "mem_event_broadcast1"}, + {0x000b0020, "mem_stream_switch_master_config_south1"}, + {0x000b001c, "mem_stream_switch_master_config_south0"}, + {0x000b0028, "mem_stream_switch_master_config_south3"}, + {0x000b0024, "mem_stream_switch_master_config_south2"}, + {0x000a0060, "mem_dma_bd3_0"}, + {0x000a0064, "mem_dma_bd3_1"}, + {0x000a0068, "mem_dma_bd3_2"}, + {0x000a006c, "mem_dma_bd3_3"}, + {0x00032004, "cm_core_status"}, + {0x0001f120, "mm_locks_overflow"}, + {0x000c0390, "mem_lock57_value"}, + {0x00034080, "cm_event_broadcast_block_east_set"}, + {0x0001df14, "mm_dma_mm2s_status_1"}, + {0x0001df10, "mm_dma_mm2s_status_0"}, + {0x000c0020, "mem_lock2_value"}, + {0x0003f240, "cm_stream_switch_slave_fifo_0_slot0"}, + {0x0001f080, "mm_lock8_value"}, + {0x00034518, "cm_event_group_stream_switch_enable"}, + {0x0001f000, "mm_lock0_value"}, + {0x000a0404, "mem_dma_bd32_1"}, + {0x000a0400, "mem_dma_bd32_0"}, + {0x000140d8, "mm_trace_status"}, + {0x000a0408, "mem_dma_bd32_2"}, + {0x000a0414, "mem_dma_bd32_5"}, + {0x000a0410, "mem_dma_bd32_4"}, + {0x000a041c, "mem_dma_bd32_7"}, + {0x000a0418, "mem_dma_bd32_6"}, + {0x000c0040, "mem_lock4_value"}, + {0x0003f204, "cm_stream_switch_slave_aie_core0_slot1"}, + {0x0003f200, "cm_stream_switch_slave_aie_core0_slot0"}, + {0x0003f20c, "cm_stream_switch_slave_aie_core0_slot3"}, + {0x0003f208, "cm_stream_switch_slave_aie_core0_slot2"}, + {0x0001451c, "mm_event_group_user_event_enable"}, + {0x00014000, "mm_timer_control"}, + {0x000a04dc, "mem_dma_bd38_7"}, + {0x000a04d8, "mem_dma_bd38_6"}, + {0x000a04d4, "mem_dma_bd38_5"}, + {0x000a04d0, "mem_dma_bd38_4"}, + {0x000a04cc, "mem_dma_bd38_3"}, + {0x000a04c8, "mem_dma_bd38_2"}, + {0x000a04c4, "mem_dma_bd38_1"}, + {0x000a04c0, "mem_dma_bd38_0"}, + {0x0003f2e8, "cm_stream_switch_slave_west_3_slot2"}, + {0x0003f2ec, "cm_stream_switch_slave_west_3_slot3"}, + {0x00014404, "mm_combo_event_control"}, + {0x0003f314, "cm_stream_switch_slave_north_2_slot1"}, + {0x0003f318, "cm_stream_switch_slave_north_2_slot2"}, + {0x0003f31c, "cm_stream_switch_slave_north_2_slot3"}, + {0x00031020, "shim_performance_counter0"}, + {0x00031024, "shim_performance_counter1"}, + {0x00014508, "mm_event_group_dma_enable"}, + {0x00014030, "shim_lock3_value"}, + {0x000340f4, "cm_timer_trig_event_high_value"}, + {0x000c0190, "mem_lock25_value"}, + {0x000d0000, "mem_lock_request"}, + {0x0001f128, "mm_locks_underflow"}, + {0x00034088, "cm_event_broadcast_block_east_value"}, + {0x00011084, "mm_performance_counter1_event_value"}, + {0x00034058, "cm_event_broadcast_block_south_value"}, + {0x0003f340, "cm_stream_switch_slave_east_1_slot0"}, + {0x0003f344, "cm_stream_switch_slave_east_1_slot1"}, + {0x0003f348, "cm_stream_switch_slave_east_1_slot2"}, + {0x0003f34c, "cm_stream_switch_slave_east_1_slot3"}, + {0x000c02a0, "mem_lock42_value"}, + {0x000a0468, "mem_dma_bd35_2"}, + {0x000a046c, "mem_dma_bd35_3"}, + {0x000a0460, "mem_dma_bd35_0"}, + {0x000140f4, "mm_timer_trig_event_high_value"}, + {0x000a0478, "mem_dma_bd35_6"}, + {0x0003ff20, "cm_stream_switch_parity_injection"}, + {0x000a0470, "mem_dma_bd35_4"}, + {0x000a0474, "mem_dma_bd35_5"}, + {0x000a04b0, "mem_dma_bd37_4"}, + {0x000a04b4, "mem_dma_bd37_5"}, + {0x000a04b8, "mem_dma_bd37_6"}, + {0x000a04bc, "mem_dma_bd37_7"}, + {0x000a04a0, "mem_dma_bd37_0"}, + {0x000a04a4, "mem_dma_bd37_1"}, + {0x000a04a8, "mem_dma_bd37_2"}, + {0x000a04ac, "mem_dma_bd37_3"}, + {0x000a03f8, "mem_dma_bd31_6"}, + {0x000a03fc, "mem_dma_bd31_7"}, + {0x000a03f0, "mem_dma_bd31_4"}, + {0x000a03f4, "mem_dma_bd31_5"}, + {0x000a03e8, "mem_dma_bd31_2"}, + {0x000a03ec, "mem_dma_bd31_3"}, + {0x000a03e0, "mem_dma_bd31_0"}, + {0x000a03e4, "mem_dma_bd31_1"}, + {0x000a0608, "mem_dma_s2mm_1_ctrl"}, + {0x0003f038, "cm_stream_switch_master_config_north1"}, + {0x0003f034, "cm_stream_switch_master_config_north0"}, + {0x0003f040, "cm_stream_switch_master_config_north3"}, + {0x0003f03c, "cm_stream_switch_master_config_north2"}, + {0x0003f048, "cm_stream_switch_master_config_north5"}, + {0x0003f044, "cm_stream_switch_master_config_north4"}, + {0x0001d044, "shim_dma_bd2_1"}, + {0x000fff00, "mem_module_clock_control"}, + {0x0001de10, "mm_dma_mm2s_0_ctrl"}, + {0x000a0674, "mem_dma_s2mm_status_5"}, + {0x000a0670, "mem_dma_s2mm_status_4"}, + {0x000a066c, "mem_dma_s2mm_status_3"}, + {0x000a0668, "mem_dma_s2mm_status_2"}, + {0x000a0664, "mem_dma_s2mm_status_1"}, + {0x000a0660, "mem_dma_s2mm_status_0"}, + {0x00014060, "mm_event_broadcast_block_west_set"}, + {0x00060000, "cm_module_clock_control"}, + {0x000b0f10, "mem_stream_switch_parity_status"}, + {0x00094408, "mem_edge_detection_event_control"}, + {0x00094034, "mem_event_broadcast9"}, + {0x0003f128, "cm_stream_switch_slave_config_south_5"}, + {0x0003f380, "cm_stream_switch_slave_mem_trace_slot0"}, + {0x0003f2a4, "cm_stream_switch_slave_south_5_slot1"}, + {0x0003f2a0, "cm_stream_switch_slave_south_5_slot0"}, + {0x0003f2ac, "cm_stream_switch_slave_south_5_slot3"}, + {0x0003f2a8, "cm_stream_switch_slave_south_5_slot2"}, + {0x000340d4, "cm_trace_control1"}, + {0x000340d0, "cm_trace_control0"}, + {0x0003f118, "cm_stream_switch_slave_config_south_1"}, + {0x000c0310, "mem_lock49_value"}, + {0x000c02f0, "mem_lock47_value"}, + {0x0001d188, "shim_dma_bd12_2"}, + {0x0001d18c, "shim_dma_bd12_3"}, + {0x0001d180, "shim_dma_bd12_0"}, + {0x0001d184, "shim_dma_bd12_1"}, + {0x0001d198, "shim_dma_bd12_6"}, + {0x0001d19c, "shim_dma_bd12_7"}, + {0x0001d190, "shim_dma_bd12_4"}, + {0x0001d194, "shim_dma_bd12_5"}, + {0x0001d150, "shim_dma_bd10_4"}, + {0x0001d154, "shim_dma_bd10_5"}, + {0x000b0260, "mem_stream_switch_slave_tile_ctrl_slot0"}, + {0x000b0264, "mem_stream_switch_slave_tile_ctrl_slot1"}, + {0x0001d140, "shim_dma_bd10_0"}, + {0x0001d144, "shim_dma_bd10_1"}, + {0x0001d148, "shim_dma_bd10_2"}, + {0x0001d14c, "shim_dma_bd10_3"}, + {0x000c00d0, "mem_lock13_value"}, + {0x0003f2cc, "cm_stream_switch_slave_west_1_slot3"}, + {0x000b025c, "mem_stream_switch_slave_dma_5_slot3"}, + {0x00014088, "mm_event_broadcast_block_east_value"}, + {0x00014054, "mm_event_broadcast_block_south_clr"}, + {0x000a0300, "mem_dma_bd24_0"}, + {0x000a0304, "mem_dma_bd24_1"}, + {0x000a0308, "mem_dma_bd24_2"}, + {0x000a030c, "mem_dma_bd24_3"}, + {0x000940a4, "mem_event_broadcast_b_block_west_clr"}, + {0x000b0f20, "mem_stream_switch_parity_injection"}, + {0x000a0610, "mem_dma_s2mm_2_ctrl"}, + {0x0001d064, "mm_dma_bd3_1"}, + {0x000c01e0, "mem_lock30_value"}, + {0x00034504, "cm_event_group_pc_enable"}, + {0x000a02d8, "mem_dma_bd22_6"}, + {0x0001d0cc, "shim_dma_bd6_3"}, + {0x000a02d0, "mem_dma_bd22_4"}, + {0x0001d0c4, "shim_dma_bd6_1"}, + {0x000c03c0, "mem_lock60_value"}, + {0x0001d0d8, "shim_dma_bd6_6"}, + {0x0001df04, "mm_dma_s2mm_status_1"}, + {0x0001df00, "mm_dma_s2mm_status_0"}, + {0x0001d0dc, "shim_dma_bd6_7"}, + {0x0001d0d0, "shim_dma_bd6_4"}, + {0x0001d0d4, "shim_dma_bd6_5"}, + {0x000c00a0, "mem_lock10_value"}, + {0x000a062c, "mem_dma_s2mm_5_start_queue"}, + {0x0001d020, "mm_dma_bd1_0"}, + {0x000a0380, "mem_dma_bd28_0"}, + {0x000a0384, "mem_dma_bd28_1"}, + {0x000a0388, "mem_dma_bd28_2"}, + {0x000a038c, "mem_dma_bd28_3"}, + {0x000a0390, "mem_dma_bd28_4"}, + {0x000a0394, "mem_dma_bd28_5"}, + {0x000a0398, "mem_dma_bd28_6"}, + {0x000a039c, "mem_dma_bd28_7"}, + {0x00034514, "cm_event_group_errors1_enable"}, + {0x000940e0, "mem_trace_event0"}, + {0x000940e4, "mem_trace_event1"}, + {0x000a0288, "mem_dma_bd20_2"}, + {0x000a028c, "mem_dma_bd20_3"}, + {0x000a0290, "mem_dma_bd20_4"}, + {0x000a0294, "mem_dma_bd20_5"}, + {0x000a0298, "mem_dma_bd20_6"}, + {0x000a029c, "mem_dma_bd20_7"}, + {0x000c03a0, "mem_lock58_value"}, + {0x00094084, "mem_event_broadcast_a_block_east_clr"}, + {0x000a060c, "mem_dma_s2mm_1_start_queue"}, + {0x0001d1e4, "shim_dma_bd15_1"}, + {0x0001d1e0, "shim_dma_bd15_0"}, + {0x0001d1ec, "shim_dma_bd15_3"}, + {0x0001d1e8, "shim_dma_bd15_2"}, + {0x0001d1f4, "shim_dma_bd15_5"}, + {0x0001d1f0, "shim_dma_bd15_4"}, + {0x00014084, "mm_event_broadcast_block_east_clr"}, + {0x0001d1f8, "shim_dma_bd15_6"}, + {0x0001d170, "shim_dma_bd11_4"}, + {0x000940a8, "mem_event_broadcast_b_block_west_value"}, + {0x00094030, "mem_event_broadcast8"}, + {0x000b010c, "mem_stream_switch_slave_config_dma_3"}, + {0x00014510, "mm_event_group_memory_conflict_enable"}, + {0x000c0260, "mem_lock38_value"}, + {0x00034034, "shim_event_broadcast_a_9"}, + {0x00034030, "shim_event_broadcast_a_8"}, + {0x0003402c, "shim_event_broadcast_a_7"}, + {0x00034028, "shim_event_broadcast_a_6"}, + {0x00034024, "shim_event_broadcast_a_5"}, + {0x00034020, "shim_event_broadcast_a_4"}, + {0x0003401c, "shim_event_broadcast_a_3"}, + {0x00034018, "shim_event_broadcast_a_2"}, + {0x00034014, "shim_event_broadcast_a_1"}, + {0x00034010, "shim_event_broadcast_a_0"}, + {0x000a0620, "mem_dma_s2mm_4_ctrl"}, + {0x0001d0b4, "shim_dma_bd5_5"}, + {0x0001d0b0, "shim_dma_bd5_4"}, + {0x0001d0bc, "shim_dma_bd5_7"}, + {0x0001d0b8, "shim_dma_bd5_6"}, + {0x0001d0a4, "shim_dma_bd5_1"}, + {0x0001d0a0, "shim_dma_bd5_0"}, + {0x0001d0ac, "shim_dma_bd5_3"}, + {0x0001d0a8, "shim_dma_bd5_2"}, + {0x0003200c, "cm_reset_event"}, + {0x000140f0, "shim_lock15_value"}, + {0x0001d07c, "shim_dma_bd3_7"}, + {0x0001d078, "shim_dma_bd3_6"}, + {0x0001d074, "shim_dma_bd3_5"}, + {0x0001d070, "shim_dma_bd3_4"}, + {0x0001d06c, "shim_dma_bd3_3"}, + {0x0001d068, "shim_dma_bd3_2"}, + {0x0001d064, "shim_dma_bd3_1"}, + {0x0001d060, "shim_dma_bd3_0"}, + {0x000c0180, "mem_lock24_value"}, + {0x000a0070, "mem_dma_bd3_4"}, + {0x000a0074, "mem_dma_bd3_5"}, + {0x000a0078, "mem_dma_bd3_6"}, + {0x000a007c, "mem_dma_bd3_7"}, + {0x00012124, "mm_parity_failing_address"}, + {0x000b0000, "mem_stream_switch_master_config_dma0"}, + {0x000b0004, "mem_stream_switch_master_config_dma1"}, + {0x000b0008, "mem_stream_switch_master_config_dma2"}, + {0x000b000c, "mem_stream_switch_master_config_dma3"}, + {0x000b0010, "mem_stream_switch_master_config_dma4"}, + {0x000b0014, "mem_stream_switch_master_config_dma5"}, + {0x000a036c, "mem_dma_bd27_3"}, + {0x000a0368, "mem_dma_bd27_2"}, + {0x000a0364, "mem_dma_bd27_1"}, + {0x000a0360, "mem_dma_bd27_0"}, + {0x000a037c, "mem_dma_bd27_7"}, + {0x000a0378, "mem_dma_bd27_6"}, + {0x000a0374, "mem_dma_bd27_5"}, + {0x000a0370, "mem_dma_bd27_4"}, + {0x000a0334, "mem_dma_bd25_5"}, + {0x000a0330, "mem_dma_bd25_4"}, + {0x000a033c, "mem_dma_bd25_7"}, + {0x000a0338, "mem_dma_bd25_6"}, + {0x000a0324, "mem_dma_bd25_1"}, + {0x000a0320, "mem_dma_bd25_0"}, + {0x000a032c, "mem_dma_bd25_3"}, + {0x000a0328, "mem_dma_bd25_2"}, + {0x0001d0ec, "shim_dma_bd7_3"}, + {0x0001d0e8, "shim_dma_bd7_2"}, + {0x000a02f4, "mem_dma_bd23_5"}, + {0x0001d0e0, "shim_dma_bd7_0"}, + {0x0001d0fc, "shim_dma_bd7_7"}, + {0x0001d0f8, "shim_dma_bd7_6"}, + {0x0001d0f4, "shim_dma_bd7_5"}, + {0x0001d0f0, "shim_dma_bd7_4"}, + {0x000b0204, "mem_stream_switch_slave_dma_0_slot1"}, + {0x000b0200, "mem_stream_switch_slave_dma_0_slot0"}, + {0x000b020c, "mem_stream_switch_slave_dma_0_slot3"}, + {0x000b0208, "mem_stream_switch_slave_dma_0_slot2"}, + {0x000a0638, "mem_dma_mm2s_1_ctrl"}, + {0x00034404, "cm_combo_event_control"}, + {0x000b0144, "mem_stream_switch_slave_config_trace"}, + {0x000a0280, "mem_dma_bd20_0"}, + {0x000a0284, "mem_dma_bd20_1"}, + {0x00032018, "cm_debug_control2"}, + {0x00032014, "cm_debug_control1"}, + {0x00032010, "cm_debug_control0"}, + {0x0001d100, "shim_dma_bd8_0"}, + {0x00014010, "mm_event_broadcast0"}, + {0x0001d108, "shim_dma_bd8_2"}, + {0x0001d10c, "shim_dma_bd8_3"}, + {0x0001d110, "shim_dma_bd8_4"}, + {0x0001d114, "shim_dma_bd8_5"}, + {0x0001d118, "shim_dma_bd8_6"}, + {0x0001d11c, "shim_dma_bd8_7"}, + {0x000c02b0, "mem_lock43_value"}, + {0x000340f8, "shim_timer_low"}, + {0x0001de08, "mm_dma_s2mm_1_ctrl"}, + {0x0009451c, "mem_event_group_broadcast_enable"}, + {0x0003f308, "cm_stream_switch_slave_north_1_slot2"}, + {0x0003f304, "cm_stream_switch_slave_north_1_slot1"}, + {0x0003f300, "cm_stream_switch_slave_north_1_slot0"}, + {0x0001d000, "shim_dma_bd0_0"}, + {0x0001d004, "shim_dma_bd0_1"}, + {0x0001d008, "shim_dma_bd0_2"}, + {0x0001d00c, "shim_dma_bd0_3"}, + {0x0001d010, "shim_dma_bd0_4"}, + {0x0001d014, "shim_dma_bd0_5"}, + {0x0001d018, "shim_dma_bd0_6"}, + {0x0001d01c, "shim_dma_bd0_7"}, + {0x000940b4, "mem_event_broadcast_b_block_north_clr"}, + {0x000b0210, "mem_stream_switch_slave_dma_1_slot0"}, + {0x000b0214, "mem_stream_switch_slave_dma_1_slot1"}, + {0x000b0218, "mem_stream_switch_slave_dma_1_slot2"}, + {0x000b021c, "mem_stream_switch_slave_dma_1_slot3"}, + {0x00034408, "cm_edge_detection_event_control"}, + {0x000c0070, "mem_lock7_value"}, + {0x0003201c, "cm_debug_status"}, + {0x000b030c, "mem_stream_switch_slave_north_3_slot3"}, + {0x000b0308, "mem_stream_switch_slave_north_3_slot2"}, + {0x000b0304, "mem_stream_switch_slave_north_3_slot1"}, + {0x000b0300, "mem_stream_switch_slave_north_3_slot0"}, + {0x0003202c, "cm_pc_event3"}, + {0x00032028, "cm_pc_event2"}, + {0x00032024, "cm_pc_event1"}, + {0x00032020, "cm_pc_event0"}, + {0x0003f000, "cm_stream_switch_master_config_aie_core0"}, + {0x000a0238, "mem_dma_bd17_6"}, + {0x000a023c, "mem_dma_bd17_7"}, + {0x0001f118, "mm_locks_event_selection_6"}, + {0x0001f11c, "mm_locks_event_selection_7"}, + {0x000a06c4, "mem_dma_s2mm_current_write_count_5"}, + {0x0001f114, "mm_locks_event_selection_5"}, + {0x0001f108, "mm_locks_event_selection_2"}, + {0x000a06b8, "mem_dma_s2mm_current_write_count_2"}, + {0x0001f100, "mm_locks_event_selection_0"}, + {0x0001f104, "mm_locks_event_selection_1"}, + {0x000a02f8, "mem_dma_bd23_6"}, + {0x00040000, "mm_lock_request"}, + {0x000940f0, "mem_timer_trig_event_low_value"}, + {0x0009404c, "mem_event_broadcast15"}, + {0x00094038, "mem_event_broadcast10"}, + {0x0009403c, "mem_event_broadcast11"}, + {0x00094040, "mem_event_broadcast12"}, + {0x00094044, "mem_event_broadcast13"}, + {0x0003f324, "cm_stream_switch_slave_north_3_slot1"}, + {0x0003f320, "cm_stream_switch_slave_north_3_slot0"}, + {0x0003f32c, "cm_stream_switch_slave_north_3_slot3"}, + {0x0003f328, "cm_stream_switch_slave_north_3_slot2"}, + {0x0003ff10, "cm_stream_switch_parity_status"}, + {0x00036030, "cm_tile_control"}, + {0x00031580, "cm_performance_counter0_event_value"}, + {0x000b02a4, "mem_stream_switch_slave_south_3_slot1"}, + {0x000b02a0, "mem_stream_switch_slave_south_3_slot0"}, + {0x000b02ac, "mem_stream_switch_slave_south_3_slot3"}, + {0x000b02a8, "mem_stream_switch_slave_south_3_slot2"}, + {0x000c0160, "mem_lock22_value"}, + {0x000340f8, "cm_timer_low"}, + {0x00094080, "mem_event_broadcast_a_block_east_set"}, + {0x00014504, "mm_event_group_watchpoint_enable"}, + {0x000c0080, "mem_lock8_value"}, + {0x000c0210, "mem_lock33_value"}, + {0x000b012c, "mem_stream_switch_slave_config_south_4"}, + {0x000a064c, "mem_dma_mm2s_3_start_queue"}, + {0x00094098, "mem_event_broadcast_b_block_south_value"}, + {0x000140d0, "shim_lock13_value"}, + {0x000940b8, "mem_event_broadcast_b_block_north_value"}, + {0x0003f04c, "cm_stream_switch_master_config_east0"}, + {0x0003f050, "cm_stream_switch_master_config_east1"}, + {0x0003f054, "cm_stream_switch_master_config_east2"}, + {0x0003f058, "cm_stream_switch_master_config_east3"}, + {0x0001d1fc, "shim_dma_bd15_7"}, + {0x000a06c8, "mem_dma_s2mm_fot_count_fifo_pop_0"}, + {0x0003f230, "cm_stream_switch_slave_tile_ctrl_slot0"}, + {0x000c0320, "mem_lock50_value"}, + {0x00034504, "shim_event_group_dma_enable"}, + {0x0003450c, "cm_event_group_core_program_flow_enable"}, + {0x00014050, "mm_event_broadcast_block_south_set"}, + {0x0001d1d4, "mm_dma_bd14_5"}, + {0x0001d1d0, "mm_dma_bd14_4"}, + {0x0001d1c4, "mm_dma_bd14_1"}, + {0x0001d1c0, "mm_dma_bd14_0"}, + {0x0001d1cc, "mm_dma_bd14_3"}, + {0x0001d1c8, "mm_dma_bd14_2"}, + {0x00034044, "cm_event_broadcast13"}, + {0x00016000, "mm_spare_reg"}, + {0x0003f148, "cm_stream_switch_slave_config_north_3"}, + {0x0003f00c, "cm_stream_switch_master_config_tile_ctrl"}, + {0x0003f140, "cm_stream_switch_slave_config_north_1"}, + {0x0003f13c, "cm_stream_switch_slave_config_north_0"}, + {0x00094504, "mem_event_group_watchpoint_enable"}, + {0x00096030, "mem_tile_control"}, + {0x0001d144, "mm_dma_bd10_1"}, + {0x0001d140, "mm_dma_bd10_0"}, + {0x0001d14c, "mm_dma_bd10_3"}, + {0x0001d148, "mm_dma_bd10_2"}, + {0x0001d154, "mm_dma_bd10_5"}, + {0x0001d150, "mm_dma_bd10_4"}, + {0x0001d194, "mm_dma_bd12_5"}, + {0x0001d190, "mm_dma_bd12_4"}, + {0x0001d18c, "mm_dma_bd12_3"}, + {0x0001d188, "mm_dma_bd12_2"}, + {0x0001d184, "mm_dma_bd12_1"}, + {0x0001d180, "mm_dma_bd12_0"}, + {0x000a01c4, "mem_dma_bd14_1"}, + {0x000a01c0, "mem_dma_bd14_0"}, + {0x000a01cc, "mem_dma_bd14_3"}, + {0x000a01c8, "mem_dma_bd14_2"}, + {0x000a01d4, "mem_dma_bd14_5"}, + {0x000a01d0, "mem_dma_bd14_4"}, + {0x000a01dc, "mem_dma_bd14_7"}, + {0x000a01d8, "mem_dma_bd14_6"}, + {0x00034058, "shim_event_broadcast_a_block_south_value"}, + {0x00032030, "cm_error_halt_control"}, + {0x00094070, "mem_event_broadcast_a_block_north_set"}, + {0x00096000, "mem_spare_reg"}, + {0x000a018c, "mem_dma_bd12_3"}, + {0x000a0188, "mem_dma_bd12_2"}, + {0x000a0184, "mem_dma_bd12_1"}, + {0x000a0180, "mem_dma_bd12_0"}, + {0x000a019c, "mem_dma_bd12_7"}, + {0x000a0198, "mem_dma_bd12_6"}, + {0x000a0194, "mem_dma_bd12_5"}, + {0x000a0190, "mem_dma_bd12_4"}, + {0x00031008, "shim_performance_control1"}, + {0x00031000, "shim_performance_control0"}, + {0x0003ff00, "cm_stream_switch_event_port_selection_0"}, + {0x0003ff04, "cm_stream_switch_event_port_selection_1"}, + {0x000a0154, "mem_dma_bd10_5"}, + {0x000a0150, "mem_dma_bd10_4"}, + {0x000a015c, "mem_dma_bd10_7"}, + {0x000a0158, "mem_dma_bd10_6"}, + {0x000a0144, "mem_dma_bd10_1"}, + {0x000a0140, "mem_dma_bd10_0"}, + {0x000a014c, "mem_dma_bd10_3"}, + {0x000a0148, "mem_dma_bd10_2"}, + {0x000a021c, "mem_dma_bd16_7"}, + {0x000a0218, "mem_dma_bd16_6"}, + {0x000a0214, "mem_dma_bd16_5"}, + {0x000a0210, "mem_dma_bd16_4"}, + {0x000a020c, "mem_dma_bd16_3"}, + {0x000a0208, "mem_dma_bd16_2"}, + {0x000a0204, "mem_dma_bd16_1"}, + {0x000a0200, "mem_dma_bd16_0"}, + {0x0001d060, "mm_dma_bd3_0"}, + {0x00094514, "mem_event_group_memory_conflict_enable"}, + {0x0003f334, "cm_stream_switch_slave_east_0_slot1"}, + {0x0003f330, "cm_stream_switch_slave_east_0_slot0"}, + {0x0003f33c, "cm_stream_switch_slave_east_0_slot3"}, + {0x0003f338, "cm_stream_switch_slave_east_0_slot2"}, + {0x00034080, "shim_event_broadcast_a_block_east_set"}, + {0x00014200, "mm_event_status0"}, + {0x00014204, "mm_event_status1"}, + {0x00014208, "mm_event_status2"}, + {0x0001420c, "mm_event_status3"}, + {0x00034074, "shim_event_broadcast_a_block_north_clr"}, + {0x0001f040, "mm_lock4_value"}, + {0x000a0630, "mem_dma_mm2s_0_ctrl"}, + {0x00031588, "cm_performance_counter2_event_value"}, + {0x000340f0, "shim_timer_trig_event_low_value"}, + {0x0003ff34, "cm_stream_switch_adaptive_clock_gate_status"}, + {0x000b0804, "mem_stream_switch_deterministic_merge_arb0_slave2_3"}, + {0x000a00b0, "mem_dma_bd5_4"}, + {0x00094000, "mem_timer_control"}, + {0x000c0420, "mem_locks_overflow_0"}, + {0x000c0424, "mem_locks_overflow_1"}, + {0x000a0270, "mem_dma_bd19_4"}, + {0x000a0274, "mem_dma_bd19_5"}, + {0x000a0278, "mem_dma_bd19_6"}, + {0x000a027c, "mem_dma_bd19_7"}, + {0x000a0260, "mem_dma_bd19_0"}, + {0x000a0264, "mem_dma_bd19_1"}, + {0x000a0268, "mem_dma_bd19_2"}, + {0x000a026c, "mem_dma_bd19_3"}, + {0x000b0128, "mem_stream_switch_slave_config_south_3"}, + {0x000b0124, "mem_stream_switch_slave_config_south_2"}, + {0x000b0120, "mem_stream_switch_slave_config_south_1"}, + {0x000b011c, "mem_stream_switch_slave_config_south_0"}, + {0x000b0130, "mem_stream_switch_slave_config_south_5"}, + {0x0003f244, "cm_stream_switch_slave_fifo_0_slot1"}, + {0x0003f248, "cm_stream_switch_slave_fifo_0_slot2"}, + {0x0001450c, "mm_event_group_lock_enable"}, + {0x0003f24c, "cm_stream_switch_slave_fifo_0_slot3"}, + {0x000c0030, "mem_lock3_value"}, + {0x000a0654, "mem_dma_mm2s_4_start_queue"}, + {0x000a0600, "mem_dma_s2mm_0_ctrl"}, + {0x00094510, "mem_event_group_stream_switch_enable"}, + {0x000c0370, "mem_lock55_value"}, + {0x000a0694, "mem_dma_mm2s_status_5"}, + {0x000a0690, "mem_dma_mm2s_status_4"}, + {0x000a0684, "mem_dma_mm2s_status_1"}, + {0x000a0680, "mem_dma_mm2s_status_0"}, + {0x000a068c, "mem_dma_mm2s_status_3"}, + {0x000a0688, "mem_dma_mm2s_status_2"}, + {0x00094058, "mem_event_broadcast_a_block_south_value"}, + {0x000940c0, "mem_event_broadcast_b_block_east_set"}, + {0x000a0648, "mem_dma_mm2s_3_ctrl"}, + {0x00034060, "cm_event_broadcast_block_west_set"}, + {0x000b0f38, "mem_stream_switch_adaptive_clock_gate_abort_period"}, + {0x00034084, "cm_event_broadcast_block_east_clr"}, + {0x0009108c, "mem_performance_counter3_event_value"}, + {0x00014020, "shim_lock2_value"}, + {0x00011024, "mm_performance_counter1"}, + {0x00011020, "mm_performance_counter0"}, + {0x000a065c, "mem_dma_mm2s_5_start_queue"}, + {0x00014068, "mm_event_broadcast_block_west_value"}, + {0x000b027c, "mem_stream_switch_slave_south_0_slot3"}, + {0x000b0270, "mem_stream_switch_slave_south_0_slot0"}, + {0x000b0274, "mem_stream_switch_slave_south_0_slot1"}, + {0x00032000, "cm_core_control"}, + {0x000c0010, "mem_lock1_value"}, + {0x000a0508, "mem_dma_bd40_2"}, + {0x000a050c, "mem_dma_bd40_3"}, + {0x000a0500, "mem_dma_bd40_0"}, + {0x000a0504, "mem_dma_bd40_1"}, + {0x000a0518, "mem_dma_bd40_6"}, + {0x000a051c, "mem_dma_bd40_7"}, + {0x000a0510, "mem_dma_bd40_4"}, + {0x000a0514, "mem_dma_bd40_5"}, + {0x000a0550, "mem_dma_bd42_4"}, + {0x000a0554, "mem_dma_bd42_5"}, + {0x000a0558, "mem_dma_bd42_6"}, + {0x000a055c, "mem_dma_bd42_7"}, + {0x000a0540, "mem_dma_bd42_0"}, + {0x000a0544, "mem_dma_bd42_1"}, + {0x000a0548, "mem_dma_bd42_2"}, + {0x000a054c, "mem_dma_bd42_3"}, + {0x000a0598, "mem_dma_bd44_6"}, + {0x000a059c, "mem_dma_bd44_7"}, + {0x000a0590, "mem_dma_bd44_4"}, + {0x000a0594, "mem_dma_bd44_5"}, + {0x000a0588, "mem_dma_bd44_2"}, + {0x000a058c, "mem_dma_bd44_3"}, + {0x000a0580, "mem_dma_bd44_0"}, + {0x000a0584, "mem_dma_bd44_1"}, + {0x0003f810, "cm_stream_switch_deterministic_merge_arb1_slave0_1"}, + {0x00094088, "mem_event_broadcast_a_block_east_value"}, + {0x00034054, "cm_event_broadcast_block_south_clr"}, + {0x000c01a0, "mem_lock26_value"}, + {0x00014070, "shim_lock7_value"}, + {0x000b02b8, "mem_stream_switch_slave_south_4_slot2"}, + {0x000b02bc, "mem_stream_switch_slave_south_4_slot3"}, + {0x000b02b0, "mem_stream_switch_slave_south_4_slot0"}, + {0x000b02b4, "mem_stream_switch_slave_south_4_slot1"}, + {0x0003420c, "shim_event_status3"}, + {0x00034208, "shim_event_status2"}, + {0x00034204, "shim_event_status1"}, + {0x00034200, "shim_event_status0"}, + {0x000c0110, "mem_lock17_value"}, + {0x00096048, "mem_memory_control"}, + {0x0003f228, "cm_stream_switch_slave_dma_1_slot2"}, + {0x000a0604, "mem_dma_s2mm_0_start_queue"}, + {0x0003f22c, "cm_stream_switch_slave_dma_1_slot3"}, + {0x0003f220, "cm_stream_switch_slave_dma_1_slot0"}, + {0x0001df24, "mm_dma_s2mm_fot_count_fifo_pop_1"}, + {0x0001df20, "mm_dma_s2mm_fot_count_fifo_pop_0"}, + {0x0003f224, "cm_stream_switch_slave_dma_1_slot1"}, + {0x000940d8, "mem_trace_status"}, + {0x00012110, "mm_ecc_scrubbing_event"}, + {0x0003f020, "cm_stream_switch_master_config_south3"}, + {0x0003f01c, "cm_stream_switch_master_config_south2"}, + {0x0003f018, "cm_stream_switch_master_config_south1"}, + {0x0003f014, "cm_stream_switch_master_config_south0"}, + {0x00031084, "shim_performance_counter1_event_value"}, + {0x00014010, "shim_lock1_value"}, + {0x000340e4, "shim_trace_event1"}, + {0x000340e0, "shim_trace_event0"}, + {0x0001421c, "mm_reserved3"}, + {0x000a040c, "mem_dma_bd32_3"}, + {0x00014214, "mm_reserved1"}, + {0x00014210, "mm_reserved0"}, + {0x000c042c, "mem_locks_underflow_1"}, + {0x000c0428, "mem_locks_underflow_0"}, + {0x000b028c, "mem_stream_switch_slave_south_1_slot3"}, + {0x000c0140, "mem_lock20_value"}, + {0x000b0288, "mem_stream_switch_slave_south_1_slot2"}, + {0x000b0284, "mem_stream_switch_slave_south_1_slot1"}, + {0x000b0280, "mem_stream_switch_slave_south_1_slot0"}, + {0x00014038, "mm_event_broadcast10"}, + {0x0001403c, "mm_event_broadcast11"}, + {0x00014040, "mm_event_broadcast12"}, + {0x00014044, "mm_event_broadcast13"}, + {0x00014048, "mm_event_broadcast14"}, + {0x0001404c, "mm_event_broadcast15"}, + {0x0003f160, "cm_stream_switch_slave_config_mem_trace"}, + {0x000c0418, "mem_locks_event_selection_6"}, + {0x000c041c, "mem_locks_event_selection_7"}, + {0x000c0410, "mem_locks_event_selection_4"}, + {0x000c0414, "mem_locks_event_selection_5"}, + {0x000c0408, "mem_locks_event_selection_2"}, + {0x000c040c, "mem_locks_event_selection_3"}, + {0x000c0400, "mem_locks_event_selection_0"}, + {0x000c0404, "mem_locks_event_selection_1"}, + {0x00094060, "mem_event_broadcast_a_block_west_set"}, + {0x0003f2e0, "cm_stream_switch_slave_west_3_slot0"}, + {0x000c0340, "mem_lock52_value"}, + {0x000c01d0, "mem_lock29_value"}, + {0x000a02fc, "mem_dma_bd23_7"}, + {0x000c03e0, "mem_lock62_value"}, + {0x0001d0e4, "shim_dma_bd7_1"}, + {0x000c01b0, "mem_lock27_value"}, + {0x0003f2e4, "cm_stream_switch_slave_west_3_slot1"}, + {0x000a02f0, "mem_dma_bd23_4"}, + {0x000a02ec, "mem_dma_bd23_3"}, + {0x000a02e8, "mem_dma_bd23_2"}, + {0x000a02e4, "mem_dma_bd23_1"}, + {0x000a02e0, "mem_dma_bd23_0"}, + {0x0003451c, "cm_event_group_broadcast_enable"}, + {0x000a0650, "mem_dma_mm2s_4_ctrl"}, + {0x00094050, "mem_event_broadcast_a_block_south_set"}, + {0x00011080, "mm_performance_counter0_event_value"}, + {0x00032038, "cm_core_processor_bus"}, + {0x0001d08c, "mm_dma_bd4_3"}, + {0x0001d088, "mm_dma_bd4_2"}, + {0x00034068, "cm_event_broadcast_block_west_value"}, + {0x0001d080, "mm_dma_bd4_0"}, + {0x0001d094, "mm_dma_bd4_5"}, + {0x0001d090, "mm_dma_bd4_4"}, + {0x00014408, "mm_edge_detection_event_control"}, + {0x00012120, "mm_ecc_failing_address"}, + {0x0001d044, "mm_dma_bd2_1"}, + {0x0001d040, "mm_dma_bd2_0"}, + {0x0001d04c, "mm_dma_bd2_3"}, + {0x0001d048, "mm_dma_bd2_2"}, + {0x0001d054, "mm_dma_bd2_5"}, + {0x0001d050, "mm_dma_bd2_4"}, + {0x0001d014, "mm_dma_bd0_5"}, + {0x0001d010, "mm_dma_bd0_4"}, + {0x0001d00c, "mm_dma_bd0_3"}, + {0x0001d008, "mm_dma_bd0_2"}, + {0x0001d004, "mm_dma_bd0_1"}, + {0x0001d000, "mm_dma_bd0_0"}, + {0x00014030, "mm_event_broadcast8"}, + {0x00014034, "mm_event_broadcast9"}, + {0x0001d0d4, "mm_dma_bd6_5"}, + {0x0001d0d0, "mm_dma_bd6_4"}, + {0x00014020, "mm_event_broadcast4"}, + {0x00014024, "mm_event_broadcast5"}, + {0x0001d0c4, "mm_dma_bd6_1"}, + {0x0001d0c0, "mm_dma_bd6_0"}, + {0x000a0464, "mem_dma_bd35_1"}, + {0x0001d0c8, "mm_dma_bd6_2"}, + {0x000a05e4, "mem_dma_bd47_1"}, + {0x000a05e0, "mem_dma_bd47_0"}, + {0x000a05ec, "mem_dma_bd47_3"}, + {0x000a05e8, "mem_dma_bd47_2"}, + {0x000a05f4, "mem_dma_bd47_5"}, + {0x000a05f0, "mem_dma_bd47_4"}, + {0x000a05fc, "mem_dma_bd47_7"}, + {0x000a05f8, "mem_dma_bd47_6"}, + {0x0001f010, "mm_lock1_value"}, + {0x000b0814, "mem_stream_switch_deterministic_merge_arb1_slave2_3"}, + {0x00031500, "cm_performance_control0"}, + {0x00031504, "cm_performance_control1"}, + {0x00031508, "cm_performance_control2"}, + {0x000b0810, "mem_stream_switch_deterministic_merge_arb1_slave0_1"}, + {0x00034044, "shim_event_broadcast_a_13"}, + {0x00034040, "shim_event_broadcast_a_12"}, + {0x0003403c, "shim_event_broadcast_a_11"}, + {0x00034038, "shim_event_broadcast_a_10"}, + {0x0003404c, "shim_event_broadcast_a_15"}, + {0x00034048, "shim_event_broadcast_a_14"}, + {0x000a0618, "mem_dma_s2mm_3_ctrl"}, + {0x00094054, "mem_event_broadcast_a_block_south_clr"}, + {0x00014078, "mm_event_broadcast_block_north_value"}, + {0x00014080, "mm_event_broadcast_block_east_set"}, + {0x000b0278, "mem_stream_switch_slave_south_0_slot2"}, + {0x000a0094, "mem_dma_bd4_5"}, + {0x000c0380, "mem_lock56_value"}, + {0x0001d104, "shim_dma_bd8_1"}, + {0x0001f060, "mm_lock6_value"}, + {0x0001d130, "mm_dma_bd9_4"}, + {0x0001d134, "mm_dma_bd9_5"}, + {0x0001d128, "mm_dma_bd9_2"}, + {0x0001d12c, "mm_dma_bd9_3"}, + {0x0001d120, "mm_dma_bd9_0"}, + {0x0001d124, "mm_dma_bd9_1"}, + {0x000c02d0, "mem_lock45_value"}, + {0x0003ff04, "shim_stream_switch_event_port_selection_1"}, + {0x0003ff00, "shim_stream_switch_event_port_selection_0"}, + {0x0003f2c8, "cm_stream_switch_slave_west_1_slot2"}, + {0x0009450c, "mem_event_group_lock_enable"}, + {0x0003f2c0, "cm_stream_switch_slave_west_1_slot0"}, + {0x0003f2c4, "cm_stream_switch_slave_west_1_slot1"}, + {0x0003f110, "cm_stream_switch_slave_config_fifo_0"}, + {0x000c0290, "mem_lock41_value"}, + {0x0001f090, "mm_lock9_value"}, + {0x00036060, "cm_accumulator_control"}, + {0x0003f250, "cm_stream_switch_slave_south_0_slot0"}, + {0x0003f254, "cm_stream_switch_slave_south_0_slot1"}, + {0x0003f258, "cm_stream_switch_slave_south_0_slot2"}, + {0x0003f25c, "cm_stream_switch_slave_south_0_slot3"}, + {0x000140c0, "shim_lock12_value"}, + {0x000c03b0, "mem_lock59_value"}, + {0x0003f310, "cm_stream_switch_slave_north_2_slot0"}, + {0x0001f0a0, "mm_lock10_value"}, + {0x0003f21c, "cm_stream_switch_slave_dma_0_slot3"}, + {0x0003f218, "cm_stream_switch_slave_dma_0_slot2"}, + {0x0003f214, "cm_stream_switch_slave_dma_0_slot1"}, + {0x0003f210, "cm_stream_switch_slave_dma_0_slot0"}, + {0x0003f30c, "cm_stream_switch_slave_north_1_slot3"}, + {0x00034208, "cm_event_status2"}, + {0x0003420c, "cm_event_status3"}, + {0x00034200, "cm_event_status0"}, + {0x00034204, "cm_event_status1"}, + {0x00034048, "cm_event_broadcast14"}, + {0x0003404c, "cm_event_broadcast15"}, + {0x00034040, "cm_event_broadcast12"}, + {0x00034500, "cm_event_group_0_enable"}, + {0x00034038, "cm_event_broadcast10"}, + {0x0003403c, "cm_event_broadcast11"}, + {0x000c0060, "mem_lock6_value"}, + {0x00034088, "shim_event_broadcast_a_block_east_value"}, + {0x0001de1c, "mm_dma_mm2s_1_start_queue"}, + {0x000a00e0, "mem_dma_bd7_0"}, + {0x000a00e4, "mem_dma_bd7_1"}, + {0x000a00e8, "mem_dma_bd7_2"}, + {0x000a00ec, "mem_dma_bd7_3"}, + {0x000a00f0, "mem_dma_bd7_4"}, + {0x000a00f4, "mem_dma_bd7_5"}, + {0x000a00f8, "mem_dma_bd7_6"}, + {0x000a00fc, "mem_dma_bd7_7"}, + {0x000a044c, "mem_dma_bd34_3"}, + {0x000a0448, "mem_dma_bd34_2"}, + {0x000a0444, "mem_dma_bd34_1"}, + {0x000a0440, "mem_dma_bd34_0"}, + {0x000a045c, "mem_dma_bd34_7"}, + {0x000a0458, "mem_dma_bd34_6"}, + {0x000a0454, "mem_dma_bd34_5"}, + {0x000a0450, "mem_dma_bd34_4"}, + {0x000a00b8, "mem_dma_bd5_6"}, + {0x000a00bc, "mem_dma_bd5_7"}, + {0x00094064, "mem_event_broadcast_a_block_west_clr"}, + {0x000a00b4, "mem_dma_bd5_5"}, + {0x000a00a8, "mem_dma_bd5_2"}, + {0x000a00ac, "mem_dma_bd5_3"}, + {0x000a00a0, "mem_dma_bd5_0"}, + {0x000a00a4, "mem_dma_bd5_1"}, + {0x000a0494, "mem_dma_bd36_5"}, + {0x000a0490, "mem_dma_bd36_4"}, + {0x000a049c, "mem_dma_bd36_7"}, + {0x000a0498, "mem_dma_bd36_6"}, + {0x000a0484, "mem_dma_bd36_1"}, + {0x000a0480, "mem_dma_bd36_0"}, + {0x000a048c, "mem_dma_bd36_3"}, + {0x000a0488, "mem_dma_bd36_2"}, + {0x000a03dc, "mem_dma_bd30_7"}, + {0x000a03d8, "mem_dma_bd30_6"}, + {0x000a03d4, "mem_dma_bd30_5"}, + {0x000a03d0, "mem_dma_bd30_4"}, + {0x000a03cc, "mem_dma_bd30_3"}, + {0x000a03c8, "mem_dma_bd30_2"}, + {0x000a03c4, "mem_dma_bd30_1"}, + {0x000a03c0, "mem_dma_bd30_0"}, + {0x000b0298, "mem_stream_switch_slave_south_2_slot2"}, + {0x00014008, "mm_event_generate"}, + {0x00031584, "cm_performance_counter1_event_value"}, + {0x000c00f0, "mem_lock15_value"}, + {0x00034050, "cm_event_broadcast_block_south_set"}, + {0x000a0128, "mem_dma_bd9_2"}, + {0x000a012c, "mem_dma_bd9_3"}, + {0x000a0120, "mem_dma_bd9_0"}, + {0x000a0124, "mem_dma_bd9_1"}, + {0x000a0138, "mem_dma_bd9_6"}, + {0x000a013c, "mem_dma_bd9_7"}, + {0x000a0130, "mem_dma_bd9_4"}, + {0x000a0134, "mem_dma_bd9_5"}, + {0x000c0170, "mem_lock23_value"}, + {0x000a000c, "mem_dma_bd0_3"}, + {0x000a0008, "mem_dma_bd0_2"}, + {0x000a0004, "mem_dma_bd0_1"}, + {0x000a0000, "mem_dma_bd0_0"}, + {0x000a001c, "mem_dma_bd0_7"}, + {0x000a0018, "mem_dma_bd0_6"}, + {0x000a0014, "mem_dma_bd0_5"}, + {0x000a0010, "mem_dma_bd0_4"}, + {0x000b0f34, "mem_stream_switch_adaptive_clock_gate_status"}, + {0x00034020, "cm_event_broadcast4"}, + {0x0003f36c, "cm_stream_switch_slave_east_3_slot3"}, + {0x00034028, "cm_event_broadcast6"}, + {0x0003402c, "cm_event_broadcast7"}, + {0x000140a0, "shim_lock10_value"}, + {0x000a009c, "mem_dma_bd4_7"}, + {0x000a0098, "mem_dma_bd4_6"}, + {0x00034510, "cm_event_group_errors0_enable"}, + {0x000a0090, "mem_dma_bd4_4"}, + {0x000a008c, "mem_dma_bd4_3"}, + {0x000a0088, "mem_dma_bd4_2"}, + {0x000a0084, "mem_dma_bd4_1"}, + {0x000a0080, "mem_dma_bd4_0"}, + {0x000a0054, "mem_dma_bd2_5"}, + {0x000a0050, "mem_dma_bd2_4"}, + {0x000a005c, "mem_dma_bd2_7"}, + {0x000a0058, "mem_dma_bd2_6"}, + {0x000a0044, "mem_dma_bd2_1"}, + {0x000a0040, "mem_dma_bd2_0"}, + {0x000a004c, "mem_dma_bd2_3"}, + {0x000a0048, "mem_dma_bd2_2"}, + {0x0003f10c, "cm_stream_switch_slave_config_tile_ctrl"}, + {0x000b0290, "mem_stream_switch_slave_south_2_slot0"}, + {0x000b0294, "mem_stream_switch_slave_south_2_slot1"}, + {0x0003f804, "cm_stream_switch_deterministic_merge_arb0_slave2_3"}, + {0x000b029c, "mem_stream_switch_slave_south_2_slot3"}, + {0x00094108, "mem_watchpoint2"}, + {0x0009410c, "mem_watchpoint3"}, + {0x00094100, "mem_watchpoint0"}, + {0x00094104, "mem_watchpoint1"}, + {0x0001de14, "mm_dma_mm2s_0_start_queue"}, + {0x0003f800, "cm_stream_switch_deterministic_merge_arb0_slave0_1"}, + {0x00014058, "mm_event_broadcast_block_south_value"}, + {0x000c0220, "mem_lock34_value"}, + {0x00094078, "mem_event_broadcast_a_block_north_value"}, + {0x0003f010, "cm_stream_switch_master_config_fifo0"}, + {0x00094094, "mem_event_broadcast_b_block_south_clr"}, + {0x000340fc, "cm_timer_high"}, + {0x000c0240, "mem_lock36_value"}, + {0x00016010, "mm_memory_control"}, + {0x00032034, "cm_error_halt_event"}, + {0x000a04f8, "mem_dma_bd39_6"}, + {0x00014400, "mm_combo_event_inputs"}, + {0x000a04f0, "mem_dma_bd39_4"}, + {0x000a04f4, "mem_dma_bd39_5"}, + {0x000a04e8, "mem_dma_bd39_2"}, + {0x000a04ec, "mem_dma_bd39_3"}, + {0x000a04e0, "mem_dma_bd39_0"}, + {0x000a04e4, "mem_dma_bd39_1"}, + {0x0009102c, "mem_performance_counter3"}, + {0x00091028, "mem_performance_counter2"}, + {0x00091024, "mem_performance_counter1"}, + {0x00091020, "mem_performance_counter0"}, + {0x0003f814, "cm_stream_switch_deterministic_merge_arb1_slave2_3"}, + {0x000c01f0, "mem_lock31_value"}, + {0x000c0150, "mem_lock21_value"}, + {0x0003f35c, "cm_stream_switch_slave_east_2_slot3"}, + {0x0003f358, "cm_stream_switch_slave_east_2_slot2"}, + {0x0003f354, "cm_stream_switch_slave_east_2_slot1"}, + {0x0003f350, "cm_stream_switch_slave_east_2_slot0"}, + {0x000a0420, "mem_dma_bd33_0"}, + {0x000a0424, "mem_dma_bd33_1"}, + {0x000a0428, "mem_dma_bd33_2"}, + {0x000a042c, "mem_dma_bd33_3"}, + {0x000a0430, "mem_dma_bd33_4"}, + {0x000a0434, "mem_dma_bd33_5"}, + {0x000a0438, "mem_dma_bd33_6"}, + {0x000a043c, "mem_dma_bd33_7"}, + {0x000b0f30, "mem_tile_control_packet_handler_status"}, + {0x0003f264, "cm_stream_switch_slave_south_1_slot1"}, + {0x0003f260, "cm_stream_switch_slave_south_1_slot0"}, + {0x0003f26c, "cm_stream_switch_slave_south_1_slot3"}, + {0x0003f268, "cm_stream_switch_slave_south_1_slot2"}, + {0x00034078, "cm_event_broadcast_block_north_value"}, + {0x00034400, "cm_combo_event_inputs"}, + {0x0001f110, "mm_locks_event_selection_4"}, + {0x000a06c0, "mem_dma_s2mm_current_write_count_4"}, + {0x000a06bc, "mem_dma_s2mm_current_write_count_3"}, + {0x0003f15c, "cm_stream_switch_slave_config_aie_trace"}, + {0x0001f10c, "mm_locks_event_selection_3"}, + {0x10, "shim_lock_step_size"}, + {0x000a06b4, "mem_dma_s2mm_current_write_count_1"}, + {0x000a06b0, "mem_dma_s2mm_current_write_count_0"}, + {0x00034070, "cm_event_broadcast_block_north_set"}, + {0x00034008, "shim_event_generate"}, + {0x000c0100, "mem_lock16_value"}, + {0x000b0818, "mem_stream_switch_deterministic_merge_arb1_ctrl"}, + {0x000140fc, "mm_timer_high"}, + {0x000c0360, "mem_lock54_value"}, + {0x8, "shim_dma_s2mm_step_size"}, + {0x00014500, "mm_event_group_0_enable"}, + {0x0001df1c, "mm_dma_s2mm_current_write_count_1"}, + {0x0001df18, "mm_dma_s2mm_current_write_count_0"}, + {0x000a0628, "mem_dma_s2mm_5_ctrl"}, + {0x0001d204, "shim_dma_s2mm_0_task_queue"}, + {0x000a047c, "mem_dma_bd35_7"}, + {0x000940c4, "mem_event_broadcast_b_block_east_clr"}, + {0x000340e0, "cm_trace_event0"}, + {0x000340e4, "cm_trace_event1"}, + {0x000c0050, "mem_lock5_value"}, + {0x00094048, "mem_event_broadcast14"}, + {0x000b0238, "mem_stream_switch_slave_dma_3_slot2"}, + {0x000b023c, "mem_stream_switch_slave_dma_3_slot3"}, + {0x000b0230, "mem_stream_switch_slave_dma_3_slot0"}, + {0x000b0234, "mem_stream_switch_slave_dma_3_slot1"}, + {0x000c03d0, "mem_lock61_value"}, + {0x000c03f0, "mem_lock63_value"}, + {0x0003f2f8, "cm_stream_switch_slave_north_0_slot2"}, + {0x0003f2fc, "cm_stream_switch_slave_north_0_slot3"}, + {0x0003f2f0, "cm_stream_switch_slave_north_0_slot0"}, + {0x0003f2f4, "cm_stream_switch_slave_north_0_slot1"}, + {0x0001d1c0, "shim_dma_bd14_0"}, + {0x0003f818, "cm_stream_switch_deterministic_merge_arb1_ctrl"}, + {0x0001d1c8, "shim_dma_bd14_2"}, + {0x0001d1cc, "shim_dma_bd14_3"}, + {0x0001d1d0, "shim_dma_bd14_4"}, + {0x0001d1d4, "shim_dma_bd14_5"}, + {0x0001d1d8, "shim_dma_bd14_6"}, + {0x0001d1dc, "shim_dma_bd14_7"}, + {0x000b0314, "mem_stream_switch_slave_trace_slot1"}, + {0x000b0310, "mem_stream_switch_slave_trace_slot0"}, + {0x000b031c, "mem_stream_switch_slave_trace_slot3"}, + {0x000b0318, "mem_stream_switch_slave_trace_slot2"}, + {0x0001d15c, "shim_dma_bd10_7"}, + {0x000c0120, "mem_lock18_value"}, + {0x000a04fc, "mem_dma_bd39_7"}, + {0x00094008, "mem_event_generate"}, + {0x0001f0f0, "mm_lock15_value"}, + {0x00014080, "shim_lock8_value"}, + {0x0003f004, "cm_stream_switch_master_config_dma0"}, + {0x0003f008, "cm_stream_switch_master_config_dma1"}, + {0x0001d090, "shim_dma_bd4_4"}, + {0x0001d094, "shim_dma_bd4_5"}, + {0x0001d098, "shim_dma_bd4_6"}, + {0x0001d09c, "shim_dma_bd4_7"}, + {0x0001d080, "shim_dma_bd4_0"}, + {0x0001d084, "shim_dma_bd4_1"}, + {0x0001d088, "shim_dma_bd4_2"}, + {0x0001d08c, "shim_dma_bd4_3"}, + {0x0001d058, "shim_dma_bd2_6"}, + {0x0001d05c, "shim_dma_bd2_7"}, + {0x0001d050, "shim_dma_bd2_4"}, + {0x0001d054, "shim_dma_bd2_5"}, + {0x0001d048, "shim_dma_bd2_2"}, + {0x0001d04c, "shim_dma_bd2_3"}, + {0x0001d040, "shim_dma_bd2_0"}, + {0x000b0118, "mem_stream_switch_slave_config_tile_ctrl"}, + {0x00014218, "mm_reserved2"}, + {0x00014060, "shim_lock6_value"}, + {0x0003f384, "cm_stream_switch_slave_mem_trace_slot1"}, + {0x0003f124, "cm_stream_switch_slave_config_south_4"}, + {0x0003f38c, "cm_stream_switch_slave_mem_trace_slot3"}, + {0x0003f388, "cm_stream_switch_slave_mem_trace_slot2"}, + {0x000a0644, "mem_dma_mm2s_2_start_queue"}, + {0x0003f114, "cm_stream_switch_slave_config_south_0"}, + {0x0003f120, "cm_stream_switch_slave_config_south_3"}, + {0x0003f11c, "cm_stream_switch_slave_config_south_2"}, + {0x000a0348, "mem_dma_bd26_2"}, + {0x000a034c, "mem_dma_bd26_3"}, + {0x000a0340, "mem_dma_bd26_0"}, + {0x000a0344, "mem_dma_bd26_1"}, + {0x000a0358, "mem_dma_bd26_6"}, + {0x000a035c, "mem_dma_bd26_7"}, + {0x000a0350, "mem_dma_bd26_4"}, + {0x000a0354, "mem_dma_bd26_5"}, + {0x000a0310, "mem_dma_bd24_4"}, + {0x000a0314, "mem_dma_bd24_5"}, + {0x000a0318, "mem_dma_bd24_6"}, + {0x000a031c, "mem_dma_bd24_7"}, + {0x000b02e4, "mem_stream_switch_slave_north_1_slot1"}, + {0x000b02e0, "mem_stream_switch_slave_north_1_slot0"}, + {0x000b02ec, "mem_stream_switch_slave_north_1_slot3"}, + {0x000b02e8, "mem_stream_switch_slave_north_1_slot2"}, + {0x0001d0c8, "shim_dma_bd6_2"}, + {0x000a02dc, "mem_dma_bd22_7"}, + {0x0001d0c0, "shim_dma_bd6_0"}, + {0x000a02d4, "mem_dma_bd22_5"}, + {0x000a02c8, "mem_dma_bd22_2"}, + {0x000a02cc, "mem_dma_bd22_3"}, + {0x000a02c0, "mem_dma_bd22_0"}, + {0x000a02c4, "mem_dma_bd22_1"}, + {0x0001f0e0, "mm_lock14_value"}, + {0x0001d1ac, "shim_dma_bd13_3"}, + {0x0001d1a8, "shim_dma_bd13_2"}, + {0x0001d1a4, "shim_dma_bd13_1"}, + {0x0001d1a0, "shim_dma_bd13_0"}, + {0x0001d1bc, "shim_dma_bd13_7"}, + {0x0001d1b8, "shim_dma_bd13_6"}, + {0x0001d1b4, "shim_dma_bd13_5"}, + {0x0001d1b0, "shim_dma_bd13_4"}, + {0x000c0270, "mem_lock39_value"}, + {0x0001d174, "shim_dma_bd11_5"}, + {0x000c0280, "mem_lock40_value"}, + {0x0001d17c, "shim_dma_bd11_7"}, + {0x0001d178, "shim_dma_bd11_6"}, + {0x0001d164, "shim_dma_bd11_1"}, + {0x0001d160, "shim_dma_bd11_0"}, + {0x0001d16c, "shim_dma_bd11_3"}, + {0x0001d168, "shim_dma_bd11_2"}, + {0x0001d124, "shim_dma_bd9_1"}, + {0x0001d120, "shim_dma_bd9_0"}, + {0x0001d12c, "shim_dma_bd9_3"}, + {0x0001d128, "shim_dma_bd9_2"}, + {0x0001d134, "shim_dma_bd9_5"}, + {0x0001d130, "shim_dma_bd9_4"}, + {0x0001d13c, "shim_dma_bd9_7"}, + {0x0001d138, "shim_dma_bd9_6"}, + {0x00034050, "shim_event_broadcast_a_block_south_set"}, + {0x00034064, "cm_event_broadcast_block_west_clr"}, + {0x0001d024, "shim_dma_bd1_1"}, + {0x0001d020, "shim_dma_bd1_0"}, + {0x0001d02c, "shim_dma_bd1_3"}, + {0x0001d028, "shim_dma_bd1_2"}, + {0x0001d034, "shim_dma_bd1_5"}, + {0x0001d030, "shim_dma_bd1_4"}, + {0x0001d03c, "shim_dma_bd1_7"}, + {0x0001d038, "shim_dma_bd1_6"}, + {0x0001f070, "mm_lock7_value"}, + {0x0001f0c0, "mm_lock12_value"}, + {0x000b0250, "mem_stream_switch_slave_dma_5_slot0"}, + {0x000b0254, "mem_stream_switch_slave_dma_5_slot1"}, + {0x000b0258, "mem_stream_switch_slave_dma_5_slot2"}, + {0x000c0330, "mem_lock51_value"}, + {0x0003f808, "cm_stream_switch_deterministic_merge_arb0_ctrl"}, + {0x00091008, "mem_performance_control2"}, + {0x00091000, "mem_performance_control0"}, + {0x00091004, "mem_performance_control1"}, + {0x00094090, "mem_event_broadcast_b_block_south_set"}, + {0x000c0300, "mem_lock48_value"}, + {0x000340d8, "cm_trace_status"}, + {0x00091080, "mem_performance_counter0_event_value"}, + {0x000140f8, "mm_timer_low"}, + {0x000c00e0, "mem_lock14_value"}, + {0x000940f4, "mem_timer_trig_event_high_value"}, + {0x000b0038, "mem_stream_switch_master_config_north3"}, + {0x000b0034, "mem_stream_switch_master_config_north2"}, + {0x0003f284, "cm_stream_switch_slave_south_3_slot1"}, + {0x0003f280, "cm_stream_switch_slave_south_3_slot0"}, + {0x000a0640, "mem_dma_mm2s_2_ctrl"}, + {0x00034008, "cm_event_generate"}, + {0x000c00b0, "mem_lock11_value"}, + {0x000c0090, "mem_lock9_value"}, + {0x00092120, "mem_ecc_failing_address"}, + {0x00012000, "mm_checkbit_error_generation"}, + {0x000a03a4, "mem_dma_bd29_1"}, + {0x000a03a0, "mem_dma_bd29_0"}, + {0x000a03ac, "mem_dma_bd29_3"}, + {0x000a03a8, "mem_dma_bd29_2"}, + {0x000a03b4, "mem_dma_bd29_5"}, + {0x000a03b0, "mem_dma_bd29_4"}, + {0x000a03bc, "mem_dma_bd29_7"}, + {0x000a03b8, "mem_dma_bd29_6"}, + {0x000fff10, "mem_module_reset_control"}, + {0x000a02a4, "mem_dma_bd21_1"}, + {0x000a02a0, "mem_dma_bd21_0"}, + {0x000a02ac, "mem_dma_bd21_3"}, + {0x000a02a8, "mem_dma_bd21_2"}, + {0x000a02b4, "mem_dma_bd21_5"}, + {0x000a02b0, "mem_dma_bd21_4"}, + {0x000a02bc, "mem_dma_bd21_7"}, + {0x000a02b8, "mem_dma_bd21_6"}, + {0x00036070, "cm_memory_control"}, + {0x000b02cc, "mem_stream_switch_slave_south_5_slot3"}, + {0x000b02c8, "mem_stream_switch_slave_south_5_slot2"}, + {0x000b02c4, "mem_stream_switch_slave_south_5_slot1"}, + {0x000b02c0, "mem_stream_switch_slave_south_5_slot0"}, + {0x00094404, "mem_combo_event_control"}, + {0x20, "shim_dma_bd_step_size"}, + {0x00032110, "cm_ecc_scrubbing_event"}, + {0x00034064, "shim_event_broadcast_a_block_west_clr"}, + {0x000a0658, "mem_dma_mm2s_5_ctrl"}, + {0x000b0138, "mem_stream_switch_slave_config_north_1"}, + {0x000b0134, "mem_stream_switch_slave_config_north_0"}, + {0x000b0140, "mem_stream_switch_slave_config_north_3"}, + {0x000b013c, "mem_stream_switch_slave_config_north_2"}, + {0x00031100, "cm_program_counter"}, + {0x0001d228, "shim_dma_mm2s_status_0"}, + {0x0001d22c, "shim_dma_mm2s_status_1"}, + {0x000a0634, "mem_dma_mm2s_0_start_queue"}, + {0x0001de04, "mm_dma_s2mm_0_start_queue"}, + {0x000340fc, "shim_timer_high"}, + {0x000a06a0, "mem_dma_event_channel_selection"}, + {0x00034520, "cm_event_group_user_event_enable"} + }; + } +}; + +/************************************************************************************* + AIE2ps Registers + *************************************************************************************/ +class AIE2psUsedRegisters : public UsedRegisters { +public: + AIE2psUsedRegisters() { + populateRegNameToValueMap(); + populateRegValueToNameMap(); + } + ~AIE2psUsedRegisters() = default; + + void populateProfileRegisters() { + // Core modules + core_addresses.emplace(aie2ps::cm_performance_control0); + core_addresses.emplace(aie2ps::cm_performance_control1); + core_addresses.emplace(aie2ps::cm_performance_control2); + core_addresses.emplace(aie2ps::cm_performance_counter0); + core_addresses.emplace(aie2ps::cm_performance_counter1); + core_addresses.emplace(aie2ps::cm_performance_counter2); + core_addresses.emplace(aie2ps::cm_performance_counter3); + core_addresses.emplace(aie2ps::cm_performance_counter0_event_value); + core_addresses.emplace(aie2ps::cm_performance_counter1_event_value); + core_addresses.emplace(aie2ps::cm_performance_counter2_event_value); + core_addresses.emplace(aie2ps::cm_performance_counter3_event_value); + + // Memory modules + memory_addresses.emplace(aie2ps::mm_performance_control0); + memory_addresses.emplace(aie2ps::mm_performance_control1); + memory_addresses.emplace(aie2ps::mm_performance_control2); + memory_addresses.emplace(aie2ps::mm_performance_control3); + memory_addresses.emplace(aie2ps::mm_performance_counter0); + memory_addresses.emplace(aie2ps::mm_performance_counter1); + memory_addresses.emplace(aie2ps::mm_performance_counter2); + memory_addresses.emplace(aie2ps::mm_performance_counter3); + memory_addresses.emplace(aie2ps::mm_performance_counter0_event_value); + memory_addresses.emplace(aie2ps::mm_performance_counter1_event_value); + + // Interface tiles + interface_addresses.emplace(aie2ps::shim_performance_control0); + interface_addresses.emplace(aie2ps::shim_performance_control1); + interface_addresses.emplace(aie2ps::shim_performance_control2); + interface_addresses.emplace(aie2ps::shim_performance_control3); + interface_addresses.emplace(aie2ps::shim_performance_control4); + interface_addresses.emplace(aie2ps::shim_performance_control5); + interface_addresses.emplace(aie2ps::shim_performance_counter0); + interface_addresses.emplace(aie2ps::shim_performance_counter1); + interface_addresses.emplace(aie2ps::shim_performance_counter2); + interface_addresses.emplace(aie2ps::shim_performance_counter3); + interface_addresses.emplace(aie2ps::shim_performance_counter4); + interface_addresses.emplace(aie2ps::shim_performance_counter5); + interface_addresses.emplace(aie2ps::shim_performance_counter0_event_value); + interface_addresses.emplace(aie2ps::shim_performance_counter1_event_value); + + // Memory tiles + memory_tile_addresses.emplace(aie2ps::mem_performance_control0); + memory_tile_addresses.emplace(aie2ps::mem_performance_control1); + memory_tile_addresses.emplace(aie2ps::mem_performance_control2); + memory_tile_addresses.emplace(aie2ps::mem_performance_control3); + memory_tile_addresses.emplace(aie2ps::mem_performance_control4); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter0); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter1); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter2); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter3); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter4); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter5); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter0_event_value); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter1_event_value); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter2_event_value); + memory_tile_addresses.emplace(aie2ps::mem_performance_counter3_event_value); + } + + void populateTraceRegisters() { + // Core modules + core_addresses.emplace(aie2ps::cm_core_status); + core_addresses.emplace(aie2ps::cm_trace_control0); + core_addresses.emplace(aie2ps::cm_trace_control1); + core_addresses.emplace(aie2ps::cm_trace_status); + core_addresses.emplace(aie2ps::cm_trace_event0); + core_addresses.emplace(aie2ps::cm_trace_event1); + core_addresses.emplace(aie2ps::cm_event_status0); + core_addresses.emplace(aie2ps::cm_event_status1); + core_addresses.emplace(aie2ps::cm_event_status2); + core_addresses.emplace(aie2ps::cm_event_status3); + core_addresses.emplace(aie2ps::cm_event_broadcast0); + core_addresses.emplace(aie2ps::cm_event_broadcast1); + core_addresses.emplace(aie2ps::cm_event_broadcast2); + core_addresses.emplace(aie2ps::cm_event_broadcast3); + core_addresses.emplace(aie2ps::cm_event_broadcast4); + core_addresses.emplace(aie2ps::cm_event_broadcast5); + core_addresses.emplace(aie2ps::cm_event_broadcast6); + core_addresses.emplace(aie2ps::cm_event_broadcast7); + core_addresses.emplace(aie2ps::cm_event_broadcast8); + core_addresses.emplace(aie2ps::cm_event_broadcast9); + core_addresses.emplace(aie2ps::cm_event_broadcast10); + core_addresses.emplace(aie2ps::cm_event_broadcast11); + core_addresses.emplace(aie2ps::cm_event_broadcast12); + core_addresses.emplace(aie2ps::cm_event_broadcast13); + core_addresses.emplace(aie2ps::cm_event_broadcast14); + core_addresses.emplace(aie2ps::cm_event_broadcast15); + core_addresses.emplace(aie2ps::cm_timer_trig_event_low_value); + core_addresses.emplace(aie2ps::cm_timer_trig_event_high_value); + core_addresses.emplace(aie2ps::cm_timer_low); + core_addresses.emplace(aie2ps::cm_timer_high); + core_addresses.emplace(aie2ps::cm_edge_detection_event_control); + core_addresses.emplace(aie2ps::cm_stream_switch_event_port_selection_0); + core_addresses.emplace(aie2ps::cm_stream_switch_event_port_selection_1); + + // Memory modules + memory_addresses.emplace(aie2ps::mm_trace_control0); + memory_addresses.emplace(aie2ps::mm_trace_control1); + memory_addresses.emplace(aie2ps::mm_trace_status); + memory_addresses.emplace(aie2ps::mm_trace_event0); + memory_addresses.emplace(aie2ps::mm_trace_event1); + memory_addresses.emplace(aie2ps::mm_event_status0); + memory_addresses.emplace(aie2ps::mm_event_status1); + memory_addresses.emplace(aie2ps::mm_event_status2); + memory_addresses.emplace(aie2ps::mm_event_status3); + memory_addresses.emplace(aie2ps::mm_event_broadcast0); + memory_addresses.emplace(aie2ps::mm_event_broadcast1); + memory_addresses.emplace(aie2ps::mm_event_broadcast2); + memory_addresses.emplace(aie2ps::mm_event_broadcast3); + memory_addresses.emplace(aie2ps::mm_event_broadcast4); + memory_addresses.emplace(aie2ps::mm_event_broadcast5); + memory_addresses.emplace(aie2ps::mm_event_broadcast6); + memory_addresses.emplace(aie2ps::mm_event_broadcast7); + memory_addresses.emplace(aie2ps::mm_event_broadcast8); + memory_addresses.emplace(aie2ps::mm_event_broadcast9); + memory_addresses.emplace(aie2ps::mm_event_broadcast10); + memory_addresses.emplace(aie2ps::mm_event_broadcast11); + memory_addresses.emplace(aie2ps::mm_event_broadcast12); + memory_addresses.emplace(aie2ps::mm_event_broadcast13); + memory_addresses.emplace(aie2ps::mm_event_broadcast14); + memory_addresses.emplace(aie2ps::mm_event_broadcast15); + + // Interface tiles + interface_addresses.emplace(aie2ps::shim_trace_control0); + interface_addresses.emplace(aie2ps::shim_trace_control1); + interface_addresses.emplace(aie2ps::shim_trace_status); + interface_addresses.emplace(aie2ps::shim_trace_event0); + interface_addresses.emplace(aie2ps::shim_trace_event1); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_0); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_1); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_2); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_3); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_4); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_5); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_6); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_7); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_8); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_9); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_10); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_11); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_12); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_13); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_14); + interface_addresses.emplace(aie2ps::shim_event_broadcast_a_15); + interface_addresses.emplace(aie2ps::shim_event_status0); + interface_addresses.emplace(aie2ps::shim_event_status1); + interface_addresses.emplace(aie2ps::shim_event_status2); + interface_addresses.emplace(aie2ps::shim_event_status3); + interface_addresses.emplace(aie2ps::shim_stream_switch_event_port_selection_0); + interface_addresses.emplace(aie2ps::shim_stream_switch_event_port_selection_1); + + // Memory tiles + memory_tile_addresses.emplace(aie2ps::mem_trace_control0); + memory_tile_addresses.emplace(aie2ps::mem_trace_control1); + memory_tile_addresses.emplace(aie2ps::mem_trace_status); + memory_tile_addresses.emplace(aie2ps::mem_trace_event0); + memory_tile_addresses.emplace(aie2ps::mem_trace_event1); + memory_tile_addresses.emplace(aie2ps::mem_dma_event_channel_selection); + memory_tile_addresses.emplace(aie2ps::mem_edge_detection_event_control); + memory_tile_addresses.emplace(aie2ps::mem_stream_switch_event_port_selection_0); + memory_tile_addresses.emplace(aie2ps::mem_stream_switch_event_port_selection_1); + memory_tile_addresses.emplace(aie2ps::mem_event_broadcast0); + memory_tile_addresses.emplace(aie2ps::mem_event_status0); + memory_tile_addresses.emplace(aie2ps::mem_event_status1); + memory_tile_addresses.emplace(aie2ps::mem_event_status2); + memory_tile_addresses.emplace(aie2ps::mem_event_status3); + memory_tile_addresses.emplace(aie2ps::mem_event_status4); + memory_tile_addresses.emplace(aie2ps::mem_event_status5); + } + + void populateRegNameToValueMap() { + regNameToValues = { + {"cm_core_bmll0_part1", aie2ps::cm_core_bmll0_part1}, + {"cm_core_bmll0_part2", aie2ps::cm_core_bmll0_part2}, + {"cm_core_bmll0_part3", aie2ps::cm_core_bmll0_part3}, + {"cm_core_bmll0_part4", aie2ps::cm_core_bmll0_part4}, + {"cm_core_bmlh0_part1", aie2ps::cm_core_bmlh0_part1}, + {"cm_core_bmlh0_part2", aie2ps::cm_core_bmlh0_part2}, + {"cm_core_bmlh0_part3", aie2ps::cm_core_bmlh0_part3}, + {"cm_core_bmlh0_part4", aie2ps::cm_core_bmlh0_part4}, + {"cm_core_bmhl0_part1", aie2ps::cm_core_bmhl0_part1}, + {"cm_core_bmhl0_part2", aie2ps::cm_core_bmhl0_part2}, + {"cm_core_bmhl0_part3", aie2ps::cm_core_bmhl0_part3}, + {"cm_core_bmhl0_part4", aie2ps::cm_core_bmhl0_part4}, + {"cm_core_bmhh0_part1", aie2ps::cm_core_bmhh0_part1}, + {"cm_core_bmhh0_part2", aie2ps::cm_core_bmhh0_part2}, + {"cm_core_bmhh0_part3", aie2ps::cm_core_bmhh0_part3}, + {"cm_core_bmhh0_part4", aie2ps::cm_core_bmhh0_part4}, + {"cm_core_bmll1_part1", aie2ps::cm_core_bmll1_part1}, + {"cm_core_bmll1_part2", aie2ps::cm_core_bmll1_part2}, + {"cm_core_bmll1_part3", aie2ps::cm_core_bmll1_part3}, + {"cm_core_bmll1_part4", aie2ps::cm_core_bmll1_part4}, + {"cm_core_bmlh1_part1", aie2ps::cm_core_bmlh1_part1}, + {"cm_core_bmlh1_part2", aie2ps::cm_core_bmlh1_part2}, + {"cm_core_bmlh1_part3", aie2ps::cm_core_bmlh1_part3}, + {"cm_core_bmlh1_part4", aie2ps::cm_core_bmlh1_part4}, + {"cm_core_bmhl1_part1", aie2ps::cm_core_bmhl1_part1}, + {"cm_core_bmhl1_part2", aie2ps::cm_core_bmhl1_part2}, + {"cm_core_bmhl1_part3", aie2ps::cm_core_bmhl1_part3}, + {"cm_core_bmhl1_part4", aie2ps::cm_core_bmhl1_part4}, + {"cm_core_bmhh1_part1", aie2ps::cm_core_bmhh1_part1}, + {"cm_core_bmhh1_part2", aie2ps::cm_core_bmhh1_part2}, + {"cm_core_bmhh1_part3", aie2ps::cm_core_bmhh1_part3}, + {"cm_core_bmhh1_part4", aie2ps::cm_core_bmhh1_part4}, + {"cm_core_bmll2_part1", aie2ps::cm_core_bmll2_part1}, + {"cm_core_bmll2_part2", aie2ps::cm_core_bmll2_part2}, + {"cm_core_bmll2_part3", aie2ps::cm_core_bmll2_part3}, + {"cm_core_bmll2_part4", aie2ps::cm_core_bmll2_part4}, + {"cm_core_bmlh2_part1", aie2ps::cm_core_bmlh2_part1}, + {"cm_core_bmlh2_part2", aie2ps::cm_core_bmlh2_part2}, + {"cm_core_bmlh2_part3", aie2ps::cm_core_bmlh2_part3}, + {"cm_core_bmlh2_part4", aie2ps::cm_core_bmlh2_part4}, + {"cm_core_bmhl2_part1", aie2ps::cm_core_bmhl2_part1}, + {"cm_core_bmhl2_part2", aie2ps::cm_core_bmhl2_part2}, + {"cm_core_bmhl2_part3", aie2ps::cm_core_bmhl2_part3}, + {"cm_core_bmhl2_part4", aie2ps::cm_core_bmhl2_part4}, + {"cm_core_bmhh2_part1", aie2ps::cm_core_bmhh2_part1}, + {"cm_core_bmhh2_part2", aie2ps::cm_core_bmhh2_part2}, + {"cm_core_bmhh2_part3", aie2ps::cm_core_bmhh2_part3}, + {"cm_core_bmhh2_part4", aie2ps::cm_core_bmhh2_part4}, + {"cm_core_bmll3_part1", aie2ps::cm_core_bmll3_part1}, + {"cm_core_bmll3_part2", aie2ps::cm_core_bmll3_part2}, + {"cm_core_bmll3_part3", aie2ps::cm_core_bmll3_part3}, + {"cm_core_bmll3_part4", aie2ps::cm_core_bmll3_part4}, + {"cm_core_bmlh3_part1", aie2ps::cm_core_bmlh3_part1}, + {"cm_core_bmlh3_part2", aie2ps::cm_core_bmlh3_part2}, + {"cm_core_bmlh3_part3", aie2ps::cm_core_bmlh3_part3}, + {"cm_core_bmlh3_part4", aie2ps::cm_core_bmlh3_part4}, + {"cm_core_bmhl3_part1", aie2ps::cm_core_bmhl3_part1}, + {"cm_core_bmhl3_part2", aie2ps::cm_core_bmhl3_part2}, + {"cm_core_bmhl3_part3", aie2ps::cm_core_bmhl3_part3}, + {"cm_core_bmhl3_part4", aie2ps::cm_core_bmhl3_part4}, + {"cm_core_bmhh3_part1", aie2ps::cm_core_bmhh3_part1}, + {"cm_core_bmhh3_part2", aie2ps::cm_core_bmhh3_part2}, + {"cm_core_bmhh3_part3", aie2ps::cm_core_bmhh3_part3}, + {"cm_core_bmhh3_part4", aie2ps::cm_core_bmhh3_part4}, + {"cm_core_bmll4_part1", aie2ps::cm_core_bmll4_part1}, + {"cm_core_bmll4_part2", aie2ps::cm_core_bmll4_part2}, + {"cm_core_bmll4_part3", aie2ps::cm_core_bmll4_part3}, + {"cm_core_bmll4_part4", aie2ps::cm_core_bmll4_part4}, + {"cm_core_bmlh4_part1", aie2ps::cm_core_bmlh4_part1}, + {"cm_core_bmlh4_part2", aie2ps::cm_core_bmlh4_part2}, + {"cm_core_bmlh4_part3", aie2ps::cm_core_bmlh4_part3}, + {"cm_core_bmlh4_part4", aie2ps::cm_core_bmlh4_part4}, + {"cm_core_bmhl4_part1", aie2ps::cm_core_bmhl4_part1}, + {"cm_core_bmhl4_part2", aie2ps::cm_core_bmhl4_part2}, + {"cm_core_bmhl4_part3", aie2ps::cm_core_bmhl4_part3}, + {"cm_core_bmhl4_part4", aie2ps::cm_core_bmhl4_part4}, + {"cm_core_bmhh4_part1", aie2ps::cm_core_bmhh4_part1}, + {"cm_core_bmhh4_part2", aie2ps::cm_core_bmhh4_part2}, + {"cm_core_bmhh4_part3", aie2ps::cm_core_bmhh4_part3}, + {"cm_core_bmhh4_part4", aie2ps::cm_core_bmhh4_part4}, + {"cm_core_bmll5_part1", aie2ps::cm_core_bmll5_part1}, + {"cm_core_bmll5_part2", aie2ps::cm_core_bmll5_part2}, + {"cm_core_bmll5_part3", aie2ps::cm_core_bmll5_part3}, + {"cm_core_bmll5_part4", aie2ps::cm_core_bmll5_part4}, + {"cm_core_bmlh5_part1", aie2ps::cm_core_bmlh5_part1}, + {"cm_core_bmlh5_part2", aie2ps::cm_core_bmlh5_part2}, + {"cm_core_bmlh5_part3", aie2ps::cm_core_bmlh5_part3}, + {"cm_core_bmlh5_part4", aie2ps::cm_core_bmlh5_part4}, + {"cm_core_bmhl5_part1", aie2ps::cm_core_bmhl5_part1}, + {"cm_core_bmhl5_part2", aie2ps::cm_core_bmhl5_part2}, + {"cm_core_bmhl5_part3", aie2ps::cm_core_bmhl5_part3}, + {"cm_core_bmhl5_part4", aie2ps::cm_core_bmhl5_part4}, + {"cm_core_bmhh5_part1", aie2ps::cm_core_bmhh5_part1}, + {"cm_core_bmhh5_part2", aie2ps::cm_core_bmhh5_part2}, + {"cm_core_bmhh5_part3", aie2ps::cm_core_bmhh5_part3}, + {"cm_core_bmhh5_part4", aie2ps::cm_core_bmhh5_part4}, + {"cm_core_bmll6_part1", aie2ps::cm_core_bmll6_part1}, + {"cm_core_bmll6_part2", aie2ps::cm_core_bmll6_part2}, + {"cm_core_bmll6_part3", aie2ps::cm_core_bmll6_part3}, + {"cm_core_bmll6_part4", aie2ps::cm_core_bmll6_part4}, + {"cm_core_bmlh6_part1", aie2ps::cm_core_bmlh6_part1}, + {"cm_core_bmlh6_part2", aie2ps::cm_core_bmlh6_part2}, + {"cm_core_bmlh6_part3", aie2ps::cm_core_bmlh6_part3}, + {"cm_core_bmlh6_part4", aie2ps::cm_core_bmlh6_part4}, + {"cm_core_bmhl6_part1", aie2ps::cm_core_bmhl6_part1}, + {"cm_core_bmhl6_part2", aie2ps::cm_core_bmhl6_part2}, + {"cm_core_bmhl6_part3", aie2ps::cm_core_bmhl6_part3}, + {"cm_core_bmhl6_part4", aie2ps::cm_core_bmhl6_part4}, + {"cm_core_bmhh6_part1", aie2ps::cm_core_bmhh6_part1}, + {"cm_core_bmhh6_part2", aie2ps::cm_core_bmhh6_part2}, + {"cm_core_bmhh6_part3", aie2ps::cm_core_bmhh6_part3}, + {"cm_core_bmhh6_part4", aie2ps::cm_core_bmhh6_part4}, + {"cm_core_bmll7_part1", aie2ps::cm_core_bmll7_part1}, + {"cm_core_bmll7_part2", aie2ps::cm_core_bmll7_part2}, + {"cm_core_bmll7_part3", aie2ps::cm_core_bmll7_part3}, + {"cm_core_bmll7_part4", aie2ps::cm_core_bmll7_part4}, + {"cm_core_bmlh7_part1", aie2ps::cm_core_bmlh7_part1}, + {"cm_core_bmlh7_part2", aie2ps::cm_core_bmlh7_part2}, + {"cm_core_bmlh7_part3", aie2ps::cm_core_bmlh7_part3}, + {"cm_core_bmlh7_part4", aie2ps::cm_core_bmlh7_part4}, + {"cm_core_bmhl7_part1", aie2ps::cm_core_bmhl7_part1}, + {"cm_core_bmhl7_part2", aie2ps::cm_core_bmhl7_part2}, + {"cm_core_bmhl7_part3", aie2ps::cm_core_bmhl7_part3}, + {"cm_core_bmhl7_part4", aie2ps::cm_core_bmhl7_part4}, + {"cm_core_bmhh7_part1", aie2ps::cm_core_bmhh7_part1}, + {"cm_core_bmhh7_part2", aie2ps::cm_core_bmhh7_part2}, + {"cm_core_bmhh7_part3", aie2ps::cm_core_bmhh7_part3}, + {"cm_core_bmhh7_part4", aie2ps::cm_core_bmhh7_part4}, + {"cm_core_x0_part1", aie2ps::cm_core_x0_part1}, + {"cm_core_x0_part2", aie2ps::cm_core_x0_part2}, + {"cm_core_x0_part3", aie2ps::cm_core_x0_part3}, + {"cm_core_x0_part4", aie2ps::cm_core_x0_part4}, + {"cm_core_x1_part1", aie2ps::cm_core_x1_part1}, + {"cm_core_x1_part2", aie2ps::cm_core_x1_part2}, + {"cm_core_x1_part3", aie2ps::cm_core_x1_part3}, + {"cm_core_x1_part4", aie2ps::cm_core_x1_part4}, + {"cm_core_x2_part1", aie2ps::cm_core_x2_part1}, + {"cm_core_x2_part2", aie2ps::cm_core_x2_part2}, + {"cm_core_x2_part3", aie2ps::cm_core_x2_part3}, + {"cm_core_x2_part4", aie2ps::cm_core_x2_part4}, + {"cm_core_x3_part1", aie2ps::cm_core_x3_part1}, + {"cm_core_x3_part2", aie2ps::cm_core_x3_part2}, + {"cm_core_x3_part3", aie2ps::cm_core_x3_part3}, + {"cm_core_x3_part4", aie2ps::cm_core_x3_part4}, + {"cm_core_x4_part1", aie2ps::cm_core_x4_part1}, + {"cm_core_x4_part2", aie2ps::cm_core_x4_part2}, + {"cm_core_x4_part3", aie2ps::cm_core_x4_part3}, + {"cm_core_x4_part4", aie2ps::cm_core_x4_part4}, + {"cm_core_x5_part1", aie2ps::cm_core_x5_part1}, + {"cm_core_x5_part2", aie2ps::cm_core_x5_part2}, + {"cm_core_x5_part3", aie2ps::cm_core_x5_part3}, + {"cm_core_x5_part4", aie2ps::cm_core_x5_part4}, + {"cm_core_x6_part1", aie2ps::cm_core_x6_part1}, + {"cm_core_x6_part2", aie2ps::cm_core_x6_part2}, + {"cm_core_x6_part3", aie2ps::cm_core_x6_part3}, + {"cm_core_x6_part4", aie2ps::cm_core_x6_part4}, + {"cm_core_x7_part1", aie2ps::cm_core_x7_part1}, + {"cm_core_x7_part2", aie2ps::cm_core_x7_part2}, + {"cm_core_x7_part3", aie2ps::cm_core_x7_part3}, + {"cm_core_x7_part4", aie2ps::cm_core_x7_part4}, + {"cm_core_x8_part1", aie2ps::cm_core_x8_part1}, + {"cm_core_x8_part2", aie2ps::cm_core_x8_part2}, + {"cm_core_x8_part3", aie2ps::cm_core_x8_part3}, + {"cm_core_x8_part4", aie2ps::cm_core_x8_part4}, + {"cm_core_x9_part1", aie2ps::cm_core_x9_part1}, + {"cm_core_x9_part2", aie2ps::cm_core_x9_part2}, + {"cm_core_x9_part3", aie2ps::cm_core_x9_part3}, + {"cm_core_x9_part4", aie2ps::cm_core_x9_part4}, + {"cm_core_x10_part1", aie2ps::cm_core_x10_part1}, + {"cm_core_x10_part2", aie2ps::cm_core_x10_part2}, + {"cm_core_x10_part3", aie2ps::cm_core_x10_part3}, + {"cm_core_x10_part4", aie2ps::cm_core_x10_part4}, + {"cm_core_x11_part1", aie2ps::cm_core_x11_part1}, + {"cm_core_x11_part2", aie2ps::cm_core_x11_part2}, + {"cm_core_x11_part3", aie2ps::cm_core_x11_part3}, + {"cm_core_x11_part4", aie2ps::cm_core_x11_part4}, + {"cm_core_ldfifol0_part1", aie2ps::cm_core_ldfifol0_part1}, + {"cm_core_ldfifol0_part2", aie2ps::cm_core_ldfifol0_part2}, + {"cm_core_ldfifol0_part3", aie2ps::cm_core_ldfifol0_part3}, + {"cm_core_ldfifol0_part4", aie2ps::cm_core_ldfifol0_part4}, + {"cm_core_ldfifoh0_part1", aie2ps::cm_core_ldfifoh0_part1}, + {"cm_core_ldfifoh0_part2", aie2ps::cm_core_ldfifoh0_part2}, + {"cm_core_ldfifoh0_part3", aie2ps::cm_core_ldfifoh0_part3}, + {"cm_core_ldfifoh0_part4", aie2ps::cm_core_ldfifoh0_part4}, + {"cm_core_ldfifol1_part1", aie2ps::cm_core_ldfifol1_part1}, + {"cm_core_ldfifol1_part2", aie2ps::cm_core_ldfifol1_part2}, + {"cm_core_ldfifol1_part3", aie2ps::cm_core_ldfifol1_part3}, + {"cm_core_ldfifol1_part4", aie2ps::cm_core_ldfifol1_part4}, + {"cm_core_ldfifoh1_part1", aie2ps::cm_core_ldfifoh1_part1}, + {"cm_core_ldfifoh1_part2", aie2ps::cm_core_ldfifoh1_part2}, + {"cm_core_ldfifoh1_part3", aie2ps::cm_core_ldfifoh1_part3}, + {"cm_core_ldfifoh1_part4", aie2ps::cm_core_ldfifoh1_part4}, + {"cm_core_stfifol_part1", aie2ps::cm_core_stfifol_part1}, + {"cm_core_stfifol_part2", aie2ps::cm_core_stfifol_part2}, + {"cm_core_stfifol_part3", aie2ps::cm_core_stfifol_part3}, + {"cm_core_stfifol_part4", aie2ps::cm_core_stfifol_part4}, + {"cm_core_stfifoh_part1", aie2ps::cm_core_stfifoh_part1}, + {"cm_core_stfifoh_part2", aie2ps::cm_core_stfifoh_part2}, + {"cm_core_stfifoh_part3", aie2ps::cm_core_stfifoh_part3}, + {"cm_core_stfifoh_part4", aie2ps::cm_core_stfifoh_part4}, + {"cm_core_fifoxtra_part1", aie2ps::cm_core_fifoxtra_part1}, + {"cm_core_fifoxtra_part2", aie2ps::cm_core_fifoxtra_part2}, + {"cm_core_fifoxtra_part3", aie2ps::cm_core_fifoxtra_part3}, + {"cm_core_fifoxtra_part4", aie2ps::cm_core_fifoxtra_part4}, + {"cm_core_eg0", aie2ps::cm_core_eg0}, + {"cm_core_eg1", aie2ps::cm_core_eg1}, + {"cm_core_eg2", aie2ps::cm_core_eg2}, + {"cm_core_eg3", aie2ps::cm_core_eg3}, + {"cm_core_eg4", aie2ps::cm_core_eg4}, + {"cm_core_eg5", aie2ps::cm_core_eg5}, + {"cm_core_eg6", aie2ps::cm_core_eg6}, + {"cm_core_eg7", aie2ps::cm_core_eg7}, + {"cm_core_eg8", aie2ps::cm_core_eg8}, + {"cm_core_eg9", aie2ps::cm_core_eg9}, + {"cm_core_eg10", aie2ps::cm_core_eg10}, + {"cm_core_eg11", aie2ps::cm_core_eg11}, + {"cm_core_f0", aie2ps::cm_core_f0}, + {"cm_core_f1", aie2ps::cm_core_f1}, + {"cm_core_f2", aie2ps::cm_core_f2}, + {"cm_core_f3", aie2ps::cm_core_f3}, + {"cm_core_f4", aie2ps::cm_core_f4}, + {"cm_core_f5", aie2ps::cm_core_f5}, + {"cm_core_f6", aie2ps::cm_core_f6}, + {"cm_core_f7", aie2ps::cm_core_f7}, + {"cm_core_f8", aie2ps::cm_core_f8}, + {"cm_core_f9", aie2ps::cm_core_f9}, + {"cm_core_f10", aie2ps::cm_core_f10}, + {"cm_core_f11", aie2ps::cm_core_f11}, + {"cm_core_r0", aie2ps::cm_core_r0}, + {"cm_core_r1", aie2ps::cm_core_r1}, + {"cm_core_r2", aie2ps::cm_core_r2}, + {"cm_core_r3", aie2ps::cm_core_r3}, + {"cm_core_r4", aie2ps::cm_core_r4}, + {"cm_core_r5", aie2ps::cm_core_r5}, + {"cm_core_r6", aie2ps::cm_core_r6}, + {"cm_core_r7", aie2ps::cm_core_r7}, + {"cm_core_r8", aie2ps::cm_core_r8}, + {"cm_core_r9", aie2ps::cm_core_r9}, + {"cm_core_r10", aie2ps::cm_core_r10}, + {"cm_core_r11", aie2ps::cm_core_r11}, + {"cm_core_r12", aie2ps::cm_core_r12}, + {"cm_core_r13", aie2ps::cm_core_r13}, + {"cm_core_r14", aie2ps::cm_core_r14}, + {"cm_core_r15", aie2ps::cm_core_r15}, + {"cm_core_r16", aie2ps::cm_core_r16}, + {"cm_core_r17", aie2ps::cm_core_r17}, + {"cm_core_r18", aie2ps::cm_core_r18}, + {"cm_core_r19", aie2ps::cm_core_r19}, + {"cm_core_r20", aie2ps::cm_core_r20}, + {"cm_core_r21", aie2ps::cm_core_r21}, + {"cm_core_r22", aie2ps::cm_core_r22}, + {"cm_core_r23", aie2ps::cm_core_r23}, + {"cm_core_r24", aie2ps::cm_core_r24}, + {"cm_core_r25", aie2ps::cm_core_r25}, + {"cm_core_r26", aie2ps::cm_core_r26}, + {"cm_core_r27", aie2ps::cm_core_r27}, + {"cm_core_r28", aie2ps::cm_core_r28}, + {"cm_core_r29", aie2ps::cm_core_r29}, + {"cm_core_r30", aie2ps::cm_core_r30}, + {"cm_core_r31", aie2ps::cm_core_r31}, + {"cm_core_m0", aie2ps::cm_core_m0}, + {"cm_core_m1", aie2ps::cm_core_m1}, + {"cm_core_m2", aie2ps::cm_core_m2}, + {"cm_core_m3", aie2ps::cm_core_m3}, + {"cm_core_m4", aie2ps::cm_core_m4}, + {"cm_core_m5", aie2ps::cm_core_m5}, + {"cm_core_m6", aie2ps::cm_core_m6}, + {"cm_core_m7", aie2ps::cm_core_m7}, + {"cm_core_dn0", aie2ps::cm_core_dn0}, + {"cm_core_dn1", aie2ps::cm_core_dn1}, + {"cm_core_dn2", aie2ps::cm_core_dn2}, + {"cm_core_dn3", aie2ps::cm_core_dn3}, + {"cm_core_dn4", aie2ps::cm_core_dn4}, + {"cm_core_dn5", aie2ps::cm_core_dn5}, + {"cm_core_dn6", aie2ps::cm_core_dn6}, + {"cm_core_dn7", aie2ps::cm_core_dn7}, + {"cm_core_dj0", aie2ps::cm_core_dj0}, + {"cm_core_dj1", aie2ps::cm_core_dj1}, + {"cm_core_dj2", aie2ps::cm_core_dj2}, + {"cm_core_dj3", aie2ps::cm_core_dj3}, + {"cm_core_dj4", aie2ps::cm_core_dj4}, + {"cm_core_dj5", aie2ps::cm_core_dj5}, + {"cm_core_dj6", aie2ps::cm_core_dj6}, + {"cm_core_dj7", aie2ps::cm_core_dj7}, + {"cm_core_dc0", aie2ps::cm_core_dc0}, + {"cm_core_dc1", aie2ps::cm_core_dc1}, + {"cm_core_dc2", aie2ps::cm_core_dc2}, + {"cm_core_dc3", aie2ps::cm_core_dc3}, + {"cm_core_dc4", aie2ps::cm_core_dc4}, + {"cm_core_dc5", aie2ps::cm_core_dc5}, + {"cm_core_dc6", aie2ps::cm_core_dc6}, + {"cm_core_dc7", aie2ps::cm_core_dc7}, + {"cm_core_p0", aie2ps::cm_core_p0}, + {"cm_core_p1", aie2ps::cm_core_p1}, + {"cm_core_p2", aie2ps::cm_core_p2}, + {"cm_core_p3", aie2ps::cm_core_p3}, + {"cm_core_p4", aie2ps::cm_core_p4}, + {"cm_core_p5", aie2ps::cm_core_p5}, + {"cm_core_p6", aie2ps::cm_core_p6}, + {"cm_core_p7", aie2ps::cm_core_p7}, + {"cm_core_s0", aie2ps::cm_core_s0}, + {"cm_core_s1", aie2ps::cm_core_s1}, + {"cm_core_s2", aie2ps::cm_core_s2}, + {"cm_core_s3", aie2ps::cm_core_s3}, + {"cm_core_pc", aie2ps::cm_core_pc}, + {"cm_program_counter", aie2ps::cm_program_counter}, + {"cm_core_fc", aie2ps::cm_core_fc}, + {"cm_core_sp", aie2ps::cm_core_sp}, + {"cm_core_lr", aie2ps::cm_core_lr}, + {"cm_core_ls", aie2ps::cm_core_ls}, + {"cm_core_le", aie2ps::cm_core_le}, + {"cm_core_lc", aie2ps::cm_core_lc}, + {"cm_core_lci", aie2ps::cm_core_lci}, + {"cm_core_cr1", aie2ps::cm_core_cr1}, + {"cm_core_cr2", aie2ps::cm_core_cr2}, + {"cm_core_cr3", aie2ps::cm_core_cr3}, + {"cm_core_sr1", aie2ps::cm_core_sr1}, + {"cm_core_sr2", aie2ps::cm_core_sr2}, + {"cm_timer_control", aie2ps::cm_timer_control}, + {"cm_event_generate", aie2ps::cm_event_generate}, + {"cm_event_broadcast0", aie2ps::cm_event_broadcast0}, + {"cm_event_broadcast1", aie2ps::cm_event_broadcast1}, + {"cm_event_broadcast2", aie2ps::cm_event_broadcast2}, + {"cm_event_broadcast3", aie2ps::cm_event_broadcast3}, + {"cm_event_broadcast4", aie2ps::cm_event_broadcast4}, + {"cm_event_broadcast5", aie2ps::cm_event_broadcast5}, + {"cm_event_broadcast6", aie2ps::cm_event_broadcast6}, + {"cm_event_broadcast7", aie2ps::cm_event_broadcast7}, + {"cm_event_broadcast8", aie2ps::cm_event_broadcast8}, + {"cm_event_broadcast9", aie2ps::cm_event_broadcast9}, + {"cm_event_broadcast10", aie2ps::cm_event_broadcast10}, + {"cm_event_broadcast11", aie2ps::cm_event_broadcast11}, + {"cm_event_broadcast12", aie2ps::cm_event_broadcast12}, + {"cm_event_broadcast13", aie2ps::cm_event_broadcast13}, + {"cm_event_broadcast14", aie2ps::cm_event_broadcast14}, + {"cm_event_broadcast15", aie2ps::cm_event_broadcast15}, + {"cm_event_broadcast_block_south_set", aie2ps::cm_event_broadcast_block_south_set}, + {"cm_event_broadcast_block_south_clr", aie2ps::cm_event_broadcast_block_south_clr}, + {"cm_event_broadcast_block_south_value", aie2ps::cm_event_broadcast_block_south_value}, + {"cm_event_broadcast_block_west_set", aie2ps::cm_event_broadcast_block_west_set}, + {"cm_event_broadcast_block_west_clr", aie2ps::cm_event_broadcast_block_west_clr}, + {"cm_event_broadcast_block_west_value", aie2ps::cm_event_broadcast_block_west_value}, + {"cm_event_broadcast_block_north_set", aie2ps::cm_event_broadcast_block_north_set}, + {"cm_event_broadcast_block_north_clr", aie2ps::cm_event_broadcast_block_north_clr}, + {"cm_event_broadcast_block_north_value", aie2ps::cm_event_broadcast_block_north_value}, + {"cm_event_broadcast_block_east_set", aie2ps::cm_event_broadcast_block_east_set}, + {"cm_event_broadcast_block_east_clr", aie2ps::cm_event_broadcast_block_east_clr}, + {"cm_event_broadcast_block_east_value", aie2ps::cm_event_broadcast_block_east_value}, + {"cm_trace_control0", aie2ps::cm_trace_control0}, + {"cm_trace_control1", aie2ps::cm_trace_control1}, + {"cm_trace_status", aie2ps::cm_trace_status}, + {"cm_trace_event0", aie2ps::cm_trace_event0}, + {"cm_trace_event1", aie2ps::cm_trace_event1}, + {"cm_timer_trig_event_low_value", aie2ps::cm_timer_trig_event_low_value}, + {"cm_timer_trig_event_high_value", aie2ps::cm_timer_trig_event_high_value}, + {"cm_timer_low", aie2ps::cm_timer_low}, + {"cm_timer_high", aie2ps::cm_timer_high}, + {"cm_event_status0", aie2ps::cm_event_status0}, + {"cm_event_status1", aie2ps::cm_event_status1}, + {"cm_event_status2", aie2ps::cm_event_status2}, + {"cm_event_status3", aie2ps::cm_event_status3}, + {"cm_combo_event_inputs", aie2ps::cm_combo_event_inputs}, + {"cm_combo_event_control", aie2ps::cm_combo_event_control}, + {"cm_edge_detection_event_control", aie2ps::cm_edge_detection_event_control}, + {"cm_event_group_0_enable", aie2ps::cm_event_group_0_enable}, + {"cm_event_group_pc_enable", aie2ps::cm_event_group_pc_enable}, + {"cm_event_group_core_stall_enable", aie2ps::cm_event_group_core_stall_enable}, + {"cm_event_group_core_program_flow_enable", aie2ps::cm_event_group_core_program_flow_enable}, + {"cm_event_group_errors0_enable", aie2ps::cm_event_group_errors0_enable}, + {"cm_event_group_errors1_enable", aie2ps::cm_event_group_errors1_enable}, + {"cm_event_group_stream_switch_enable", aie2ps::cm_event_group_stream_switch_enable}, + {"cm_event_group_broadcast_enable", aie2ps::cm_event_group_broadcast_enable}, + {"cm_event_group_user_event_enable", aie2ps::cm_event_group_user_event_enable}, + {"cm_accumulator_control", aie2ps::cm_accumulator_control}, + {"cm_memory_control", aie2ps::cm_memory_control}, + {"cm_performance_control0", aie2ps::cm_performance_control0}, + {"cm_performance_control1", aie2ps::cm_performance_control1}, + {"cm_performance_control2", aie2ps::cm_performance_control2}, + {"cm_performance_counter0", aie2ps::cm_performance_counter0}, + {"cm_performance_counter1", aie2ps::cm_performance_counter1}, + {"cm_performance_counter2", aie2ps::cm_performance_counter2}, + {"cm_performance_counter3", aie2ps::cm_performance_counter3}, + {"cm_performance_counter0_event_value", aie2ps::cm_performance_counter0_event_value}, + {"cm_performance_counter1_event_value", aie2ps::cm_performance_counter1_event_value}, + {"cm_performance_counter2_event_value", aie2ps::cm_performance_counter2_event_value}, + {"cm_performance_counter3_event_value", aie2ps::cm_performance_counter3_event_value}, + {"cm_core_control", aie2ps::cm_core_control}, + {"cm_core_status", aie2ps::cm_core_status}, + {"cm_enable_events", aie2ps::cm_enable_events}, + {"cm_reset_event", aie2ps::cm_reset_event}, + {"cm_debug_control0", aie2ps::cm_debug_control0}, + {"cm_debug_control1", aie2ps::cm_debug_control1}, + {"cm_debug_control2", aie2ps::cm_debug_control2}, + {"cm_debug_status", aie2ps::cm_debug_status}, + {"cm_pc_event0", aie2ps::cm_pc_event0}, + {"cm_pc_event1", aie2ps::cm_pc_event1}, + {"cm_pc_event2", aie2ps::cm_pc_event2}, + {"cm_pc_event3", aie2ps::cm_pc_event3}, + {"cm_error_halt_control", aie2ps::cm_error_halt_control}, + {"cm_error_halt_event", aie2ps::cm_error_halt_event}, + {"cm_core_processor_bus", aie2ps::cm_core_processor_bus}, + {"cm_ecc_scrubbing_event", aie2ps::cm_ecc_scrubbing_event}, + {"cm_stream_switch_master_config_aie_core0", aie2ps::cm_stream_switch_master_config_aie_core0}, + {"cm_stream_switch_master_config_dma0", aie2ps::cm_stream_switch_master_config_dma0}, + {"cm_stream_switch_master_config_dma1", aie2ps::cm_stream_switch_master_config_dma1}, + {"cm_stream_switch_master_config_tile_ctrl", aie2ps::cm_stream_switch_master_config_tile_ctrl}, + {"cm_stream_switch_master_config_fifo0", aie2ps::cm_stream_switch_master_config_fifo0}, + {"cm_stream_switch_master_config_south0", aie2ps::cm_stream_switch_master_config_south0}, + {"cm_stream_switch_master_config_south1", aie2ps::cm_stream_switch_master_config_south1}, + {"cm_stream_switch_master_config_south2", aie2ps::cm_stream_switch_master_config_south2}, + {"cm_stream_switch_master_config_south3", aie2ps::cm_stream_switch_master_config_south3}, + {"cm_stream_switch_master_config_west0", aie2ps::cm_stream_switch_master_config_west0}, + {"cm_stream_switch_master_config_west1", aie2ps::cm_stream_switch_master_config_west1}, + {"cm_stream_switch_master_config_west2", aie2ps::cm_stream_switch_master_config_west2}, + {"cm_stream_switch_master_config_west3", aie2ps::cm_stream_switch_master_config_west3}, + {"cm_stream_switch_master_config_north0", aie2ps::cm_stream_switch_master_config_north0}, + {"cm_stream_switch_master_config_north1", aie2ps::cm_stream_switch_master_config_north1}, + {"cm_stream_switch_master_config_north2", aie2ps::cm_stream_switch_master_config_north2}, + {"cm_stream_switch_master_config_north3", aie2ps::cm_stream_switch_master_config_north3}, + {"cm_stream_switch_master_config_north4", aie2ps::cm_stream_switch_master_config_north4}, + {"cm_stream_switch_master_config_north5", aie2ps::cm_stream_switch_master_config_north5}, + {"cm_stream_switch_master_config_east0", aie2ps::cm_stream_switch_master_config_east0}, + {"cm_stream_switch_master_config_east1", aie2ps::cm_stream_switch_master_config_east1}, + {"cm_stream_switch_master_config_east2", aie2ps::cm_stream_switch_master_config_east2}, + {"cm_stream_switch_master_config_east3", aie2ps::cm_stream_switch_master_config_east3}, + {"cm_stream_switch_slave_config_aie_core0", aie2ps::cm_stream_switch_slave_config_aie_core0}, + {"cm_stream_switch_slave_config_dma_0", aie2ps::cm_stream_switch_slave_config_dma_0}, + {"cm_stream_switch_slave_config_dma_1", aie2ps::cm_stream_switch_slave_config_dma_1}, + {"cm_stream_switch_slave_config_tile_ctrl", aie2ps::cm_stream_switch_slave_config_tile_ctrl}, + {"cm_stream_switch_slave_config_fifo_0", aie2ps::cm_stream_switch_slave_config_fifo_0}, + {"cm_stream_switch_slave_config_south_0", aie2ps::cm_stream_switch_slave_config_south_0}, + {"cm_stream_switch_slave_config_south_1", aie2ps::cm_stream_switch_slave_config_south_1}, + {"cm_stream_switch_slave_config_south_2", aie2ps::cm_stream_switch_slave_config_south_2}, + {"cm_stream_switch_slave_config_south_3", aie2ps::cm_stream_switch_slave_config_south_3}, + {"cm_stream_switch_slave_config_south_4", aie2ps::cm_stream_switch_slave_config_south_4}, + {"cm_stream_switch_slave_config_south_5", aie2ps::cm_stream_switch_slave_config_south_5}, + {"cm_stream_switch_slave_config_west_0", aie2ps::cm_stream_switch_slave_config_west_0}, + {"cm_stream_switch_slave_config_west_1", aie2ps::cm_stream_switch_slave_config_west_1}, + {"cm_stream_switch_slave_config_west_2", aie2ps::cm_stream_switch_slave_config_west_2}, + {"cm_stream_switch_slave_config_west_3", aie2ps::cm_stream_switch_slave_config_west_3}, + {"cm_stream_switch_slave_config_north_0", aie2ps::cm_stream_switch_slave_config_north_0}, + {"cm_stream_switch_slave_config_north_1", aie2ps::cm_stream_switch_slave_config_north_1}, + {"cm_stream_switch_slave_config_north_2", aie2ps::cm_stream_switch_slave_config_north_2}, + {"cm_stream_switch_slave_config_north_3", aie2ps::cm_stream_switch_slave_config_north_3}, + {"cm_stream_switch_slave_config_east_0", aie2ps::cm_stream_switch_slave_config_east_0}, + {"cm_stream_switch_slave_config_east_1", aie2ps::cm_stream_switch_slave_config_east_1}, + {"cm_stream_switch_slave_config_east_2", aie2ps::cm_stream_switch_slave_config_east_2}, + {"cm_stream_switch_slave_config_east_3", aie2ps::cm_stream_switch_slave_config_east_3}, + {"cm_stream_switch_slave_config_aie_trace", aie2ps::cm_stream_switch_slave_config_aie_trace}, + {"cm_stream_switch_slave_config_mem_trace", aie2ps::cm_stream_switch_slave_config_mem_trace}, + {"cm_stream_switch_slave_aie_core0_slot0", aie2ps::cm_stream_switch_slave_aie_core0_slot0}, + {"cm_stream_switch_slave_aie_core0_slot1", aie2ps::cm_stream_switch_slave_aie_core0_slot1}, + {"cm_stream_switch_slave_aie_core0_slot2", aie2ps::cm_stream_switch_slave_aie_core0_slot2}, + {"cm_stream_switch_slave_aie_core0_slot3", aie2ps::cm_stream_switch_slave_aie_core0_slot3}, + {"cm_stream_switch_slave_dma_0_slot0", aie2ps::cm_stream_switch_slave_dma_0_slot0}, + {"cm_stream_switch_slave_dma_0_slot1", aie2ps::cm_stream_switch_slave_dma_0_slot1}, + {"cm_stream_switch_slave_dma_0_slot2", aie2ps::cm_stream_switch_slave_dma_0_slot2}, + {"cm_stream_switch_slave_dma_0_slot3", aie2ps::cm_stream_switch_slave_dma_0_slot3}, + {"cm_stream_switch_slave_dma_1_slot0", aie2ps::cm_stream_switch_slave_dma_1_slot0}, + {"cm_stream_switch_slave_dma_1_slot1", aie2ps::cm_stream_switch_slave_dma_1_slot1}, + {"cm_stream_switch_slave_dma_1_slot2", aie2ps::cm_stream_switch_slave_dma_1_slot2}, + {"cm_stream_switch_slave_dma_1_slot3", aie2ps::cm_stream_switch_slave_dma_1_slot3}, + {"cm_stream_switch_slave_tile_ctrl_slot0", aie2ps::cm_stream_switch_slave_tile_ctrl_slot0}, + {"cm_stream_switch_slave_tile_ctrl_slot1", aie2ps::cm_stream_switch_slave_tile_ctrl_slot1}, + {"cm_stream_switch_slave_tile_ctrl_slot2", aie2ps::cm_stream_switch_slave_tile_ctrl_slot2}, + {"cm_stream_switch_slave_tile_ctrl_slot3", aie2ps::cm_stream_switch_slave_tile_ctrl_slot3}, + {"cm_stream_switch_slave_fifo_0_slot0", aie2ps::cm_stream_switch_slave_fifo_0_slot0}, + {"cm_stream_switch_slave_fifo_0_slot1", aie2ps::cm_stream_switch_slave_fifo_0_slot1}, + {"cm_stream_switch_slave_fifo_0_slot2", aie2ps::cm_stream_switch_slave_fifo_0_slot2}, + {"cm_stream_switch_slave_fifo_0_slot3", aie2ps::cm_stream_switch_slave_fifo_0_slot3}, + {"cm_stream_switch_slave_south_0_slot0", aie2ps::cm_stream_switch_slave_south_0_slot0}, + {"cm_stream_switch_slave_south_0_slot1", aie2ps::cm_stream_switch_slave_south_0_slot1}, + {"cm_stream_switch_slave_south_0_slot2", aie2ps::cm_stream_switch_slave_south_0_slot2}, + {"cm_stream_switch_slave_south_0_slot3", aie2ps::cm_stream_switch_slave_south_0_slot3}, + {"cm_stream_switch_slave_south_1_slot0", aie2ps::cm_stream_switch_slave_south_1_slot0}, + {"cm_stream_switch_slave_south_1_slot1", aie2ps::cm_stream_switch_slave_south_1_slot1}, + {"cm_stream_switch_slave_south_1_slot2", aie2ps::cm_stream_switch_slave_south_1_slot2}, + {"cm_stream_switch_slave_south_1_slot3", aie2ps::cm_stream_switch_slave_south_1_slot3}, + {"cm_stream_switch_slave_south_2_slot0", aie2ps::cm_stream_switch_slave_south_2_slot0}, + {"cm_stream_switch_slave_south_2_slot1", aie2ps::cm_stream_switch_slave_south_2_slot1}, + {"cm_stream_switch_slave_south_2_slot2", aie2ps::cm_stream_switch_slave_south_2_slot2}, + {"cm_stream_switch_slave_south_2_slot3", aie2ps::cm_stream_switch_slave_south_2_slot3}, + {"cm_stream_switch_slave_south_3_slot0", aie2ps::cm_stream_switch_slave_south_3_slot0}, + {"cm_stream_switch_slave_south_3_slot1", aie2ps::cm_stream_switch_slave_south_3_slot1}, + {"cm_stream_switch_slave_south_3_slot2", aie2ps::cm_stream_switch_slave_south_3_slot2}, + {"cm_stream_switch_slave_south_3_slot3", aie2ps::cm_stream_switch_slave_south_3_slot3}, + {"cm_stream_switch_slave_south_4_slot0", aie2ps::cm_stream_switch_slave_south_4_slot0}, + {"cm_stream_switch_slave_south_4_slot1", aie2ps::cm_stream_switch_slave_south_4_slot1}, + {"cm_stream_switch_slave_south_4_slot2", aie2ps::cm_stream_switch_slave_south_4_slot2}, + {"cm_stream_switch_slave_south_4_slot3", aie2ps::cm_stream_switch_slave_south_4_slot3}, + {"cm_stream_switch_slave_south_5_slot0", aie2ps::cm_stream_switch_slave_south_5_slot0}, + {"cm_stream_switch_slave_south_5_slot1", aie2ps::cm_stream_switch_slave_south_5_slot1}, + {"cm_stream_switch_slave_south_5_slot2", aie2ps::cm_stream_switch_slave_south_5_slot2}, + {"cm_stream_switch_slave_south_5_slot3", aie2ps::cm_stream_switch_slave_south_5_slot3}, + {"cm_stream_switch_slave_west_0_slot0", aie2ps::cm_stream_switch_slave_west_0_slot0}, + {"cm_stream_switch_slave_west_0_slot1", aie2ps::cm_stream_switch_slave_west_0_slot1}, + {"cm_stream_switch_slave_west_0_slot2", aie2ps::cm_stream_switch_slave_west_0_slot2}, + {"cm_stream_switch_slave_west_0_slot3", aie2ps::cm_stream_switch_slave_west_0_slot3}, + {"cm_stream_switch_slave_west_1_slot0", aie2ps::cm_stream_switch_slave_west_1_slot0}, + {"cm_stream_switch_slave_west_1_slot1", aie2ps::cm_stream_switch_slave_west_1_slot1}, + {"cm_stream_switch_slave_west_1_slot2", aie2ps::cm_stream_switch_slave_west_1_slot2}, + {"cm_stream_switch_slave_west_1_slot3", aie2ps::cm_stream_switch_slave_west_1_slot3}, + {"cm_stream_switch_slave_west_2_slot0", aie2ps::cm_stream_switch_slave_west_2_slot0}, + {"cm_stream_switch_slave_west_2_slot1", aie2ps::cm_stream_switch_slave_west_2_slot1}, + {"cm_stream_switch_slave_west_2_slot2", aie2ps::cm_stream_switch_slave_west_2_slot2}, + {"cm_stream_switch_slave_west_2_slot3", aie2ps::cm_stream_switch_slave_west_2_slot3}, + {"cm_stream_switch_slave_west_3_slot0", aie2ps::cm_stream_switch_slave_west_3_slot0}, + {"cm_stream_switch_slave_west_3_slot1", aie2ps::cm_stream_switch_slave_west_3_slot1}, + {"cm_stream_switch_slave_west_3_slot2", aie2ps::cm_stream_switch_slave_west_3_slot2}, + {"cm_stream_switch_slave_west_3_slot3", aie2ps::cm_stream_switch_slave_west_3_slot3}, + {"cm_stream_switch_slave_north_0_slot0", aie2ps::cm_stream_switch_slave_north_0_slot0}, + {"cm_stream_switch_slave_north_0_slot1", aie2ps::cm_stream_switch_slave_north_0_slot1}, + {"cm_stream_switch_slave_north_0_slot2", aie2ps::cm_stream_switch_slave_north_0_slot2}, + {"cm_stream_switch_slave_north_0_slot3", aie2ps::cm_stream_switch_slave_north_0_slot3}, + {"cm_stream_switch_slave_north_1_slot0", aie2ps::cm_stream_switch_slave_north_1_slot0}, + {"cm_stream_switch_slave_north_1_slot1", aie2ps::cm_stream_switch_slave_north_1_slot1}, + {"cm_stream_switch_slave_north_1_slot2", aie2ps::cm_stream_switch_slave_north_1_slot2}, + {"cm_stream_switch_slave_north_1_slot3", aie2ps::cm_stream_switch_slave_north_1_slot3}, + {"cm_stream_switch_slave_north_2_slot0", aie2ps::cm_stream_switch_slave_north_2_slot0}, + {"cm_stream_switch_slave_north_2_slot1", aie2ps::cm_stream_switch_slave_north_2_slot1}, + {"cm_stream_switch_slave_north_2_slot2", aie2ps::cm_stream_switch_slave_north_2_slot2}, + {"cm_stream_switch_slave_north_2_slot3", aie2ps::cm_stream_switch_slave_north_2_slot3}, + {"cm_stream_switch_slave_north_3_slot0", aie2ps::cm_stream_switch_slave_north_3_slot0}, + {"cm_stream_switch_slave_north_3_slot1", aie2ps::cm_stream_switch_slave_north_3_slot1}, + {"cm_stream_switch_slave_north_3_slot2", aie2ps::cm_stream_switch_slave_north_3_slot2}, + {"cm_stream_switch_slave_north_3_slot3", aie2ps::cm_stream_switch_slave_north_3_slot3}, + {"cm_stream_switch_slave_east_0_slot0", aie2ps::cm_stream_switch_slave_east_0_slot0}, + {"cm_stream_switch_slave_east_0_slot1", aie2ps::cm_stream_switch_slave_east_0_slot1}, + {"cm_stream_switch_slave_east_0_slot2", aie2ps::cm_stream_switch_slave_east_0_slot2}, + {"cm_stream_switch_slave_east_0_slot3", aie2ps::cm_stream_switch_slave_east_0_slot3}, + {"cm_stream_switch_slave_east_1_slot0", aie2ps::cm_stream_switch_slave_east_1_slot0}, + {"cm_stream_switch_slave_east_1_slot1", aie2ps::cm_stream_switch_slave_east_1_slot1}, + {"cm_stream_switch_slave_east_1_slot2", aie2ps::cm_stream_switch_slave_east_1_slot2}, + {"cm_stream_switch_slave_east_1_slot3", aie2ps::cm_stream_switch_slave_east_1_slot3}, + {"cm_stream_switch_slave_east_2_slot0", aie2ps::cm_stream_switch_slave_east_2_slot0}, + {"cm_stream_switch_slave_east_2_slot1", aie2ps::cm_stream_switch_slave_east_2_slot1}, + {"cm_stream_switch_slave_east_2_slot2", aie2ps::cm_stream_switch_slave_east_2_slot2}, + {"cm_stream_switch_slave_east_2_slot3", aie2ps::cm_stream_switch_slave_east_2_slot3}, + {"cm_stream_switch_slave_east_3_slot0", aie2ps::cm_stream_switch_slave_east_3_slot0}, + {"cm_stream_switch_slave_east_3_slot1", aie2ps::cm_stream_switch_slave_east_3_slot1}, + {"cm_stream_switch_slave_east_3_slot2", aie2ps::cm_stream_switch_slave_east_3_slot2}, + {"cm_stream_switch_slave_east_3_slot3", aie2ps::cm_stream_switch_slave_east_3_slot3}, + {"cm_stream_switch_slave_aie_trace_slot0", aie2ps::cm_stream_switch_slave_aie_trace_slot0}, + {"cm_stream_switch_slave_aie_trace_slot1", aie2ps::cm_stream_switch_slave_aie_trace_slot1}, + {"cm_stream_switch_slave_aie_trace_slot2", aie2ps::cm_stream_switch_slave_aie_trace_slot2}, + {"cm_stream_switch_slave_aie_trace_slot3", aie2ps::cm_stream_switch_slave_aie_trace_slot3}, + {"cm_stream_switch_slave_mem_trace_slot0", aie2ps::cm_stream_switch_slave_mem_trace_slot0}, + {"cm_stream_switch_slave_mem_trace_slot1", aie2ps::cm_stream_switch_slave_mem_trace_slot1}, + {"cm_stream_switch_slave_mem_trace_slot2", aie2ps::cm_stream_switch_slave_mem_trace_slot2}, + {"cm_stream_switch_slave_mem_trace_slot3", aie2ps::cm_stream_switch_slave_mem_trace_slot3}, + {"cm_stream_switch_deterministic_merge_arb0_slave0_1", aie2ps::cm_stream_switch_deterministic_merge_arb0_slave0_1}, + {"cm_stream_switch_deterministic_merge_arb0_slave2_3", aie2ps::cm_stream_switch_deterministic_merge_arb0_slave2_3}, + {"cm_stream_switch_deterministic_merge_arb0_ctrl", aie2ps::cm_stream_switch_deterministic_merge_arb0_ctrl}, + {"cm_stream_switch_deterministic_merge_arb1_slave0_1", aie2ps::cm_stream_switch_deterministic_merge_arb1_slave0_1}, + {"cm_stream_switch_deterministic_merge_arb1_slave2_3", aie2ps::cm_stream_switch_deterministic_merge_arb1_slave2_3}, + {"cm_stream_switch_deterministic_merge_arb1_ctrl", aie2ps::cm_stream_switch_deterministic_merge_arb1_ctrl}, + {"cm_stream_switch_event_port_selection_0", aie2ps::cm_stream_switch_event_port_selection_0}, + {"cm_stream_switch_event_port_selection_1", aie2ps::cm_stream_switch_event_port_selection_1}, + {"cm_stream_switch_parity_status", aie2ps::cm_stream_switch_parity_status}, + {"cm_stream_switch_parity_injection", aie2ps::cm_stream_switch_parity_injection}, + {"cm_tile_control_packet_handler_status", aie2ps::cm_tile_control_packet_handler_status}, + {"cm_stream_switch_adaptive_clock_gate_status", aie2ps::cm_stream_switch_adaptive_clock_gate_status}, + {"cm_stream_switch_adaptive_clock_gate_abort_period", aie2ps::cm_stream_switch_adaptive_clock_gate_abort_period}, + {"cm_module_clock_control", aie2ps::cm_module_clock_control}, + {"cm_tile_control", aie2ps::cm_tile_control}, + {"mm_performance_control0", aie2ps::mm_performance_control0}, + {"mm_performance_control1", aie2ps::mm_performance_control1}, + {"mm_performance_control2", aie2ps::mm_performance_control2}, + {"mm_performance_control3", aie2ps::mm_performance_control3}, + {"mm_performance_counter0", aie2ps::mm_performance_counter0}, + {"mm_performance_counter1", aie2ps::mm_performance_counter1}, + {"mm_performance_counter2", aie2ps::mm_performance_counter2}, + {"mm_performance_counter3", aie2ps::mm_performance_counter3}, + {"mm_performance_counter0_event_value", aie2ps::mm_performance_counter0_event_value}, + {"mm_performance_counter1_event_value", aie2ps::mm_performance_counter1_event_value}, + {"mm_timer_control", aie2ps::mm_timer_control}, + {"mm_event_generate", aie2ps::mm_event_generate}, + {"mm_event_broadcast0", aie2ps::mm_event_broadcast0}, + {"mm_event_broadcast1", aie2ps::mm_event_broadcast1}, + {"mm_event_broadcast2", aie2ps::mm_event_broadcast2}, + {"mm_event_broadcast3", aie2ps::mm_event_broadcast3}, + {"mm_event_broadcast4", aie2ps::mm_event_broadcast4}, + {"mm_event_broadcast5", aie2ps::mm_event_broadcast5}, + {"mm_event_broadcast6", aie2ps::mm_event_broadcast6}, + {"mm_event_broadcast7", aie2ps::mm_event_broadcast7}, + {"mm_event_broadcast8", aie2ps::mm_event_broadcast8}, + {"mm_event_broadcast9", aie2ps::mm_event_broadcast9}, + {"mm_event_broadcast10", aie2ps::mm_event_broadcast10}, + {"mm_event_broadcast11", aie2ps::mm_event_broadcast11}, + {"mm_event_broadcast12", aie2ps::mm_event_broadcast12}, + {"mm_event_broadcast13", aie2ps::mm_event_broadcast13}, + {"mm_event_broadcast14", aie2ps::mm_event_broadcast14}, + {"mm_event_broadcast15", aie2ps::mm_event_broadcast15}, + {"mm_event_broadcast_block_south_set", aie2ps::mm_event_broadcast_block_south_set}, + {"mm_event_broadcast_block_south_clr", aie2ps::mm_event_broadcast_block_south_clr}, + {"mm_event_broadcast_block_south_value", aie2ps::mm_event_broadcast_block_south_value}, + {"mm_event_broadcast_block_west_set", aie2ps::mm_event_broadcast_block_west_set}, + {"mm_event_broadcast_block_west_clr", aie2ps::mm_event_broadcast_block_west_clr}, + {"mm_event_broadcast_block_west_value", aie2ps::mm_event_broadcast_block_west_value}, + {"mm_event_broadcast_block_north_set", aie2ps::mm_event_broadcast_block_north_set}, + {"mm_event_broadcast_block_north_clr", aie2ps::mm_event_broadcast_block_north_clr}, + {"mm_event_broadcast_block_north_value", aie2ps::mm_event_broadcast_block_north_value}, + {"mm_event_broadcast_block_east_set", aie2ps::mm_event_broadcast_block_east_set}, + {"mm_event_broadcast_block_east_clr", aie2ps::mm_event_broadcast_block_east_clr}, + {"mm_event_broadcast_block_east_value", aie2ps::mm_event_broadcast_block_east_value}, + {"mm_trace_control0", aie2ps::mm_trace_control0}, + {"mm_trace_control1", aie2ps::mm_trace_control1}, + {"mm_trace_status", aie2ps::mm_trace_status}, + {"mm_trace_event0", aie2ps::mm_trace_event0}, + {"mm_trace_event1", aie2ps::mm_trace_event1}, + {"mm_timer_trig_event_low_value", aie2ps::mm_timer_trig_event_low_value}, + {"mm_timer_trig_event_high_value", aie2ps::mm_timer_trig_event_high_value}, + {"mm_timer_low", aie2ps::mm_timer_low}, + {"mm_timer_high", aie2ps::mm_timer_high}, + {"mm_watchpoint0", aie2ps::mm_watchpoint0}, + {"mm_watchpoint1", aie2ps::mm_watchpoint1}, + {"mm_event_status0", aie2ps::mm_event_status0}, + {"mm_event_status1", aie2ps::mm_event_status1}, + {"mm_event_status2", aie2ps::mm_event_status2}, + {"mm_event_status3", aie2ps::mm_event_status3}, + {"mm_combo_event_inputs", aie2ps::mm_combo_event_inputs}, + {"mm_combo_event_control", aie2ps::mm_combo_event_control}, + {"mm_edge_detection_event_control", aie2ps::mm_edge_detection_event_control}, + {"mm_event_group_0_enable", aie2ps::mm_event_group_0_enable}, + {"mm_event_group_watchpoint_enable", aie2ps::mm_event_group_watchpoint_enable}, + {"mm_event_group_dma_enable", aie2ps::mm_event_group_dma_enable}, + {"mm_event_group_lock_enable", aie2ps::mm_event_group_lock_enable}, + {"mm_event_group_memory_conflict_enable", aie2ps::mm_event_group_memory_conflict_enable}, + {"mm_event_group_error_enable", aie2ps::mm_event_group_error_enable}, + {"mm_event_group_broadcast_enable", aie2ps::mm_event_group_broadcast_enable}, + {"mm_event_group_user_event_enable", aie2ps::mm_event_group_user_event_enable}, + {"mm_memory_control", aie2ps::mm_memory_control}, + {"mm_dma_bd0_0", aie2ps::mm_dma_bd0_0}, + {"mm_dma_bd0_1", aie2ps::mm_dma_bd0_1}, + {"mm_dma_bd0_2", aie2ps::mm_dma_bd0_2}, + {"mm_dma_bd0_3", aie2ps::mm_dma_bd0_3}, + {"mm_dma_bd0_4", aie2ps::mm_dma_bd0_4}, + {"mm_dma_bd0_5", aie2ps::mm_dma_bd0_5}, + {"mm_dma_bd1_0", aie2ps::mm_dma_bd1_0}, + {"mm_dma_bd1_1", aie2ps::mm_dma_bd1_1}, + {"mm_dma_bd1_2", aie2ps::mm_dma_bd1_2}, + {"mm_dma_bd1_3", aie2ps::mm_dma_bd1_3}, + {"mm_dma_bd1_4", aie2ps::mm_dma_bd1_4}, + {"mm_dma_bd1_5", aie2ps::mm_dma_bd1_5}, + {"mm_dma_bd2_0", aie2ps::mm_dma_bd2_0}, + {"mm_dma_bd2_1", aie2ps::mm_dma_bd2_1}, + {"mm_dma_bd2_2", aie2ps::mm_dma_bd2_2}, + {"mm_dma_bd2_3", aie2ps::mm_dma_bd2_3}, + {"mm_dma_bd2_4", aie2ps::mm_dma_bd2_4}, + {"mm_dma_bd2_5", aie2ps::mm_dma_bd2_5}, + {"mm_dma_bd3_0", aie2ps::mm_dma_bd3_0}, + {"mm_dma_bd3_1", aie2ps::mm_dma_bd3_1}, + {"mm_dma_bd3_2", aie2ps::mm_dma_bd3_2}, + {"mm_dma_bd3_3", aie2ps::mm_dma_bd3_3}, + {"mm_dma_bd3_4", aie2ps::mm_dma_bd3_4}, + {"mm_dma_bd3_5", aie2ps::mm_dma_bd3_5}, + {"mm_dma_bd4_0", aie2ps::mm_dma_bd4_0}, + {"mm_dma_bd4_1", aie2ps::mm_dma_bd4_1}, + {"mm_dma_bd4_2", aie2ps::mm_dma_bd4_2}, + {"mm_dma_bd4_3", aie2ps::mm_dma_bd4_3}, + {"mm_dma_bd4_4", aie2ps::mm_dma_bd4_4}, + {"mm_dma_bd4_5", aie2ps::mm_dma_bd4_5}, + {"mm_dma_bd5_0", aie2ps::mm_dma_bd5_0}, + {"mm_dma_bd5_1", aie2ps::mm_dma_bd5_1}, + {"mm_dma_bd5_2", aie2ps::mm_dma_bd5_2}, + {"mm_dma_bd5_3", aie2ps::mm_dma_bd5_3}, + {"mm_dma_bd5_4", aie2ps::mm_dma_bd5_4}, + {"mm_dma_bd5_5", aie2ps::mm_dma_bd5_5}, + {"mm_dma_bd6_0", aie2ps::mm_dma_bd6_0}, + {"mm_dma_bd6_1", aie2ps::mm_dma_bd6_1}, + {"mm_dma_bd6_2", aie2ps::mm_dma_bd6_2}, + {"mm_dma_bd6_3", aie2ps::mm_dma_bd6_3}, + {"mm_dma_bd6_4", aie2ps::mm_dma_bd6_4}, + {"mm_dma_bd6_5", aie2ps::mm_dma_bd6_5}, + {"mm_dma_bd7_0", aie2ps::mm_dma_bd7_0}, + {"mm_dma_bd7_1", aie2ps::mm_dma_bd7_1}, + {"mm_dma_bd7_2", aie2ps::mm_dma_bd7_2}, + {"mm_dma_bd7_3", aie2ps::mm_dma_bd7_3}, + {"mm_dma_bd7_4", aie2ps::mm_dma_bd7_4}, + {"mm_dma_bd7_5", aie2ps::mm_dma_bd7_5}, + {"mm_dma_bd8_0", aie2ps::mm_dma_bd8_0}, + {"mm_dma_bd8_1", aie2ps::mm_dma_bd8_1}, + {"mm_dma_bd8_2", aie2ps::mm_dma_bd8_2}, + {"mm_dma_bd8_3", aie2ps::mm_dma_bd8_3}, + {"mm_dma_bd8_4", aie2ps::mm_dma_bd8_4}, + {"mm_dma_bd8_5", aie2ps::mm_dma_bd8_5}, + {"mm_dma_bd9_0", aie2ps::mm_dma_bd9_0}, + {"mm_dma_bd9_1", aie2ps::mm_dma_bd9_1}, + {"mm_dma_bd9_2", aie2ps::mm_dma_bd9_2}, + {"mm_dma_bd9_3", aie2ps::mm_dma_bd9_3}, + {"mm_dma_bd9_4", aie2ps::mm_dma_bd9_4}, + {"mm_dma_bd9_5", aie2ps::mm_dma_bd9_5}, + {"mm_dma_bd10_0", aie2ps::mm_dma_bd10_0}, + {"mm_dma_bd10_1", aie2ps::mm_dma_bd10_1}, + {"mm_dma_bd10_2", aie2ps::mm_dma_bd10_2}, + {"mm_dma_bd10_3", aie2ps::mm_dma_bd10_3}, + {"mm_dma_bd10_4", aie2ps::mm_dma_bd10_4}, + {"mm_dma_bd10_5", aie2ps::mm_dma_bd10_5}, + {"mm_dma_bd11_0", aie2ps::mm_dma_bd11_0}, + {"mm_dma_bd11_1", aie2ps::mm_dma_bd11_1}, + {"mm_dma_bd11_2", aie2ps::mm_dma_bd11_2}, + {"mm_dma_bd11_3", aie2ps::mm_dma_bd11_3}, + {"mm_dma_bd11_4", aie2ps::mm_dma_bd11_4}, + {"mm_dma_bd11_5", aie2ps::mm_dma_bd11_5}, + {"mm_dma_bd12_0", aie2ps::mm_dma_bd12_0}, + {"mm_dma_bd12_1", aie2ps::mm_dma_bd12_1}, + {"mm_dma_bd12_2", aie2ps::mm_dma_bd12_2}, + {"mm_dma_bd12_3", aie2ps::mm_dma_bd12_3}, + {"mm_dma_bd12_4", aie2ps::mm_dma_bd12_4}, + {"mm_dma_bd12_5", aie2ps::mm_dma_bd12_5}, + {"mm_dma_bd13_0", aie2ps::mm_dma_bd13_0}, + {"mm_dma_bd13_1", aie2ps::mm_dma_bd13_1}, + {"mm_dma_bd13_2", aie2ps::mm_dma_bd13_2}, + {"mm_dma_bd13_3", aie2ps::mm_dma_bd13_3}, + {"mm_dma_bd13_4", aie2ps::mm_dma_bd13_4}, + {"mm_dma_bd13_5", aie2ps::mm_dma_bd13_5}, + {"mm_dma_bd14_0", aie2ps::mm_dma_bd14_0}, + {"mm_dma_bd14_1", aie2ps::mm_dma_bd14_1}, + {"mm_dma_bd14_2", aie2ps::mm_dma_bd14_2}, + {"mm_dma_bd14_3", aie2ps::mm_dma_bd14_3}, + {"mm_dma_bd14_4", aie2ps::mm_dma_bd14_4}, + {"mm_dma_bd14_5", aie2ps::mm_dma_bd14_5}, + {"mm_dma_bd15_0", aie2ps::mm_dma_bd15_0}, + {"mm_dma_bd15_1", aie2ps::mm_dma_bd15_1}, + {"mm_dma_bd15_2", aie2ps::mm_dma_bd15_2}, + {"mm_dma_bd15_3", aie2ps::mm_dma_bd15_3}, + {"mm_dma_bd15_4", aie2ps::mm_dma_bd15_4}, + {"mm_dma_bd15_5", aie2ps::mm_dma_bd15_5}, + {"mm_dma_s2mm_0_ctrl", aie2ps::mm_dma_s2mm_0_ctrl}, + {"mm_dma_s2mm_0_start_queue", aie2ps::mm_dma_s2mm_0_start_queue}, + {"mm_dma_s2mm_1_ctrl", aie2ps::mm_dma_s2mm_1_ctrl}, + {"mm_dma_s2mm_1_start_queue", aie2ps::mm_dma_s2mm_1_start_queue}, + {"mm_dma_mm2s_0_ctrl", aie2ps::mm_dma_mm2s_0_ctrl}, + {"mm_dma_mm2s_0_start_queue", aie2ps::mm_dma_mm2s_0_start_queue}, + {"mm_dma_mm2s_1_ctrl", aie2ps::mm_dma_mm2s_1_ctrl}, + {"mm_dma_mm2s_1_start_queue", aie2ps::mm_dma_mm2s_1_start_queue}, + {"mm_dma_s2mm_status_0", aie2ps::mm_dma_s2mm_status_0}, + {"mm_dma_s2mm_status_1", aie2ps::mm_dma_s2mm_status_1}, + {"mm_dma_mm2s_status_0", aie2ps::mm_dma_mm2s_status_0}, + {"mm_dma_mm2s_status_1", aie2ps::mm_dma_mm2s_status_1}, + {"mm_dma_s2mm_current_write_count_0", aie2ps::mm_dma_s2mm_current_write_count_0}, + {"mm_dma_s2mm_current_write_count_1", aie2ps::mm_dma_s2mm_current_write_count_1}, + {"mm_dma_s2mm_fot_count_fifo_pop_0", aie2ps::mm_dma_s2mm_fot_count_fifo_pop_0}, + {"mm_dma_s2mm_fot_count_fifo_pop_1", aie2ps::mm_dma_s2mm_fot_count_fifo_pop_1}, + {"mm_lock0_value", aie2ps::mm_lock0_value}, + {"mm_lock1_value", aie2ps::mm_lock1_value}, + {"mm_lock2_value", aie2ps::mm_lock2_value}, + {"mm_lock3_value", aie2ps::mm_lock3_value}, + {"mm_lock4_value", aie2ps::mm_lock4_value}, + {"mm_lock5_value", aie2ps::mm_lock5_value}, + {"mm_lock6_value", aie2ps::mm_lock6_value}, + {"mm_lock7_value", aie2ps::mm_lock7_value}, + {"mm_lock8_value", aie2ps::mm_lock8_value}, + {"mm_lock9_value", aie2ps::mm_lock9_value}, + {"mm_lock10_value", aie2ps::mm_lock10_value}, + {"mm_lock11_value", aie2ps::mm_lock11_value}, + {"mm_lock12_value", aie2ps::mm_lock12_value}, + {"mm_lock13_value", aie2ps::mm_lock13_value}, + {"mm_lock14_value", aie2ps::mm_lock14_value}, + {"mm_lock15_value", aie2ps::mm_lock15_value}, + {"mm_locks_event_selection_0", aie2ps::mm_locks_event_selection_0}, + {"mm_locks_event_selection_1", aie2ps::mm_locks_event_selection_1}, + {"mm_locks_event_selection_2", aie2ps::mm_locks_event_selection_2}, + {"mm_locks_event_selection_3", aie2ps::mm_locks_event_selection_3}, + {"mm_locks_event_selection_4", aie2ps::mm_locks_event_selection_4}, + {"mm_locks_event_selection_5", aie2ps::mm_locks_event_selection_5}, + {"mm_locks_event_selection_6", aie2ps::mm_locks_event_selection_6}, + {"mm_locks_event_selection_7", aie2ps::mm_locks_event_selection_7}, + {"mm_locks_overflow", aie2ps::mm_locks_overflow}, + {"mm_locks_underflow", aie2ps::mm_locks_underflow}, + {"mm_lock_request", aie2ps::mm_lock_request}, + {"mem_performance_control0", aie2ps::mem_performance_control0}, + {"mem_performance_control1", aie2ps::mem_performance_control1}, + {"mem_performance_control2", aie2ps::mem_performance_control2}, + {"mem_performance_control3", aie2ps::mem_performance_control3}, + {"mem_performance_control4", aie2ps::mem_performance_control4}, + {"mem_performance_counter0", aie2ps::mem_performance_counter0}, + {"mem_performance_counter1", aie2ps::mem_performance_counter1}, + {"mem_performance_counter2", aie2ps::mem_performance_counter2}, + {"mem_performance_counter3", aie2ps::mem_performance_counter3}, + {"mem_performance_counter4", aie2ps::mem_performance_counter4}, + {"mem_performance_counter5", aie2ps::mem_performance_counter5}, + {"mem_performance_counter0_event_value", aie2ps::mem_performance_counter0_event_value}, + {"mem_performance_counter1_event_value", aie2ps::mem_performance_counter1_event_value}, + {"mem_performance_counter2_event_value", aie2ps::mem_performance_counter2_event_value}, + {"mem_performance_counter3_event_value", aie2ps::mem_performance_counter3_event_value}, + {"mem_timer_control", aie2ps::mem_timer_control}, + {"mem_event_generate", aie2ps::mem_event_generate}, + {"mem_event_broadcast0", aie2ps::mem_event_broadcast0}, + {"mem_event_broadcast1", aie2ps::mem_event_broadcast1}, + {"mem_event_broadcast2", aie2ps::mem_event_broadcast2}, + {"mem_event_broadcast3", aie2ps::mem_event_broadcast3}, + {"mem_event_broadcast4", aie2ps::mem_event_broadcast4}, + {"mem_event_broadcast5", aie2ps::mem_event_broadcast5}, + {"mem_event_broadcast6", aie2ps::mem_event_broadcast6}, + {"mem_event_broadcast7", aie2ps::mem_event_broadcast7}, + {"mem_event_broadcast8", aie2ps::mem_event_broadcast8}, + {"mem_event_broadcast9", aie2ps::mem_event_broadcast9}, + {"mem_event_broadcast10", aie2ps::mem_event_broadcast10}, + {"mem_event_broadcast11", aie2ps::mem_event_broadcast11}, + {"mem_event_broadcast12", aie2ps::mem_event_broadcast12}, + {"mem_event_broadcast13", aie2ps::mem_event_broadcast13}, + {"mem_event_broadcast14", aie2ps::mem_event_broadcast14}, + {"mem_event_broadcast15", aie2ps::mem_event_broadcast15}, + {"mem_event_broadcast_a_block_south_set", aie2ps::mem_event_broadcast_a_block_south_set}, + {"mem_event_broadcast_a_block_south_clr", aie2ps::mem_event_broadcast_a_block_south_clr}, + {"mem_event_broadcast_a_block_south_value", aie2ps::mem_event_broadcast_a_block_south_value}, + {"mem_event_broadcast_a_block_west_set", aie2ps::mem_event_broadcast_a_block_west_set}, + {"mem_event_broadcast_a_block_west_clr", aie2ps::mem_event_broadcast_a_block_west_clr}, + {"mem_event_broadcast_a_block_west_value", aie2ps::mem_event_broadcast_a_block_west_value}, + {"mem_event_broadcast_a_block_north_set", aie2ps::mem_event_broadcast_a_block_north_set}, + {"mem_event_broadcast_a_block_north_clr", aie2ps::mem_event_broadcast_a_block_north_clr}, + {"mem_event_broadcast_a_block_north_value", aie2ps::mem_event_broadcast_a_block_north_value}, + {"mem_event_broadcast_a_block_east_set", aie2ps::mem_event_broadcast_a_block_east_set}, + {"mem_event_broadcast_a_block_east_clr", aie2ps::mem_event_broadcast_a_block_east_clr}, + {"mem_event_broadcast_a_block_east_value", aie2ps::mem_event_broadcast_a_block_east_value}, + {"mem_event_broadcast_b_block_south_set", aie2ps::mem_event_broadcast_b_block_south_set}, + {"mem_event_broadcast_b_block_south_clr", aie2ps::mem_event_broadcast_b_block_south_clr}, + {"mem_event_broadcast_b_block_south_value", aie2ps::mem_event_broadcast_b_block_south_value}, + {"mem_event_broadcast_b_block_west_set", aie2ps::mem_event_broadcast_b_block_west_set}, + {"mem_event_broadcast_b_block_west_clr", aie2ps::mem_event_broadcast_b_block_west_clr}, + {"mem_event_broadcast_b_block_west_value", aie2ps::mem_event_broadcast_b_block_west_value}, + {"mem_event_broadcast_b_block_north_set", aie2ps::mem_event_broadcast_b_block_north_set}, + {"mem_event_broadcast_b_block_north_clr", aie2ps::mem_event_broadcast_b_block_north_clr}, + {"mem_event_broadcast_b_block_north_value", aie2ps::mem_event_broadcast_b_block_north_value}, + {"mem_event_broadcast_b_block_east_set", aie2ps::mem_event_broadcast_b_block_east_set}, + {"mem_event_broadcast_b_block_east_clr", aie2ps::mem_event_broadcast_b_block_east_clr}, + {"mem_event_broadcast_b_block_east_value", aie2ps::mem_event_broadcast_b_block_east_value}, + {"mem_trace_control0", aie2ps::mem_trace_control0}, + {"mem_trace_control1", aie2ps::mem_trace_control1}, + {"mem_trace_status", aie2ps::mem_trace_status}, + {"mem_trace_event0", aie2ps::mem_trace_event0}, + {"mem_trace_event1", aie2ps::mem_trace_event1}, + {"mem_timer_trig_event_low_value", aie2ps::mem_timer_trig_event_low_value}, + {"mem_timer_trig_event_high_value", aie2ps::mem_timer_trig_event_high_value}, + {"mem_timer_low", aie2ps::mem_timer_low}, + {"mem_timer_high", aie2ps::mem_timer_high}, + {"mem_watchpoint0", aie2ps::mem_watchpoint0}, + {"mem_watchpoint1", aie2ps::mem_watchpoint1}, + {"mem_watchpoint2", aie2ps::mem_watchpoint2}, + {"mem_watchpoint3", aie2ps::mem_watchpoint3}, + {"mem_event_status0", aie2ps::mem_event_status0}, + {"mem_event_status1", aie2ps::mem_event_status1}, + {"mem_event_status2", aie2ps::mem_event_status2}, + {"mem_event_status3", aie2ps::mem_event_status3}, + {"mem_event_status4", aie2ps::mem_event_status4}, + {"mem_event_status5", aie2ps::mem_event_status5}, + {"mem_combo_event_inputs", aie2ps::mem_combo_event_inputs}, + {"mem_combo_event_control", aie2ps::mem_combo_event_control}, + {"mem_edge_detection_event_control", aie2ps::mem_edge_detection_event_control}, + {"mem_event_group_0_enable", aie2ps::mem_event_group_0_enable}, + {"mem_event_group_watchpoint_enable", aie2ps::mem_event_group_watchpoint_enable}, + {"mem_event_group_dma_enable", aie2ps::mem_event_group_dma_enable}, + {"mem_event_group_lock_enable", aie2ps::mem_event_group_lock_enable}, + {"mem_event_group_stream_switch_enable", aie2ps::mem_event_group_stream_switch_enable}, + {"mem_event_group_memory_conflict_enable", aie2ps::mem_event_group_memory_conflict_enable}, + {"mem_event_group_error_enable", aie2ps::mem_event_group_error_enable}, + {"mem_event_group_broadcast_enable", aie2ps::mem_event_group_broadcast_enable}, + {"mem_event_group_user_event_enable", aie2ps::mem_event_group_user_event_enable}, + {"mem_memory_control", aie2ps::mem_memory_control}, + {"mem_dma_bd0_0", aie2ps::mem_dma_bd0_0}, + {"mem_dma_bd0_1", aie2ps::mem_dma_bd0_1}, + {"mem_dma_bd0_2", aie2ps::mem_dma_bd0_2}, + {"mem_dma_bd0_3", aie2ps::mem_dma_bd0_3}, + {"mem_dma_bd0_4", aie2ps::mem_dma_bd0_4}, + {"mem_dma_bd0_5", aie2ps::mem_dma_bd0_5}, + {"mem_dma_bd0_6", aie2ps::mem_dma_bd0_6}, + {"mem_dma_bd0_7", aie2ps::mem_dma_bd0_7}, + {"mem_dma_bd1_0", aie2ps::mem_dma_bd1_0}, + {"mem_dma_bd1_1", aie2ps::mem_dma_bd1_1}, + {"mem_dma_bd1_2", aie2ps::mem_dma_bd1_2}, + {"mem_dma_bd1_3", aie2ps::mem_dma_bd1_3}, + {"mem_dma_bd1_4", aie2ps::mem_dma_bd1_4}, + {"mem_dma_bd1_5", aie2ps::mem_dma_bd1_5}, + {"mem_dma_bd1_6", aie2ps::mem_dma_bd1_6}, + {"mem_dma_bd1_7", aie2ps::mem_dma_bd1_7}, + {"mem_dma_bd2_0", aie2ps::mem_dma_bd2_0}, + {"mem_dma_bd2_1", aie2ps::mem_dma_bd2_1}, + {"mem_dma_bd2_2", aie2ps::mem_dma_bd2_2}, + {"mem_dma_bd2_3", aie2ps::mem_dma_bd2_3}, + {"mem_dma_bd2_4", aie2ps::mem_dma_bd2_4}, + {"mem_dma_bd2_5", aie2ps::mem_dma_bd2_5}, + {"mem_dma_bd2_6", aie2ps::mem_dma_bd2_6}, + {"mem_dma_bd2_7", aie2ps::mem_dma_bd2_7}, + {"mem_dma_bd3_0", aie2ps::mem_dma_bd3_0}, + {"mem_dma_bd3_1", aie2ps::mem_dma_bd3_1}, + {"mem_dma_bd3_2", aie2ps::mem_dma_bd3_2}, + {"mem_dma_bd3_3", aie2ps::mem_dma_bd3_3}, + {"mem_dma_bd3_4", aie2ps::mem_dma_bd3_4}, + {"mem_dma_bd3_5", aie2ps::mem_dma_bd3_5}, + {"mem_dma_bd3_6", aie2ps::mem_dma_bd3_6}, + {"mem_dma_bd3_7", aie2ps::mem_dma_bd3_7}, + {"mem_dma_bd4_0", aie2ps::mem_dma_bd4_0}, + {"mem_dma_bd4_1", aie2ps::mem_dma_bd4_1}, + {"mem_dma_bd4_2", aie2ps::mem_dma_bd4_2}, + {"mem_dma_bd4_3", aie2ps::mem_dma_bd4_3}, + {"mem_dma_bd4_4", aie2ps::mem_dma_bd4_4}, + {"mem_dma_bd4_5", aie2ps::mem_dma_bd4_5}, + {"mem_dma_bd4_6", aie2ps::mem_dma_bd4_6}, + {"mem_dma_bd4_7", aie2ps::mem_dma_bd4_7}, + {"mem_dma_bd5_0", aie2ps::mem_dma_bd5_0}, + {"mem_dma_bd5_1", aie2ps::mem_dma_bd5_1}, + {"mem_dma_bd5_2", aie2ps::mem_dma_bd5_2}, + {"mem_dma_bd5_3", aie2ps::mem_dma_bd5_3}, + {"mem_dma_bd5_4", aie2ps::mem_dma_bd5_4}, + {"mem_dma_bd5_5", aie2ps::mem_dma_bd5_5}, + {"mem_dma_bd5_6", aie2ps::mem_dma_bd5_6}, + {"mem_dma_bd5_7", aie2ps::mem_dma_bd5_7}, + {"mem_dma_bd6_0", aie2ps::mem_dma_bd6_0}, + {"mem_dma_bd6_1", aie2ps::mem_dma_bd6_1}, + {"mem_dma_bd6_2", aie2ps::mem_dma_bd6_2}, + {"mem_dma_bd6_3", aie2ps::mem_dma_bd6_3}, + {"mem_dma_bd6_4", aie2ps::mem_dma_bd6_4}, + {"mem_dma_bd6_5", aie2ps::mem_dma_bd6_5}, + {"mem_dma_bd6_6", aie2ps::mem_dma_bd6_6}, + {"mem_dma_bd6_7", aie2ps::mem_dma_bd6_7}, + {"mem_dma_bd7_0", aie2ps::mem_dma_bd7_0}, + {"mem_dma_bd7_1", aie2ps::mem_dma_bd7_1}, + {"mem_dma_bd7_2", aie2ps::mem_dma_bd7_2}, + {"mem_dma_bd7_3", aie2ps::mem_dma_bd7_3}, + {"mem_dma_bd7_4", aie2ps::mem_dma_bd7_4}, + {"mem_dma_bd7_5", aie2ps::mem_dma_bd7_5}, + {"mem_dma_bd7_6", aie2ps::mem_dma_bd7_6}, + {"mem_dma_bd7_7", aie2ps::mem_dma_bd7_7}, + {"mem_dma_bd8_0", aie2ps::mem_dma_bd8_0}, + {"mem_dma_bd8_1", aie2ps::mem_dma_bd8_1}, + {"mem_dma_bd8_2", aie2ps::mem_dma_bd8_2}, + {"mem_dma_bd8_3", aie2ps::mem_dma_bd8_3}, + {"mem_dma_bd8_4", aie2ps::mem_dma_bd8_4}, + {"mem_dma_bd8_5", aie2ps::mem_dma_bd8_5}, + {"mem_dma_bd8_6", aie2ps::mem_dma_bd8_6}, + {"mem_dma_bd8_7", aie2ps::mem_dma_bd8_7}, + {"mem_dma_bd9_0", aie2ps::mem_dma_bd9_0}, + {"mem_dma_bd9_1", aie2ps::mem_dma_bd9_1}, + {"mem_dma_bd9_2", aie2ps::mem_dma_bd9_2}, + {"mem_dma_bd9_3", aie2ps::mem_dma_bd9_3}, + {"mem_dma_bd9_4", aie2ps::mem_dma_bd9_4}, + {"mem_dma_bd9_5", aie2ps::mem_dma_bd9_5}, + {"mem_dma_bd9_6", aie2ps::mem_dma_bd9_6}, + {"mem_dma_bd9_7", aie2ps::mem_dma_bd9_7}, + {"mem_dma_bd10_0", aie2ps::mem_dma_bd10_0}, + {"mem_dma_bd10_1", aie2ps::mem_dma_bd10_1}, + {"mem_dma_bd10_2", aie2ps::mem_dma_bd10_2}, + {"mem_dma_bd10_3", aie2ps::mem_dma_bd10_3}, + {"mem_dma_bd10_4", aie2ps::mem_dma_bd10_4}, + {"mem_dma_bd10_5", aie2ps::mem_dma_bd10_5}, + {"mem_dma_bd10_6", aie2ps::mem_dma_bd10_6}, + {"mem_dma_bd10_7", aie2ps::mem_dma_bd10_7}, + {"mem_dma_bd11_0", aie2ps::mem_dma_bd11_0}, + {"mem_dma_bd11_1", aie2ps::mem_dma_bd11_1}, + {"mem_dma_bd11_2", aie2ps::mem_dma_bd11_2}, + {"mem_dma_bd11_3", aie2ps::mem_dma_bd11_3}, + {"mem_dma_bd11_4", aie2ps::mem_dma_bd11_4}, + {"mem_dma_bd11_5", aie2ps::mem_dma_bd11_5}, + {"mem_dma_bd11_6", aie2ps::mem_dma_bd11_6}, + {"mem_dma_bd11_7", aie2ps::mem_dma_bd11_7}, + {"mem_dma_bd12_0", aie2ps::mem_dma_bd12_0}, + {"mem_dma_bd12_1", aie2ps::mem_dma_bd12_1}, + {"mem_dma_bd12_2", aie2ps::mem_dma_bd12_2}, + {"mem_dma_bd12_3", aie2ps::mem_dma_bd12_3}, + {"mem_dma_bd12_4", aie2ps::mem_dma_bd12_4}, + {"mem_dma_bd12_5", aie2ps::mem_dma_bd12_5}, + {"mem_dma_bd12_6", aie2ps::mem_dma_bd12_6}, + {"mem_dma_bd12_7", aie2ps::mem_dma_bd12_7}, + {"mem_dma_bd13_0", aie2ps::mem_dma_bd13_0}, + {"mem_dma_bd13_1", aie2ps::mem_dma_bd13_1}, + {"mem_dma_bd13_2", aie2ps::mem_dma_bd13_2}, + {"mem_dma_bd13_3", aie2ps::mem_dma_bd13_3}, + {"mem_dma_bd13_4", aie2ps::mem_dma_bd13_4}, + {"mem_dma_bd13_5", aie2ps::mem_dma_bd13_5}, + {"mem_dma_bd13_6", aie2ps::mem_dma_bd13_6}, + {"mem_dma_bd13_7", aie2ps::mem_dma_bd13_7}, + {"mem_dma_bd14_0", aie2ps::mem_dma_bd14_0}, + {"mem_dma_bd14_1", aie2ps::mem_dma_bd14_1}, + {"mem_dma_bd14_2", aie2ps::mem_dma_bd14_2}, + {"mem_dma_bd14_3", aie2ps::mem_dma_bd14_3}, + {"mem_dma_bd14_4", aie2ps::mem_dma_bd14_4}, + {"mem_dma_bd14_5", aie2ps::mem_dma_bd14_5}, + {"mem_dma_bd14_6", aie2ps::mem_dma_bd14_6}, + {"mem_dma_bd14_7", aie2ps::mem_dma_bd14_7}, + {"mem_dma_bd15_0", aie2ps::mem_dma_bd15_0}, + {"mem_dma_bd15_1", aie2ps::mem_dma_bd15_1}, + {"mem_dma_bd15_2", aie2ps::mem_dma_bd15_2}, + {"mem_dma_bd15_3", aie2ps::mem_dma_bd15_3}, + {"mem_dma_bd15_4", aie2ps::mem_dma_bd15_4}, + {"mem_dma_bd15_5", aie2ps::mem_dma_bd15_5}, + {"mem_dma_bd15_6", aie2ps::mem_dma_bd15_6}, + {"mem_dma_bd15_7", aie2ps::mem_dma_bd15_7}, + {"mem_dma_bd16_0", aie2ps::mem_dma_bd16_0}, + {"mem_dma_bd16_1", aie2ps::mem_dma_bd16_1}, + {"mem_dma_bd16_2", aie2ps::mem_dma_bd16_2}, + {"mem_dma_bd16_3", aie2ps::mem_dma_bd16_3}, + {"mem_dma_bd16_4", aie2ps::mem_dma_bd16_4}, + {"mem_dma_bd16_5", aie2ps::mem_dma_bd16_5}, + {"mem_dma_bd16_6", aie2ps::mem_dma_bd16_6}, + {"mem_dma_bd16_7", aie2ps::mem_dma_bd16_7}, + {"mem_dma_bd17_0", aie2ps::mem_dma_bd17_0}, + {"mem_dma_bd17_1", aie2ps::mem_dma_bd17_1}, + {"mem_dma_bd17_2", aie2ps::mem_dma_bd17_2}, + {"mem_dma_bd17_3", aie2ps::mem_dma_bd17_3}, + {"mem_dma_bd17_4", aie2ps::mem_dma_bd17_4}, + {"mem_dma_bd17_5", aie2ps::mem_dma_bd17_5}, + {"mem_dma_bd17_6", aie2ps::mem_dma_bd17_6}, + {"mem_dma_bd17_7", aie2ps::mem_dma_bd17_7}, + {"mem_dma_bd18_0", aie2ps::mem_dma_bd18_0}, + {"mem_dma_bd18_1", aie2ps::mem_dma_bd18_1}, + {"mem_dma_bd18_2", aie2ps::mem_dma_bd18_2}, + {"mem_dma_bd18_3", aie2ps::mem_dma_bd18_3}, + {"mem_dma_bd18_4", aie2ps::mem_dma_bd18_4}, + {"mem_dma_bd18_5", aie2ps::mem_dma_bd18_5}, + {"mem_dma_bd18_6", aie2ps::mem_dma_bd18_6}, + {"mem_dma_bd18_7", aie2ps::mem_dma_bd18_7}, + {"mem_dma_bd19_0", aie2ps::mem_dma_bd19_0}, + {"mem_dma_bd19_1", aie2ps::mem_dma_bd19_1}, + {"mem_dma_bd19_2", aie2ps::mem_dma_bd19_2}, + {"mem_dma_bd19_3", aie2ps::mem_dma_bd19_3}, + {"mem_dma_bd19_4", aie2ps::mem_dma_bd19_4}, + {"mem_dma_bd19_5", aie2ps::mem_dma_bd19_5}, + {"mem_dma_bd19_6", aie2ps::mem_dma_bd19_6}, + {"mem_dma_bd19_7", aie2ps::mem_dma_bd19_7}, + {"mem_dma_bd20_0", aie2ps::mem_dma_bd20_0}, + {"mem_dma_bd20_1", aie2ps::mem_dma_bd20_1}, + {"mem_dma_bd20_2", aie2ps::mem_dma_bd20_2}, + {"mem_dma_bd20_3", aie2ps::mem_dma_bd20_3}, + {"mem_dma_bd20_4", aie2ps::mem_dma_bd20_4}, + {"mem_dma_bd20_5", aie2ps::mem_dma_bd20_5}, + {"mem_dma_bd20_6", aie2ps::mem_dma_bd20_6}, + {"mem_dma_bd20_7", aie2ps::mem_dma_bd20_7}, + {"mem_dma_bd21_0", aie2ps::mem_dma_bd21_0}, + {"mem_dma_bd21_1", aie2ps::mem_dma_bd21_1}, + {"mem_dma_bd21_2", aie2ps::mem_dma_bd21_2}, + {"mem_dma_bd21_3", aie2ps::mem_dma_bd21_3}, + {"mem_dma_bd21_4", aie2ps::mem_dma_bd21_4}, + {"mem_dma_bd21_5", aie2ps::mem_dma_bd21_5}, + {"mem_dma_bd21_6", aie2ps::mem_dma_bd21_6}, + {"mem_dma_bd21_7", aie2ps::mem_dma_bd21_7}, + {"mem_dma_bd22_0", aie2ps::mem_dma_bd22_0}, + {"mem_dma_bd22_1", aie2ps::mem_dma_bd22_1}, + {"mem_dma_bd22_2", aie2ps::mem_dma_bd22_2}, + {"mem_dma_bd22_3", aie2ps::mem_dma_bd22_3}, + {"mem_dma_bd22_4", aie2ps::mem_dma_bd22_4}, + {"mem_dma_bd22_5", aie2ps::mem_dma_bd22_5}, + {"mem_dma_bd22_6", aie2ps::mem_dma_bd22_6}, + {"mem_dma_bd22_7", aie2ps::mem_dma_bd22_7}, + {"mem_dma_bd23_0", aie2ps::mem_dma_bd23_0}, + {"mem_dma_bd23_1", aie2ps::mem_dma_bd23_1}, + {"mem_dma_bd23_2", aie2ps::mem_dma_bd23_2}, + {"mem_dma_bd23_3", aie2ps::mem_dma_bd23_3}, + {"mem_dma_bd23_4", aie2ps::mem_dma_bd23_4}, + {"mem_dma_bd23_5", aie2ps::mem_dma_bd23_5}, + {"mem_dma_bd23_6", aie2ps::mem_dma_bd23_6}, + {"mem_dma_bd23_7", aie2ps::mem_dma_bd23_7}, + {"mem_dma_bd24_0", aie2ps::mem_dma_bd24_0}, + {"mem_dma_bd24_1", aie2ps::mem_dma_bd24_1}, + {"mem_dma_bd24_2", aie2ps::mem_dma_bd24_2}, + {"mem_dma_bd24_3", aie2ps::mem_dma_bd24_3}, + {"mem_dma_bd24_4", aie2ps::mem_dma_bd24_4}, + {"mem_dma_bd24_5", aie2ps::mem_dma_bd24_5}, + {"mem_dma_bd24_6", aie2ps::mem_dma_bd24_6}, + {"mem_dma_bd24_7", aie2ps::mem_dma_bd24_7}, + {"mem_dma_bd25_0", aie2ps::mem_dma_bd25_0}, + {"mem_dma_bd25_1", aie2ps::mem_dma_bd25_1}, + {"mem_dma_bd25_2", aie2ps::mem_dma_bd25_2}, + {"mem_dma_bd25_3", aie2ps::mem_dma_bd25_3}, + {"mem_dma_bd25_4", aie2ps::mem_dma_bd25_4}, + {"mem_dma_bd25_5", aie2ps::mem_dma_bd25_5}, + {"mem_dma_bd25_6", aie2ps::mem_dma_bd25_6}, + {"mem_dma_bd25_7", aie2ps::mem_dma_bd25_7}, + {"mem_dma_bd26_0", aie2ps::mem_dma_bd26_0}, + {"mem_dma_bd26_1", aie2ps::mem_dma_bd26_1}, + {"mem_dma_bd26_2", aie2ps::mem_dma_bd26_2}, + {"mem_dma_bd26_3", aie2ps::mem_dma_bd26_3}, + {"mem_dma_bd26_4", aie2ps::mem_dma_bd26_4}, + {"mem_dma_bd26_5", aie2ps::mem_dma_bd26_5}, + {"mem_dma_bd26_6", aie2ps::mem_dma_bd26_6}, + {"mem_dma_bd26_7", aie2ps::mem_dma_bd26_7}, + {"mem_dma_bd27_0", aie2ps::mem_dma_bd27_0}, + {"mem_dma_bd27_1", aie2ps::mem_dma_bd27_1}, + {"mem_dma_bd27_2", aie2ps::mem_dma_bd27_2}, + {"mem_dma_bd27_3", aie2ps::mem_dma_bd27_3}, + {"mem_dma_bd27_4", aie2ps::mem_dma_bd27_4}, + {"mem_dma_bd27_5", aie2ps::mem_dma_bd27_5}, + {"mem_dma_bd27_6", aie2ps::mem_dma_bd27_6}, + {"mem_dma_bd27_7", aie2ps::mem_dma_bd27_7}, + {"mem_dma_bd28_0", aie2ps::mem_dma_bd28_0}, + {"mem_dma_bd28_1", aie2ps::mem_dma_bd28_1}, + {"mem_dma_bd28_2", aie2ps::mem_dma_bd28_2}, + {"mem_dma_bd28_3", aie2ps::mem_dma_bd28_3}, + {"mem_dma_bd28_4", aie2ps::mem_dma_bd28_4}, + {"mem_dma_bd28_5", aie2ps::mem_dma_bd28_5}, + {"mem_dma_bd28_6", aie2ps::mem_dma_bd28_6}, + {"mem_dma_bd28_7", aie2ps::mem_dma_bd28_7}, + {"mem_dma_bd29_0", aie2ps::mem_dma_bd29_0}, + {"mem_dma_bd29_1", aie2ps::mem_dma_bd29_1}, + {"mem_dma_bd29_2", aie2ps::mem_dma_bd29_2}, + {"mem_dma_bd29_3", aie2ps::mem_dma_bd29_3}, + {"mem_dma_bd29_4", aie2ps::mem_dma_bd29_4}, + {"mem_dma_bd29_5", aie2ps::mem_dma_bd29_5}, + {"mem_dma_bd29_6", aie2ps::mem_dma_bd29_6}, + {"mem_dma_bd29_7", aie2ps::mem_dma_bd29_7}, + {"mem_dma_bd30_0", aie2ps::mem_dma_bd30_0}, + {"mem_dma_bd30_1", aie2ps::mem_dma_bd30_1}, + {"mem_dma_bd30_2", aie2ps::mem_dma_bd30_2}, + {"mem_dma_bd30_3", aie2ps::mem_dma_bd30_3}, + {"mem_dma_bd30_4", aie2ps::mem_dma_bd30_4}, + {"mem_dma_bd30_5", aie2ps::mem_dma_bd30_5}, + {"mem_dma_bd30_6", aie2ps::mem_dma_bd30_6}, + {"mem_dma_bd30_7", aie2ps::mem_dma_bd30_7}, + {"mem_dma_bd31_0", aie2ps::mem_dma_bd31_0}, + {"mem_dma_bd31_1", aie2ps::mem_dma_bd31_1}, + {"mem_dma_bd31_2", aie2ps::mem_dma_bd31_2}, + {"mem_dma_bd31_3", aie2ps::mem_dma_bd31_3}, + {"mem_dma_bd31_4", aie2ps::mem_dma_bd31_4}, + {"mem_dma_bd31_5", aie2ps::mem_dma_bd31_5}, + {"mem_dma_bd31_6", aie2ps::mem_dma_bd31_6}, + {"mem_dma_bd31_7", aie2ps::mem_dma_bd31_7}, + {"mem_dma_bd32_0", aie2ps::mem_dma_bd32_0}, + {"mem_dma_bd32_1", aie2ps::mem_dma_bd32_1}, + {"mem_dma_bd32_2", aie2ps::mem_dma_bd32_2}, + {"mem_dma_bd32_3", aie2ps::mem_dma_bd32_3}, + {"mem_dma_bd32_4", aie2ps::mem_dma_bd32_4}, + {"mem_dma_bd32_5", aie2ps::mem_dma_bd32_5}, + {"mem_dma_bd32_6", aie2ps::mem_dma_bd32_6}, + {"mem_dma_bd32_7", aie2ps::mem_dma_bd32_7}, + {"mem_dma_bd33_0", aie2ps::mem_dma_bd33_0}, + {"mem_dma_bd33_1", aie2ps::mem_dma_bd33_1}, + {"mem_dma_bd33_2", aie2ps::mem_dma_bd33_2}, + {"mem_dma_bd33_3", aie2ps::mem_dma_bd33_3}, + {"mem_dma_bd33_4", aie2ps::mem_dma_bd33_4}, + {"mem_dma_bd33_5", aie2ps::mem_dma_bd33_5}, + {"mem_dma_bd33_6", aie2ps::mem_dma_bd33_6}, + {"mem_dma_bd33_7", aie2ps::mem_dma_bd33_7}, + {"mem_dma_bd34_0", aie2ps::mem_dma_bd34_0}, + {"mem_dma_bd34_1", aie2ps::mem_dma_bd34_1}, + {"mem_dma_bd34_2", aie2ps::mem_dma_bd34_2}, + {"mem_dma_bd34_3", aie2ps::mem_dma_bd34_3}, + {"mem_dma_bd34_4", aie2ps::mem_dma_bd34_4}, + {"mem_dma_bd34_5", aie2ps::mem_dma_bd34_5}, + {"mem_dma_bd34_6", aie2ps::mem_dma_bd34_6}, + {"mem_dma_bd34_7", aie2ps::mem_dma_bd34_7}, + {"mem_dma_bd35_0", aie2ps::mem_dma_bd35_0}, + {"mem_dma_bd35_1", aie2ps::mem_dma_bd35_1}, + {"mem_dma_bd35_2", aie2ps::mem_dma_bd35_2}, + {"mem_dma_bd35_3", aie2ps::mem_dma_bd35_3}, + {"mem_dma_bd35_4", aie2ps::mem_dma_bd35_4}, + {"mem_dma_bd35_5", aie2ps::mem_dma_bd35_5}, + {"mem_dma_bd35_6", aie2ps::mem_dma_bd35_6}, + {"mem_dma_bd35_7", aie2ps::mem_dma_bd35_7}, + {"mem_dma_bd36_0", aie2ps::mem_dma_bd36_0}, + {"mem_dma_bd36_1", aie2ps::mem_dma_bd36_1}, + {"mem_dma_bd36_2", aie2ps::mem_dma_bd36_2}, + {"mem_dma_bd36_3", aie2ps::mem_dma_bd36_3}, + {"mem_dma_bd36_4", aie2ps::mem_dma_bd36_4}, + {"mem_dma_bd36_5", aie2ps::mem_dma_bd36_5}, + {"mem_dma_bd36_6", aie2ps::mem_dma_bd36_6}, + {"mem_dma_bd36_7", aie2ps::mem_dma_bd36_7}, + {"mem_dma_bd37_0", aie2ps::mem_dma_bd37_0}, + {"mem_dma_bd37_1", aie2ps::mem_dma_bd37_1}, + {"mem_dma_bd37_2", aie2ps::mem_dma_bd37_2}, + {"mem_dma_bd37_3", aie2ps::mem_dma_bd37_3}, + {"mem_dma_bd37_4", aie2ps::mem_dma_bd37_4}, + {"mem_dma_bd37_5", aie2ps::mem_dma_bd37_5}, + {"mem_dma_bd37_6", aie2ps::mem_dma_bd37_6}, + {"mem_dma_bd37_7", aie2ps::mem_dma_bd37_7}, + {"mem_dma_bd38_0", aie2ps::mem_dma_bd38_0}, + {"mem_dma_bd38_1", aie2ps::mem_dma_bd38_1}, + {"mem_dma_bd38_2", aie2ps::mem_dma_bd38_2}, + {"mem_dma_bd38_3", aie2ps::mem_dma_bd38_3}, + {"mem_dma_bd38_4", aie2ps::mem_dma_bd38_4}, + {"mem_dma_bd38_5", aie2ps::mem_dma_bd38_5}, + {"mem_dma_bd38_6", aie2ps::mem_dma_bd38_6}, + {"mem_dma_bd38_7", aie2ps::mem_dma_bd38_7}, + {"mem_dma_bd39_0", aie2ps::mem_dma_bd39_0}, + {"mem_dma_bd39_1", aie2ps::mem_dma_bd39_1}, + {"mem_dma_bd39_2", aie2ps::mem_dma_bd39_2}, + {"mem_dma_bd39_3", aie2ps::mem_dma_bd39_3}, + {"mem_dma_bd39_4", aie2ps::mem_dma_bd39_4}, + {"mem_dma_bd39_5", aie2ps::mem_dma_bd39_5}, + {"mem_dma_bd39_6", aie2ps::mem_dma_bd39_6}, + {"mem_dma_bd39_7", aie2ps::mem_dma_bd39_7}, + {"mem_dma_bd40_0", aie2ps::mem_dma_bd40_0}, + {"mem_dma_bd40_1", aie2ps::mem_dma_bd40_1}, + {"mem_dma_bd40_2", aie2ps::mem_dma_bd40_2}, + {"mem_dma_bd40_3", aie2ps::mem_dma_bd40_3}, + {"mem_dma_bd40_4", aie2ps::mem_dma_bd40_4}, + {"mem_dma_bd40_5", aie2ps::mem_dma_bd40_5}, + {"mem_dma_bd40_6", aie2ps::mem_dma_bd40_6}, + {"mem_dma_bd40_7", aie2ps::mem_dma_bd40_7}, + {"mem_dma_bd41_0", aie2ps::mem_dma_bd41_0}, + {"mem_dma_bd41_1", aie2ps::mem_dma_bd41_1}, + {"mem_dma_bd41_2", aie2ps::mem_dma_bd41_2}, + {"mem_dma_bd41_3", aie2ps::mem_dma_bd41_3}, + {"mem_dma_bd41_4", aie2ps::mem_dma_bd41_4}, + {"mem_dma_bd41_5", aie2ps::mem_dma_bd41_5}, + {"mem_dma_bd41_6", aie2ps::mem_dma_bd41_6}, + {"mem_dma_bd41_7", aie2ps::mem_dma_bd41_7}, + {"mem_dma_bd42_0", aie2ps::mem_dma_bd42_0}, + {"mem_dma_bd42_1", aie2ps::mem_dma_bd42_1}, + {"mem_dma_bd42_2", aie2ps::mem_dma_bd42_2}, + {"mem_dma_bd42_3", aie2ps::mem_dma_bd42_3}, + {"mem_dma_bd42_4", aie2ps::mem_dma_bd42_4}, + {"mem_dma_bd42_5", aie2ps::mem_dma_bd42_5}, + {"mem_dma_bd42_6", aie2ps::mem_dma_bd42_6}, + {"mem_dma_bd42_7", aie2ps::mem_dma_bd42_7}, + {"mem_dma_bd43_0", aie2ps::mem_dma_bd43_0}, + {"mem_dma_bd43_1", aie2ps::mem_dma_bd43_1}, + {"mem_dma_bd43_2", aie2ps::mem_dma_bd43_2}, + {"mem_dma_bd43_3", aie2ps::mem_dma_bd43_3}, + {"mem_dma_bd43_4", aie2ps::mem_dma_bd43_4}, + {"mem_dma_bd43_5", aie2ps::mem_dma_bd43_5}, + {"mem_dma_bd43_6", aie2ps::mem_dma_bd43_6}, + {"mem_dma_bd43_7", aie2ps::mem_dma_bd43_7}, + {"mem_dma_bd44_0", aie2ps::mem_dma_bd44_0}, + {"mem_dma_bd44_1", aie2ps::mem_dma_bd44_1}, + {"mem_dma_bd44_2", aie2ps::mem_dma_bd44_2}, + {"mem_dma_bd44_3", aie2ps::mem_dma_bd44_3}, + {"mem_dma_bd44_4", aie2ps::mem_dma_bd44_4}, + {"mem_dma_bd44_5", aie2ps::mem_dma_bd44_5}, + {"mem_dma_bd44_6", aie2ps::mem_dma_bd44_6}, + {"mem_dma_bd44_7", aie2ps::mem_dma_bd44_7}, + {"mem_dma_bd45_0", aie2ps::mem_dma_bd45_0}, + {"mem_dma_bd45_1", aie2ps::mem_dma_bd45_1}, + {"mem_dma_bd45_2", aie2ps::mem_dma_bd45_2}, + {"mem_dma_bd45_3", aie2ps::mem_dma_bd45_3}, + {"mem_dma_bd45_4", aie2ps::mem_dma_bd45_4}, + {"mem_dma_bd45_5", aie2ps::mem_dma_bd45_5}, + {"mem_dma_bd45_6", aie2ps::mem_dma_bd45_6}, + {"mem_dma_bd45_7", aie2ps::mem_dma_bd45_7}, + {"mem_dma_bd46_0", aie2ps::mem_dma_bd46_0}, + {"mem_dma_bd46_1", aie2ps::mem_dma_bd46_1}, + {"mem_dma_bd46_2", aie2ps::mem_dma_bd46_2}, + {"mem_dma_bd46_3", aie2ps::mem_dma_bd46_3}, + {"mem_dma_bd46_4", aie2ps::mem_dma_bd46_4}, + {"mem_dma_bd46_5", aie2ps::mem_dma_bd46_5}, + {"mem_dma_bd46_6", aie2ps::mem_dma_bd46_6}, + {"mem_dma_bd46_7", aie2ps::mem_dma_bd46_7}, + {"mem_dma_bd47_0", aie2ps::mem_dma_bd47_0}, + {"mem_dma_bd47_1", aie2ps::mem_dma_bd47_1}, + {"mem_dma_bd47_2", aie2ps::mem_dma_bd47_2}, + {"mem_dma_bd47_3", aie2ps::mem_dma_bd47_3}, + {"mem_dma_bd47_4", aie2ps::mem_dma_bd47_4}, + {"mem_dma_bd47_5", aie2ps::mem_dma_bd47_5}, + {"mem_dma_bd47_6", aie2ps::mem_dma_bd47_6}, + {"mem_dma_bd47_7", aie2ps::mem_dma_bd47_7}, + {"mem_dma_s2mm_0_ctrl", aie2ps::mem_dma_s2mm_0_ctrl}, + {"mem_dma_s2mm_0_start_queue", aie2ps::mem_dma_s2mm_0_start_queue}, + {"mem_dma_s2mm_1_ctrl", aie2ps::mem_dma_s2mm_1_ctrl}, + {"mem_dma_s2mm_1_start_queue", aie2ps::mem_dma_s2mm_1_start_queue}, + {"mem_dma_s2mm_2_ctrl", aie2ps::mem_dma_s2mm_2_ctrl}, + {"mem_dma_s2mm_2_start_queue", aie2ps::mem_dma_s2mm_2_start_queue}, + {"mem_dma_s2mm_3_ctrl", aie2ps::mem_dma_s2mm_3_ctrl}, + {"mem_dma_s2mm_3_start_queue", aie2ps::mem_dma_s2mm_3_start_queue}, + {"mem_dma_s2mm_4_ctrl", aie2ps::mem_dma_s2mm_4_ctrl}, + {"mem_dma_s2mm_4_start_queue", aie2ps::mem_dma_s2mm_4_start_queue}, + {"mem_dma_s2mm_5_ctrl", aie2ps::mem_dma_s2mm_5_ctrl}, + {"mem_dma_s2mm_5_start_queue", aie2ps::mem_dma_s2mm_5_start_queue}, + {"mem_dma_mm2s_0_ctrl", aie2ps::mem_dma_mm2s_0_ctrl}, + {"mem_dma_mm2s_0_start_queue", aie2ps::mem_dma_mm2s_0_start_queue}, + {"mem_dma_mm2s_1_ctrl", aie2ps::mem_dma_mm2s_1_ctrl}, + {"mem_dma_mm2s_1_start_queue", aie2ps::mem_dma_mm2s_1_start_queue}, + {"mem_dma_mm2s_2_ctrl", aie2ps::mem_dma_mm2s_2_ctrl}, + {"mem_dma_mm2s_2_start_queue", aie2ps::mem_dma_mm2s_2_start_queue}, + {"mem_dma_mm2s_3_ctrl", aie2ps::mem_dma_mm2s_3_ctrl}, + {"mem_dma_mm2s_3_start_queue", aie2ps::mem_dma_mm2s_3_start_queue}, + {"mem_dma_mm2s_4_ctrl", aie2ps::mem_dma_mm2s_4_ctrl}, + {"mem_dma_mm2s_4_start_queue", aie2ps::mem_dma_mm2s_4_start_queue}, + {"mem_dma_mm2s_5_ctrl", aie2ps::mem_dma_mm2s_5_ctrl}, + {"mem_dma_mm2s_5_start_queue", aie2ps::mem_dma_mm2s_5_start_queue}, + {"mem_dma_s2mm_status_0", aie2ps::mem_dma_s2mm_status_0}, + {"mem_dma_s2mm_status_1", aie2ps::mem_dma_s2mm_status_1}, + {"mem_dma_s2mm_status_2", aie2ps::mem_dma_s2mm_status_2}, + {"mem_dma_s2mm_status_3", aie2ps::mem_dma_s2mm_status_3}, + {"mem_dma_s2mm_status_4", aie2ps::mem_dma_s2mm_status_4}, + {"mem_dma_s2mm_status_5", aie2ps::mem_dma_s2mm_status_5}, + {"mem_dma_mm2s_status_0", aie2ps::mem_dma_mm2s_status_0}, + {"mem_dma_mm2s_status_1", aie2ps::mem_dma_mm2s_status_1}, + {"mem_dma_mm2s_status_2", aie2ps::mem_dma_mm2s_status_2}, + {"mem_dma_mm2s_status_3", aie2ps::mem_dma_mm2s_status_3}, + {"mem_dma_mm2s_status_4", aie2ps::mem_dma_mm2s_status_4}, + {"mem_dma_mm2s_status_5", aie2ps::mem_dma_mm2s_status_5}, + {"mem_dma_event_channel_selection", aie2ps::mem_dma_event_channel_selection}, + {"mem_dma_s2mm_current_write_count_0", aie2ps::mem_dma_s2mm_current_write_count_0}, + {"mem_dma_s2mm_current_write_count_1", aie2ps::mem_dma_s2mm_current_write_count_1}, + {"mem_dma_s2mm_current_write_count_2", aie2ps::mem_dma_s2mm_current_write_count_2}, + {"mem_dma_s2mm_current_write_count_3", aie2ps::mem_dma_s2mm_current_write_count_3}, + {"mem_dma_s2mm_current_write_count_4", aie2ps::mem_dma_s2mm_current_write_count_4}, + {"mem_dma_s2mm_current_write_count_5", aie2ps::mem_dma_s2mm_current_write_count_5}, + {"mem_dma_s2mm_fot_count_fifo_pop_0", aie2ps::mem_dma_s2mm_fot_count_fifo_pop_0}, + {"mem_dma_s2mm_fot_count_fifo_pop_1", aie2ps::mem_dma_s2mm_fot_count_fifo_pop_1}, + {"mem_dma_s2mm_fot_count_fifo_pop_2", aie2ps::mem_dma_s2mm_fot_count_fifo_pop_2}, + {"mem_dma_s2mm_fot_count_fifo_pop_3", aie2ps::mem_dma_s2mm_fot_count_fifo_pop_3}, + {"mem_dma_s2mm_fot_count_fifo_pop_4", aie2ps::mem_dma_s2mm_fot_count_fifo_pop_4}, + {"mem_dma_s2mm_fot_count_fifo_pop_5", aie2ps::mem_dma_s2mm_fot_count_fifo_pop_5}, + {"mem_dma_mm2s_0_constant_pad_value", aie2ps::mem_dma_mm2s_0_constant_pad_value}, + {"mem_dma_mm2s_1_constant_pad_value", aie2ps::mem_dma_mm2s_1_constant_pad_value}, + {"mem_dma_mm2s_2_constant_pad_value", aie2ps::mem_dma_mm2s_2_constant_pad_value}, + {"mem_dma_mm2s_3_constant_pad_value", aie2ps::mem_dma_mm2s_3_constant_pad_value}, + {"mem_dma_mm2s_4_constant_pad_value", aie2ps::mem_dma_mm2s_4_constant_pad_value}, + {"mem_dma_mm2s_5_constant_pad_value", aie2ps::mem_dma_mm2s_5_constant_pad_value}, + {"mem_stream_switch_master_config_dma0", aie2ps::mem_stream_switch_master_config_dma0}, + {"mem_stream_switch_master_config_dma1", aie2ps::mem_stream_switch_master_config_dma1}, + {"mem_stream_switch_master_config_dma2", aie2ps::mem_stream_switch_master_config_dma2}, + {"mem_stream_switch_master_config_dma3", aie2ps::mem_stream_switch_master_config_dma3}, + {"mem_stream_switch_master_config_dma4", aie2ps::mem_stream_switch_master_config_dma4}, + {"mem_stream_switch_master_config_dma5", aie2ps::mem_stream_switch_master_config_dma5}, + {"mem_stream_switch_master_config_tile_ctrl", aie2ps::mem_stream_switch_master_config_tile_ctrl}, + {"mem_stream_switch_master_config_south0", aie2ps::mem_stream_switch_master_config_south0}, + {"mem_stream_switch_master_config_south1", aie2ps::mem_stream_switch_master_config_south1}, + {"mem_stream_switch_master_config_south2", aie2ps::mem_stream_switch_master_config_south2}, + {"mem_stream_switch_master_config_south3", aie2ps::mem_stream_switch_master_config_south3}, + {"mem_stream_switch_master_config_north0", aie2ps::mem_stream_switch_master_config_north0}, + {"mem_stream_switch_master_config_north1", aie2ps::mem_stream_switch_master_config_north1}, + {"mem_stream_switch_master_config_north2", aie2ps::mem_stream_switch_master_config_north2}, + {"mem_stream_switch_master_config_north3", aie2ps::mem_stream_switch_master_config_north3}, + {"mem_stream_switch_master_config_north4", aie2ps::mem_stream_switch_master_config_north4}, + {"mem_stream_switch_master_config_north5", aie2ps::mem_stream_switch_master_config_north5}, + {"mem_stream_switch_slave_config_dma_0", aie2ps::mem_stream_switch_slave_config_dma_0}, + {"mem_stream_switch_slave_config_dma_1", aie2ps::mem_stream_switch_slave_config_dma_1}, + {"mem_stream_switch_slave_config_dma_2", aie2ps::mem_stream_switch_slave_config_dma_2}, + {"mem_stream_switch_slave_config_dma_3", aie2ps::mem_stream_switch_slave_config_dma_3}, + {"mem_stream_switch_slave_config_dma_4", aie2ps::mem_stream_switch_slave_config_dma_4}, + {"mem_stream_switch_slave_config_dma_5", aie2ps::mem_stream_switch_slave_config_dma_5}, + {"mem_stream_switch_slave_config_tile_ctrl", aie2ps::mem_stream_switch_slave_config_tile_ctrl}, + {"mem_stream_switch_slave_config_south_0", aie2ps::mem_stream_switch_slave_config_south_0}, + {"mem_stream_switch_slave_config_south_1", aie2ps::mem_stream_switch_slave_config_south_1}, + {"mem_stream_switch_slave_config_south_2", aie2ps::mem_stream_switch_slave_config_south_2}, + {"mem_stream_switch_slave_config_south_3", aie2ps::mem_stream_switch_slave_config_south_3}, + {"mem_stream_switch_slave_config_south_4", aie2ps::mem_stream_switch_slave_config_south_4}, + {"mem_stream_switch_slave_config_south_5", aie2ps::mem_stream_switch_slave_config_south_5}, + {"mem_stream_switch_slave_config_north_0", aie2ps::mem_stream_switch_slave_config_north_0}, + {"mem_stream_switch_slave_config_north_1", aie2ps::mem_stream_switch_slave_config_north_1}, + {"mem_stream_switch_slave_config_north_2", aie2ps::mem_stream_switch_slave_config_north_2}, + {"mem_stream_switch_slave_config_north_3", aie2ps::mem_stream_switch_slave_config_north_3}, + {"mem_stream_switch_slave_config_trace", aie2ps::mem_stream_switch_slave_config_trace}, + {"mem_stream_switch_slave_dma_0_slot0", aie2ps::mem_stream_switch_slave_dma_0_slot0}, + {"mem_stream_switch_slave_dma_0_slot1", aie2ps::mem_stream_switch_slave_dma_0_slot1}, + {"mem_stream_switch_slave_dma_0_slot2", aie2ps::mem_stream_switch_slave_dma_0_slot2}, + {"mem_stream_switch_slave_dma_0_slot3", aie2ps::mem_stream_switch_slave_dma_0_slot3}, + {"mem_stream_switch_slave_dma_1_slot0", aie2ps::mem_stream_switch_slave_dma_1_slot0}, + {"mem_stream_switch_slave_dma_1_slot1", aie2ps::mem_stream_switch_slave_dma_1_slot1}, + {"mem_stream_switch_slave_dma_1_slot2", aie2ps::mem_stream_switch_slave_dma_1_slot2}, + {"mem_stream_switch_slave_dma_1_slot3", aie2ps::mem_stream_switch_slave_dma_1_slot3}, + {"mem_stream_switch_slave_dma_2_slot0", aie2ps::mem_stream_switch_slave_dma_2_slot0}, + {"mem_stream_switch_slave_dma_2_slot1", aie2ps::mem_stream_switch_slave_dma_2_slot1}, + {"mem_stream_switch_slave_dma_2_slot2", aie2ps::mem_stream_switch_slave_dma_2_slot2}, + {"mem_stream_switch_slave_dma_2_slot3", aie2ps::mem_stream_switch_slave_dma_2_slot3}, + {"mem_stream_switch_slave_dma_3_slot0", aie2ps::mem_stream_switch_slave_dma_3_slot0}, + {"mem_stream_switch_slave_dma_3_slot1", aie2ps::mem_stream_switch_slave_dma_3_slot1}, + {"mem_stream_switch_slave_dma_3_slot2", aie2ps::mem_stream_switch_slave_dma_3_slot2}, + {"mem_stream_switch_slave_dma_3_slot3", aie2ps::mem_stream_switch_slave_dma_3_slot3}, + {"mem_stream_switch_slave_dma_4_slot0", aie2ps::mem_stream_switch_slave_dma_4_slot0}, + {"mem_stream_switch_slave_dma_4_slot1", aie2ps::mem_stream_switch_slave_dma_4_slot1}, + {"mem_stream_switch_slave_dma_4_slot2", aie2ps::mem_stream_switch_slave_dma_4_slot2}, + {"mem_stream_switch_slave_dma_4_slot3", aie2ps::mem_stream_switch_slave_dma_4_slot3}, + {"mem_stream_switch_slave_dma_5_slot0", aie2ps::mem_stream_switch_slave_dma_5_slot0}, + {"mem_stream_switch_slave_dma_5_slot1", aie2ps::mem_stream_switch_slave_dma_5_slot1}, + {"mem_stream_switch_slave_dma_5_slot2", aie2ps::mem_stream_switch_slave_dma_5_slot2}, + {"mem_stream_switch_slave_dma_5_slot3", aie2ps::mem_stream_switch_slave_dma_5_slot3}, + {"mem_stream_switch_slave_tile_ctrl_slot0", aie2ps::mem_stream_switch_slave_tile_ctrl_slot0}, + {"mem_stream_switch_slave_tile_ctrl_slot1", aie2ps::mem_stream_switch_slave_tile_ctrl_slot1}, + {"mem_stream_switch_slave_tile_ctrl_slot2", aie2ps::mem_stream_switch_slave_tile_ctrl_slot2}, + {"mem_stream_switch_slave_tile_ctrl_slot3", aie2ps::mem_stream_switch_slave_tile_ctrl_slot3}, + {"mem_stream_switch_slave_south_0_slot0", aie2ps::mem_stream_switch_slave_south_0_slot0}, + {"mem_stream_switch_slave_south_0_slot1", aie2ps::mem_stream_switch_slave_south_0_slot1}, + {"mem_stream_switch_slave_south_0_slot2", aie2ps::mem_stream_switch_slave_south_0_slot2}, + {"mem_stream_switch_slave_south_0_slot3", aie2ps::mem_stream_switch_slave_south_0_slot3}, + {"mem_stream_switch_slave_south_1_slot0", aie2ps::mem_stream_switch_slave_south_1_slot0}, + {"mem_stream_switch_slave_south_1_slot1", aie2ps::mem_stream_switch_slave_south_1_slot1}, + {"mem_stream_switch_slave_south_1_slot2", aie2ps::mem_stream_switch_slave_south_1_slot2}, + {"mem_stream_switch_slave_south_1_slot3", aie2ps::mem_stream_switch_slave_south_1_slot3}, + {"mem_stream_switch_slave_south_2_slot0", aie2ps::mem_stream_switch_slave_south_2_slot0}, + {"mem_stream_switch_slave_south_2_slot1", aie2ps::mem_stream_switch_slave_south_2_slot1}, + {"mem_stream_switch_slave_south_2_slot2", aie2ps::mem_stream_switch_slave_south_2_slot2}, + {"mem_stream_switch_slave_south_2_slot3", aie2ps::mem_stream_switch_slave_south_2_slot3}, + {"mem_stream_switch_slave_south_3_slot0", aie2ps::mem_stream_switch_slave_south_3_slot0}, + {"mem_stream_switch_slave_south_3_slot1", aie2ps::mem_stream_switch_slave_south_3_slot1}, + {"mem_stream_switch_slave_south_3_slot2", aie2ps::mem_stream_switch_slave_south_3_slot2}, + {"mem_stream_switch_slave_south_3_slot3", aie2ps::mem_stream_switch_slave_south_3_slot3}, + {"mem_stream_switch_slave_south_4_slot0", aie2ps::mem_stream_switch_slave_south_4_slot0}, + {"mem_stream_switch_slave_south_4_slot1", aie2ps::mem_stream_switch_slave_south_4_slot1}, + {"mem_stream_switch_slave_south_4_slot2", aie2ps::mem_stream_switch_slave_south_4_slot2}, + {"mem_stream_switch_slave_south_4_slot3", aie2ps::mem_stream_switch_slave_south_4_slot3}, + {"mem_stream_switch_slave_south_5_slot0", aie2ps::mem_stream_switch_slave_south_5_slot0}, + {"mem_stream_switch_slave_south_5_slot1", aie2ps::mem_stream_switch_slave_south_5_slot1}, + {"mem_stream_switch_slave_south_5_slot2", aie2ps::mem_stream_switch_slave_south_5_slot2}, + {"mem_stream_switch_slave_south_5_slot3", aie2ps::mem_stream_switch_slave_south_5_slot3}, + {"mem_stream_switch_slave_north_0_slot0", aie2ps::mem_stream_switch_slave_north_0_slot0}, + {"mem_stream_switch_slave_north_0_slot1", aie2ps::mem_stream_switch_slave_north_0_slot1}, + {"mem_stream_switch_slave_north_0_slot2", aie2ps::mem_stream_switch_slave_north_0_slot2}, + {"mem_stream_switch_slave_north_0_slot3", aie2ps::mem_stream_switch_slave_north_0_slot3}, + {"mem_stream_switch_slave_north_1_slot0", aie2ps::mem_stream_switch_slave_north_1_slot0}, + {"mem_stream_switch_slave_north_1_slot1", aie2ps::mem_stream_switch_slave_north_1_slot1}, + {"mem_stream_switch_slave_north_1_slot2", aie2ps::mem_stream_switch_slave_north_1_slot2}, + {"mem_stream_switch_slave_north_1_slot3", aie2ps::mem_stream_switch_slave_north_1_slot3}, + {"mem_stream_switch_slave_north_2_slot0", aie2ps::mem_stream_switch_slave_north_2_slot0}, + {"mem_stream_switch_slave_north_2_slot1", aie2ps::mem_stream_switch_slave_north_2_slot1}, + {"mem_stream_switch_slave_north_2_slot2", aie2ps::mem_stream_switch_slave_north_2_slot2}, + {"mem_stream_switch_slave_north_2_slot3", aie2ps::mem_stream_switch_slave_north_2_slot3}, + {"mem_stream_switch_slave_north_3_slot0", aie2ps::mem_stream_switch_slave_north_3_slot0}, + {"mem_stream_switch_slave_north_3_slot1", aie2ps::mem_stream_switch_slave_north_3_slot1}, + {"mem_stream_switch_slave_north_3_slot2", aie2ps::mem_stream_switch_slave_north_3_slot2}, + {"mem_stream_switch_slave_north_3_slot3", aie2ps::mem_stream_switch_slave_north_3_slot3}, + {"mem_stream_switch_slave_trace_slot0", aie2ps::mem_stream_switch_slave_trace_slot0}, + {"mem_stream_switch_slave_trace_slot1", aie2ps::mem_stream_switch_slave_trace_slot1}, + {"mem_stream_switch_slave_trace_slot2", aie2ps::mem_stream_switch_slave_trace_slot2}, + {"mem_stream_switch_slave_trace_slot3", aie2ps::mem_stream_switch_slave_trace_slot3}, + {"mem_stream_switch_deterministic_merge_arb0_slave0_1", aie2ps::mem_stream_switch_deterministic_merge_arb0_slave0_1}, + {"mem_stream_switch_deterministic_merge_arb0_slave2_3", aie2ps::mem_stream_switch_deterministic_merge_arb0_slave2_3}, + {"mem_stream_switch_deterministic_merge_arb0_ctrl", aie2ps::mem_stream_switch_deterministic_merge_arb0_ctrl}, + {"mem_stream_switch_deterministic_merge_arb1_slave0_1", aie2ps::mem_stream_switch_deterministic_merge_arb1_slave0_1}, + {"mem_stream_switch_deterministic_merge_arb1_slave2_3", aie2ps::mem_stream_switch_deterministic_merge_arb1_slave2_3}, + {"mem_stream_switch_deterministic_merge_arb1_ctrl", aie2ps::mem_stream_switch_deterministic_merge_arb1_ctrl}, + {"mem_stream_switch_event_port_selection_0", aie2ps::mem_stream_switch_event_port_selection_0}, + {"mem_stream_switch_event_port_selection_1", aie2ps::mem_stream_switch_event_port_selection_1}, + {"mem_stream_switch_parity_status", aie2ps::mem_stream_switch_parity_status}, + {"mem_stream_switch_parity_injection", aie2ps::mem_stream_switch_parity_injection}, + {"mem_tile_control_packet_handler_status", aie2ps::mem_tile_control_packet_handler_status}, + {"mem_stream_switch_adaptive_clock_gate_status", aie2ps::mem_stream_switch_adaptive_clock_gate_status}, + {"mem_stream_switch_adaptive_clock_gate_abort_period", aie2ps::mem_stream_switch_adaptive_clock_gate_abort_period}, + {"mem_lock0_value", aie2ps::mem_lock0_value}, + {"mem_lock1_value", aie2ps::mem_lock1_value}, + {"mem_lock2_value", aie2ps::mem_lock2_value}, + {"mem_lock3_value", aie2ps::mem_lock3_value}, + {"mem_lock4_value", aie2ps::mem_lock4_value}, + {"mem_lock5_value", aie2ps::mem_lock5_value}, + {"mem_lock6_value", aie2ps::mem_lock6_value}, + {"mem_lock7_value", aie2ps::mem_lock7_value}, + {"mem_lock8_value", aie2ps::mem_lock8_value}, + {"mem_lock9_value", aie2ps::mem_lock9_value}, + {"mem_lock10_value", aie2ps::mem_lock10_value}, + {"mem_lock11_value", aie2ps::mem_lock11_value}, + {"mem_lock12_value", aie2ps::mem_lock12_value}, + {"mem_lock13_value", aie2ps::mem_lock13_value}, + {"mem_lock14_value", aie2ps::mem_lock14_value}, + {"mem_lock15_value", aie2ps::mem_lock15_value}, + {"mem_lock16_value", aie2ps::mem_lock16_value}, + {"mem_lock17_value", aie2ps::mem_lock17_value}, + {"mem_lock18_value", aie2ps::mem_lock18_value}, + {"mem_lock19_value", aie2ps::mem_lock19_value}, + {"mem_lock20_value", aie2ps::mem_lock20_value}, + {"mem_lock21_value", aie2ps::mem_lock21_value}, + {"mem_lock22_value", aie2ps::mem_lock22_value}, + {"mem_lock23_value", aie2ps::mem_lock23_value}, + {"mem_lock24_value", aie2ps::mem_lock24_value}, + {"mem_lock25_value", aie2ps::mem_lock25_value}, + {"mem_lock26_value", aie2ps::mem_lock26_value}, + {"mem_lock27_value", aie2ps::mem_lock27_value}, + {"mem_lock28_value", aie2ps::mem_lock28_value}, + {"mem_lock29_value", aie2ps::mem_lock29_value}, + {"mem_lock30_value", aie2ps::mem_lock30_value}, + {"mem_lock31_value", aie2ps::mem_lock31_value}, + {"mem_lock32_value", aie2ps::mem_lock32_value}, + {"mem_lock33_value", aie2ps::mem_lock33_value}, + {"mem_lock34_value", aie2ps::mem_lock34_value}, + {"mem_lock35_value", aie2ps::mem_lock35_value}, + {"mem_lock36_value", aie2ps::mem_lock36_value}, + {"mem_lock37_value", aie2ps::mem_lock37_value}, + {"mem_lock38_value", aie2ps::mem_lock38_value}, + {"mem_lock39_value", aie2ps::mem_lock39_value}, + {"mem_lock40_value", aie2ps::mem_lock40_value}, + {"mem_lock41_value", aie2ps::mem_lock41_value}, + {"mem_lock42_value", aie2ps::mem_lock42_value}, + {"mem_lock43_value", aie2ps::mem_lock43_value}, + {"mem_lock44_value", aie2ps::mem_lock44_value}, + {"mem_lock45_value", aie2ps::mem_lock45_value}, + {"mem_lock46_value", aie2ps::mem_lock46_value}, + {"mem_lock47_value", aie2ps::mem_lock47_value}, + {"mem_lock48_value", aie2ps::mem_lock48_value}, + {"mem_lock49_value", aie2ps::mem_lock49_value}, + {"mem_lock50_value", aie2ps::mem_lock50_value}, + {"mem_lock51_value", aie2ps::mem_lock51_value}, + {"mem_lock52_value", aie2ps::mem_lock52_value}, + {"mem_lock53_value", aie2ps::mem_lock53_value}, + {"mem_lock54_value", aie2ps::mem_lock54_value}, + {"mem_lock55_value", aie2ps::mem_lock55_value}, + {"mem_lock56_value", aie2ps::mem_lock56_value}, + {"mem_lock57_value", aie2ps::mem_lock57_value}, + {"mem_lock58_value", aie2ps::mem_lock58_value}, + {"mem_lock59_value", aie2ps::mem_lock59_value}, + {"mem_lock60_value", aie2ps::mem_lock60_value}, + {"mem_lock61_value", aie2ps::mem_lock61_value}, + {"mem_lock62_value", aie2ps::mem_lock62_value}, + {"mem_lock63_value", aie2ps::mem_lock63_value}, + {"mem_locks_event_selection_0", aie2ps::mem_locks_event_selection_0}, + {"mem_locks_event_selection_1", aie2ps::mem_locks_event_selection_1}, + {"mem_locks_event_selection_2", aie2ps::mem_locks_event_selection_2}, + {"mem_locks_event_selection_3", aie2ps::mem_locks_event_selection_3}, + {"mem_locks_event_selection_4", aie2ps::mem_locks_event_selection_4}, + {"mem_locks_event_selection_5", aie2ps::mem_locks_event_selection_5}, + {"mem_locks_event_selection_6", aie2ps::mem_locks_event_selection_6}, + {"mem_locks_event_selection_7", aie2ps::mem_locks_event_selection_7}, + {"mem_locks_overflow_0", aie2ps::mem_locks_overflow_0}, + {"mem_locks_overflow_1", aie2ps::mem_locks_overflow_1}, + {"mem_locks_underflow_0", aie2ps::mem_locks_underflow_0}, + {"mem_locks_underflow_1", aie2ps::mem_locks_underflow_1}, + {"mem_lock_request", aie2ps::mem_lock_request}, + {"mem_module_clock_control", aie2ps::mem_module_clock_control}, + {"mem_tile_control", aie2ps::mem_tile_control}, + {"shim_lock_step_size", aie2ps::shim_lock_step_size}, + {"shim_dma_bd_step_size", aie2ps::shim_dma_bd_step_size}, + {"shim_dma_s2mm_step_size", aie2ps::shim_dma_s2mm_step_size}, + {"shim_lock0_value", aie2ps::shim_lock0_value}, + {"shim_lock1_value", aie2ps::shim_lock1_value}, + {"shim_lock2_value", aie2ps::shim_lock2_value}, + {"shim_lock3_value", aie2ps::shim_lock3_value}, + {"shim_lock4_value", aie2ps::shim_lock4_value}, + {"shim_lock5_value", aie2ps::shim_lock5_value}, + {"shim_lock6_value", aie2ps::shim_lock6_value}, + {"shim_lock7_value", aie2ps::shim_lock7_value}, + {"shim_lock8_value", aie2ps::shim_lock8_value}, + {"shim_lock9_value", aie2ps::shim_lock9_value}, + {"shim_lock10_value", aie2ps::shim_lock10_value}, + {"shim_lock11_value", aie2ps::shim_lock11_value}, + {"shim_lock12_value", aie2ps::shim_lock12_value}, + {"shim_lock13_value", aie2ps::shim_lock13_value}, + {"shim_lock14_value", aie2ps::shim_lock14_value}, + {"shim_lock15_value", aie2ps::shim_lock15_value}, + {"shim_locks_event_selection_0", aie2ps::shim_locks_event_selection_0}, + {"shim_locks_event_selection_1", aie2ps::shim_locks_event_selection_1}, + {"shim_locks_event_selection_2", aie2ps::shim_locks_event_selection_2}, + {"shim_locks_event_selection_3", aie2ps::shim_locks_event_selection_3}, + {"shim_locks_event_selection_4", aie2ps::shim_locks_event_selection_4}, + {"shim_locks_event_selection_5", aie2ps::shim_locks_event_selection_5}, + {"shim_locks_overflow", aie2ps::shim_locks_overflow}, + {"shim_locks_underflow", aie2ps::shim_locks_underflow}, + {"shim_interrupt_controller_2nd_level_mask", aie2ps::shim_interrupt_controller_2nd_level_mask}, + {"shim_interrupt_controller_2nd_level_enable", aie2ps::shim_interrupt_controller_2nd_level_enable}, + {"shim_interrupt_controller_2nd_level_disable", aie2ps::shim_interrupt_controller_2nd_level_disable}, + {"shim_interrupt_controller_2nd_level_status", aie2ps::shim_interrupt_controller_2nd_level_status}, + {"shim_interrupt_controller_2nd_level_interrupt", aie2ps::shim_interrupt_controller_2nd_level_interrupt}, + {"shim_me_aximm_config", aie2ps::shim_me_aximm_config}, + {"shim_mux_config", aie2ps::shim_mux_config}, + {"shim_demux_config", aie2ps::shim_demux_config}, + {"shim_axi_mm_outstanding_transactions", aie2ps::shim_axi_mm_outstanding_transactions}, + {"shim_smid", aie2ps::shim_smid}, + {"shim_dma_bd0_0", aie2ps::shim_dma_bd0_0}, + {"shim_dma_bd0_1", aie2ps::shim_dma_bd0_1}, + {"shim_dma_bd0_2", aie2ps::shim_dma_bd0_2}, + {"shim_dma_bd0_3", aie2ps::shim_dma_bd0_3}, + {"shim_dma_bd0_4", aie2ps::shim_dma_bd0_4}, + {"shim_dma_bd0_5", aie2ps::shim_dma_bd0_5}, + {"shim_dma_bd0_6", aie2ps::shim_dma_bd0_6}, + {"shim_dma_bd0_7", aie2ps::shim_dma_bd0_7}, + {"shim_dma_bd0_8", aie2ps::shim_dma_bd0_8}, + {"shim_dma_bd1_0", aie2ps::shim_dma_bd1_0}, + {"shim_dma_bd1_1", aie2ps::shim_dma_bd1_1}, + {"shim_dma_bd1_2", aie2ps::shim_dma_bd1_2}, + {"shim_dma_bd1_3", aie2ps::shim_dma_bd1_3}, + {"shim_dma_bd1_4", aie2ps::shim_dma_bd1_4}, + {"shim_dma_bd1_5", aie2ps::shim_dma_bd1_5}, + {"shim_dma_bd1_6", aie2ps::shim_dma_bd1_6}, + {"shim_dma_bd1_7", aie2ps::shim_dma_bd1_7}, + {"shim_dma_bd1_8", aie2ps::shim_dma_bd1_8}, + {"shim_dma_bd2_0", aie2ps::shim_dma_bd2_0}, + {"shim_dma_bd2_1", aie2ps::shim_dma_bd2_1}, + {"shim_dma_bd2_2", aie2ps::shim_dma_bd2_2}, + {"shim_dma_bd2_3", aie2ps::shim_dma_bd2_3}, + {"shim_dma_bd2_4", aie2ps::shim_dma_bd2_4}, + {"shim_dma_bd2_5", aie2ps::shim_dma_bd2_5}, + {"shim_dma_bd2_6", aie2ps::shim_dma_bd2_6}, + {"shim_dma_bd2_7", aie2ps::shim_dma_bd2_7}, + {"shim_dma_bd2_8", aie2ps::shim_dma_bd2_8}, + {"shim_dma_bd3_0", aie2ps::shim_dma_bd3_0}, + {"shim_dma_bd3_1", aie2ps::shim_dma_bd3_1}, + {"shim_dma_bd3_2", aie2ps::shim_dma_bd3_2}, + {"shim_dma_bd3_3", aie2ps::shim_dma_bd3_3}, + {"shim_dma_bd3_4", aie2ps::shim_dma_bd3_4}, + {"shim_dma_bd3_5", aie2ps::shim_dma_bd3_5}, + {"shim_dma_bd3_6", aie2ps::shim_dma_bd3_6}, + {"shim_dma_bd3_7", aie2ps::shim_dma_bd3_7}, + {"shim_dma_bd3_8", aie2ps::shim_dma_bd3_8}, + {"shim_dma_bd4_0", aie2ps::shim_dma_bd4_0}, + {"shim_dma_bd4_1", aie2ps::shim_dma_bd4_1}, + {"shim_dma_bd4_2", aie2ps::shim_dma_bd4_2}, + {"shim_dma_bd4_3", aie2ps::shim_dma_bd4_3}, + {"shim_dma_bd4_4", aie2ps::shim_dma_bd4_4}, + {"shim_dma_bd4_5", aie2ps::shim_dma_bd4_5}, + {"shim_dma_bd4_6", aie2ps::shim_dma_bd4_6}, + {"shim_dma_bd4_7", aie2ps::shim_dma_bd4_7}, + {"shim_dma_bd4_8", aie2ps::shim_dma_bd4_8}, + {"shim_dma_bd5_0", aie2ps::shim_dma_bd5_0}, + {"shim_dma_bd5_1", aie2ps::shim_dma_bd5_1}, + {"shim_dma_bd5_2", aie2ps::shim_dma_bd5_2}, + {"shim_dma_bd5_3", aie2ps::shim_dma_bd5_3}, + {"shim_dma_bd5_4", aie2ps::shim_dma_bd5_4}, + {"shim_dma_bd5_5", aie2ps::shim_dma_bd5_5}, + {"shim_dma_bd5_6", aie2ps::shim_dma_bd5_6}, + {"shim_dma_bd5_7", aie2ps::shim_dma_bd5_7}, + {"shim_dma_bd5_8", aie2ps::shim_dma_bd5_8}, + {"shim_dma_bd6_0", aie2ps::shim_dma_bd6_0}, + {"shim_dma_bd6_1", aie2ps::shim_dma_bd6_1}, + {"shim_dma_bd6_2", aie2ps::shim_dma_bd6_2}, + {"shim_dma_bd6_3", aie2ps::shim_dma_bd6_3}, + {"shim_dma_bd6_4", aie2ps::shim_dma_bd6_4}, + {"shim_dma_bd6_5", aie2ps::shim_dma_bd6_5}, + {"shim_dma_bd6_6", aie2ps::shim_dma_bd6_6}, + {"shim_dma_bd6_7", aie2ps::shim_dma_bd6_7}, + {"shim_dma_bd6_8", aie2ps::shim_dma_bd6_8}, + {"shim_dma_bd7_0", aie2ps::shim_dma_bd7_0}, + {"shim_dma_bd7_1", aie2ps::shim_dma_bd7_1}, + {"shim_dma_bd7_2", aie2ps::shim_dma_bd7_2}, + {"shim_dma_bd7_3", aie2ps::shim_dma_bd7_3}, + {"shim_dma_bd7_4", aie2ps::shim_dma_bd7_4}, + {"shim_dma_bd7_5", aie2ps::shim_dma_bd7_5}, + {"shim_dma_bd7_6", aie2ps::shim_dma_bd7_6}, + {"shim_dma_bd7_7", aie2ps::shim_dma_bd7_7}, + {"shim_dma_bd7_8", aie2ps::shim_dma_bd7_8}, + {"shim_dma_bd8_0", aie2ps::shim_dma_bd8_0}, + {"shim_dma_bd8_1", aie2ps::shim_dma_bd8_1}, + {"shim_dma_bd8_2", aie2ps::shim_dma_bd8_2}, + {"shim_dma_bd8_3", aie2ps::shim_dma_bd8_3}, + {"shim_dma_bd8_4", aie2ps::shim_dma_bd8_4}, + {"shim_dma_bd8_5", aie2ps::shim_dma_bd8_5}, + {"shim_dma_bd8_6", aie2ps::shim_dma_bd8_6}, + {"shim_dma_bd8_7", aie2ps::shim_dma_bd8_7}, + {"shim_dma_bd8_8", aie2ps::shim_dma_bd8_8}, + {"shim_dma_bd9_0", aie2ps::shim_dma_bd9_0}, + {"shim_dma_bd9_1", aie2ps::shim_dma_bd9_1}, + {"shim_dma_bd9_2", aie2ps::shim_dma_bd9_2}, + {"shim_dma_bd9_3", aie2ps::shim_dma_bd9_3}, + {"shim_dma_bd9_4", aie2ps::shim_dma_bd9_4}, + {"shim_dma_bd9_5", aie2ps::shim_dma_bd9_5}, + {"shim_dma_bd9_6", aie2ps::shim_dma_bd9_6}, + {"shim_dma_bd9_7", aie2ps::shim_dma_bd9_7}, + {"shim_dma_bd9_8", aie2ps::shim_dma_bd9_8}, + {"shim_dma_bd10_0", aie2ps::shim_dma_bd10_0}, + {"shim_dma_bd10_1", aie2ps::shim_dma_bd10_1}, + {"shim_dma_bd10_2", aie2ps::shim_dma_bd10_2}, + {"shim_dma_bd10_3", aie2ps::shim_dma_bd10_3}, + {"shim_dma_bd10_4", aie2ps::shim_dma_bd10_4}, + {"shim_dma_bd10_5", aie2ps::shim_dma_bd10_5}, + {"shim_dma_bd10_6", aie2ps::shim_dma_bd10_6}, + {"shim_dma_bd10_7", aie2ps::shim_dma_bd10_7}, + {"shim_dma_bd10_8", aie2ps::shim_dma_bd10_8}, + {"shim_dma_bd11_0", aie2ps::shim_dma_bd11_0}, + {"shim_dma_bd11_1", aie2ps::shim_dma_bd11_1}, + {"shim_dma_bd11_2", aie2ps::shim_dma_bd11_2}, + {"shim_dma_bd11_3", aie2ps::shim_dma_bd11_3}, + {"shim_dma_bd11_4", aie2ps::shim_dma_bd11_4}, + {"shim_dma_bd11_5", aie2ps::shim_dma_bd11_5}, + {"shim_dma_bd11_6", aie2ps::shim_dma_bd11_6}, + {"shim_dma_bd11_7", aie2ps::shim_dma_bd11_7}, + {"shim_dma_bd11_8", aie2ps::shim_dma_bd11_8}, + {"shim_dma_bd12_0", aie2ps::shim_dma_bd12_0}, + {"shim_dma_bd12_1", aie2ps::shim_dma_bd12_1}, + {"shim_dma_bd12_2", aie2ps::shim_dma_bd12_2}, + {"shim_dma_bd12_3", aie2ps::shim_dma_bd12_3}, + {"shim_dma_bd12_4", aie2ps::shim_dma_bd12_4}, + {"shim_dma_bd12_5", aie2ps::shim_dma_bd12_5}, + {"shim_dma_bd12_6", aie2ps::shim_dma_bd12_6}, + {"shim_dma_bd12_7", aie2ps::shim_dma_bd12_7}, + {"shim_dma_bd12_8", aie2ps::shim_dma_bd12_8}, + {"shim_dma_bd13_0", aie2ps::shim_dma_bd13_0}, + {"shim_dma_bd13_1", aie2ps::shim_dma_bd13_1}, + {"shim_dma_bd13_2", aie2ps::shim_dma_bd13_2}, + {"shim_dma_bd13_3", aie2ps::shim_dma_bd13_3}, + {"shim_dma_bd13_4", aie2ps::shim_dma_bd13_4}, + {"shim_dma_bd13_5", aie2ps::shim_dma_bd13_5}, + {"shim_dma_bd13_6", aie2ps::shim_dma_bd13_6}, + {"shim_dma_bd13_7", aie2ps::shim_dma_bd13_7}, + {"shim_dma_bd13_8", aie2ps::shim_dma_bd13_8}, + {"shim_dma_bd14_0", aie2ps::shim_dma_bd14_0}, + {"shim_dma_bd14_1", aie2ps::shim_dma_bd14_1}, + {"shim_dma_bd14_2", aie2ps::shim_dma_bd14_2}, + {"shim_dma_bd14_3", aie2ps::shim_dma_bd14_3}, + {"shim_dma_bd14_4", aie2ps::shim_dma_bd14_4}, + {"shim_dma_bd14_5", aie2ps::shim_dma_bd14_5}, + {"shim_dma_bd14_6", aie2ps::shim_dma_bd14_6}, + {"shim_dma_bd14_7", aie2ps::shim_dma_bd14_7}, + {"shim_dma_bd14_8", aie2ps::shim_dma_bd14_8}, + {"shim_dma_bd15_0", aie2ps::shim_dma_bd15_0}, + {"shim_dma_bd15_1", aie2ps::shim_dma_bd15_1}, + {"shim_dma_bd15_2", aie2ps::shim_dma_bd15_2}, + {"shim_dma_bd15_3", aie2ps::shim_dma_bd15_3}, + {"shim_dma_bd15_4", aie2ps::shim_dma_bd15_4}, + {"shim_dma_bd15_5", aie2ps::shim_dma_bd15_5}, + {"shim_dma_bd15_6", aie2ps::shim_dma_bd15_6}, + {"shim_dma_bd15_7", aie2ps::shim_dma_bd15_7}, + {"shim_dma_bd15_8", aie2ps::shim_dma_bd15_8}, + {"shim_dma_s2mm_0_ctrl", aie2ps::shim_dma_s2mm_0_ctrl}, + {"shim_dma_s2mm_0_task_queue", aie2ps::shim_dma_s2mm_0_task_queue}, + {"shim_dma_s2mm_1_ctrl", aie2ps::shim_dma_s2mm_1_ctrl}, + {"shim_dma_s2mm_1_task_queue", aie2ps::shim_dma_s2mm_1_task_queue}, + {"shim_dma_mm2s_0_ctrl", aie2ps::shim_dma_mm2s_0_ctrl}, + {"shim_dma_mm2s_0_task_queue", aie2ps::shim_dma_mm2s_0_task_queue}, + {"shim_dma_mm2s_1_ctrl", aie2ps::shim_dma_mm2s_1_ctrl}, + {"shim_dma_mm2s_1_task_queue", aie2ps::shim_dma_mm2s_1_task_queue}, + {"shim_dma_s2mm_status_0", aie2ps::shim_dma_s2mm_status_0}, + {"shim_dma_s2mm_status_1", aie2ps::shim_dma_s2mm_status_1}, + {"shim_dma_mm2s_status_0", aie2ps::shim_dma_mm2s_status_0}, + {"shim_dma_mm2s_status_1", aie2ps::shim_dma_mm2s_status_1}, + {"shim_dma_s2mm_current_write_count_0", aie2ps::shim_dma_s2mm_current_write_count_0}, + {"shim_dma_s2mm_current_write_count_1", aie2ps::shim_dma_s2mm_current_write_count_1}, + {"shim_dma_s2mm_fot_count_fifo_pop_0", aie2ps::shim_dma_s2mm_fot_count_fifo_pop_0}, + {"shim_dma_s2mm_fot_count_fifo_pop_1", aie2ps::shim_dma_s2mm_fot_count_fifo_pop_1}, + {"shim_dma_mm2s_0_response_fifo_parity_error_injection", aie2ps::shim_dma_mm2s_0_response_fifo_parity_error_injection}, + {"shim_dma_mm2s_1_response_fifo_parity_error_injection", aie2ps::shim_dma_mm2s_1_response_fifo_parity_error_injection}, + {"shim_dma_pause", aie2ps::shim_dma_pause}, + {"shim_lock_request", aie2ps::shim_lock_request}, + {"shim_performance_control0", aie2ps::shim_performance_control0}, + {"shim_performance_control1", aie2ps::shim_performance_control1}, + {"shim_performance_control2", aie2ps::shim_performance_control2}, + {"shim_performance_control3", aie2ps::shim_performance_control3}, + {"shim_performance_control4", aie2ps::shim_performance_control4}, + {"shim_performance_control5", aie2ps::shim_performance_control5}, + {"shim_performance_counter0", aie2ps::shim_performance_counter0}, + {"shim_performance_counter1", aie2ps::shim_performance_counter1}, + {"shim_performance_counter2", aie2ps::shim_performance_counter2}, + {"shim_performance_counter3", aie2ps::shim_performance_counter3}, + {"shim_performance_counter4", aie2ps::shim_performance_counter4}, + {"shim_performance_counter5", aie2ps::shim_performance_counter5}, + {"shim_performance_counter0_event_value", aie2ps::shim_performance_counter0_event_value}, + {"shim_performance_counter1_event_value", aie2ps::shim_performance_counter1_event_value}, + {"shim_event_generate", aie2ps::shim_event_generate}, + {"shim_event_broadcast_a_0", aie2ps::shim_event_broadcast_a_0}, + {"shim_event_broadcast_a_1", aie2ps::shim_event_broadcast_a_1}, + {"shim_event_broadcast_a_2", aie2ps::shim_event_broadcast_a_2}, + {"shim_event_broadcast_a_3", aie2ps::shim_event_broadcast_a_3}, + {"shim_event_broadcast_a_4", aie2ps::shim_event_broadcast_a_4}, + {"shim_event_broadcast_a_5", aie2ps::shim_event_broadcast_a_5}, + {"shim_event_broadcast_a_6", aie2ps::shim_event_broadcast_a_6}, + {"shim_event_broadcast_a_7", aie2ps::shim_event_broadcast_a_7}, + {"shim_event_broadcast_a_8", aie2ps::shim_event_broadcast_a_8}, + {"shim_event_broadcast_a_9", aie2ps::shim_event_broadcast_a_9}, + {"shim_event_broadcast_a_10", aie2ps::shim_event_broadcast_a_10}, + {"shim_event_broadcast_a_11", aie2ps::shim_event_broadcast_a_11}, + {"shim_event_broadcast_a_12", aie2ps::shim_event_broadcast_a_12}, + {"shim_event_broadcast_a_13", aie2ps::shim_event_broadcast_a_13}, + {"shim_event_broadcast_a_14", aie2ps::shim_event_broadcast_a_14}, + {"shim_event_broadcast_a_15", aie2ps::shim_event_broadcast_a_15}, + {"shim_event_broadcast_a_block_south_set", aie2ps::shim_event_broadcast_a_block_south_set}, + {"shim_event_broadcast_a_block_south_clr", aie2ps::shim_event_broadcast_a_block_south_clr}, + {"shim_event_broadcast_a_block_south_value", aie2ps::shim_event_broadcast_a_block_south_value}, + {"shim_event_broadcast_a_block_west_set", aie2ps::shim_event_broadcast_a_block_west_set}, + {"shim_event_broadcast_a_block_west_clr", aie2ps::shim_event_broadcast_a_block_west_clr}, + {"shim_event_broadcast_a_block_west_value", aie2ps::shim_event_broadcast_a_block_west_value}, + {"shim_event_broadcast_a_block_north_set", aie2ps::shim_event_broadcast_a_block_north_set}, + {"shim_event_broadcast_a_block_north_clr", aie2ps::shim_event_broadcast_a_block_north_clr}, + {"shim_event_broadcast_a_block_north_value", aie2ps::shim_event_broadcast_a_block_north_value}, + {"shim_event_broadcast_a_block_east_set", aie2ps::shim_event_broadcast_a_block_east_set}, + {"shim_event_broadcast_a_block_east_clr", aie2ps::shim_event_broadcast_a_block_east_clr}, + {"shim_event_broadcast_a_block_east_value", aie2ps::shim_event_broadcast_a_block_east_value}, + {"shim_trace_control0", aie2ps::shim_trace_control0}, + {"shim_trace_control1", aie2ps::shim_trace_control1}, + {"shim_trace_status", aie2ps::shim_trace_status}, + {"shim_trace_event0", aie2ps::shim_trace_event0}, + {"shim_trace_event1", aie2ps::shim_trace_event1}, + {"shim_timer_trig_event_low_value", aie2ps::shim_timer_trig_event_low_value}, + {"shim_timer_trig_event_high_value", aie2ps::shim_timer_trig_event_high_value}, + {"shim_timer_low", aie2ps::shim_timer_low}, + {"shim_timer_high", aie2ps::shim_timer_high}, + {"shim_event_status0", aie2ps::shim_event_status0}, + {"shim_event_status1", aie2ps::shim_event_status1}, + {"shim_event_status2", aie2ps::shim_event_status2}, + {"shim_event_status3", aie2ps::shim_event_status3}, + {"shim_event_group_dma_enable", aie2ps::shim_event_group_dma_enable}, + {"shim_stream_switch_event_port_selection_0", aie2ps::shim_stream_switch_event_port_selection_0}, + {"shim_stream_switch_event_port_selection_1", aie2ps::shim_stream_switch_event_port_selection_1}, + {"npi_me_isr", aie2ps::npi_me_isr}, + {"npi_me_itr", aie2ps::npi_me_itr}, + {"npi_me_imr0", aie2ps::npi_me_imr0}, + {"npi_me_ier0", aie2ps::npi_me_ier0}, + {"npi_me_idr0", aie2ps::npi_me_idr0}, + {"npi_me_imr1", aie2ps::npi_me_imr1}, + {"npi_me_ier1", aie2ps::npi_me_ier1}, + {"npi_me_idr1", aie2ps::npi_me_idr1}, + {"npi_me_imr2", aie2ps::npi_me_imr2}, + {"npi_me_ier2", aie2ps::npi_me_ier2}, + {"npi_me_idr2", aie2ps::npi_me_idr2}, + {"npi_me_imr3", aie2ps::npi_me_imr3}, + {"npi_me_ier3", aie2ps::npi_me_ier3}, + {"npi_me_idr3", aie2ps::npi_me_idr3}, + {"npi_me_ior", aie2ps::npi_me_ior}, + {"npi_me_pll_status", aie2ps::npi_me_pll_status}, + {"npi_me_secure_reg", aie2ps::npi_me_secure_reg}, + {"uc_base_address", aie2ps::uc_base_address}, + {"uc_mdm_dbg_ctrl_status", aie2ps::uc_mdm_dbg_ctrl_status}, + {"uc_mdm_dbg_data", aie2ps::uc_mdm_dbg_data}, + {"uc_mdm_dbg_lock", aie2ps::uc_mdm_dbg_lock}, + {"uc_mdm_pcctrlr", aie2ps::uc_mdm_pcctrlr}, + {"uc_mdm_pccmdr", aie2ps::uc_mdm_pccmdr}, + {"uc_mdm_pcsr", aie2ps::uc_mdm_pcsr}, + {"uc_mdm_pcdrr", aie2ps::uc_mdm_pcdrr}, + {"uc_mdm_pcwr", aie2ps::uc_mdm_pcwr}, + {"uc_core_status", aie2ps::uc_core_status}, + {"uc_core_control", aie2ps::uc_core_control}, + {"uc_core_interrupt_status", aie2ps::uc_core_interrupt_status}, + {"uc_module_aximm_offset", aie2ps::uc_module_aximm_offset}, + {"uc_module_axi_mm_outstanding_transactions", aie2ps::uc_module_axi_mm_outstanding_transactions}, + {"uc_memory_zeroization", aie2ps::uc_memory_zeroization}, + {"uc_memory_privileged", aie2ps::uc_memory_privileged}, + {"uc_memory_dm_ecc_scrubbing_period", aie2ps::uc_memory_dm_ecc_scrubbing_period}, + {"uc_memory_dm_ecc_error_generation", aie2ps::uc_memory_dm_ecc_error_generation}, + {"uc_dma_dm2mm_status", aie2ps::uc_dma_dm2mm_status}, + {"uc_dma_dm2mm_control", aie2ps::uc_dma_dm2mm_control}, + {"uc_dma_dm2mm_axi_control", aie2ps::uc_dma_dm2mm_axi_control}, + {"uc_dma_mm2dm_status", aie2ps::uc_dma_mm2dm_status}, + {"uc_dma_mm2dm_control", aie2ps::uc_dma_mm2dm_control}, + {"uc_dma_mm2dm_axi_control", aie2ps::uc_dma_mm2dm_axi_control}, + {"uc_dma_pause", aie2ps::uc_dma_pause} + }; + } + + void populateRegValueToNameMap() { + regValueToName= { + {0x000940a0, "mem_event_broadcast_b_block_west_set"}, + {0x00009320, "shim_dma_s2mm_status_0"}, + {0x00009324, "shim_dma_s2mm_status_1"}, + {0x000a061c, "mem_dma_s2mm_3_start_queue"}, + {0x00030330, "cm_core_bmll3_part4"}, + {0x00030310, "cm_core_bmll3_part2"}, + {0x00030320, "cm_core_bmll3_part3"}, + {0x00030300, "cm_core_bmll3_part1"}, + {0x000b5580, "uc_mdm_pcdrr"}, + {0x000c0230, "mem_lock35_value"}, + {0x00002104, "shim_mux_config"}, + {0x000a0614, "mem_dma_s2mm_2_start_queue"}, + {0x000340f4, "shim_timer_trig_event_high_value"}, + {0x00034068, "shim_event_broadcast_a_block_west_value"}, + {0x0001d10c, "mm_dma_bd8_3"}, + {0x000b0228, "mem_stream_switch_slave_dma_2_slot2"}, + {0x0001d104, "mm_dma_bd8_1"}, + {0x000000e0, "shim_lock14_value"}, + {0x0001d100, "mm_dma_bd8_0"}, + {0x0003f2d4, "cm_stream_switch_slave_west_2_slot1"}, + {0x0003f2d0, "cm_stream_switch_slave_west_2_slot0"}, + {0x0003f2dc, "cm_stream_switch_slave_west_2_slot3"}, + {0x0003f2d8, "cm_stream_switch_slave_west_2_slot2"}, + {0x000c0000, "mem_lock0_value"}, + {0x000c0130, "mem_lock19_value"}, + {0x000b55c0, "uc_mdm_pcwr"}, + {0x000a0254, "mem_dma_bd18_5"}, + {0x000a0250, "mem_dma_bd18_4"}, + {0x000a025c, "mem_dma_bd18_7"}, + {0x000a0258, "mem_dma_bd18_6"}, + {0x000a0244, "mem_dma_bd18_1"}, + {0x000a0240, "mem_dma_bd18_0"}, + {0x000a024c, "mem_dma_bd18_3"}, + {0x000a0248, "mem_dma_bd18_2"}, + {0x00032bf0, "cm_core_dc7"}, + {0x0000930c, "shim_dma_s2mm_1_task_queue"}, + {0x00030750, "cm_core_bmlh7_part2"}, + {0x00032b80, "cm_core_dc0"}, + {0x000c0110, "uc_dma_mm2dm_status"}, + {0x000c02c0, "mem_lock44_value"}, + {0x00009310, "shim_dma_mm2s_0_ctrl"}, + {0x0001de0c, "mm_dma_s2mm_1_start_queue"}, + {0x00030740, "cm_core_bmlh7_part1"}, + {0x000c0038, "uc_memory_dm_ecc_scrubbing_period"}, + {0x00034508, "cm_event_group_core_stall_enable"}, + {0x00094214, "mem_event_status5"}, + {0x00094200, "mem_event_status0"}, + {0x00094204, "mem_event_status1"}, + {0x00094208, "mem_event_status2"}, + {0x0009420c, "mem_event_status3"}, + {0x0003ff38, "cm_stream_switch_adaptive_clock_gate_abort_period"}, + {0x00094500, "mem_event_group_0_enable"}, + {0x0003f104, "cm_stream_switch_slave_config_dma_0"}, + {0x000c01c0, "mem_lock28_value"}, + {0x00030480, "cm_core_bmhl4_part1"}, + {0x00014514, "mm_event_group_error_enable"}, + {0x000304a0, "cm_core_bmhl4_part3"}, + {0x00030490, "cm_core_bmhl4_part2"}, + {0x000c00c0, "mem_lock12_value"}, + {0x000304b0, "cm_core_bmhl4_part4"}, + {0x00009300, "shim_dma_s2mm_0_ctrl"}, + {0x00014074, "mm_event_broadcast_block_north_clr"}, + {0x00034068, "cm_event_broadcast_block_west_value"}, + {0x000340f0, "cm_timer_trig_event_low_value"}, + {0x00000000, "shim_lock0_value"}, + {0x000307d0, "cm_core_bmhh7_part2"}, + {0x000307e0, "cm_core_bmhh7_part3"}, + {0x000307c0, "cm_core_bmhh7_part1"}, + {0x000307f0, "cm_core_bmhh7_part4"}, + {0x000b02d0, "mem_stream_switch_slave_north_0_slot0"}, + {0x000b02d4, "mem_stream_switch_slave_north_0_slot1"}, + {0x000b02d8, "mem_stream_switch_slave_north_0_slot2"}, + {0x000b02dc, "mem_stream_switch_slave_north_0_slot3"}, + {0x0003f278, "cm_stream_switch_slave_south_2_slot2"}, + {0x0003f27c, "cm_stream_switch_slave_south_2_slot3"}, + {0x0003f270, "cm_stream_switch_slave_south_2_slot0"}, + {0x0003f274, "cm_stream_switch_slave_south_2_slot1"}, + {0x0001f050, "mm_lock5_value"}, + {0x00031a80, "cm_core_x10_part1"}, + {0x00031aa0, "cm_core_x10_part3"}, + {0x00031a90, "cm_core_x10_part2"}, + {0x00031ab0, "cm_core_x10_part4"}, + {0x00002108, "shim_demux_config"}, + {0x000940f8, "mem_timer_low"}, + {0x0001d1f0, "mm_dma_bd15_4"}, + {0x0001d1f4, "mm_dma_bd15_5"}, + {0x000a063c, "mem_dma_mm2s_1_start_queue"}, + {0x0001d1e0, "mm_dma_bd15_0"}, + {0x0001d1e4, "mm_dma_bd15_1"}, + {0x0001d1e8, "mm_dma_bd15_2"}, + {0x0001d1ec, "mm_dma_bd15_3"}, + {0x00094400, "mem_combo_event_inputs"}, + {0x000b5440, "uc_mdm_pcctrlr"}, + {0x0003f100, "cm_stream_switch_slave_config_aie_core0"}, + {0x000c0200, "mem_lock32_value"}, + {0x000340d8, "shim_trace_status"}, + {0x0000004c, "npi_me_idr1"}, + {0x00009340, "shim_dma_mm2s_0_response_fifo_parity_error_injection"}, + {0x00014070, "mm_event_broadcast_block_north_set"}, + {0x0001d160, "mm_dma_bd11_0"}, + {0x0001d164, "mm_dma_bd11_1"}, + {0x0001d168, "mm_dma_bd11_2"}, + {0x0001d16c, "mm_dma_bd11_3"}, + {0x0001d170, "mm_dma_bd11_4"}, + {0x0001d174, "mm_dma_bd11_5"}, + {0x0001d1b0, "mm_dma_bd13_4"}, + {0x0001d1b4, "mm_dma_bd13_5"}, + {0x0001d1a8, "mm_dma_bd13_2"}, + {0x0001d1ac, "mm_dma_bd13_3"}, + {0x0001d1a0, "mm_dma_bd13_0"}, + {0x0001d1a4, "mm_dma_bd13_1"}, + {0x00094514, "mem_event_group_memory_conflict_enable"}, + {0x000140e0, "mm_trace_event0"}, + {0x000140e4, "mm_trace_event1"}, + {0x000a0230, "mem_dma_bd17_4"}, + {0x000a0234, "mem_dma_bd17_5"}, + {0x000a0228, "mem_dma_bd17_2"}, + {0x000a022c, "mem_dma_bd17_3"}, + {0x000a0220, "mem_dma_bd17_0"}, + {0x000a0224, "mem_dma_bd17_1"}, + {0x000a01e0, "mem_dma_bd15_0"}, + {0x000a01e4, "mem_dma_bd15_1"}, + {0x000a01e8, "mem_dma_bd15_2"}, + {0x000a01ec, "mem_dma_bd15_3"}, + {0x000a01f0, "mem_dma_bd15_4"}, + {0x000a01f4, "mem_dma_bd15_5"}, + {0x000a01f8, "mem_dma_bd15_6"}, + {0x000a01fc, "mem_dma_bd15_7"}, + {0x000a06dc, "mem_dma_s2mm_fot_count_fifo_pop_5"}, + {0x000a06d8, "mem_dma_s2mm_fot_count_fifo_pop_4"}, + {0x000a06cc, "mem_dma_s2mm_fot_count_fifo_pop_1"}, + {0x0001f0d0, "mm_lock13_value"}, + {0x000a06d4, "mem_dma_s2mm_fot_count_fifo_pop_3"}, + {0x000a06d0, "mem_dma_s2mm_fot_count_fifo_pop_2"}, + {0x0003f230, "cm_stream_switch_slave_tile_ctrl_slot0"}, + {0x0003f234, "cm_stream_switch_slave_tile_ctrl_slot1"}, + {0x0003f238, "cm_stream_switch_slave_tile_ctrl_slot2"}, + {0x0003f23c, "cm_stream_switch_slave_tile_ctrl_slot3"}, + {0x0003f14c, "cm_stream_switch_slave_config_east_0"}, + {0x0003f150, "cm_stream_switch_slave_config_east_1"}, + {0x0003f154, "cm_stream_switch_slave_config_east_2"}, + {0x0003f158, "cm_stream_switch_slave_config_east_3"}, + {0x000a0504, "mem_dma_bd40_1"}, + {0x00094070, "mem_event_broadcast_a_block_north_set"}, + {0x000a01ac, "mem_dma_bd13_3"}, + {0x000a01a0, "mem_dma_bd13_0"}, + {0x000a01a4, "mem_dma_bd13_1"}, + {0x000a01b8, "mem_dma_bd13_6"}, + {0x000a01bc, "mem_dma_bd13_7"}, + {0x000a01b0, "mem_dma_bd13_4"}, + {0x000a01b4, "mem_dma_bd13_5"}, + {0x000a0170, "mem_dma_bd11_4"}, + {0x000a0174, "mem_dma_bd11_5"}, + {0x000a017c, "mem_dma_bd11_7"}, + {0x000a0160, "mem_dma_bd11_0"}, + {0x000a0164, "mem_dma_bd11_1"}, + {0x000a0168, "mem_dma_bd11_2"}, + {0x000a016c, "mem_dma_bd11_3"}, + {0x000940fc, "mem_timer_high"}, + {0x0003f374, "cm_stream_switch_slave_aie_trace_slot1"}, + {0x0003f370, "cm_stream_switch_slave_aie_trace_slot0"}, + {0x0003f37c, "cm_stream_switch_slave_aie_trace_slot3"}, + {0x0003f378, "cm_stream_switch_slave_aie_trace_slot2"}, + {0x0001d050, "mm_dma_bd2_4"}, + {0x00037524, "cm_performance_counter1"}, + {0x00037520, "cm_performance_counter0"}, + {0x0003752c, "cm_performance_counter3"}, + {0x00037528, "cm_performance_counter2"}, + {0x000b0018, "mem_stream_switch_master_config_tile_ctrl"}, + {0x000940c8, "mem_event_broadcast_b_block_east_value"}, + {0x0003f2bc, "cm_stream_switch_slave_west_0_slot3"}, + {0x0003f2b8, "cm_stream_switch_slave_west_0_slot2"}, + {0x0003f2b4, "cm_stream_switch_slave_west_0_slot1"}, + {0x0003f2b0, "cm_stream_switch_slave_west_0_slot0"}, + {0x000940d4, "mem_trace_control1"}, + {0x000940d0, "mem_trace_control0"}, + {0x0001f030, "mm_lock3_value"}, + {0x00014028, "mm_event_broadcast6"}, + {0x0001402c, "mm_event_broadcast7"}, + {0x00030660, "cm_core_bmlh6_part3"}, + {0x00030650, "cm_core_bmlh6_part2"}, + {0x00030640, "cm_core_bmlh6_part1"}, + {0x000301a0, "cm_core_bmhl1_part3"}, + {0x000301b0, "cm_core_bmhl1_part4"}, + {0x00030670, "cm_core_bmlh6_part4"}, + {0x00014018, "mm_event_broadcast2"}, + {0x00000040, "shim_lock4_value"}, + {0x0001401c, "mm_event_broadcast3"}, + {0x00014010, "mm_event_broadcast0"}, + {0x00014014, "mm_event_broadcast1"}, + {0x00000090, "shim_lock9_value"}, + {0x00009250, "shim_dma_bd12_4"}, + {0x0003ff30, "cm_tile_control_packet_handler_status"}, + {0x00034030, "cm_event_broadcast8"}, + {0x00034034, "cm_event_broadcast9"}, + {0x0003f368, "cm_stream_switch_slave_east_3_slot2"}, + {0x0003f36c, "cm_stream_switch_slave_east_3_slot3"}, + {0x0003f360, "cm_stream_switch_slave_east_3_slot0"}, + {0x0003f364, "cm_stream_switch_slave_east_3_slot1"}, + {0x00034010, "cm_event_broadcast0"}, + {0x00034014, "cm_event_broadcast1"}, + {0x00034018, "cm_event_broadcast2"}, + {0x0003401c, "cm_event_broadcast3"}, + {0x00091084, "mem_performance_counter1_event_value"}, + {0x000305d0, "cm_core_bmhh5_part2"}, + {0x000305e0, "cm_core_bmhh5_part3"}, + {0x000305f0, "cm_core_bmhh5_part4"}, + {0x00000040, "npi_me_idr0"}, + {0x00000064, "npi_me_idr3"}, + {0x000091f0, "shim_dma_bd10_4"}, + {0x00000058, "npi_me_idr2"}, + {0x000091f4, "shim_dma_bd10_5"}, + {0x000091f8, "shim_dma_bd10_6"}, + {0x0003f02c, "cm_stream_switch_master_config_west2"}, + {0x0003f030, "cm_stream_switch_master_config_west3"}, + {0x0003f024, "cm_stream_switch_master_config_west0"}, + {0x0003f028, "cm_stream_switch_master_config_west1"}, + {0x0003f144, "cm_stream_switch_slave_config_north_2"}, + {0x00000030, "npi_me_isr"}, + {0x000a05c0, "mem_dma_bd46_0"}, + {0x000a05c4, "mem_dma_bd46_1"}, + {0x000a05c8, "mem_dma_bd46_2"}, + {0x000a05cc, "mem_dma_bd46_3"}, + {0x000a05d0, "mem_dma_bd46_4"}, + {0x000a05d4, "mem_dma_bd46_5"}, + {0x000a05d8, "mem_dma_bd46_6"}, + {0x000a05dc, "mem_dma_bd46_7"}, + {0x00031a40, "cm_core_x9_part1"}, + {0x00014100, "mm_watchpoint0"}, + {0x00014104, "mm_watchpoint1"}, + {0x00094068, "mem_event_broadcast_a_block_west_value"}, + {0x0001de18, "mm_dma_mm2s_1_ctrl"}, + {0x000140f0, "mm_timer_trig_event_low_value"}, + {0x000b0808, "mem_stream_switch_deterministic_merge_arb0_ctrl"}, + {0x0003f28c, "cm_stream_switch_slave_south_3_slot3"}, + {0x0003f288, "cm_stream_switch_slave_south_3_slot2"}, + {0x000b0030, "mem_stream_switch_master_config_north1"}, + {0x000b002c, "mem_stream_switch_master_config_north0"}, + {0x000b0040, "mem_stream_switch_master_config_north5"}, + {0x000b003c, "mem_stream_switch_master_config_north4"}, + {0x000140d4, "mm_trace_control1"}, + {0x000140d0, "mm_trace_control0"}, + {0x00034078, "shim_event_broadcast_a_block_north_value"}, + {0x00034054, "shim_event_broadcast_a_block_south_clr"}, + {0x00030220, "cm_core_bmll2_part3"}, + {0x00030210, "cm_core_bmll2_part2"}, + {0x00030200, "cm_core_bmll2_part1"}, + {0x00030230, "cm_core_bmll2_part4"}, + {0x00009338, "shim_dma_s2mm_fot_count_fifo_pop_0"}, + {0x0000933c, "shim_dma_s2mm_fot_count_fifo_pop_1"}, + {0x000c0114, "uc_dma_mm2dm_control"}, + {0x00014064, "mm_event_broadcast_block_west_clr"}, + {0x000c02e0, "mem_lock46_value"}, + {0x0001d114, "mm_dma_bd8_5"}, + {0x0001d110, "mm_dma_bd8_4"}, + {0x000b022c, "mem_stream_switch_slave_dma_2_slot3"}, + {0x0001d108, "mm_dma_bd8_2"}, + {0x000b0224, "mem_stream_switch_slave_dma_2_slot1"}, + {0x000b0220, "mem_stream_switch_slave_dma_2_slot0"}, + {0x00001004, "shim_interrupt_controller_2nd_level_enable"}, + {0x0003404c, "shim_event_broadcast_a_15"}, + {0x0003758c, "cm_performance_counter3_event_value"}, + {0x00030570, "cm_core_bmlh5_part4"}, + {0x000b0018, "uc_mdm_dbg_lock"}, + {0x00030540, "cm_core_bmlh5_part1"}, + {0x00030550, "cm_core_bmlh5_part2"}, + {0x00030560, "cm_core_bmlh5_part3"}, + {0x00091088, "mem_performance_counter2_event_value"}, + {0x0003f108, "cm_stream_switch_slave_config_dma_1"}, + {0x000a052c, "mem_dma_bd41_3"}, + {0x000a0528, "mem_dma_bd41_2"}, + {0x000a0524, "mem_dma_bd41_1"}, + {0x000a0520, "mem_dma_bd41_0"}, + {0x000a053c, "mem_dma_bd41_7"}, + {0x000a0538, "mem_dma_bd41_6"}, + {0x000a0534, "mem_dma_bd41_5"}, + {0x000a0530, "mem_dma_bd41_4"}, + {0x000a0574, "mem_dma_bd43_5"}, + {0x000a0570, "mem_dma_bd43_4"}, + {0x000a057c, "mem_dma_bd43_7"}, + {0x000a0578, "mem_dma_bd43_6"}, + {0x000a0564, "mem_dma_bd43_1"}, + {0x000a0560, "mem_dma_bd43_0"}, + {0x000a056c, "mem_dma_bd43_3"}, + {0x000a0568, "mem_dma_bd43_2"}, + {0x000c0350, "mem_lock53_value"}, + {0x000000b0, "shim_lock11_value"}, + {0x000b0244, "mem_stream_switch_slave_dma_4_slot1"}, + {0x000b0240, "mem_stream_switch_slave_dma_4_slot0"}, + {0x000b024c, "mem_stream_switch_slave_dma_4_slot3"}, + {0x000b0248, "mem_stream_switch_slave_dma_4_slot2"}, + {0x000a05bc, "mem_dma_bd45_7"}, + {0x000a05b8, "mem_dma_bd45_6"}, + {0x000a05b4, "mem_dma_bd45_5"}, + {0x000a05b0, "mem_dma_bd45_4"}, + {0x000a05ac, "mem_dma_bd45_3"}, + {0x000a05a8, "mem_dma_bd45_2"}, + {0x000a05a4, "mem_dma_bd45_1"}, + {0x000a05a0, "mem_dma_bd45_0"}, + {0x000c03f0, "mem_lock63_value"}, + {0x00000050, "shim_lock5_value"}, + {0x00034084, "shim_event_broadcast_a_block_east_clr"}, + {0x0003f290, "cm_stream_switch_slave_south_4_slot0"}, + {0x0003f294, "cm_stream_switch_slave_south_4_slot1"}, + {0x0003f298, "cm_stream_switch_slave_south_4_slot2"}, + {0x0003f29c, "cm_stream_switch_slave_south_4_slot3"}, + {0x00094520, "mem_event_group_user_event_enable"}, + {0x00000034, "npi_me_itr"}, + {0x00030500, "cm_core_bmll5_part1"}, + {0x00030510, "cm_core_bmll5_part2"}, + {0x00030520, "cm_core_bmll5_part3"}, + {0x00030530, "cm_core_bmll5_part4"}, + {0x00000104, "shim_locks_event_selection_1"}, + {0x00000100, "shim_locks_event_selection_0"}, + {0x0000010c, "shim_locks_event_selection_3"}, + {0x000b02b4, "mem_stream_switch_slave_south_4_slot1"}, + {0x00000114, "shim_locks_event_selection_5"}, + {0x00000110, "shim_locks_event_selection_4"}, + {0x000319a0, "cm_core_x6_part3"}, + {0x00031990, "cm_core_x6_part2"}, + {0x00031980, "cm_core_x6_part1"}, + {0x000327b0, "cm_core_f11"}, + {0x000327a0, "cm_core_f10"}, + {0x000319b0, "cm_core_x6_part4"}, + {0x0001100c, "mm_performance_control2"}, + {0x00011010, "mm_performance_control3"}, + {0x00011000, "mm_performance_control0"}, + {0x00011008, "mm_performance_control1"}, + {0x0003f134, "cm_stream_switch_slave_config_west_2"}, + {0x0003f138, "cm_stream_switch_slave_config_west_3"}, + {0x0003f12c, "cm_stream_switch_slave_config_west_0"}, + {0x0003f130, "cm_stream_switch_slave_config_west_1"}, + {0x00014518, "mm_event_group_broadcast_enable"}, + {0x00034070, "shim_event_broadcast_a_block_north_set"}, + {0x00032480, "cm_core_ldfifol1_part1"}, + {0x00032490, "cm_core_ldfifol1_part2"}, + {0x000324a0, "cm_core_ldfifol1_part3"}, + {0x000324b0, "cm_core_ldfifol1_part4"}, + {0x00094210, "mem_event_status4"}, + {0x000092a4, "shim_dma_bd14_1"}, + {0x000a010c, "mem_dma_bd8_3"}, + {0x000a0108, "mem_dma_bd8_2"}, + {0x000a0104, "mem_dma_bd8_1"}, + {0x000a0100, "mem_dma_bd8_0"}, + {0x000a011c, "mem_dma_bd8_7"}, + {0x000a0118, "mem_dma_bd8_6"}, + {0x000a0114, "mem_dma_bd8_5"}, + {0x000a0110, "mem_dma_bd8_4"}, + {0x000092b4, "shim_dma_bd14_5"}, + {0x000a00c4, "mem_dma_bd6_1"}, + {0x000a00c0, "mem_dma_bd6_0"}, + {0x000a00cc, "mem_dma_bd6_3"}, + {0x000a00c8, "mem_dma_bd6_2"}, + {0x000a00d4, "mem_dma_bd6_5"}, + {0x000a00d0, "mem_dma_bd6_4"}, + {0x000a00dc, "mem_dma_bd6_7"}, + {0x000a00d8, "mem_dma_bd6_6"}, + {0x000940b0, "mem_event_broadcast_b_block_north_set"}, + {0x000c0118, "uc_dma_mm2dm_axi_control"}, + {0x0001d0f0, "mm_dma_bd7_4"}, + {0x0001d0f4, "mm_dma_bd7_5"}, + {0x0001d0e0, "mm_dma_bd7_0"}, + {0x0001d0e4, "mm_dma_bd7_1"}, + {0x0001d0e8, "mm_dma_bd7_2"}, + {0x0001d0ec, "mm_dma_bd7_3"}, + {0x000b02f8, "mem_stream_switch_slave_north_2_slot2"}, + {0x000b02fc, "mem_stream_switch_slave_north_2_slot3"}, + {0x000b02f0, "mem_stream_switch_slave_north_2_slot0"}, + {0x000b02f4, "mem_stream_switch_slave_north_2_slot1"}, + {0x0001d0a8, "mm_dma_bd5_2"}, + {0x0001d0ac, "mm_dma_bd5_3"}, + {0x0001d0a0, "mm_dma_bd5_0"}, + {0x0001d0a4, "mm_dma_bd5_1"}, + {0x0001d0b0, "mm_dma_bd5_4"}, + {0x0001d0b4, "mm_dma_bd5_5"}, + {0x00094518, "mem_event_group_error_enable"}, + {0x0001f020, "mm_lock2_value"}, + {0x00030080, "cm_core_bmhl0_part1"}, + {0x000300a0, "cm_core_bmhl0_part3"}, + {0x00030090, "cm_core_bmhl0_part2"}, + {0x000302b0, "cm_core_bmhl2_part4"}, + {0x000302a0, "cm_core_bmhl2_part3"}, + {0x00030290, "cm_core_bmhl2_part2"}, + {0x00030280, "cm_core_bmhl2_part1"}, + {0x00034060, "shim_event_broadcast_a_block_west_set"}, + {0x000a0028, "mem_dma_bd1_2"}, + {0x000a002c, "mem_dma_bd1_3"}, + {0x000a0020, "mem_dma_bd1_0"}, + {0x000a0024, "mem_dma_bd1_1"}, + {0x000a0038, "mem_dma_bd1_6"}, + {0x000a003c, "mem_dma_bd1_7"}, + {0x000a0030, "mem_dma_bd1_4"}, + {0x000a0034, "mem_dma_bd1_5"}, + {0x000340d0, "shim_trace_control0"}, + {0x000340d4, "shim_trace_control1"}, + {0x000a0610, "mem_dma_s2mm_2_ctrl"}, + {0x0001d064, "mm_dma_bd3_1"}, + {0x0001d068, "mm_dma_bd3_2"}, + {0x0001d06c, "mm_dma_bd3_3"}, + {0x0001d070, "mm_dma_bd3_4"}, + {0x0001d074, "mm_dma_bd3_5"}, + {0x00034074, "cm_event_broadcast_block_north_clr"}, + {0x0001d030, "mm_dma_bd1_4"}, + {0x0001d034, "mm_dma_bd1_5"}, + {0x0001d028, "mm_dma_bd1_2"}, + {0x0001d02c, "mm_dma_bd1_3"}, + {0x00038008, "cm_enable_events"}, + {0x0001d024, "mm_dma_bd1_1"}, + {0x000c0250, "mem_lock37_value"}, + {0x000b0110, "mem_stream_switch_slave_config_dma_4"}, + {0x000b0114, "mem_stream_switch_slave_config_dma_5"}, + {0x000b0100, "mem_stream_switch_slave_config_dma_0"}, + {0x000b0104, "mem_stream_switch_slave_config_dma_1"}, + {0x000b0108, "mem_stream_switch_slave_config_dma_2"}, + {0x00094508, "mem_event_group_dma_enable"}, + {0x00094028, "mem_event_broadcast6"}, + {0x0009402c, "mem_event_broadcast7"}, + {0x000326a0, "cm_core_eg10"}, + {0x00094024, "mem_event_broadcast5"}, + {0x00094018, "mem_event_broadcast2"}, + {0x0009401c, "mem_event_broadcast3"}, + {0x00094010, "mem_event_broadcast0"}, + {0x00094014, "mem_event_broadcast1"}, + {0x000b0020, "mem_stream_switch_master_config_south1"}, + {0x000b001c, "mem_stream_switch_master_config_south0"}, + {0x000b0028, "mem_stream_switch_master_config_south3"}, + {0x000b0024, "mem_stream_switch_master_config_south2"}, + {0x000a0060, "mem_dma_bd3_0"}, + {0x000a0064, "mem_dma_bd3_1"}, + {0x000a0068, "mem_dma_bd3_2"}, + {0x000a006c, "mem_dma_bd3_3"}, + {0x000c003c, "uc_memory_dm_ecc_error_generation"}, + {0x00038004, "cm_core_status"}, + {0x0001f120, "mm_locks_overflow"}, + {0x0001de08, "mm_dma_s2mm_1_ctrl"}, + {0x00030440, "cm_core_bmlh4_part1"}, + {0x00030460, "cm_core_bmlh4_part3"}, + {0x00030450, "cm_core_bmlh4_part2"}, + {0x00030470, "cm_core_bmlh4_part4"}, + {0x00003000, "shim_smid"}, + {0x000a0624, "mem_dma_s2mm_4_start_queue"}, + {0x000a06f4, "mem_dma_mm2s_5_constant_pad_value"}, + {0x0001f0b0, "mm_lock11_value"}, + {0x00034080, "cm_event_broadcast_block_east_set"}, + {0x0001df14, "mm_dma_mm2s_status_1"}, + {0x0001df10, "mm_dma_mm2s_status_0"}, + {0x000c0020, "mem_lock2_value"}, + {0x00031a30, "cm_core_x8_part4"}, + {0x00031a00, "cm_core_x8_part1"}, + {0x00031018, "shim_performance_control5"}, + {0x00031a20, "cm_core_x8_part3"}, + {0x00031a10, "cm_core_x8_part2"}, + {0x00031014, "shim_performance_control4"}, + {0x0001f080, "mm_lock8_value"}, + {0x00034518, "cm_event_group_stream_switch_enable"}, + {0x000a0158, "mem_dma_bd10_6"}, + {0x000a0144, "mem_dma_bd10_1"}, + {0x000a0140, "mem_dma_bd10_0"}, + {0x0001f000, "mm_lock0_value"}, + {0x000a014c, "mem_dma_bd10_3"}, + {0x00032790, "cm_core_f9"}, + {0x00032780, "cm_core_f8"}, + {0x00000080, "shim_lock8_value"}, + {0x00032710, "cm_core_f1"}, + {0x00032700, "cm_core_f0"}, + {0x00032730, "cm_core_f3"}, + {0x00032720, "cm_core_f2"}, + {0x00032750, "cm_core_f5"}, + {0x00032740, "cm_core_f4"}, + {0x00032770, "cm_core_f7"}, + {0x00032760, "cm_core_f6"}, + {0x000a0404, "mem_dma_bd32_1"}, + {0x000a0400, "mem_dma_bd32_0"}, + {0x000140d8, "mm_trace_status"}, + {0x000a0408, "mem_dma_bd32_2"}, + {0x000a0414, "mem_dma_bd32_5"}, + {0x000a0410, "mem_dma_bd32_4"}, + {0x000a041c, "mem_dma_bd32_7"}, + {0x000a0418, "mem_dma_bd32_6"}, + {0x000c0040, "mem_lock4_value"}, + {0x0003f204, "cm_stream_switch_slave_aie_core0_slot1"}, + {0x0003f200, "cm_stream_switch_slave_aie_core0_slot0"}, + {0x0003f20c, "cm_stream_switch_slave_aie_core0_slot3"}, + {0x0003f208, "cm_stream_switch_slave_aie_core0_slot2"}, + {0x0001451c, "mm_event_group_user_event_enable"}, + {0x00014000, "mm_timer_control"}, + {0x00009284, "shim_dma_bd13_5"}, + {0x000a04dc, "mem_dma_bd38_7"}, + {0x000a04d8, "mem_dma_bd38_6"}, + {0x00032d10, "cm_core_fc"}, + {0x000a04d0, "mem_dma_bd38_4"}, + {0x000a04cc, "mem_dma_bd38_3"}, + {0x000a04c8, "mem_dma_bd38_2"}, + {0x000a04c4, "mem_dma_bd38_1"}, + {0x000a04c0, "mem_dma_bd38_0"}, + {0x0003f2e8, "cm_stream_switch_slave_west_3_slot2"}, + {0x00031080, "shim_performance_counter0_event_value"}, + {0x0003f2ec, "cm_stream_switch_slave_west_3_slot3"}, + {0x00001008, "shim_interrupt_controller_2nd_level_disable"}, + {0x000c0108, "uc_dma_dm2mm_axi_control"}, + {0x0003f310, "cm_stream_switch_slave_north_2_slot0"}, + {0x0003f314, "cm_stream_switch_slave_north_2_slot1"}, + {0x0003f318, "cm_stream_switch_slave_north_2_slot2"}, + {0x0003f31c, "cm_stream_switch_slave_north_2_slot3"}, + {0x00031030, "shim_performance_counter4"}, + {0x00031034, "shim_performance_counter5"}, + {0x00031028, "shim_performance_counter2"}, + {0x0003102C, "shim_performance_counter3"}, + {0x00031020, "shim_performance_counter0"}, + {0x00031024, "shim_performance_counter1"}, + {0x00014508, "mm_event_group_dma_enable"}, + {0x00000030, "shim_lock3_value"}, + {0x000340f4, "cm_timer_trig_event_high_value"}, + {0x0001d134, "mm_dma_bd9_5"}, + {0x000c0190, "mem_lock25_value"}, + {0x000d0000, "mem_lock_request"}, + {0x0001f128, "mm_locks_underflow"}, + {0x00034088, "cm_event_broadcast_block_east_value"}, + {0x00011084, "mm_performance_counter1_event_value"}, + {0x00034058, "cm_event_broadcast_block_south_value"}, + {0x0003f340, "cm_stream_switch_slave_east_1_slot0"}, + {0x0003f344, "cm_stream_switch_slave_east_1_slot1"}, + {0x0003f348, "cm_stream_switch_slave_east_1_slot2"}, + {0x0003f34c, "cm_stream_switch_slave_east_1_slot3"}, + {0x000c02a0, "mem_lock42_value"}, + {0x000a0468, "mem_dma_bd35_2"}, + {0x000a046c, "mem_dma_bd35_3"}, + {0x000a0460, "mem_dma_bd35_0"}, + {0x000a0464, "mem_dma_bd35_1"}, + {0x000a0478, "mem_dma_bd35_6"}, + {0x0003ff20, "cm_stream_switch_parity_injection"}, + {0x000a0470, "mem_dma_bd35_4"}, + {0x000a0474, "mem_dma_bd35_5"}, + {0x000a04b0, "mem_dma_bd37_4"}, + {0x00032510, "cm_core_stfifol_part2"}, + {0x000a04b8, "mem_dma_bd37_6"}, + {0x000a04bc, "mem_dma_bd37_7"}, + {0x000a04a0, "mem_dma_bd37_0"}, + {0x000a04a4, "mem_dma_bd37_1"}, + {0x000a04a8, "mem_dma_bd37_2"}, + {0x00032530, "cm_core_stfifol_part4"}, + {0x000a03f8, "mem_dma_bd31_6"}, + {0x000a03fc, "mem_dma_bd31_7"}, + {0x000a03f0, "mem_dma_bd31_4"}, + {0x000a03f4, "mem_dma_bd31_5"}, + {0x000a03e8, "mem_dma_bd31_2"}, + {0x000a03ec, "mem_dma_bd31_3"}, + {0x000a03e0, "mem_dma_bd31_0"}, + {0x000a03e4, "mem_dma_bd31_1"}, + {0x000a0608, "mem_dma_s2mm_1_ctrl"}, + {0x0003f038, "cm_stream_switch_master_config_north1"}, + {0x0003f034, "cm_stream_switch_master_config_north0"}, + {0x0003f040, "cm_stream_switch_master_config_north3"}, + {0x0003f03c, "cm_stream_switch_master_config_north2"}, + {0x0003f048, "cm_stream_switch_master_config_north5"}, + {0x0003f044, "cm_stream_switch_master_config_north4"}, + {0x00009064, "shim_dma_bd2_1"}, + {0x000fff00, "mem_module_clock_control"}, + {0x0001de10, "mm_dma_mm2s_0_ctrl"}, + {0x000a0674, "mem_dma_s2mm_status_5"}, + {0x000a0670, "mem_dma_s2mm_status_4"}, + {0x000a066c, "mem_dma_s2mm_status_3"}, + {0x000a0668, "mem_dma_s2mm_status_2"}, + {0x000a0664, "mem_dma_s2mm_status_1"}, + {0x000a0660, "mem_dma_s2mm_status_0"}, + {0x00000120, "shim_locks_overflow"}, + {0x00032570, "cm_core_stfifoh_part4"}, + {0x00032560, "cm_core_stfifoh_part3"}, + {0x00032550, "cm_core_stfifoh_part2"}, + {0x00032540, "cm_core_stfifoh_part1"}, + {0x00014060, "mm_event_broadcast_block_west_set"}, + {0x00060000, "cm_module_clock_control"}, + {0x000b0f10, "mem_stream_switch_parity_status"}, + {0x000300b0, "cm_core_bmhl0_part4"}, + {0x00094408, "mem_edge_detection_event_control"}, + {0x0003f128, "cm_stream_switch_slave_config_south_5"}, + {0x0003f124, "cm_stream_switch_slave_config_south_4"}, + {0x0003f2a4, "cm_stream_switch_slave_south_5_slot1"}, + {0x0003f2a0, "cm_stream_switch_slave_south_5_slot0"}, + {0x0003f2ac, "cm_stream_switch_slave_south_5_slot3"}, + {0x0003f2a8, "cm_stream_switch_slave_south_5_slot2"}, + {0x000340d4, "cm_trace_control1"}, + {0x000340d0, "cm_trace_control0"}, + {0x00032ca0, "cm_core_s2"}, + {0x00032cb0, "cm_core_s3"}, + {0x00032c80, "cm_core_s0"}, + {0x00032c90, "cm_core_s1"}, + {0x0003f118, "cm_stream_switch_slave_config_south_1"}, + {0x00032b20, "cm_core_dj2"}, + {0x00032b30, "cm_core_dj3"}, + {0x00032b00, "cm_core_dj0"}, + {0x00032b10, "cm_core_dj1"}, + {0x00032b60, "cm_core_dj6"}, + {0x00032b70, "cm_core_dj7"}, + {0x00032b40, "cm_core_dj4"}, + {0x00032b50, "cm_core_dj5"}, + {0x000c02f0, "mem_lock47_value"}, + {0x00009248, "shim_dma_bd12_2"}, + {0x0000924c, "shim_dma_bd12_3"}, + {0x00009240, "shim_dma_bd12_0"}, + {0x00009244, "shim_dma_bd12_1"}, + {0x00009258, "shim_dma_bd12_6"}, + {0x0000925c, "shim_dma_bd12_7"}, + {0x00032d20, "cm_core_sp"}, + {0x00009254, "shim_dma_bd12_5"}, + {0x00009260, "shim_dma_bd12_8"}, + {0x000b0268, "mem_stream_switch_slave_tile_ctrl_slot2"}, + {0x000b026c, "mem_stream_switch_slave_tile_ctrl_slot3"}, + {0x000b0260, "mem_stream_switch_slave_tile_ctrl_slot0"}, + {0x000b0264, "mem_stream_switch_slave_tile_ctrl_slot1"}, + {0x000091e0, "shim_dma_bd10_0"}, + {0x000091e4, "shim_dma_bd10_1"}, + {0x000091e8, "shim_dma_bd10_2"}, + {0x000091ec, "shim_dma_bd10_3"}, + {0x00009200, "shim_dma_bd10_8"}, + {0x000b0f00, "mem_stream_switch_event_port_selection_0"}, + {0x000c00d0, "mem_lock13_value"}, + {0x0003f2cc, "cm_stream_switch_slave_west_1_slot3"}, + {0x00014088, "mm_event_broadcast_block_east_value"}, + {0x00009318, "shim_dma_mm2s_1_ctrl"}, + {0x00014054, "mm_event_broadcast_block_south_clr"}, + {0x000b02e4, "mem_stream_switch_slave_north_1_slot1"}, + {0x000b02e0, "mem_stream_switch_slave_north_1_slot0"}, + {0x000b02ec, "mem_stream_switch_slave_north_1_slot3"}, + {0x000b02e8, "mem_stream_switch_slave_north_1_slot2"}, + {0x000940a4, "mem_event_broadcast_b_block_west_clr"}, + {0x000b0f20, "mem_stream_switch_parity_injection"}, + {0x0001d060, "mm_dma_bd3_0"}, + {0x000b0f04, "mem_stream_switch_event_port_selection_1"}, + {0x000c01e0, "mem_lock30_value"}, + {0x00034504, "cm_event_group_pc_enable"}, + {0x00009128, "shim_dma_bd6_2"}, + {0x0000912c, "shim_dma_bd6_3"}, + {0x00009120, "shim_dma_bd6_0"}, + {0x00009124, "shim_dma_bd6_1"}, + {0x000c03c0, "mem_lock60_value"}, + {0x00009138, "shim_dma_bd6_6"}, + {0x0001df04, "mm_dma_s2mm_status_1"}, + {0x0001df00, "mm_dma_s2mm_status_0"}, + {0x0000913c, "shim_dma_bd6_7"}, + {0x00009130, "shim_dma_bd6_4"}, + {0x00009134, "shim_dma_bd6_5"}, + {0x00001010, "shim_interrupt_controller_2nd_level_interrupt"}, + {0x20, "shim_dma_bd_step_size"}, + {0x000c00a0, "mem_lock10_value"}, + {0x000a062c, "mem_dma_s2mm_5_start_queue"}, + {0x00009308, "shim_dma_s2mm_1_ctrl"}, + {0x0001d020, "mm_dma_bd1_0"}, + {0x000a0380, "mem_dma_bd28_0"}, + {0x000a0384, "mem_dma_bd28_1"}, + {0x000a0388, "mem_dma_bd28_2"}, + {0x000a038c, "mem_dma_bd28_3"}, + {0x000a0390, "mem_dma_bd28_4"}, + {0x000a0394, "mem_dma_bd28_5"}, + {0x000a0398, "mem_dma_bd28_6"}, + {0x000a039c, "mem_dma_bd28_7"}, + {0x00034514, "cm_event_group_errors1_enable"}, + {0x00009290, "shim_dma_bd13_8"}, + {0x000a0280, "mem_dma_bd20_0"}, + {0x000a0284, "mem_dma_bd20_1"}, + {0x000a0288, "mem_dma_bd20_2"}, + {0x000a028c, "mem_dma_bd20_3"}, + {0x000a0290, "mem_dma_bd20_4"}, + {0x000a0294, "mem_dma_bd20_5"}, + {0x000a0298, "mem_dma_bd20_6"}, + {0x000a029c, "mem_dma_bd20_7"}, + {0x00040000, "mm_lock_request"}, + {0x00094084, "mem_event_broadcast_a_block_east_clr"}, + {0x000c0270, "mem_lock39_value"}, + {0x00032850, "cm_core_r5"}, + {0x00032840, "cm_core_r4"}, + {0x00032870, "cm_core_r7"}, + {0x00032860, "cm_core_r6"}, + {0x00032810, "cm_core_r1"}, + {0x00032800, "cm_core_r0"}, + {0x00014084, "mm_event_broadcast_block_east_clr"}, + {0x00032820, "cm_core_r2"}, + {0x000092f0, "shim_dma_bd15_8"}, + {0x00032890, "cm_core_r9"}, + {0x00032880, "cm_core_r8"}, + {0x00009230, "shim_dma_bd11_8"}, + {0x00009220, "shim_dma_bd11_4"}, + {0x000940a8, "mem_event_broadcast_b_block_west_value"}, + {0x00094030, "mem_event_broadcast8"}, + {0x00094034, "mem_event_broadcast9"}, + {0x00014510, "mm_event_group_memory_conflict_enable"}, + {0x000c0260, "mem_lock38_value"}, + {0x00034034, "shim_event_broadcast_a_9"}, + {0x00034030, "shim_event_broadcast_a_8"}, + {0x0003402c, "shim_event_broadcast_a_7"}, + {0x00034028, "shim_event_broadcast_a_6"}, + {0x00034024, "shim_event_broadcast_a_5"}, + {0x00034020, "shim_event_broadcast_a_4"}, + {0x0003401c, "shim_event_broadcast_a_3"}, + {0x00094020, "mem_event_broadcast4"}, + {0x00034014, "shim_event_broadcast_a_1"}, + {0x00034010, "shim_event_broadcast_a_0"}, + {0x000326b0, "cm_core_eg11"}, + {0x00009348, "shim_dma_pause"}, + {0x00002120, "shim_axi_mm_outstanding_transactions"}, + {0x000a0620, "mem_dma_s2mm_4_ctrl"}, + {0x00009104, "shim_dma_bd5_5"}, + {0x00009100, "shim_dma_bd5_4"}, + {0x0000910c, "shim_dma_bd5_7"}, + {0x00009108, "shim_dma_bd5_6"}, + {0x0003f240, "cm_stream_switch_slave_fifo_0_slot0"}, + {0x0003f244, "cm_stream_switch_slave_fifo_0_slot1"}, + {0x0003f248, "cm_stream_switch_slave_fifo_0_slot2"}, + {0x0003f24c, "cm_stream_switch_slave_fifo_0_slot3"}, + {0x000091c8, "shim_dma_bd9_6"}, + {0x00009110, "shim_dma_bd5_8"}, + {0x000000f0, "shim_lock15_value"}, + {0x000090ac, "shim_dma_bd3_7"}, + {0x000090a8, "shim_dma_bd3_6"}, + {0x000090a4, "shim_dma_bd3_5"}, + {0x000090a0, "shim_dma_bd3_4"}, + {0x0000909c, "shim_dma_bd3_3"}, + {0x00009098, "shim_dma_bd3_2"}, + {0x00009094, "shim_dma_bd3_1"}, + {0x00009090, "shim_dma_bd3_0"}, + {0x000090b0, "shim_dma_bd3_8"}, + {0x000c0180, "mem_lock24_value"}, + {0x000a0070, "mem_dma_bd3_4"}, + {0x000a0074, "mem_dma_bd3_5"}, + {0x000a0078, "mem_dma_bd3_6"}, + {0x000a007c, "mem_dma_bd3_7"}, + {0x000b0000, "mem_stream_switch_master_config_dma0"}, + {0x000b0004, "mem_stream_switch_master_config_dma1"}, + {0x000b0008, "mem_stream_switch_master_config_dma2"}, + {0x000b000c, "mem_stream_switch_master_config_dma3"}, + {0x000b0010, "mem_stream_switch_master_config_dma4"}, + {0x000b0014, "mem_stream_switch_master_config_dma5"}, + {0x000a036c, "mem_dma_bd27_3"}, + {0x000a0368, "mem_dma_bd27_2"}, + {0x000a0364, "mem_dma_bd27_1"}, + {0x000a0360, "mem_dma_bd27_0"}, + {0x000a037c, "mem_dma_bd27_7"}, + {0x000a0378, "mem_dma_bd27_6"}, + {0x000a0374, "mem_dma_bd27_5"}, + {0x000a0370, "mem_dma_bd27_4"}, + {0x000a0334, "mem_dma_bd25_5"}, + {0x000a0330, "mem_dma_bd25_4"}, + {0x000a033c, "mem_dma_bd25_7"}, + {0x000a0338, "mem_dma_bd25_6"}, + {0x000a0324, "mem_dma_bd25_1"}, + {0x000a0320, "mem_dma_bd25_0"}, + {0x000a032c, "mem_dma_bd25_3"}, + {0x000a0328, "mem_dma_bd25_2"}, + {0x000a02fc, "mem_dma_bd23_7"}, + {0x000a02f8, "mem_dma_bd23_6"}, + {0x000a02f4, "mem_dma_bd23_5"}, + {0x000a02f0, "mem_dma_bd23_4"}, + {0x000a02ec, "mem_dma_bd23_3"}, + {0x000a02e8, "mem_dma_bd23_2"}, + {0x000a02e4, "mem_dma_bd23_1"}, + {0x000a02e0, "mem_dma_bd23_0"}, + {0x00009170, "shim_dma_bd7_8"}, + {0x000b0204, "mem_stream_switch_slave_dma_0_slot1"}, + {0x000b0200, "mem_stream_switch_slave_dma_0_slot0"}, + {0x000b020c, "mem_stream_switch_slave_dma_0_slot3"}, + {0x000b0208, "mem_stream_switch_slave_dma_0_slot2"}, + {0x000092e4, "shim_dma_bd15_5"}, + {0x000a0638, "mem_dma_mm2s_1_ctrl"}, + {0x00034404, "cm_combo_event_control"}, + {0x000b0144, "mem_stream_switch_slave_config_trace"}, + {0x000940e0, "mem_trace_event0"}, + {0x000940e4, "mem_trace_event1"}, + {0x00032600, "cm_core_eg0"}, + {0x00032610, "cm_core_eg1"}, + {0x00038014, "cm_debug_control1"}, + {0x00038010, "cm_debug_control0"}, + {0x00032640, "cm_core_eg4"}, + {0x00032650, "cm_core_eg5"}, + {0x00032660, "cm_core_eg6"}, + {0x00032670, "cm_core_eg7"}, + {0x000091a0, "shim_dma_bd8_8"}, + {0x00009180, "shim_dma_bd8_0"}, + {0x00000128, "shim_locks_underflow"}, + {0x00009188, "shim_dma_bd8_2"}, + {0x0000918c, "shim_dma_bd8_3"}, + {0x00009190, "shim_dma_bd8_4"}, + {0x00009194, "shim_dma_bd8_5"}, + {0x00009198, "shim_dma_bd8_6"}, + {0x0000919c, "shim_dma_bd8_7"}, + {0x000092ec, "shim_dma_bd15_7"}, + {0x000c02b0, "mem_lock43_value"}, + {0x000340f8, "shim_timer_low"}, + {0x000c0390, "mem_lock57_value"}, + {0x0009451c, "mem_event_group_broadcast_enable"}, + {0x0003f308, "cm_stream_switch_slave_north_1_slot2"}, + {0x0003f304, "cm_stream_switch_slave_north_1_slot1"}, + {0x0003f300, "cm_stream_switch_slave_north_1_slot0"}, + {0x00009000, "shim_dma_bd0_0"}, + {0x00009004, "shim_dma_bd0_1"}, + {0x00009008, "shim_dma_bd0_2"}, + {0x0000900c, "shim_dma_bd0_3"}, + {0x00009010, "shim_dma_bd0_4"}, + {0x00009014, "shim_dma_bd0_5"}, + {0x00009018, "shim_dma_bd0_6"}, + {0x0000901c, "shim_dma_bd0_7"}, + {0x00009020, "shim_dma_bd0_8"}, + {0x000940b4, "mem_event_broadcast_b_block_north_clr"}, + {0x000b0210, "mem_stream_switch_slave_dma_1_slot0"}, + {0x000b0214, "mem_stream_switch_slave_dma_1_slot1"}, + {0x000b0218, "mem_stream_switch_slave_dma_1_slot2"}, + {0x000b021c, "mem_stream_switch_slave_dma_1_slot3"}, + {0x00034408, "cm_edge_detection_event_control"}, + {0x00034050, "shim_event_broadcast_a_block_south_set"}, + {0x000c0070, "mem_lock7_value"}, + {0x0003801c, "cm_debug_status"}, + {0x000b030c, "mem_stream_switch_slave_north_3_slot3"}, + {0x000b0308, "mem_stream_switch_slave_north_3_slot2"}, + {0x000b0304, "mem_stream_switch_slave_north_3_slot1"}, + {0x000b0300, "mem_stream_switch_slave_north_3_slot0"}, + {0x0003802c, "cm_pc_event3"}, + {0x00038028, "cm_pc_event2"}, + {0x00038024, "cm_pc_event1"}, + {0x00038020, "cm_pc_event0"}, + {0x0003f000, "cm_stream_switch_master_config_aie_core0"}, + {0x000a0238, "mem_dma_bd17_6"}, + {0x000a023c, "mem_dma_bd17_7"}, + {0x0001f118, "mm_locks_event_selection_6"}, + {0x0001f11c, "mm_locks_event_selection_7"}, + {0x0001f110, "mm_locks_event_selection_4"}, + {0x0001f114, "mm_locks_event_selection_5"}, + {0x0001f108, "mm_locks_event_selection_2"}, + {0x000a06b8, "mem_dma_s2mm_current_write_count_2"}, + {0x0001f100, "mm_locks_event_selection_0"}, + {0x0001f104, "mm_locks_event_selection_1"}, + {0x000940f0, "mem_timer_trig_event_low_value"}, + {0x0009404c, "mem_event_broadcast15"}, + {0x00094038, "mem_event_broadcast10"}, + {0x0009403c, "mem_event_broadcast11"}, + {0x00094040, "mem_event_broadcast12"}, + {0x00094044, "mem_event_broadcast13"}, + {0x0003f324, "cm_stream_switch_slave_north_3_slot1"}, + {0x0003f320, "cm_stream_switch_slave_north_3_slot0"}, + {0x0003f32c, "cm_stream_switch_slave_north_3_slot3"}, + {0x0003f328, "cm_stream_switch_slave_north_3_slot2"}, + {0x00030130, "cm_core_bmll1_part4"}, + {0x00030100, "cm_core_bmll1_part1"}, + {0x00030110, "cm_core_bmll1_part2"}, + {0x00030120, "cm_core_bmll1_part3"}, + {0x00031830, "cm_core_x0_part4"}, + {0x00031800, "cm_core_x0_part1"}, + {0x0003ff10, "cm_stream_switch_parity_status"}, + {0x00060020, "cm_tile_control"}, + {0x00031810, "cm_core_x0_part2"}, + {0x00030350, "cm_core_bmlh3_part2"}, + {0x00030360, "cm_core_bmlh3_part3"}, + {0x00037580, "cm_performance_counter0_event_value"}, + {0x00030340, "cm_core_bmlh3_part1"}, + {0x00030370, "cm_core_bmlh3_part4"}, + {0x000b02a4, "mem_stream_switch_slave_south_3_slot1"}, + {0x000b02a0, "mem_stream_switch_slave_south_3_slot0"}, + {0x000b02ac, "mem_stream_switch_slave_south_3_slot3"}, + {0x000b02a8, "mem_stream_switch_slave_south_3_slot2"}, + {0x000c0160, "mem_lock22_value"}, + {0x000340f8, "cm_timer_low"}, + {0x00094080, "mem_event_broadcast_a_block_east_set"}, + {0x00014504, "mm_event_group_watchpoint_enable"}, + {0x000c0080, "mem_lock8_value"}, + {0x000c0210, "mem_lock33_value"}, + {0x000c0024, "uc_module_axi_mm_outstanding_transactions"}, + {0x000a064c, "mem_dma_mm2s_3_start_queue"}, + {0x000092d4, "shim_dma_bd15_1"}, + {0x00000208, "npi_me_secure_reg"}, + {0x000092d0, "shim_dma_bd15_0"}, + {0x000092dc, "shim_dma_bd15_3"}, + {0x000306a0, "cm_core_bmhl6_part3"}, + {0x00030690, "cm_core_bmhl6_part2"}, + {0x00030680, "cm_core_bmhl6_part1"}, + {0x000092d8, "shim_dma_bd15_2"}, + {0x00094098, "mem_event_broadcast_b_block_south_value"}, + {0x000306b0, "cm_core_bmhl6_part4"}, + {0x000000d0, "shim_lock13_value"}, + {0x000940b8, "mem_event_broadcast_b_block_north_value"}, + {0x000092e0, "shim_dma_bd15_4"}, + {0x0003f04c, "cm_stream_switch_master_config_east0"}, + {0x0003f050, "cm_stream_switch_master_config_east1"}, + {0x0003f054, "cm_stream_switch_master_config_east2"}, + {0x0003f058, "cm_stream_switch_master_config_east3"}, + {0x00032830, "cm_core_r3"}, + {0x000092e8, "shim_dma_bd15_6"}, + {0x000a06c8, "mem_dma_s2mm_fot_count_fifo_pop_0"}, + {0x000305b0, "cm_core_bmhl5_part4"}, + {0x00030580, "cm_core_bmhl5_part1"}, + {0x00030590, "cm_core_bmhl5_part2"}, + {0x000305a0, "cm_core_bmhl5_part3"}, + {0x000b0800, "mem_stream_switch_deterministic_merge_arb0_slave0_1"}, + {0x000c0320, "mem_lock50_value"}, + {0x00034504, "shim_event_group_dma_enable"}, + {0x0003450c, "cm_event_group_core_program_flow_enable"}, + {0x00014050, "mm_event_broadcast_block_south_set"}, + {0x000303f0, "cm_core_bmhh3_part4"}, + {0x000303d0, "cm_core_bmhh3_part2"}, + {0x000303e0, "cm_core_bmhh3_part3"}, + {0x000303c0, "cm_core_bmhh3_part1"}, + {0x00031890, "cm_core_x2_part2"}, + {0x0001d1d4, "mm_dma_bd14_5"}, + {0x0001d1d0, "mm_dma_bd14_4"}, + {0x0001d1c4, "mm_dma_bd14_1"}, + {0x0001d1c0, "mm_dma_bd14_0"}, + {0x0001d1cc, "mm_dma_bd14_3"}, + {0x0001d1c8, "mm_dma_bd14_2"}, + {0x00034500, "cm_event_group_0_enable"}, + {0x0003f148, "cm_stream_switch_slave_config_north_3"}, + {0x0003f00c, "cm_stream_switch_master_config_tile_ctrl"}, + {0x0003f140, "cm_stream_switch_slave_config_north_1"}, + {0x0003f13c, "cm_stream_switch_slave_config_north_0"}, + {0x00094504, "mem_event_group_watchpoint_enable"}, + {0x000fff20, "mem_tile_control"}, + {0x000c0060, "mem_lock6_value"}, + {0x0001d144, "mm_dma_bd10_1"}, + {0x0001d140, "mm_dma_bd10_0"}, + {0x0001d14c, "mm_dma_bd10_3"}, + {0x0001d148, "mm_dma_bd10_2"}, + {0x0001d154, "mm_dma_bd10_5"}, + {0x0001d150, "mm_dma_bd10_4"}, + {0x0001d194, "mm_dma_bd12_5"}, + {0x0001d190, "mm_dma_bd12_4"}, + {0x0001d18c, "mm_dma_bd12_3"}, + {0x0001d188, "mm_dma_bd12_2"}, + {0x0001d184, "mm_dma_bd12_1"}, + {0x0001d180, "mm_dma_bd12_0"}, + {0x000b0290, "mem_stream_switch_slave_south_2_slot0"}, + {0x000a01c4, "mem_dma_bd14_1"}, + {0x000a01c0, "mem_dma_bd14_0"}, + {0x000a01cc, "mem_dma_bd14_3"}, + {0x000a01c8, "mem_dma_bd14_2"}, + {0x000a01d4, "mem_dma_bd14_5"}, + {0x000a01d0, "mem_dma_bd14_4"}, + {0x000a01dc, "mem_dma_bd14_7"}, + {0x000a01d8, "mem_dma_bd14_6"}, + {0x000b0294, "mem_stream_switch_slave_south_2_slot1"}, + {0x00034058, "shim_event_broadcast_a_block_south_value"}, + {0x00038030, "cm_error_halt_control"}, + {0x000090cc, "shim_dma_bd4_3"}, + {0x0003f2e4, "cm_stream_switch_slave_west_3_slot1"}, + {0x000b0298, "mem_stream_switch_slave_south_2_slot2"}, + {0x000a01a8, "mem_dma_bd13_2"}, + {0x000c0120, "uc_dma_pause"}, + {0x000a018c, "mem_dma_bd12_3"}, + {0x000a0188, "mem_dma_bd12_2"}, + {0x000a0184, "mem_dma_bd12_1"}, + {0x000a0180, "mem_dma_bd12_0"}, + {0x000a019c, "mem_dma_bd12_7"}, + {0x000a0198, "mem_dma_bd12_6"}, + {0x000a0194, "mem_dma_bd12_5"}, + {0x000a0190, "mem_dma_bd12_4"}, + {0x00031010, "shim_performance_control3"}, + {0x0003100C, "shim_performance_control2"}, + {0x00031008, "shim_performance_control1"}, + {0x00031000, "shim_performance_control0"}, + {0x0003ff00, "cm_stream_switch_event_port_selection_0"}, + {0x0003ff04, "cm_stream_switch_event_port_selection_1"}, + {0x000a0154, "mem_dma_bd10_5"}, + {0x000a0150, "mem_dma_bd10_4"}, + {0x000a015c, "mem_dma_bd10_7"}, + {0x00030630, "cm_core_bmll6_part4"}, + {0x00030620, "cm_core_bmll6_part3"}, + {0x00030610, "cm_core_bmll6_part2"}, + {0x00030600, "cm_core_bmll6_part1"}, + {0x000a0148, "mem_dma_bd10_2"}, + {0x000a021c, "mem_dma_bd16_7"}, + {0x000a0218, "mem_dma_bd16_6"}, + {0x000a0214, "mem_dma_bd16_5"}, + {0x000a0210, "mem_dma_bd16_4"}, + {0x000a020c, "mem_dma_bd16_3"}, + {0x000a0208, "mem_dma_bd16_2"}, + {0x000a0204, "mem_dma_bd16_1"}, + {0x000a0200, "mem_dma_bd16_0"}, + {0x0003f334, "cm_stream_switch_slave_east_0_slot1"}, + {0x0003f330, "cm_stream_switch_slave_east_0_slot0"}, + {0x0003f33c, "cm_stream_switch_slave_east_0_slot3"}, + {0x0003f338, "cm_stream_switch_slave_east_0_slot2"}, + {0x00034080, "shim_event_broadcast_a_block_east_set"}, + {0x00014200, "mm_event_status0"}, + {0x00014204, "mm_event_status1"}, + {0x00014208, "mm_event_status2"}, + {0x0001420c, "mm_event_status3"}, + {0x00032d00, "cm_core_pc"}, + {0x00034074, "shim_event_broadcast_a_block_north_clr"}, + {0x0001f040, "mm_lock4_value"}, + {0x000a0178, "mem_dma_bd11_6"}, + {0x00034018, "shim_event_broadcast_a_2"}, + {0x000a0630, "mem_dma_mm2s_0_ctrl"}, + {0x00000050, "npi_me_imr2"}, + {0x00032c70, "cm_core_p7"}, + {0x00032c60, "cm_core_p6"}, + {0x00032c50, "cm_core_p5"}, + {0x00032c40, "cm_core_p4"}, + {0x00032c30, "cm_core_p3"}, + {0x00032c20, "cm_core_p2"}, + {0x00032c10, "cm_core_p1"}, + {0x00032c00, "cm_core_p0"}, + {0x00037588, "cm_performance_counter2_event_value"}, + {0x00009314, "shim_dma_mm2s_0_task_queue"}, + {0x0003ff34, "cm_stream_switch_adaptive_clock_gate_status"}, + {0x000302e0, "cm_core_bmhh2_part3"}, + {0x000302d0, "cm_core_bmhh2_part2"}, + {0x000302c0, "cm_core_bmhh2_part1"}, + {0x000302f0, "cm_core_bmhh2_part4"}, + {0x000b0804, "mem_stream_switch_deterministic_merge_arb0_slave2_3"}, + {0x000a00b0, "mem_dma_bd5_4"}, + {0x00094000, "mem_timer_control"}, + {0x000c0420, "mem_locks_overflow_0"}, + {0x000c0424, "mem_locks_overflow_1"}, + {0x000a0270, "mem_dma_bd19_4"}, + {0x000a0274, "mem_dma_bd19_5"}, + {0x000a0278, "mem_dma_bd19_6"}, + {0x000a027c, "mem_dma_bd19_7"}, + {0x000a0260, "mem_dma_bd19_0"}, + {0x000a0264, "mem_dma_bd19_1"}, + {0x000a0268, "mem_dma_bd19_2"}, + {0x000a026c, "mem_dma_bd19_3"}, + {0x000b0128, "mem_stream_switch_slave_config_south_3"}, + {0x000b0124, "mem_stream_switch_slave_config_south_2"}, + {0x000b0120, "mem_stream_switch_slave_config_south_1"}, + {0x000b011c, "mem_stream_switch_slave_config_south_0"}, + {0x000b0130, "mem_stream_switch_slave_config_south_5"}, + {0x000b012c, "mem_stream_switch_slave_config_south_4"}, + {0x000090fc, "shim_dma_bd5_3"}, + {0x0001450c, "mm_event_group_lock_enable"}, + {0x000090f8, "shim_dma_bd5_2"}, + {0x000c0030, "mem_lock3_value"}, + {0x000c0330, "mem_lock51_value"}, + {0x000a0654, "mem_dma_mm2s_4_start_queue"}, + {0x000a0600, "mem_dma_s2mm_0_ctrl"}, + {0x00094510, "mem_event_group_stream_switch_enable"}, + {0x00030050, "cm_core_bmlh0_part2"}, + {0x000c0370, "mem_lock55_value"}, + {0x000a0694, "mem_dma_mm2s_status_5"}, + {0x000a0690, "mem_dma_mm2s_status_4"}, + {0x000a0684, "mem_dma_mm2s_status_1"}, + {0x000a0680, "mem_dma_mm2s_status_0"}, + {0x000a068c, "mem_dma_mm2s_status_3"}, + {0x000a0688, "mem_dma_mm2s_status_2"}, + {0x00094058, "mem_event_broadcast_a_block_south_value"}, + {0x000940c0, "mem_event_broadcast_b_block_east_set"}, + {0x000a0648, "mem_dma_mm2s_3_ctrl"}, + {0x00034060, "cm_event_broadcast_block_west_set"}, + {0x00009344, "shim_dma_mm2s_1_response_fifo_parity_error_injection"}, + {0x000b0f38, "mem_stream_switch_adaptive_clock_gate_abort_period"}, + {0x00034084, "cm_event_broadcast_block_east_clr"}, + {0x0009108c, "mem_performance_counter3_event_value"}, + {0x00000020, "shim_lock2_value"}, + {0x0001102c, "mm_performance_counter3"}, + {0x00011028, "mm_performance_counter2"}, + {0x00011024, "mm_performance_counter1"}, + {0x00011020, "mm_performance_counter0"}, + {0x000a065c, "mem_dma_mm2s_5_start_queue"}, + {0x00014068, "mm_event_broadcast_block_west_value"}, + {0x000b027c, "mem_stream_switch_slave_south_0_slot3"}, + {0x000b0270, "mem_stream_switch_slave_south_0_slot0"}, + {0x000b0274, "mem_stream_switch_slave_south_0_slot1"}, + {0x00001000, "shim_interrupt_controller_2nd_level_mask"}, + {0x00038000, "cm_core_control"}, + {0x000c0010, "mem_lock1_value"}, + {0x000a0508, "mem_dma_bd40_2"}, + {0x000a050c, "mem_dma_bd40_3"}, + {0x000a0500, "mem_dma_bd40_0"}, + {0x00032ad0, "cm_core_dn5"}, + {0x000a0518, "mem_dma_bd40_6"}, + {0x000a051c, "mem_dma_bd40_7"}, + {0x00032a80, "cm_core_dn0"}, + {0x000a0514, "mem_dma_bd40_5"}, + {0x000a0550, "mem_dma_bd42_4"}, + {0x000a0554, "mem_dma_bd42_5"}, + {0x000a0558, "mem_dma_bd42_6"}, + {0x000a055c, "mem_dma_bd42_7"}, + {0x000a0540, "mem_dma_bd42_0"}, + {0x000a0544, "mem_dma_bd42_1"}, + {0x000a0548, "mem_dma_bd42_2"}, + {0x000a054c, "mem_dma_bd42_3"}, + {0x000a0598, "mem_dma_bd44_6"}, + {0x000a059c, "mem_dma_bd44_7"}, + {0x000a0590, "mem_dma_bd44_4"}, + {0x000a0594, "mem_dma_bd44_5"}, + {0x000a0588, "mem_dma_bd44_2"}, + {0x000a058c, "mem_dma_bd44_3"}, + {0x000a0580, "mem_dma_bd44_0"}, + {0x000a0584, "mem_dma_bd44_1"}, + {0x0003f810, "cm_stream_switch_deterministic_merge_arb1_slave0_1"}, + {0x000c0100, "uc_dma_dm2mm_status"}, + {0x00094088, "mem_event_broadcast_a_block_east_value"}, + {0x00034054, "cm_event_broadcast_block_south_clr"}, + {0x0003f814, "cm_stream_switch_deterministic_merge_arb1_slave2_3"}, + {0x00000070, "shim_lock7_value"}, + {0x000b02b8, "mem_stream_switch_slave_south_4_slot2"}, + {0x000b02bc, "mem_stream_switch_slave_south_4_slot3"}, + {0x000b02b0, "mem_stream_switch_slave_south_4_slot0"}, + {0x000a0124, "mem_dma_bd9_1"}, + {0x0003420c, "shim_event_status3"}, + {0x00034208, "shim_event_status2"}, + {0x00034204, "shim_event_status1"}, + {0x00034200, "shim_event_status0"}, + {0x000304f0, "cm_core_bmhh4_part4"}, + {0x000304c0, "cm_core_bmhh4_part1"}, + {0x000304e0, "cm_core_bmhh4_part3"}, + {0x000304d0, "cm_core_bmhh4_part2"}, + {0x0003f228, "cm_stream_switch_slave_dma_1_slot2"}, + {0x000a06e8, "mem_dma_mm2s_2_constant_pad_value"}, + {0x000a0604, "mem_dma_s2mm_0_start_queue"}, + {0x0003f22c, "cm_stream_switch_slave_dma_1_slot3"}, + {0x0003f220, "cm_stream_switch_slave_dma_1_slot0"}, + {0x0001df24, "mm_dma_s2mm_fot_count_fifo_pop_1"}, + {0x0001df20, "mm_dma_s2mm_fot_count_fifo_pop_0"}, + {0x0003f224, "cm_stream_switch_slave_dma_1_slot1"}, + {0x000940d8, "mem_trace_status"}, + {0x0003f020, "cm_stream_switch_master_config_south3"}, + {0x0003f01c, "cm_stream_switch_master_config_south2"}, + {0x0003f018, "cm_stream_switch_master_config_south1"}, + {0x0003f014, "cm_stream_switch_master_config_south0"}, + {0x00031084, "shim_performance_counter1_event_value"}, + {0x00000010, "shim_lock1_value"}, + {0x000a06ec, "mem_dma_mm2s_3_constant_pad_value"}, + {0x000340e4, "shim_trace_event1"}, + {0x000340e0, "shim_trace_event0"}, + {0x0000010c, "npi_me_pll_status"}, + {0x000a040c, "mem_dma_bd32_3"}, + {0x000c0008, "uc_core_interrupt_status"}, + {0x000c042c, "mem_locks_underflow_1"}, + {0x000c0428, "mem_locks_underflow_0"}, + {0x000b028c, "mem_stream_switch_slave_south_1_slot3"}, + {0x000c0140, "mem_lock20_value"}, + {0x000b0288, "mem_stream_switch_slave_south_1_slot2"}, + {0x000b0284, "mem_stream_switch_slave_south_1_slot1"}, + {0x00034078, "cm_event_broadcast_block_north_value"}, + {0x000b0280, "mem_stream_switch_slave_south_1_slot0"}, + {0x00014038, "mm_event_broadcast10"}, + {0x0001403c, "mm_event_broadcast11"}, + {0x00014040, "mm_event_broadcast12"}, + {0x00014044, "mm_event_broadcast13"}, + {0x00014048, "mm_event_broadcast14"}, + {0x0001404c, "mm_event_broadcast15"}, + {0x0003f160, "cm_stream_switch_slave_config_mem_trace"}, + {0x000c0418, "mem_locks_event_selection_6"}, + {0x000c041c, "mem_locks_event_selection_7"}, + {0x000c0410, "mem_locks_event_selection_4"}, + {0x000c0414, "mem_locks_event_selection_5"}, + {0x000c0408, "mem_locks_event_selection_2"}, + {0x000c040c, "mem_locks_event_selection_3"}, + {0x000c0400, "mem_locks_event_selection_0"}, + {0x000c0404, "mem_locks_event_selection_1"}, + {0x00094060, "mem_event_broadcast_a_block_west_set"}, + {0x000318d0, "cm_core_x3_part2"}, + {0x000318e0, "cm_core_x3_part3"}, + {0x000318c0, "cm_core_x3_part1"}, + {0x0003f2e0, "cm_stream_switch_slave_west_3_slot0"}, + {0x000318f0, "cm_core_x3_part4"}, + {0x000c0340, "mem_lock52_value"}, + {0x000c01d0, "mem_lock29_value"}, + {0x0000915c, "shim_dma_bd7_3"}, + {0x000c03e0, "mem_lock62_value"}, + {0x00009154, "shim_dma_bd7_1"}, + {0x00032d80, "cm_core_cr1"}, + {0x000c01b0, "mem_lock27_value"}, + {0x00032da0, "cm_core_cr3"}, + {0x00032d90, "cm_core_cr2"}, + {0x0000916c, "shim_dma_bd7_7"}, + {0x00009168, "shim_dma_bd7_6"}, + {0x0000931c, "shim_dma_mm2s_1_task_queue"}, + {0x00009164, "shim_dma_bd7_5"}, + {0x00009160, "shim_dma_bd7_4"}, + {0x0003451c, "cm_event_group_broadcast_enable"}, + {0x000a0650, "mem_dma_mm2s_4_ctrl"}, + {0x00094050, "mem_event_broadcast_a_block_south_set"}, + {0x00011080, "mm_performance_counter0_event_value"}, + {0x000c0020, "uc_module_aximm_offset"}, + {0x00038038, "cm_core_processor_bus"}, + {0x0001d08c, "mm_dma_bd4_3"}, + {0x0001d088, "mm_dma_bd4_2"}, + {0x0001d084, "mm_dma_bd4_1"}, + {0x0001d080, "mm_dma_bd4_0"}, + {0x0001d094, "mm_dma_bd4_5"}, + {0x0001d090, "mm_dma_bd4_4"}, + {0x00014408, "mm_edge_detection_event_control"}, + {0x00032dc0, "cm_core_sr1"}, + {0x00032dd0, "cm_core_sr2"}, + {0x0001d044, "mm_dma_bd2_1"}, + {0x0001d040, "mm_dma_bd2_0"}, + {0x0001d04c, "mm_dma_bd2_3"}, + {0x0001d048, "mm_dma_bd2_2"}, + {0x0001d054, "mm_dma_bd2_5"}, + {0x000a04d4, "mem_dma_bd38_5"}, + {0x00009184, "shim_dma_bd8_1"}, + {0x000b0010, "uc_mdm_dbg_ctrl_status"}, + {0x0001d014, "mm_dma_bd0_5"}, + {0x0001d010, "mm_dma_bd0_4"}, + {0x0001d00c, "mm_dma_bd0_3"}, + {0x0001d008, "mm_dma_bd0_2"}, + {0x0001d004, "mm_dma_bd0_1"}, + {0x0001d000, "mm_dma_bd0_0"}, + {0x00014030, "mm_event_broadcast8"}, + {0x00014034, "mm_event_broadcast9"}, + {0x0001d0d4, "mm_dma_bd6_5"}, + {0x0001d0d0, "mm_dma_bd6_4"}, + {0x00014020, "mm_event_broadcast4"}, + {0x00014024, "mm_event_broadcast5"}, + {0x0001d0c4, "mm_dma_bd6_1"}, + {0x0001d0c0, "mm_dma_bd6_0"}, + {0x0001d0cc, "mm_dma_bd6_3"}, + {0x0001d0c8, "mm_dma_bd6_2"}, + {0x000a05e4, "mem_dma_bd47_1"}, + {0x000a05e0, "mem_dma_bd47_0"}, + {0x000a05ec, "mem_dma_bd47_3"}, + {0x000a05e8, "mem_dma_bd47_2"}, + {0x000a05f4, "mem_dma_bd47_5"}, + {0x000a05f0, "mem_dma_bd47_4"}, + {0x000a05fc, "mem_dma_bd47_7"}, + {0x000a05f8, "mem_dma_bd47_6"}, + {0x00032d70, "cm_core_lci"}, + {0x0001f010, "mm_lock1_value"}, + {0x000b0814, "mem_stream_switch_deterministic_merge_arb1_slave2_3"}, + {0x00037500, "cm_performance_control0"}, + {0x00037504, "cm_performance_control1"}, + {0x00037508, "cm_performance_control2"}, + {0x000b0810, "mem_stream_switch_deterministic_merge_arb1_slave0_1"}, + {0x00034044, "shim_event_broadcast_a_13"}, + {0x00034040, "shim_event_broadcast_a_12"}, + {0x0003403c, "shim_event_broadcast_a_11"}, + {0x00034038, "shim_event_broadcast_a_10"}, + {0x0001de00, "mm_dma_s2mm_0_ctrl"}, + {0x00034048, "shim_event_broadcast_a_14"}, + {0x00032430, "cm_core_ldfifol0_part4"}, + {0x00032400, "cm_core_ldfifol0_part1"}, + {0x00032420, "cm_core_ldfifol0_part3"}, + {0x00032410, "cm_core_ldfifol0_part2"}, + {0x000a0618, "mem_dma_s2mm_3_ctrl"}, + {0x00094054, "mem_event_broadcast_a_block_south_clr"}, + {0x00030430, "cm_core_bmll4_part4"}, + {0x00030400, "cm_core_bmll4_part1"}, + {0x00030420, "cm_core_bmll4_part3"}, + {0x00030410, "cm_core_bmll4_part2"}, + {0x000300c0, "cm_core_bmhh0_part1"}, + {0x000300e0, "cm_core_bmhh0_part3"}, + {0x000300d0, "cm_core_bmhh0_part2"}, + {0x000300f0, "cm_core_bmhh0_part4"}, + {0x00038018, "cm_debug_control2"}, + {0x00032620, "cm_core_eg2"}, + {0x00032630, "cm_core_eg3"}, + {0x00030000, "cm_core_bmll0_part1"}, + {0x00030020, "cm_core_bmll0_part3"}, + {0x00030010, "cm_core_bmll0_part2"}, + {0x00030030, "cm_core_bmll0_part4"}, + {0x00014078, "mm_event_broadcast_block_north_value"}, + {0x00032680, "cm_core_eg8"}, + {0x00014080, "mm_event_broadcast_block_east_set"}, + {0x000b0278, "mem_stream_switch_slave_south_0_slot2"}, + {0x000a0094, "mem_dma_bd4_5"}, + {0x000c0380, "mem_lock56_value"}, + {0x00032690, "cm_core_eg9"}, + {0x0001f060, "mm_lock6_value"}, + {0x0001d130, "mm_dma_bd9_4"}, + {0x000a0080, "mem_dma_bd4_0"}, + {0x0001d128, "mm_dma_bd9_2"}, + {0x0001d12c, "mm_dma_bd9_3"}, + {0x0001d120, "mm_dma_bd9_0"}, + {0x0001d124, "mm_dma_bd9_1"}, + {0x000b010c, "mem_stream_switch_slave_config_dma_3"}, + {0x000c02d0, "mem_lock45_value"}, + {0x000329f0, "cm_core_r31"}, + {0x000329e0, "cm_core_r30"}, + {0x000a02a4, "mem_dma_bd21_1"}, + {0x0003ff00, "shim_stream_switch_event_port_selection_0"}, + {0x00030180, "cm_core_bmhl1_part1"}, + {0x0003f2c8, "cm_stream_switch_slave_west_1_slot2"}, + {0x0009450c, "mem_event_group_lock_enable"}, + {0x0003f2c0, "cm_stream_switch_slave_west_1_slot0"}, + {0x0003f2c4, "cm_stream_switch_slave_west_1_slot1"}, + {0x00030190, "cm_core_bmhl1_part2"}, + {0x0003f110, "cm_stream_switch_slave_config_fifo_0"}, + {0x000c0290, "mem_lock41_value"}, + {0x00034000, "cm_timer_control"}, + {0x0001f090, "mm_lock9_value"}, + {0x00030710, "cm_core_bmll7_part2"}, + {0x00030720, "cm_core_bmll7_part3"}, + {0x00030700, "cm_core_bmll7_part1"}, + {0x00030730, "cm_core_bmll7_part4"}, + {0x00036060, "cm_accumulator_control"}, + {0x000a06e0, "mem_dma_mm2s_0_constant_pad_value"}, + {0x000319d0, "cm_core_x7_part2"}, + {0x0003f250, "cm_stream_switch_slave_south_0_slot0"}, + {0x0003f254, "cm_stream_switch_slave_south_0_slot1"}, + {0x0003f258, "cm_stream_switch_slave_south_0_slot2"}, + {0x0003f25c, "cm_stream_switch_slave_south_0_slot3"}, + {0x000000c0, "shim_lock12_value"}, + {0x000c03b0, "mem_lock59_value"}, + {0x00014404, "mm_combo_event_control"}, + {0x0001f0a0, "mm_lock10_value"}, + {0x000b54c0, "uc_mdm_pcsr"}, + {0x0003f21c, "cm_stream_switch_slave_dma_0_slot3"}, + {0x0003f218, "cm_stream_switch_slave_dma_0_slot2"}, + {0x0003f214, "cm_stream_switch_slave_dma_0_slot1"}, + {0x0003f210, "cm_stream_switch_slave_dma_0_slot0"}, + {0x0003f30c, "cm_stream_switch_slave_north_1_slot3"}, + {0x00034208, "cm_event_status2"}, + {0x0003420c, "cm_event_status3"}, + {0x00034200, "cm_event_status0"}, + {0x00034204, "cm_event_status1"}, + {0x00009330, "shim_dma_s2mm_current_write_count_0"}, + {0x00009334, "shim_dma_s2mm_current_write_count_1"}, + {0x00034048, "cm_event_broadcast14"}, + {0x0003404c, "cm_event_broadcast15"}, + {0x00034040, "cm_event_broadcast12"}, + {0x00034044, "cm_event_broadcast13"}, + {0x00034038, "cm_event_broadcast10"}, + {0x0003403c, "cm_event_broadcast11"}, + {0x000301f0, "cm_core_bmhh1_part4"}, + {0x000301c0, "cm_core_bmhh1_part1"}, + {0x000301d0, "cm_core_bmhh1_part2"}, + {0x000301e0, "cm_core_bmhh1_part3"}, + {0x00034088, "shim_event_broadcast_a_block_east_value"}, + {0x0001de1c, "mm_dma_mm2s_1_start_queue"}, + {0x000a00e0, "mem_dma_bd7_0"}, + {0x000a00e4, "mem_dma_bd7_1"}, + {0x000a00e8, "mem_dma_bd7_2"}, + {0x000a00ec, "mem_dma_bd7_3"}, + {0x000a00f0, "mem_dma_bd7_4"}, + {0x000a00f4, "mem_dma_bd7_5"}, + {0x000a00f8, "mem_dma_bd7_6"}, + {0x000a00fc, "mem_dma_bd7_7"}, + {0x000a044c, "mem_dma_bd34_3"}, + {0x000a0448, "mem_dma_bd34_2"}, + {0x000a0444, "mem_dma_bd34_1"}, + {0x000a0440, "mem_dma_bd34_0"}, + {0x000a045c, "mem_dma_bd34_7"}, + {0x000a0458, "mem_dma_bd34_6"}, + {0x000a0454, "mem_dma_bd34_5"}, + {0x000a0450, "mem_dma_bd34_4"}, + {0x000a00b8, "mem_dma_bd5_6"}, + {0x000a00bc, "mem_dma_bd5_7"}, + {0x00094064, "mem_event_broadcast_a_block_west_clr"}, + {0x000a00b4, "mem_dma_bd5_5"}, + {0x000a00a8, "mem_dma_bd5_2"}, + {0x000a00ac, "mem_dma_bd5_3"}, + {0x000a00a0, "mem_dma_bd5_0"}, + {0x000a00a4, "mem_dma_bd5_1"}, + {0x000a0494, "mem_dma_bd36_5"}, + {0x000a0490, "mem_dma_bd36_4"}, + {0x000a049c, "mem_dma_bd36_7"}, + {0x000a0498, "mem_dma_bd36_6"}, + {0x000a0484, "mem_dma_bd36_1"}, + {0x000a0480, "mem_dma_bd36_0"}, + {0x000a048c, "mem_dma_bd36_3"}, + {0x000a0488, "mem_dma_bd36_2"}, + {0x000a03dc, "mem_dma_bd30_7"}, + {0x000a03d8, "mem_dma_bd30_6"}, + {0x000a03d4, "mem_dma_bd30_5"}, + {0x000a03d0, "mem_dma_bd30_4"}, + {0x000a03cc, "mem_dma_bd30_3"}, + {0x000a03c8, "mem_dma_bd30_2"}, + {0x000a03c4, "mem_dma_bd30_1"}, + {0x000a03c0, "mem_dma_bd30_0"}, + {0x000329a0, "cm_core_r26"}, + {0x000b029c, "mem_stream_switch_slave_south_2_slot3"}, + {0x00009158, "shim_dma_bd7_2"}, + {0x00032ae0, "cm_core_dn6"}, + {0x00032af0, "cm_core_dn7"}, + {0x00032ac0, "cm_core_dn4"}, + {0x00014008, "mm_event_generate"}, + {0x00037584, "cm_performance_counter1_event_value"}, + {0x000c00f0, "mem_lock15_value"}, + {0x00032aa0, "cm_core_dn2"}, + {0x00094100, "mem_watchpoint0"}, + {0x00032ab0, "cm_core_dn3"}, + {0x000a0510, "mem_dma_bd40_4"}, + {0x000a0128, "mem_dma_bd9_2"}, + {0x000a012c, "mem_dma_bd9_3"}, + {0x000a0120, "mem_dma_bd9_0"}, + {0x00032a90, "cm_core_dn1"}, + {0x000a0138, "mem_dma_bd9_6"}, + {0x000a013c, "mem_dma_bd9_7"}, + {0x000a0130, "mem_dma_bd9_4"}, + {0x000a0134, "mem_dma_bd9_5"}, + {0x000c0170, "mem_lock23_value"}, + {0x000a000c, "mem_dma_bd0_3"}, + {0x000a0008, "mem_dma_bd0_2"}, + {0x000a0004, "mem_dma_bd0_1"}, + {0x000a0000, "mem_dma_bd0_0"}, + {0x000a001c, "mem_dma_bd0_7"}, + {0x000a0018, "mem_dma_bd0_6"}, + {0x000a0014, "mem_dma_bd0_5"}, + {0x000a0010, "mem_dma_bd0_4"}, + {0x000b0f34, "mem_stream_switch_adaptive_clock_gate_status"}, + {0x00034020, "cm_event_broadcast4"}, + {0x00034024, "cm_event_broadcast5"}, + {0x00034028, "cm_event_broadcast6"}, + {0x0003402c, "cm_event_broadcast7"}, + {0x0003ff04, "shim_stream_switch_event_port_selection_1"}, + {0x000000a0, "shim_lock10_value"}, + {0x0000003c, "npi_me_ier0"}, + {0x00000048, "npi_me_ier1"}, + {0x00000054, "npi_me_ier2"}, + {0x00000060, "npi_me_ier3"}, + {0x000a009c, "mem_dma_bd4_7"}, + {0x000a0098, "mem_dma_bd4_6"}, + {0x00034510, "cm_event_group_errors0_enable"}, + {0x000a0090, "mem_dma_bd4_4"}, + {0x000a008c, "mem_dma_bd4_3"}, + {0x000a0088, "mem_dma_bd4_2"}, + {0x000a0084, "mem_dma_bd4_1"}, + {0x000305c0, "cm_core_bmhh5_part1"}, + {0x000a0054, "mem_dma_bd2_5"}, + {0x000a0050, "mem_dma_bd2_4"}, + {0x000a005c, "mem_dma_bd2_7"}, + {0x000a0058, "mem_dma_bd2_6"}, + {0x000a0044, "mem_dma_bd2_1"}, + {0x000a0040, "mem_dma_bd2_0"}, + {0x000a004c, "mem_dma_bd2_3"}, + {0x000a0048, "mem_dma_bd2_2"}, + {0x000a06e4, "mem_dma_mm2s_1_constant_pad_value"}, + {0x0003f10c, "cm_stream_switch_slave_config_tile_ctrl"}, + {0x000329c0, "cm_core_r28"}, + {0x000329d0, "cm_core_r29"}, + {0x00032980, "cm_core_r24"}, + {0x00032990, "cm_core_r25"}, + {0x0003f804, "cm_stream_switch_deterministic_merge_arb0_slave2_3"}, + {0x000329b0, "cm_core_r27"}, + {0x00032940, "cm_core_r20"}, + {0x00032950, "cm_core_r21"}, + {0x00032960, "cm_core_r22"}, + {0x00032970, "cm_core_r23"}, + {0x00094108, "mem_watchpoint2"}, + {0x0009410c, "mem_watchpoint3"}, + {0x00034050, "cm_event_broadcast_block_south_set"}, + {0x00094104, "mem_watchpoint1"}, + {0x0001de14, "mm_dma_mm2s_0_start_queue"}, + {0x0003f800, "cm_stream_switch_deterministic_merge_arb0_slave0_1"}, + {0x00014058, "mm_event_broadcast_block_south_value"}, + {0x00000000, "uc_base_address"}, + {0x000c0220, "mem_lock34_value"}, + {0x00094078, "mem_event_broadcast_a_block_north_value"}, + {0x0003f010, "cm_stream_switch_master_config_fifo0"}, + {0x00094094, "mem_event_broadcast_b_block_south_clr"}, + {0x000340fc, "cm_timer_high"}, + {0x000c0240, "mem_lock36_value"}, + {0x00009150, "shim_dma_bd7_0"}, + {0x00031970, "cm_core_x5_part4"}, + {0x00031940, "cm_core_x5_part1"}, + {0x00031950, "cm_core_x5_part2"}, + {0x00031960, "cm_core_x5_part3"}, + {0x000c0004, "uc_core_control"}, + {0x00016010, "mm_memory_control"}, + {0x00038034, "cm_error_halt_event"}, + {0x000a04f8, "mem_dma_bd39_6"}, + {0x00014400, "mm_combo_event_inputs"}, + {0x000a04f0, "mem_dma_bd39_4"}, + {0x000a04f4, "mem_dma_bd39_5"}, + {0x000a04e8, "mem_dma_bd39_2"}, + {0x000a04ec, "mem_dma_bd39_3"}, + {0x000a04e0, "mem_dma_bd39_0"}, + {0x000a04e4, "mem_dma_bd39_1"}, + {0x00091034, "mem_performance_counter5"}, + {0x00091030, "mem_performance_counter4"}, + {0x0009102c, "mem_performance_counter3"}, + {0x00091028, "mem_performance_counter2"}, + {0x00091024, "mem_performance_counter1"}, + {0x00091020, "mem_performance_counter0"}, + {0x000c01a0, "mem_lock26_value"}, + {0x000c01f0, "mem_lock31_value"}, + {0x00030390, "cm_core_bmhl3_part2"}, + {0x000303a0, "cm_core_bmhl3_part3"}, + {0x000c0150, "mem_lock21_value"}, + {0x00030380, "cm_core_bmhl3_part1"}, + {0x000303b0, "cm_core_bmhl3_part4"}, + {0x0003f35c, "cm_stream_switch_slave_east_2_slot3"}, + {0x0003f358, "cm_stream_switch_slave_east_2_slot2"}, + {0x0003f354, "cm_stream_switch_slave_east_2_slot1"}, + {0x0003f350, "cm_stream_switch_slave_east_2_slot0"}, + {0x000a0420, "mem_dma_bd33_0"}, + {0x000a0424, "mem_dma_bd33_1"}, + {0x000a0428, "mem_dma_bd33_2"}, + {0x000a042c, "mem_dma_bd33_3"}, + {0x000a0430, "mem_dma_bd33_4"}, + {0x000a0434, "mem_dma_bd33_5"}, + {0x000a0438, "mem_dma_bd33_6"}, + {0x000a043c, "mem_dma_bd33_7"}, + {0x000b0f30, "mem_tile_control_packet_handler_status"}, + {0x0003f264, "cm_stream_switch_slave_south_1_slot1"}, + {0x0003f260, "cm_stream_switch_slave_south_1_slot0"}, + {0x0003f26c, "cm_stream_switch_slave_south_1_slot3"}, + {0x0003f268, "cm_stream_switch_slave_south_1_slot2"}, + {0x00030140, "cm_core_bmlh1_part1"}, + {0x00030150, "cm_core_bmlh1_part2"}, + {0x00030160, "cm_core_bmlh1_part3"}, + {0x00030170, "cm_core_bmlh1_part4"}, + {0x00034400, "cm_combo_event_inputs"}, + {0x000a06c4, "mem_dma_s2mm_current_write_count_5"}, + {0x000a06c0, "mem_dma_s2mm_current_write_count_4"}, + {0x000c0110, "mem_lock17_value"}, + {0x000a06bc, "mem_dma_s2mm_current_write_count_3"}, + {0x0003f15c, "cm_stream_switch_slave_config_aie_trace"}, + {0x0001f10c, "mm_locks_event_selection_3"}, + {0x10, "shim_lock_step_size"}, + {0x000a06b4, "mem_dma_s2mm_current_write_count_1"}, + {0x000a06b0, "mem_dma_s2mm_current_write_count_0"}, + {0x00034070, "cm_event_broadcast_block_north_set"}, + {0x00034008, "shim_event_generate"}, + {0x000c0030, "uc_memory_zeroization"}, + {0x00032bd0, "cm_core_dc5"}, + {0x00032bc0, "cm_core_dc4"}, + {0x00030770, "cm_core_bmlh7_part4"}, + {0x00032be0, "cm_core_dc6"}, + {0x00032b90, "cm_core_dc1"}, + {0x00030760, "cm_core_bmlh7_part3"}, + {0x00032bb0, "cm_core_dc3"}, + {0x00032ba0, "cm_core_dc2"}, + {0x0000c000, "shim_lock_request"}, + {0x000c0100, "mem_lock16_value"}, + {0x00032440, "cm_core_ldfifoh0_part1"}, + {0x00032460, "cm_core_ldfifoh0_part3"}, + {0x00032450, "cm_core_ldfifoh0_part2"}, + {0x00032470, "cm_core_ldfifoh0_part4"}, + {0x000b0818, "mem_stream_switch_deterministic_merge_arb1_ctrl"}, + {0x000324f0, "cm_core_ldfifoh1_part4"}, + {0x000140fc, "mm_timer_high"}, + {0x000324c0, "cm_core_ldfifoh1_part1"}, + {0x000324d0, "cm_core_ldfifoh1_part2"}, + {0x000324e0, "cm_core_ldfifoh1_part3"}, + {0x000c0360, "mem_lock54_value"}, + {0x8, "shim_dma_s2mm_step_size"}, + {0x000b0014, "uc_mdm_dbg_data"}, + {0x00014500, "mm_event_group_0_enable"}, + {0x0001df1c, "mm_dma_s2mm_current_write_count_1"}, + {0x0001df18, "mm_dma_s2mm_current_write_count_0"}, + {0x000a0628, "mem_dma_s2mm_5_ctrl"}, + {0x000c0310, "mem_lock49_value"}, + {0x00009304, "shim_dma_s2mm_0_task_queue"}, + {0x000a047c, "mem_dma_bd35_7"}, + {0x000940c4, "mem_event_broadcast_b_block_east_clr"}, + {0x000340e0, "cm_trace_event0"}, + {0x000340e4, "cm_trace_event1"}, + {0x00000044, "npi_me_imr1"}, + {0x00032520, "cm_core_stfifol_part3"}, + {0x00031a50, "cm_core_x9_part2"}, + {0x00031a60, "cm_core_x9_part3"}, + {0x00031a70, "cm_core_x9_part4"}, + {0x000a04b4, "mem_dma_bd37_5"}, + {0x000c0050, "mem_lock5_value"}, + {0x00032500, "cm_core_stfifol_part1"}, + {0x00094048, "mem_event_broadcast14"}, + {0x000b0238, "mem_stream_switch_slave_dma_3_slot2"}, + {0x000b023c, "mem_stream_switch_slave_dma_3_slot3"}, + {0x000b0230, "mem_stream_switch_slave_dma_3_slot0"}, + {0x000b0234, "mem_stream_switch_slave_dma_3_slot1"}, + {0x00031900, "cm_core_x4_part1"}, + {0x00031920, "cm_core_x4_part3"}, + {0x00031910, "cm_core_x4_part2"}, + {0x00031930, "cm_core_x4_part4"}, + {0x000a04ac, "mem_dma_bd37_3"}, + {0x000c03d0, "mem_lock61_value"}, + {0x000328b0, "cm_core_r11"}, + {0x000328a0, "cm_core_r10"}, + {0x000328d0, "cm_core_r13"}, + {0x000328c0, "cm_core_r12"}, + {0x000328f0, "cm_core_r15"}, + {0x000328e0, "cm_core_r14"}, + {0x00032910, "cm_core_r17"}, + {0x00032900, "cm_core_r16"}, + {0x00032930, "cm_core_r19"}, + {0x00032920, "cm_core_r18"}, + {0x0003f2f8, "cm_stream_switch_slave_north_0_slot2"}, + {0x0003f2fc, "cm_stream_switch_slave_north_0_slot3"}, + {0x0003f2f0, "cm_stream_switch_slave_north_0_slot0"}, + {0x0003f2f4, "cm_stream_switch_slave_north_0_slot1"}, + {0x000306f0, "cm_core_bmhh6_part4"}, + {0x000306e0, "cm_core_bmhh6_part3"}, + {0x000306d0, "cm_core_bmhh6_part2"}, + {0x000306c0, "cm_core_bmhh6_part1"}, + {0x000092c0, "shim_dma_bd14_8"}, + {0x000092a0, "shim_dma_bd14_0"}, + {0x0003f818, "cm_stream_switch_deterministic_merge_arb1_ctrl"}, + {0x000092a8, "shim_dma_bd14_2"}, + {0x000092ac, "shim_dma_bd14_3"}, + {0x000092b0, "shim_dma_bd14_4"}, + {0x000a06f0, "mem_dma_mm2s_4_constant_pad_value"}, + {0x000092b8, "shim_dma_bd14_6"}, + {0x000092bc, "shim_dma_bd14_7"}, + {0x000b0314, "mem_stream_switch_slave_trace_slot1"}, + {0x000b0310, "mem_stream_switch_slave_trace_slot0"}, + {0x000b031c, "mem_stream_switch_slave_trace_slot3"}, + {0x000b0318, "mem_stream_switch_slave_trace_slot2"}, + {0x000091fc, "shim_dma_bd10_7"}, + {0x000c0120, "mem_lock18_value"}, + {0x000a04fc, "mem_dma_bd39_7"}, + {0x00094008, "mem_event_generate"}, + {0x00000108, "shim_locks_event_selection_2"}, + {0x0001f0f0, "mm_lock15_value"}, + {0x00030270, "cm_core_bmlh2_part4"}, + {0x00030260, "cm_core_bmlh2_part3"}, + {0x00030250, "cm_core_bmlh2_part2"}, + {0x00030240, "cm_core_bmlh2_part1"}, + {0x00031820, "cm_core_x0_part3"}, + {0x0003f004, "cm_stream_switch_master_config_dma0"}, + {0x0003f008, "cm_stream_switch_master_config_dma1"}, + {0x000090e0, "shim_dma_bd4_8"}, + {0x000090d0, "shim_dma_bd4_4"}, + {0x000090d4, "shim_dma_bd4_5"}, + {0x000090d8, "shim_dma_bd4_6"}, + {0x000090dc, "shim_dma_bd4_7"}, + {0x000090c0, "shim_dma_bd4_0"}, + {0x000090c4, "shim_dma_bd4_1"}, + {0x000090c8, "shim_dma_bd4_2"}, + {0x000140f4, "mm_timer_trig_event_high_value"}, + {0x00009080, "shim_dma_bd2_8"}, + {0x00009078, "shim_dma_bd2_6"}, + {0x0000907c, "shim_dma_bd2_7"}, + {0x00009070, "shim_dma_bd2_4"}, + {0x00009074, "shim_dma_bd2_5"}, + {0x00009068, "shim_dma_bd2_2"}, + {0x0000906c, "shim_dma_bd2_3"}, + {0x00009060, "shim_dma_bd2_0"}, + {0x000b0118, "mem_stream_switch_slave_config_tile_ctrl"}, + {0x000c0034, "uc_memory_privileged"}, + {0x00000060, "shim_lock6_value"}, + {0x0003f384, "cm_stream_switch_slave_mem_trace_slot1"}, + {0x0003f380, "cm_stream_switch_slave_mem_trace_slot0"}, + {0x0003f38c, "cm_stream_switch_slave_mem_trace_slot3"}, + {0x0003f388, "cm_stream_switch_slave_mem_trace_slot2"}, + {0x000a0644, "mem_dma_mm2s_2_start_queue"}, + {0x0003f114, "cm_stream_switch_slave_config_south_0"}, + {0x0003f120, "cm_stream_switch_slave_config_south_3"}, + {0x0003f11c, "cm_stream_switch_slave_config_south_2"}, + {0x000a0348, "mem_dma_bd26_2"}, + {0x000a034c, "mem_dma_bd26_3"}, + {0x000a0340, "mem_dma_bd26_0"}, + {0x000a0344, "mem_dma_bd26_1"}, + {0x000a0358, "mem_dma_bd26_6"}, + {0x000a035c, "mem_dma_bd26_7"}, + {0x000a0350, "mem_dma_bd26_4"}, + {0x000a0354, "mem_dma_bd26_5"}, + {0x000a0310, "mem_dma_bd24_4"}, + {0x000a0314, "mem_dma_bd24_5"}, + {0x000a0318, "mem_dma_bd24_6"}, + {0x000a031c, "mem_dma_bd24_7"}, + {0x000a0300, "mem_dma_bd24_0"}, + {0x000a0304, "mem_dma_bd24_1"}, + {0x000a0308, "mem_dma_bd24_2"}, + {0x000a030c, "mem_dma_bd24_3"}, + {0x00009140, "shim_dma_bd6_8"}, + {0x000a02d8, "mem_dma_bd22_6"}, + {0x000a02dc, "mem_dma_bd22_7"}, + {0x000a02d0, "mem_dma_bd22_4"}, + {0x000a02d4, "mem_dma_bd22_5"}, + {0x000a02c8, "mem_dma_bd22_2"}, + {0x000a02cc, "mem_dma_bd22_3"}, + {0x000a02c0, "mem_dma_bd22_0"}, + {0x000a02c4, "mem_dma_bd22_1"}, + {0x0001f0e0, "mm_lock14_value"}, + {0x00032a40, "cm_core_m4"}, + {0x00032a50, "cm_core_m5"}, + {0x00032a60, "cm_core_m6"}, + {0x00032a70, "cm_core_m7"}, + {0x00032a00, "cm_core_m0"}, + {0x00032a10, "cm_core_m1"}, + {0x00032a20, "cm_core_m2"}, + {0x00032a30, "cm_core_m3"}, + {0x0000927c, "shim_dma_bd13_3"}, + {0x00009278, "shim_dma_bd13_2"}, + {0x00009274, "shim_dma_bd13_1"}, + {0x00009270, "shim_dma_bd13_0"}, + {0x0000928c, "shim_dma_bd13_7"}, + {0x00009288, "shim_dma_bd13_6"}, + {0x000c03a0, "mem_lock58_value"}, + {0x00009280, "shim_dma_bd13_4"}, + {0x000a060c, "mem_dma_s2mm_1_start_queue"}, + {0x000307b0, "cm_core_bmhl7_part4"}, + {0x00030790, "cm_core_bmhl7_part2"}, + {0x000307a0, "cm_core_bmhl7_part3"}, + {0x00030780, "cm_core_bmhl7_part1"}, + {0x00009224, "shim_dma_bd11_5"}, + {0x000c0280, "mem_lock40_value"}, + {0x0000922c, "shim_dma_bd11_7"}, + {0x00009228, "shim_dma_bd11_6"}, + {0x00009214, "shim_dma_bd11_1"}, + {0x00009210, "shim_dma_bd11_0"}, + {0x0000921c, "shim_dma_bd11_3"}, + {0x00009218, "shim_dma_bd11_2"}, + {0x000091b4, "shim_dma_bd9_1"}, + {0x000091b0, "shim_dma_bd9_0"}, + {0x000091bc, "shim_dma_bd9_3"}, + {0x000091b8, "shim_dma_bd9_2"}, + {0x000091c4, "shim_dma_bd9_5"}, + {0x000091c0, "shim_dma_bd9_4"}, + {0x000091cc, "shim_dma_bd9_7"}, + {0x0003800c, "cm_reset_event"}, + {0x000091d0, "shim_dma_bd9_8"}, + {0x00009050, "shim_dma_bd1_8"}, + {0x00034064, "cm_event_broadcast_block_west_clr"}, + {0x00009034, "shim_dma_bd1_1"}, + {0x00009030, "shim_dma_bd1_0"}, + {0x0000903c, "shim_dma_bd1_3"}, + {0x00009038, "shim_dma_bd1_2"}, + {0x00009044, "shim_dma_bd1_5"}, + {0x00009040, "shim_dma_bd1_4"}, + {0x0000904c, "shim_dma_bd1_7"}, + {0x00009048, "shim_dma_bd1_6"}, + {0x0000100c, "shim_interrupt_controller_2nd_level_status"}, + {0x0001f070, "mm_lock7_value"}, + {0x0001f0c0, "mm_lock12_value"}, + {0x000090f4, "shim_dma_bd5_1"}, + {0x000b0250, "mem_stream_switch_slave_dma_5_slot0"}, + {0x000b0254, "mem_stream_switch_slave_dma_5_slot1"}, + {0x000b0258, "mem_stream_switch_slave_dma_5_slot2"}, + {0x000b025c, "mem_stream_switch_slave_dma_5_slot3"}, + {0x00002100, "shim_me_aximm_config"}, + {0x000090f0, "shim_dma_bd5_0"}, + {0x0003f808, "cm_stream_switch_deterministic_merge_arb0_ctrl"}, + {0x00091008, "mem_performance_control2"}, + {0x0009100c, "mem_performance_control3"}, + {0x00091000, "mem_performance_control0"}, + {0x00091004, "mem_performance_control1"}, + {0x00000038, "npi_me_imr0"}, + {0x00094090, "mem_event_broadcast_b_block_south_set"}, + {0x00091010, "mem_performance_control4"}, + {0x0000005c, "npi_me_imr3"}, + {0x000c0300, "mem_lock48_value"}, + {0x000340d8, "cm_trace_status"}, + {0x00091080, "mem_performance_counter0_event_value"}, + {0x00030070, "cm_core_bmlh0_part4"}, + {0x00030040, "cm_core_bmlh0_part1"}, + {0x00030060, "cm_core_bmlh0_part3"}, + {0x000140f8, "mm_timer_low"}, + {0x000c00e0, "mem_lock14_value"}, + {0x00031840, "cm_core_x1_part1"}, + {0x00031850, "cm_core_x1_part2"}, + {0x00031860, "cm_core_x1_part3"}, + {0x00031870, "cm_core_x1_part4"}, + {0x000940f4, "mem_timer_trig_event_high_value"}, + {0x000b0038, "mem_stream_switch_master_config_north3"}, + {0x000b0034, "mem_stream_switch_master_config_north2"}, + {0x000318b0, "cm_core_x2_part4"}, + {0x000318a0, "cm_core_x2_part3"}, + {0x0003f284, "cm_stream_switch_slave_south_3_slot1"}, + {0x00031880, "cm_core_x2_part1"}, + {0x00096048, "mem_memory_control"}, + {0x000a0640, "mem_dma_mm2s_2_ctrl"}, + {0x00034008, "cm_event_generate"}, + {0x000c00b0, "mem_lock11_value"}, + {0x000c0090, "mem_lock9_value"}, + {0x00031af0, "cm_core_x11_part4"}, + {0x00031ac0, "cm_core_x11_part1"}, + {0x00031ad0, "cm_core_x11_part2"}, + {0x00031ae0, "cm_core_x11_part3"}, + {0x000a03a4, "mem_dma_bd29_1"}, + {0x000a03a0, "mem_dma_bd29_0"}, + {0x000a03ac, "mem_dma_bd29_3"}, + {0x000a03a8, "mem_dma_bd29_2"}, + {0x000a03b4, "mem_dma_bd29_5"}, + {0x000a03b0, "mem_dma_bd29_4"}, + {0x000a03bc, "mem_dma_bd29_7"}, + {0x000a03b8, "mem_dma_bd29_6"}, + {0x000340f0, "shim_timer_trig_event_low_value"}, + {0x0003f280, "cm_stream_switch_slave_south_3_slot0"}, + {0x000a02a0, "mem_dma_bd21_0"}, + {0x000a02ac, "mem_dma_bd21_3"}, + {0x000a02a8, "mem_dma_bd21_2"}, + {0x000a02b4, "mem_dma_bd21_5"}, + {0x000a02b0, "mem_dma_bd21_4"}, + {0x000a02bc, "mem_dma_bd21_7"}, + {0x000a02b8, "mem_dma_bd21_6"}, + {0x00036070, "cm_memory_control"}, + {0x000b02cc, "mem_stream_switch_slave_south_5_slot3"}, + {0x000b02c8, "mem_stream_switch_slave_south_5_slot2"}, + {0x000b02c4, "mem_stream_switch_slave_south_5_slot1"}, + {0x000b02c0, "mem_stream_switch_slave_south_5_slot0"}, + {0x000319f0, "cm_core_x7_part4"}, + {0x00094404, "mem_combo_event_control"}, + {0x000319e0, "cm_core_x7_part3"}, + {0x000319c0, "cm_core_x7_part1"}, + {0x00094074, "mem_event_broadcast_a_block_north_clr"}, + {0x00032590, "cm_core_fifoxtra_part2"}, + {0x000325a0, "cm_core_fifoxtra_part3"}, + {0x00032580, "cm_core_fifoxtra_part1"}, + {0x000325b0, "cm_core_fifoxtra_part4"}, + {0x0000006c, "npi_me_ior"}, + {0x00038110, "cm_ecc_scrubbing_event"}, + {0x00034064, "shim_event_broadcast_a_block_west_clr"}, + {0x00032d40, "cm_core_ls"}, + {0x00032d30, "cm_core_lr"}, + {0x00032d60, "cm_core_lc"}, + {0x00032d50, "cm_core_le"}, + {0x000a0658, "mem_dma_mm2s_5_ctrl"}, + {0x000b0138, "mem_stream_switch_slave_config_north_1"}, + {0x000b0134, "mem_stream_switch_slave_config_north_0"}, + {0x000b0140, "mem_stream_switch_slave_config_north_3"}, + {0x000b013c, "mem_stream_switch_slave_config_north_2"}, + {0x00032d00, "cm_program_counter"}, + {0x00009328, "shim_dma_mm2s_status_0"}, + {0x0000932c, "shim_dma_mm2s_status_1"}, + {0x000b5480, "uc_mdm_pccmdr"}, + {0x000a0634, "mem_dma_mm2s_0_start_queue"}, + {0x0001de04, "mm_dma_s2mm_0_start_queue"}, + {0x000340fc, "shim_timer_high"}, + {0x000c0000, "uc_core_status"}, + {0x000a06a0, "mem_dma_event_channel_selection"}, + {0x00034520, "cm_event_group_user_event_enable"}, + {0x000c0104, "uc_dma_dm2mm_control"} + }; + } +}; + +} // end XDP namespace + +#endif diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.cpp index e8e66dcc3b3..942cddf9509 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.cpp +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.cpp @@ -1,5 +1,18 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved. +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ #define XDP_PLUGIN_SOURCE @@ -14,10 +27,22 @@ #include "core/common/message.h" #include "core/include/experimental/xrt-next.h" +#include "xdp/profile/device/utility.h" +#include "xdp/profile/device/xdp_base_device.h" #include "xdp/profile/database/static_info/aie_util.h" #include "xdp/profile/database/database.h" #include "xdp/profile/database/static_info/aie_constructs.h" #include "xdp/profile/plugin/vp_base/info.h" +#include "xdp/profile/writer/aie_debug/aie_debug_writer.h" + +#ifdef XDP_CLIENT_BUILD +#include "client/aie_debug.h" +#elif XDP_VE2_BUILD +#include "ve2/aie_debug.h" +#else +#include "core/edge/user/shim.h" +#include "edge/aie_debug.h" +#endif namespace xdp { using severity_level = xrt_core::message::severity_level; @@ -25,8 +50,10 @@ namespace xdp { bool AieDebugPlugin::live = false; - AieDebugPlugin:: - AieDebugPlugin() : XDPPlugin() + /**************************************************************************** + * Constructor + ***************************************************************************/ + AieDebugPlugin::AieDebugPlugin() : XDPPlugin() { AieDebugPlugin::live = true; @@ -34,270 +61,173 @@ namespace xdp { db->getStaticInfo().setAieApplication(); } - AieDebugPlugin:: - ~AieDebugPlugin() + /**************************************************************************** + * Destructor + ***************************************************************************/ + AieDebugPlugin::~AieDebugPlugin() { - // Stop the polling thread - endPoll(); - free(op); + xrt_core::message::send(severity_level::info, "XRT", "Calling ~AieDebugPlugin destructor."); + + for (const auto& kv : handleToAIEData) + endPollforDevice(kv.first); - if (VPDatabase::alive()) - db->unregisterPlugin(this); + XDPPlugin::endWrite(); + handleToAIEData.clear(); + + if (VPDatabase::alive()) { + for (auto w : writers) { + w->write(false); + } + db->unregisterPlugin(this);} AieDebugPlugin::live = false; } - bool - AieDebugPlugin:: - alive() + /**************************************************************************** + * Check if plugin is alive + ***************************************************************************/ + bool AieDebugPlugin::alive() { return AieDebugPlugin::live; } - void - AieDebugPlugin:: - updateAIEDevice(void* handle) { - if (!xrt_core::config::get_aie_debug()) - return; - - // AIE Debug plugin is built only for client - mHwContext = xrt_core::hw_context_int::create_hw_context_from_implementation(handle); - auto device = xrt_core::hw_context_int::get_core_device(mHwContext); - auto deviceID = getDeviceIDFromHandle(handle); - - (db->getStaticInfo()).updateDeviceClient(deviceID, device); - (db->getStaticInfo()).setDeviceName(deviceID, "win_device"); + /**************************************************************************** + * Get device ID from handle + ***************************************************************************/ + uint64_t AieDebugPlugin::getDeviceIDFromHandle(void* handle) + { + xrt_core::message::send(severity_level::info, "XRT", "Calling AIE DEBUG AieDebugPlugin::getDeviceIDFromHandle."); + auto itr = handleToAIEData.find(handle); + if (itr != handleToAIEData.end()) + return itr->second.deviceID; - // Delete old data for this handle - if (handleToAIEData.find(handle) != handleToAIEData.end()) - handleToAIEData.erase(handle); +#ifdef XDP_CLIENT_BUILD + return db->addDevice("win_device"); +#else + //return db->addDevice(util::getDebugIpLayoutPath(handle)); + return db->addDevice("temp_edge_device"); +#endif + } - //Setting up struct - auto& aieData = handleToAIEData[handle]; - aieData.deviceID = deviceID; - - metadataReader = (db->getStaticInfo()).getAIEmetadataReader(); - if (!metadataReader) + /**************************************************************************** + * Update AIE device + ***************************************************************************/ + void AieDebugPlugin::updateAIEDevice(void* handle) + { + if (!xrt_core::config::get_aie_debug() || !handle) return; + xrt_core::message::send(severity_level::info, "XRT", "Calling AIE DEBUG update AIE device."); - transactionHandler = std::make_unique(mHwContext, "AIE Debug"); - xdp::aie::driver_config meta_config = getAIEConfigMetadata(); - - XAie_Config cfg { - meta_config.hw_gen, - meta_config.base_address, - meta_config.column_shift, - meta_config.row_shift, - meta_config.num_rows, - meta_config.num_columns, - meta_config.shim_row, - meta_config.mem_row_start, - meta_config.mem_num_rows, - meta_config.aie_tile_row_start, - meta_config.aie_tile_num_rows, - {0} // PartProp - }; - - auto regValues = parseMetrics(); - std::vector op_profile_data; - - int counterId = 0; - for (auto const& kv : moduleTypes) { - auto type = kv.first; - auto name = kv.second; - - // Registers for current module - auto& Regs = regValues[type]; - if (Regs.empty()) - continue; - - std::vector tiles; - if (type == module_type::shim) { - tiles = metadataReader->getInterfaceTiles("all", "all", "input_output"); - } else { - tiles = metadataReader->getTiles("all", type, "all"); - } - - if (tiles.empty()) { - std::stringstream msg; - msg << "AIE Debug found no tiles for module: " << name << "."; - xrt_core::message::send(severity_level::debug, "XRT", msg.str()); - continue; - } + // Handle relates to HW context in case of Client XRT +#ifdef XDP_CLIENT_BUILD + xrt::hw_context context = xrt_core::hw_context_int::create_hw_context_from_implementation(handle); + auto device = xrt_core::hw_context_int::get_core_device(context); +#else - std::sort(tiles.begin(), tiles.end()); - tiles.erase(std::unique(tiles.begin(), tiles.end()), tiles.end()); - std::stringstream msg; - msg << "AIE Debug monitoring tiles of type " << name << ":\n"; - for (const auto& t: tiles) - msg << t.col << "," << t.row << " "; - xrt_core::message::send(severity_level::debug, "XRT", msg.str()); - - for (auto &tile : tiles) { - for (size_t i = 0; i < Regs.size(); i++) { - op_profile_data.emplace_back(register_data_t{Regs[i] + (tile.col << 25) + (tile.row << 20)}); - counterId++; - } - } +#endif + auto deviceID = getDeviceIDFromHandle(handle); + std::stringstream msg; + msg<<"AieDebugPlugin::updateAIEDevice. Device Id =. "<getStaticInfo()).updateDeviceClient(deviceID, device); + (db->getStaticInfo()).setDeviceName(deviceID, "win_device"); +#else + (db->getStaticInfo()).updateDevice(deviceID, nullptr, handle); + std::string deviceName = util::getDeviceName(handle); + if (deviceName != "") + (db->getStaticInfo()).setDeviceName(deviceID, deviceName); +#endif } - auto RC = XAie_CfgInitialize(&aieDevInst, &cfg); - if (RC != XAIE_OK) { - xrt_core::message::send(severity_level::warning, "XRT", "AIE Driver Initialization Failed."); + // Delete old data + if (handleToAIEData.find(handle) != handleToAIEData.end()) +#ifdef XDP_CLIENT_BUILD + return; +#else + handleToAIEData.erase(handle); +#endif + auto& AIEData = handleToAIEData[handle]; + + AIEData.deviceID = deviceID; + AIEData.metadata = std::make_unique(deviceID, handle); + if (AIEData.metadata->aieMetadataEmpty()) + { + AIEData.valid = false; + xrt_core::message::send(severity_level::debug, "XRT", + "AIE DEBUG : no AIE metadata available for this xclbin update, skipping updateAIEDevice()"); return; } - - op_size = sizeof(read_register_op_t) + sizeof(register_data_t) * (counterId - 1); - op = (read_register_op_t*)malloc(op_size); - op->count = counterId; - for (size_t i = 0; i < op_profile_data.size(); i++) - op->data[i] = op_profile_data[i]; - - #if 0 - /* For larger debug buffer support, only one Debug BO can be alive at a time. - * Need ML Timeline Buffer to be created at update device to capture all calls. - * So, skip this poll - */ - poll(); - #endif - } - - - void - AieDebugPlugin:: - endAIEDebugRead(void* /*handle*/) - { - endPoll(); - } - - std::map> - AieDebugPlugin:: - parseMetrics() - { - std::map> regValues { - {module_type::core, {}}, - {module_type::dma, {}}, - {module_type::shim, {}}, - {module_type::mem_tile, {}} - }; - std::vector metricsConfig; - - metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_core_registers()); - metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_memory_registers()); - metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_interface_registers()); - metricsConfig.push_back(xrt_core::config::get_aie_debug_settings_memory_tile_registers()); - - unsigned int module = 0; - for (auto const& kv : moduleTypes) { - auto type = kv.first; - std::vector metricsSettings = getSettingsVector(metricsConfig[module++]); - - for (auto& s : metricsSettings) { - try { - uint64_t val = stoul(s,nullptr,16); - regValues[type].push_back(val); - } catch (...) { - xrt_core::message::send(severity_level::warning, "XRT", "Error Parsing Metric String."); - } - } - } - - return regValues; - } - - std::vector - AieDebugPlugin:: - getSettingsVector(std::string settingsString) - { - if (settingsString.empty()) - return {}; - - // Each of the metrics can have ; separated multiple values. Process and save all - std::vector settingsVector; - boost::replace_all(settingsString, " ", ""); - boost::split(settingsVector, settingsString, boost::is_any_of(",")); - return settingsVector; + AIEData.valid = true; + + // Parse user settings + AIEData.metadata->parseMetrics(); + +#ifdef XDP_CLIENT_BUILD + AIEData.metadata->setHwContext(context); + AIEData.implementation = std::make_unique(db, AIEData.metadata); +#elif XDP_VE2_BUILD + AIEData.implementation = std::make_unique(db, AIEData.metadata); +#else + AIEData.implementation = std::make_unique(db, AIEData.metadata); +#endif + + auto& implementation = AIEData.implementation; + implementation->updateAIEDevice(handle); + + // Open writer for this device + auto time = std::time(nullptr); +#ifdef _WIN32 + std::tm tm{}; + localtime_s(&tm, &time); + std::string deviceName = "win_device"; +#else + auto tm = *std::localtime(&time); + std::string deviceName = util::getDeviceName(handle); +#endif + + std::ostringstream timeOss; + timeOss << std::put_time(&tm, "_%Y_%m_%d_%H%M%S"); + std::string timestamp = timeOss.str(); + + std::string outputFile = "aie_debug_" + deviceName + timestamp + ".csv"; + VPWriter* writer = new AIEDebugWriter(outputFile.c_str(), deviceName.c_str(), mIndex); + writers.push_back(writer); + db->getStaticInfo().addOpenedFile(writer->getcurrentFileName(), "AIE_DEBUG"); + + mIndex++; } - void - AieDebugPlugin:: - endPoll() + /**************************************************************************** + * Finish debugging + ***************************************************************************/ + void AieDebugPlugin::endAIEDebugRead(void* handle) { - static bool finished = false; - if (!finished) { - finished = true; - poll(); - } + xrt_core::message::send(severity_level::info, "XRT", "AIE Debug endAIEDebugRead"); + auto deviceID = getDeviceIDFromHandle(handle); + xrt_core::message::send(severity_level::debug, "XRT", + "AieDebugPlugin::endAIEDebugRead deviceID is " + std::to_string(deviceID)); + handleToAIEData[handle].implementation->poll(deviceID, handle); } - void - AieDebugPlugin:: - poll() + /**************************************************************************** + * End polling + ***************************************************************************/ + void AieDebugPlugin::endPollforDevice(void* handle) { - xrt_core::message::send(severity_level::debug, "XRT", "Calling AIE Poll."); - - if (db->infoAvailable(xdp::info::ml_timeline)) { - db->broadcast(VPDatabase::MessageType::READ_RECORD_TIMESTAMPS, nullptr); - xrt_core::message::send(severity_level::debug, "XRT", "Done reading recorded timestamps."); - } - - xrt::bo resultBO; - uint32_t* output = nullptr; - try { - resultBO = xrt_core::bo_int::create_debug_bo(mHwContext, 0x20000); - output = resultBO.map(); - memset(output, 0, 0x20000); - } catch (std::exception& e) { - std::stringstream msg; - msg << "Unable to create 128KB buffer for AIE Debug results. Cannot get AIE Debug info. " << e.what() << std::endl; - xrt_core::message::send(xrt_core::message::severity_level::warning, "XRT", msg.str()); - return; - } - - XAie_StartTransaction(&aieDevInst, XAIE_TRANSACTION_DISABLE_AUTO_FLUSH); - - if (!transactionHandler->initializeKernel("XDP_KERNEL")) + xrt_core::message::send(severity_level::info, "XRT", "AIE Debug endPollforDevice"); + if (handleToAIEData.empty()) return; - XAie_AddCustomTxnOp(&aieDevInst, XAIE_IO_CUSTOM_OP_READ_REGS, (void*)op, op_size); - txn_ptr = XAie_ExportSerializedTransaction(&aieDevInst, 1, 0); - - if (!transactionHandler->submitTransaction(txn_ptr)) + auto& AIEData = handleToAIEData[handle]; + if (!AIEData.valid) return; - XAie_ClearTransaction(&aieDevInst); - - resultBO.sync(XCL_BO_SYNC_BO_FROM_DEVICE); + //AIEData.implementation->poll(0, handle); - for (uint32_t i = 0; i < op->count; i++) { - std::stringstream msg; - int col = (op->data[i].address >> 25) & 0x1F; - int row = (op->data[i].address >> 20) & 0x1F; - int reg = (op->data[i].address) & 0xFFFFF; - - msg << "Debug tile (" << col << ", " << row << ") " - << "hex address/values: " << std::hex << reg << " : " - << output[i] << std::dec; - xrt_core::message::send(xrt_core::message::severity_level::debug, "XRT", msg.str()); - } - } - - aie::driver_config - AieDebugPlugin:: - getAIEConfigMetadata() - { - return metadataReader->getDriverConfig(); - } - - uint64_t - AieDebugPlugin:: - getDeviceIDFromHandle(void* handle) - { - auto itr = handleToAIEData.find(handle); - if (itr != handleToAIEData.end()) - return itr->second.deviceID; - - return db->addDevice("win_device"); + handleToAIEData.erase(handle); } } // end namespace xdp diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.h b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.h index 4d4aadfa83e..23e6be3426d 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.h +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/aie_debug_plugin.h @@ -1,24 +1,30 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved. +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ #ifndef XDP_AIE_DEBUG_PLUGIN_DOT_H #define XDP_AIE_DEBUG_PLUGIN_DOT_H -#include #include -#include "xdp/profile/device/common/client_transaction.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_impl.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_metadata.h" #include "xdp/profile/database/static_info/aie_constructs.h" #include "xdp/profile/database/static_info/filetypes/base_filetype_impl.h" #include "xdp/profile/plugin/vp_base/vp_base_plugin.h" -#include "core/include/xrt/xrt_hw_context.h" - -extern "C" { - #include - #include -} - namespace xdp { class AieDebugPlugin : public XDPPlugin @@ -26,41 +32,27 @@ namespace xdp { public: AieDebugPlugin(); ~AieDebugPlugin(); + static bool alive(); void updateAIEDevice(void* handle); void endAIEDebugRead(void* handle); - static bool alive(); - + void endPollforDevice(void* handle); + private: - void endPoll(); - void poll(); - std::vector getSettingsVector(std::string settingsString); - std::map> parseMetrics(); - aie::driver_config getAIEConfigMetadata(); uint64_t getDeviceIDFromHandle(void* handle); - const std::map moduleTypes = { - {module_type::core, "AIE"}, - {module_type::dma, "DMA"}, - {module_type::shim, "Interface"}, - {module_type::mem_tile, "Memory Tile"} - }; - - xrt::hw_context mHwContext; - std::unique_ptr transactionHandler; - uint8_t* txn_ptr; - XAie_DevInst aieDevInst = {0}; - const aie::BaseFiletypeImpl* metadataReader = nullptr; - read_register_op_t* op; - std::size_t op_size; - + private: static bool live; + uint32_t mIndex = 0; + + // This struct and handleToAIEData map is created to provision multiple AIEs + // on the same machine, each denoted by its own handle struct AIEData { uint64_t deviceID; - std::atomic threadCtrlBool; - std::thread thread; + bool valid; + std::unique_ptr implementation; + std::shared_ptr metadata; }; - std::map handleToAIEData; - + std::map handleToAIEData; }; } // end namespace xdp diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.cpp new file mode 100755 index 00000000000..870675afd4c --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.cpp @@ -0,0 +1,203 @@ +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#define XDP_PLUGIN_SOURCE + +#include "xdp/profile/plugin/aie_debug/client/aie_debug.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_metadata.h" + +#include +#include + +#include "core/common/api/bo_int.h" +#include "core/common/api/hw_context_int.h" +#include "core/common/config_reader.h" +#include "core/common/message.h" +#include "core/include/experimental/xrt-next.h" + +#include "xdp/profile/database/static_info/aie_util.h" +#include "xdp/profile/database/database.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/plugin/vp_base/info.h" + +namespace xdp { + using severity_level = xrt_core::message::severity_level; + using tile_type = xdp::tile_type; + using module_type = xdp::module_type; + + /**************************************************************************** + * Client constructor + ***************************************************************************/ + AieDebug_WinImpl::AieDebug_WinImpl(VPDatabase* database, std::shared_ptr metadata) + : AieDebugImpl(database, metadata) + { + hwContext = metadata->getHwContext(); + transactionHandler = std::make_unique(hwContext, "AIE Debug Setup"); + } + + /**************************************************************************** + * Poll all registers + ***************************************************************************/ + void AieDebug_WinImpl::poll(const uint64_t deviceID, void* /*handle*/) + { + xrt_core::message::send(severity_level::debug, "XRT", "Calling AIE Poll."); + + if (db->infoAvailable(xdp::info::ml_timeline)) { + db->broadcast(VPDatabase::MessageType::READ_RECORD_TIMESTAMPS, nullptr); + xrt_core::message::send(severity_level::debug, "XRT", "Done reading recorded timestamps."); + } + + xrt::bo resultBO; + uint32_t* output = nullptr; + try { + resultBO = xrt_core::bo_int::create_debug_bo(hwContext, 0x20000); + output = resultBO.map(); + memset(output, 0, 0x20000); + } catch (std::exception& e) { + std::stringstream msg; + msg << "Unable to create 128KB buffer for AIE Debug results. Cannot get AIE Debug info. " << e.what() << std::endl; + xrt_core::message::send(xrt_core::message::severity_level::warning, "XRT", msg.str()); + return; + } + + XAie_StartTransaction(&aieDevInst, XAIE_TRANSACTION_DISABLE_AUTO_FLUSH); + + if (!transactionHandler->initializeKernel("XDP_KERNEL")) + return; + + XAie_AddCustomTxnOp(&aieDevInst, XAIE_IO_CUSTOM_OP_READ_REGS, (void*)op, op_size); + txn_ptr = XAie_ExportSerializedTransaction(&aieDevInst, 1, 0); + + if (!transactionHandler->submitTransaction(txn_ptr)) + return; + + XAie_ClearTransaction(&aieDevInst); + + resultBO.sync(XCL_BO_SYNC_BO_FROM_DEVICE); + + for (uint32_t i = 0; i < op->count; i++) { + uint8_t col = (op->data[i].address >> 25) & 0x1F; + uint8_t row = (op->data[i].address >> 20) & 0x1F; + uint64_t reg = (op->data[i].address) & 0xFFFFF; + + if (aie::isDebugVerbosity()) { + std::stringstream msg; + msg << "Debug tile (" << +col << ", " << +row << ") " << "hex address/values: " + << std::hex << reg << " : " << output[i] << std::dec; + xrt_core::message::send(xrt_core::message::severity_level::debug, "XRT", msg.str()); + } + + tile_type tile; + tile.col = col; + tile.row = row; + + if (debugTileMap.find(tile) == debugTileMap.end()) + debugTileMap[tile] = std::make_unique(col, row, reg); + + auto regName = metadata->lookupRegisterName(reg); + debugTileMap[tile]->addOffsetName(reg, regName); + debugTileMap[tile]->addValue(output[i]); + } + + // Add values to database + for (auto& tileAddr : debugTileMap) + tileAddr.second->printValues(static_cast(deviceID), db); + } + + /**************************************************************************** + * Update device + ***************************************************************************/ + void AieDebug_WinImpl::updateDevice() + { + // Do nothing for now + } + + /**************************************************************************** + * Update AIE device + ***************************************************************************/ + void AieDebug_WinImpl::updateAIEDevice(void* /*handle*/) + { + if (!xrt_core::config::get_aie_debug()) + return; + + auto regValues = metadata->getRegisterValues(); + std::vector op_debug_data; + + // Traverse all module types + int counterId = 0; + for (int module = 0; module < metadata->getNumModules(); ++module) { + auto configMetrics = metadata->getConfigMetricsVec(module); + if (configMetrics.empty()) + continue; + + auto type = metadata->getModuleType(module); + auto name = moduleTypes.at(type); + + // List of registers to read for current module + auto Regs = regValues[type]; + if (Regs.empty()) + continue; + + if (aie::isDebugVerbosity()) { + std::stringstream msg; + msg << "AIE Debug monitoring tiles of type " << name << ":\n"; + for (auto& tileMetric : configMetrics) + msg << tileMetric.first.col << "," << tileMetric.first.row << " "; + xrt_core::message::send(severity_level::debug, "XRT", msg.str()); + } + + // Traverse all active tiles for this module type + for (auto& tileMetric : configMetrics) { + auto tile = tileMetric.first; + auto tileOffset = XAie_GetTileAddr(&aieDevInst, tile.row, tile.col); + + for (int i = 0; i < Regs.size(); i++) { + op_debug_data.emplace_back(register_data_t{Regs[i] + tileOffset}); + counterId++; + } + } + } + + auto meta_config = metadata->getAIEConfigMetadata(); + XAie_Config cfg { + meta_config.hw_gen, + meta_config.base_address, + meta_config.column_shift, + meta_config.row_shift, + meta_config.num_rows, + meta_config.num_columns, + meta_config.shim_row, + meta_config.mem_row_start, + meta_config.mem_num_rows, + meta_config.aie_tile_row_start, + meta_config.aie_tile_num_rows, + {0} // PartProp + }; + + auto RC = XAie_CfgInitialize(&aieDevInst, &cfg); + if (RC != XAIE_OK) { + xrt_core::message::send(severity_level::warning, "XRT", "AIE Driver Initialization Failed."); + return; + } + + op_size = sizeof(read_register_op_t) + sizeof(register_data_t) * (counterId - 1); + op = (read_register_op_t*)malloc(op_size); + op->count = counterId; + for (int i = 0; i < op_debug_data.size(); i++) + op->data[i] = op_debug_data[i]; + } + +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.h b/src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.h new file mode 100755 index 00000000000..33d5d764e13 --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/client/aie_debug.h @@ -0,0 +1,73 @@ +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_H +#define AIE_DEBUG_H + +#include +#include + +#include "xdp/profile/plugin/aie_debug/aie_debug_impl.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_metadata.h" +#include "xdp/profile/device/common/client_transaction.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/database/static_info/filetypes/base_filetype_impl.h" +#include "xdp/profile/plugin/vp_base/vp_base_plugin.h" + +#include "core/include/xrt/xrt_hw_context.h" + +extern "C" { + #include + #include +} + +namespace xdp { + class ClientReadableTile; + + class AieDebug_WinImpl : public AieDebugImpl { + public: + AieDebug_WinImpl(VPDatabase* database, std::shared_ptr metadata); + ~AieDebug_WinImpl() = default; + void updateDevice(); + void updateAIEDevice(void* handle); + void poll(const uint64_t index, void* handle); + + private: + xrt::hw_context hwContext; + std::unique_ptr transactionHandler; + uint8_t* txn_ptr; + XAie_DevInst aieDevInst = {0}; + read_register_op_t* op; + std::size_t op_size; + + std::map> debugTileMap; + }; + + class ClientReadableTile : public BaseReadableTile { + public: + ClientReadableTile(uint8_t c, uint8_t r, uint64_t to) { + col = c; + row = r; + tileOffset = to; + } + void addValue(uint32_t val) { + values.push_back(val); + } + void readValues(XAie_DevInst* /*aieDevInst*/) {} + }; +} // end namespace xdp + +#endif diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.cpp new file mode 100644 index 00000000000..7166c84143f --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.cpp @@ -0,0 +1,183 @@ +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#define XDP_PLUGIN_SOURCE + +#include "xdp/profile/plugin/aie_debug/edge/aie_debug.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_metadata.h" +#include "xdp/profile/plugin/aie_debug/generations/aie1_attributes.h" +#include "xdp/profile/plugin/aie_debug/generations/aie1_registers.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2_attributes.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2_registers.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2ps_attributes.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h" + +#include +#include +#include + +#include "core/common/message.h" +#include "core/common/time.h" +#include "core/edge/user/shim.h" +#include "core/include/xrt/xrt_kernel.h" +#include "core/common/api/bo_int.h" +#include "core/common/api/hw_context_int.h" +#include "core/common/config_reader.h" +#include "core/include/experimental/xrt-next.h" + +#include "xdp/profile/database/static_info/aie_util.h" +#include "xdp/profile/database/database.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/plugin/vp_base/info.h" + +namespace { + static void* fetchAieDevInst(void* devHandle) + { + auto drv = ZYNQ::shim::handleCheck(devHandle); + if (!drv) + return nullptr ; + auto aieArray = drv->getAieArray(); + if (!aieArray) + return nullptr; + return aieArray->get_dev(); + } + + static void* allocateAieDevice(void* devHandle) + { + auto aieDevInst = static_cast(fetchAieDevInst(devHandle)); + if (!aieDevInst) + return nullptr; + return new xaiefal::XAieDev(aieDevInst, false); + } + + static void deallocateAieDevice(void* aieDevice) + { + auto object = static_cast(aieDevice); + if (object != nullptr) + delete object; + } +} // end anonymous namespace + +namespace xdp { + using severity_level = xrt_core::message::severity_level; + using tile_type = xdp::tile_type; + using module_type = xdp::module_type; + + /**************************************************************************** + * Edge constructor + ***************************************************************************/ + AieDebug_EdgeImpl::AieDebug_EdgeImpl(VPDatabase* database, std::shared_ptr metadata) + : AieDebugImpl(database, metadata) + { + // Nothing to do + } + + /**************************************************************************** + * Edge destructor + ***************************************************************************/ + AieDebug_EdgeImpl::~AieDebug_EdgeImpl() { + // Nothing to do + } + + /**************************************************************************** + * Poll all registers + ***************************************************************************/ + void AieDebug_EdgeImpl::poll(const uint64_t deviceID, void* handle) + { + xrt_core::message::send(severity_level::debug, "XRT", "Calling AIE Poll."); + + if (!(db->getStaticInfo().isDeviceReady(deviceID))) { + xrt_core::message::send(severity_level::debug, "XRT", + "Device is not ready, so no debug polling will occur."); + return; + } + + XAie_DevInst* aieDevInst = + static_cast(db->getStaticInfo().getAieDevInst(fetchAieDevInst, handle)); + if (!aieDevInst) { + xrt_core::message::send(severity_level::debug, "XRT", + "AIE device instance is not available, so no debug polling will occur."); + return; + } + + for (auto& tileAddr : debugTileMap) { + tileAddr.second->readValues(aieDevInst); + tileAddr.second->printValues(deviceID, db); + } + } + + /**************************************************************************** + * Update device + ***************************************************************************/ + void AieDebug_EdgeImpl::updateDevice() + { + // Do nothing for now + } + + /**************************************************************************** + * Compile list of registers to read + ***************************************************************************/ + void AieDebug_EdgeImpl::updateAIEDevice(void* handle) + { + if (!xrt_core::config::get_aie_debug()) + return; + XAie_DevInst* aieDevInst = + static_cast(db->getStaticInfo().getAieDevInst(fetchAieDevInst, handle)); + + std::unique_ptr debugPlugin; + auto regValues = metadata->getRegisterValues(); + + // Traverse all module types + int counterId = 0; + for (int module = 0; module < metadata->getNumModules(); ++module) { + auto configMetrics = metadata->getConfigMetricsVec(module); + if (configMetrics.empty()) + continue; + + module_type mod = metadata->getModuleType(module); + auto name = moduleTypes.at(mod); + + // List of registers to read for current module + auto& Regs = regValues[mod]; + if (Regs.empty()) + continue; + + if (aie::isDebugVerbosity()) { + std::stringstream msg; + msg << "AIE Debug monitoring tiles of type " << name << ":\n"; + for (auto& tileMetric : configMetrics) + msg << +tileMetric.first.col << "," << +tileMetric.first.row << " "; + xrt_core::message::send(severity_level::debug, "XRT", msg.str()); + } + + // Traverse all active and/or requested tiles + for (auto& tileMetric : configMetrics) { + auto tile = tileMetric.first; + auto tileOffset = XAie_GetTileAddr(aieDevInst, tile.row, tile.col); + + // Traverse all registers within tile + for (auto& regAddr : Regs) { + if (debugTileMap.find(tile) == debugTileMap.end()) + debugTileMap[tile] = std::make_unique(tile.col, tile.row, tileOffset); + + auto regName = metadata->lookupRegisterName(regAddr); + debugTileMap[tile]->addOffsetName(regAddr, regName); + } + } + } + } + +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.h b/src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.h new file mode 100644 index 00000000000..072247f5d7a --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/edge/aie_debug.h @@ -0,0 +1,75 @@ +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_H +#define AIE_DEBUG_H + +#include +#include + +#include "xdp/profile/plugin/aie_debug/aie_debug_impl.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/database/static_info/filetypes/base_filetype_impl.h" +#include "xdp/profile/plugin/vp_base/vp_base_plugin.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_plugin.h" + +#include "core/edge/common/aie_parser.h" +#include "xaiefal/xaiefal.hpp" + +extern "C" { + #include + #include +} + +namespace xdp { + class EdgeReadableTile; + + class AieDebug_EdgeImpl : public AieDebugImpl { + public: + AieDebug_EdgeImpl(VPDatabase* database, std::shared_ptr metadata); + ~AieDebug_EdgeImpl(); + void updateDevice(); + void updateAIEDevice(void* handle); + void poll(const uint64_t index, void* handle); + + private: + + std::map> debugAddresses; + std::map> debugTileMap; + const std::vector falModuleTypes = { + XAIE_CORE_MOD, XAIE_MEM_MOD, XAIE_PL_MOD, XAIE_MEM_MOD}; + }; + + class EdgeReadableTile: public BaseReadableTile { + public: + EdgeReadableTile(uint8_t c, uint8_t r, uint64_t to) { + col = c; + row = r; + tileOffset = to; + } + + void readValues(XAie_DevInst* aieDevInst) { + for (auto& offset : relativeOffsets) { + uint32_t val = 0; + XAie_Read32(aieDevInst, offset + tileOffset, &val); + values.push_back(val); + } + } +}; + +} // end namespace xdp + +#endif diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_attributes.h b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_attributes.h new file mode 100755 index 00000000000..41c9d6e15ba --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_attributes.h @@ -0,0 +1,287 @@ +// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +// ####################################################################### +// Copyright (c) 2022 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#ifndef AIE1_ATTRIBUTES_H_ +#define AIE1_ATTRIBUTES_H_ + +namespace aie1 +{ + +// Version- or Part-Specific Constants +// ################################### + +// Hardware generation +// See: https://gitenterprise.xilinx.com/ai-engine/aie-rt/blob/main/driver/src/global/xaiegbl_defs.h#L46 +const unsigned int hw_gen = 1; +// Tile architecture (used to determine broadcast direction) +const char * const tile_arch = "checkerboard"; +// Total number of rows/columns in AIE array +const unsigned int max_rows = 8; +const unsigned int max_cols = 50; +// First row of AIE tiles +// NOTE: row 0 is interface tiles +const unsigned int row_offset = 1; +// Base address of AIE array +const unsigned long long aie_base = 0x20000000000; +// Tile stride (used in addressing) +const unsigned int tile_stride = 0x40000; +// AIE Clock frequency (in MHz) +const unsigned int clock_freq_mhz = 1250; +// Bit widths +const unsigned int stream_bit_width = 32; +const unsigned int cascade_bit_width = 384; +// Trace events per module/tile +const unsigned int num_trace_events = 8; +// Counters per module/tile +const unsigned int cm_num_counters = 4; +const unsigned int mm_num_counters = 2; +const unsigned int mm_num_counter_events = 2; +const unsigned int shim_num_counters = 2; +const unsigned int mem_num_counters = 0; +// Broadcast channels per module/tile +const unsigned int cm_num_broadcasts = 16; +const unsigned int mm_num_broadcasts = 16; +const unsigned int shim_num_braodcasts = 16; +const unsigned int mem_num_broadcasts = 16; +// Stream switch event ports per module/tile +const unsigned int cm_num_ss_event_ports = 8; +const unsigned int shim_num_ss_event_ports = 8; +const unsigned int mem_num_ss_event_ports = 0; +// Event status registers (i.e., sticky bits) +const unsigned int cm_num_event_status_regs = 4; +const unsigned int mm_num_event_status_regs = 4; +const unsigned int shim_num_event_status_regs = 4; +const unsigned int mem_num_event_status_regs = 0; +// Microcontrollers (uC) per interface tile +const unsigned int shim_num_uc = 0; +// BD metadata per tile +const unsigned int mm_num_bds = 16; +const unsigned int mm_num_bd_regs = 7; +const unsigned int shim_num_bds = 0; +const unsigned int shim_num_bd_regs = 0; +const unsigned int mem_num_bds = 0; +const unsigned int mem_num_bd_regs = 0; +// Locks per tile +const unsigned int mm_num_locks = 16; +const unsigned int shim_num_locks = 16; +const unsigned int mem_num_locks = 0; +// Group events +const unsigned int cm_num_group_events = 9; +const unsigned int cm_group_core_stall_index = 3; +const unsigned int cm_group_program_flow_index = 4; +const unsigned int cm_group_stream_switch_index = 7; +// Event masks +const unsigned int shim_event_mask = 0x7f; + +// Version-Specific Event IDs +// ################################### + +const unsigned int cm_event_none = 0; +const unsigned int cm_event_true = 1; +const unsigned int cm_event_perf_count_0 = 5; +const unsigned int cm_event_perf_count_1 = 6; +const unsigned int cm_event_perf_count_2 = 7; +const unsigned int cm_event_perf_count_3 = 8; +const unsigned int cm_event_combo_event_0 = 9; +const unsigned int cm_event_combo_event_1 = 10; +const unsigned int cm_event_combo_event_2 = 11; +const unsigned int cm_event_combo_event_3 = 12; +const unsigned int cm_event_group_core_stall = 22; +const unsigned int cm_event_memory_stall = 23; +const unsigned int cm_event_stream_stall = 24; +const unsigned int cm_event_cascade_stall = 25; +const unsigned int cm_event_lock_stall = 26; +const unsigned int cm_event_active = 28; +const unsigned int cm_event_disabled = 29; +const unsigned int cm_event_group_core_program_flow = 32; +const unsigned int cm_event_instr_event_0 = 33; +const unsigned int cm_event_instr_event_1 = 34; +const unsigned int cm_event_instr_call = 35; +const unsigned int cm_event_instr_return = 36; +const unsigned int cm_event_instr_vector = 37; +const unsigned int cm_event_instr_load = 38; +const unsigned int cm_event_instr_store = 39; +const unsigned int cm_event_instr_stream_get = 40; +const unsigned int cm_event_instr_stream_put = 41; +const unsigned int cm_event_instr_cascade_get = 42; +const unsigned int cm_event_instr_cascade_put = 43; +const unsigned int cm_event_fp_huge = 50; +const unsigned int cm_event_fp_tiny = 51; +const unsigned int cm_event_fp_invalid = 52; +const unsigned int cm_event_fp_infinity = 53; +const unsigned int cm_event_group_stream_switch = 73; +const unsigned int cm_event_port_idle_0 = 74; +const unsigned int cm_event_port_running_0 = 75; +const unsigned int cm_event_port_stalled_0 = 76; +const unsigned int cm_event_port_tlast_0 = 77; +const unsigned int cm_event_port_idle_1 = 78; +const unsigned int cm_event_port_running_1 = 79; +const unsigned int cm_event_port_stalled_1 = 80; +const unsigned int cm_event_port_tlast_1 = 81; +const unsigned int cm_event_port_idle_2 = 82; +const unsigned int cm_event_port_running_2 = 83; +const unsigned int cm_event_port_stalled_2 = 84; +const unsigned int cm_event_port_tlast_2 = 85; +const unsigned int cm_event_port_idle_3 = 86; +const unsigned int cm_event_port_running_3 = 87; +const unsigned int cm_event_port_stalled_3 = 88; +const unsigned int cm_event_port_tlast_3 = 89; +const unsigned int cm_event_port_idle_4 = 90; +const unsigned int cm_event_port_running_4 = 91; +const unsigned int cm_event_port_stalled_4 = 92; +const unsigned int cm_event_port_tlast_4 = 93; +const unsigned int cm_event_port_idle_5 = 94; +const unsigned int cm_event_port_running_5 = 95; +const unsigned int cm_event_port_stalled_5 = 96; +const unsigned int cm_event_port_tlast_5 = 97; +const unsigned int cm_event_port_idle_6 = 98; +const unsigned int cm_event_port_running_6 = 99; +const unsigned int cm_event_port_stalled_6 = 100; +const unsigned int cm_event_port_tlast_6 = 101; +const unsigned int cm_event_port_idle_7 = 102; +const unsigned int cm_event_port_running_7 = 103; +const unsigned int cm_event_port_stalled_7 = 104; +const unsigned int cm_event_port_tlast_7 = 105; +const unsigned int cm_event_broadcast_0 = 107; +const unsigned int cm_event_broadcast_1 = 108; +const unsigned int cm_event_broadcast_2 = 109; +const unsigned int cm_event_broadcast_3 = 110; +const unsigned int cm_event_broadcast_4 = 111; +const unsigned int cm_event_broadcast_5 = 112; +const unsigned int cm_event_broadcast_6 = 113; +const unsigned int cm_event_broadcast_7 = 114; +const unsigned int cm_event_broadcast_8 = 115; +const unsigned int cm_event_broadcast_9 = 116; +const unsigned int cm_event_broadcast_10 = 117; +const unsigned int cm_event_broadcast_11 = 118; +const unsigned int cm_event_broadcast_12 = 119; +const unsigned int cm_event_broadcast_13 = 120; +const unsigned int cm_event_broadcast_14 = 121; +const unsigned int cm_event_broadcast_15 = 122; +const unsigned int cm_event_user_event_0 = 124; +const unsigned int cm_event_user_event_1 = 125; +const unsigned int cm_event_user_event_2 = 126; +const unsigned int cm_event_user_event_3 = 127; + +const unsigned int mm_event_perf_count_0 = 5; +const unsigned int mm_event_perf_count_1 = 6; +const unsigned int mm_event_group_dma_activity = 20; +const unsigned int mm_event_dma_finish_bd_s2mm_chan0 = 25; +const unsigned int mm_event_dma_finish_bd_s2mm_chan1 = 26; +const unsigned int mm_event_dma_finish_bd_mm2s_chan0 = 27; +const unsigned int mm_event_dma_finish_bd_mm2s_chan1 = 28; +const unsigned int mm_event_dma_stall_s2mm_chan0 = 33; +const unsigned int mm_event_dma_stall_s2mm_chan1 = 34; +const unsigned int mm_event_dma_stall_mm2s_chan0 = 35; +const unsigned int mm_event_dma_stall_mm2s_chan1 = 36; +const unsigned int mm_event_group_lock = 43; +const unsigned int mm_event_group_memory_conflict = 76; +const unsigned int mm_event_group_error = 86; +const unsigned int mm_event_broadcast_14 = 121; +const unsigned int mm_event_broadcast_15 = 122; + +const unsigned int shim_event_perf_count_0 = 5; +const unsigned int shim_event_perf_count_1 = 6; +const unsigned int shim_event_combo_event_3 = 10; +const unsigned int shim_event_group_dma_activity = 11; +const unsigned int shim_event_dma_s2mm_0_start_bd = 12; +const unsigned int shim_event_dma_s2mm_1_start_bd = 13; +const unsigned int shim_event_dma_mm2s_0_start_bd = 14; +const unsigned int shim_event_dma_mm2s_1_start_bd = 15; +const unsigned int shim_event_dma_s2mm_0_finished_bd = 16; +const unsigned int shim_event_dma_s2mm_1_finished_bd = 17; +const unsigned int shim_event_dma_mm2s_0_finished_bd = 18; +const unsigned int shim_event_dma_mm2s_1_finished_bd = 19; +const unsigned int shim_event_dma_s2mm_0_stalled_lock = 24; +const unsigned int shim_event_dma_s2mm_1_stalled_lock = 25; +const unsigned int shim_event_dma_mm2s_0_stalled_lock = 26; +const unsigned int shim_event_dma_mm2s_1_stalled_lock = 27; +const unsigned int shim_event_port_idle_0 = 74; +const unsigned int shim_event_port_running_0 = 75; +const unsigned int shim_event_port_stalled_0 = 76; +const unsigned int shim_event_port_tlast_0 = 77; +const unsigned int shim_event_port_idle_1 = 78; +const unsigned int shim_event_port_running_1 = 79; +const unsigned int shim_event_port_stalled_1 = 80; +const unsigned int shim_event_port_tlast_1 = 81; +const unsigned int shim_event_port_idle_2 = 82; +const unsigned int shim_event_port_running_2 = 83; +const unsigned int shim_event_port_stalled_2 = 84; +const unsigned int shim_event_port_tlast_2 = 85; +const unsigned int shim_event_port_idle_3 = 86; +const unsigned int shim_event_port_running_3 = 87; +const unsigned int shim_event_port_stalled_3 = 88; +const unsigned int shim_event_port_tlast_3 = 89; +const unsigned int shim_event_port_idle_4 = 90; +const unsigned int shim_event_port_running_4 = 91; +const unsigned int shim_event_port_stalled_4 = 92; +const unsigned int shim_event_port_tlast_4 = 93; +const unsigned int shim_event_port_idle_5 = 94; +const unsigned int shim_event_port_running_5 = 95; +const unsigned int shim_event_port_stalled_5 = 96; +const unsigned int shim_event_port_tlast_5 = 97; +const unsigned int shim_event_port_idle_6 = 98; +const unsigned int shim_event_port_running_6 = 99; +const unsigned int shim_event_port_stalled_6 = 100; +const unsigned int shim_event_port_tlast_6 = 101; +const unsigned int shim_event_port_idle_7 = 102; +const unsigned int shim_event_port_running_7 = 103; +const unsigned int shim_event_port_stalled_7 = 104; +const unsigned int shim_event_port_tlast_7 = 105; +const unsigned int shim_event_broadcast_0 = 107; +const unsigned int shim_event_broadcast_1 = 108; +const unsigned int shim_event_broadcast_2 = 109; +const unsigned int shim_event_broadcast_3 = 110; +const unsigned int shim_event_broadcast_4 = 111; +const unsigned int shim_event_broadcast_5 = 112; +const unsigned int shim_event_broadcast_6 = 113; +const unsigned int shim_event_broadcast_7 = 114; +const unsigned int shim_event_broadcast_8 = 115; +const unsigned int shim_event_broadcast_9 = 116; +const unsigned int shim_event_broadcast_10 = 117; +const unsigned int shim_event_broadcast_11 = 118; +const unsigned int shim_event_broadcast_12 = 119; +const unsigned int shim_event_broadcast_13 = 120; +const unsigned int shim_event_broadcast_14 = 121; +const unsigned int shim_event_broadcast_15 = 122; +const unsigned int shim_event_user_event_0 = 124; +const unsigned int shim_event_user_event_1 = 125; + +// Version-Specific Port Indices +// ################################### + +const unsigned int cm_dma_channel0_port_index = 2; +const unsigned int cm_dma_channel1_port_index = 3; +const unsigned int cm_core_trace_slave_port_index = 25; +const unsigned int cm_mem_trace_slave_port_index = 26; + +const unsigned int shim_south0_slave_port_index = 3; +const unsigned int shim_south0_master_port_index = 3; +const unsigned int shim_north0_slave_port_index = 15; +const unsigned int shim_north0_master_port_index = 13; + +} // namespace aie1 + +#endif /* AIE1_ATTRIBUTES_H_ */ diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_registers.h b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_registers.h new file mode 100644 index 00000000000..cf87c739a64 --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie1_registers.h @@ -0,0 +1,1266 @@ +// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +// ####################################################################### +// Copyright (c) 2022 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#ifndef AIE1_REGISTERS_H_ +#define AIE1_REGISTERS_H_ + +namespace aie1 +{ + +// Register definitions for AIE1 +// ################################### + +// Register definitions for CM +// ################################### +// Program Counter +const unsigned int cm_program_counter = 0x00030280; +// Core MD0 +const unsigned int cm_md0 = 0x00030440; +// Core MD1 +const unsigned int cm_md1 = 0x00030450; +// Core MC0 +const unsigned int cm_mc0 = 0x00030460; +// Core MC1 +const unsigned int cm_mc1 = 0x00030470; +// Performance Counters 1-0 Start and Stop Event +const unsigned int cm_performance_control0 = 0x00031000; +// Performance Counters 3-2 Start and Stop Event +const unsigned int cm_performance_control1 = 0x00031004; +// Performance Counters Reset Events +const unsigned int cm_performance_control2 = 0x00031008; +// Performance Counter0 +const unsigned int cm_performance_counter0 = 0x00031020; +// Performance Counter1 +const unsigned int cm_performance_counter1 = 0x00031024; +// Performance Counter2 +const unsigned int cm_performance_counter2 = 0x00031028; +// Performance Counter3 +const unsigned int cm_performance_counter3 = 0x0003102c; +// Performance Counter0 Event Value. +const unsigned int cm_performance_counter0_event_value = 0x00031080; +// Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated +const unsigned int cm_performance_counter1_event_value = 0x00031084; +// Performance Counter2 Event Value. When the Performance Counter2 reach this value, an event will be generated +const unsigned int cm_performance_counter2_event_value = 0x00031088; +// Performance Counter3 Event Value. When the Performance Counter3 reach this value, an event will be generated +const unsigned int cm_performance_counter3_event_value = 0x0003108c; +// Control of the AI Engine +const unsigned int cm_core_control = 0x00032000; +// The status of the AI Engine +const unsigned int cm_core_status = 0x00032004; +// Set enable event trigger +const unsigned int cm_enable_events = 0x00032008; +// Set reset event trigger +const unsigned int cm_reset_event = 0x0003200c; +// Debug control of manual debug stall and single step count +const unsigned int cm_debug_control0 = 0x00032010; +// Debug Halt Event Control +const unsigned int cm_debug_control1 = 0x00032014; +// Debug Halt Control +const unsigned int cm_debug_control2 = 0x00032018; +// Debug Status +const unsigned int cm_debug_status = 0x0003201c; +// PC_Event0 +const unsigned int cm_pc_event0 = 0x00032020; +// PC_Event1 +const unsigned int cm_pc_event1 = 0x00032024; +// PC_Event2 +const unsigned int cm_pc_event2 = 0x00032028; +// PC_Event3 +const unsigned int cm_pc_event3 = 0x0003202c; +// Error Halt Control +const unsigned int cm_error_halt_control = 0x00032030; +// Error Halt Event +const unsigned int cm_error_halt_event = 0x00032034; +// ECC scrubbing event +const unsigned int cm_ecc_scrubbing_event = 0x00032110; +// Control of Internal Timer +const unsigned int cm_timer_control = 0x00034000; +// Generate an internal event +const unsigned int cm_event_generate = 0x00034008; +// Control of which Internal Event to Broadcast0 +const unsigned int cm_event_broadcast0 = 0x00034010; +// Control of which Internal Event to Broadcast1 +const unsigned int cm_event_broadcast1 = 0x00034014; +// Control of which Internal Event to Broadcast2 +const unsigned int cm_event_broadcast2 = 0x00034018; +// Control of which Internal Event to Broadcast3 +const unsigned int cm_event_broadcast3 = 0x0003401c; +// Control of which Internal Event to Broadcast4 +const unsigned int cm_event_broadcast4 = 0x00034020; +// Control of which Internal Event to Broadcast5 +const unsigned int cm_event_broadcast5 = 0x00034024; +// Control of which Internal Event to Broadcast6 +const unsigned int cm_event_broadcast6 = 0x00034028; +// Control of which Internal Event to Broadcast7 +const unsigned int cm_event_broadcast7 = 0x0003402c; +// Control of which Internal Event to Broadcast8 +const unsigned int cm_event_broadcast8 = 0x00034030; +// Control of which Internal Event to Broadcast9 +const unsigned int cm_event_broadcast9 = 0x00034034; +// Control of which Internal Event to Broadcast10 +const unsigned int cm_event_broadcast10 = 0x00034038; +// Control of which Internal Event to Broadcast11 +const unsigned int cm_event_broadcast11 = 0x0003403c; +// Control of which Internal Event to Broadcast12 +const unsigned int cm_event_broadcast12 = 0x00034040; +// Control of which Internal Event to Broadcast13 +const unsigned int cm_event_broadcast13 = 0x00034044; +// Control of which Internal Event to Broadcast14 +const unsigned int cm_event_broadcast14 = 0x00034048; +// Control of which Internal Event to Broadcast15 +const unsigned int cm_event_broadcast15 = 0x0003404c; +// Set block of broadcast signals to South +const unsigned int cm_event_broadcast_block_south_set = 0x00034050; +// Clear block of broadcast signals to South +const unsigned int cm_event_broadcast_block_south_clr = 0x00034054; +// Current value of block for broadcast signals to South +const unsigned int cm_event_broadcast_block_south_value = 0x00034058; +// Set block of broadcast signals to West +const unsigned int cm_event_broadcast_block_west_set = 0x00034060; +// Clear block of broadcast signals to West +const unsigned int cm_event_broadcast_block_west_clr = 0x00034064; +// Current value of block for broadcast signals to West +const unsigned int cm_event_broadcast_block_west_value = 0x00034068; +// Set block of broadcast signals to North +const unsigned int cm_event_broadcast_block_north_set = 0x00034070; +// Clear block of broadcast signals to North +const unsigned int cm_event_broadcast_block_north_clr = 0x00034074; +// Current value of block for broadcast signals to North +const unsigned int cm_event_broadcast_block_north_value = 0x00034078; +// Set block of broadcast signals to East +const unsigned int cm_event_broadcast_block_east_set = 0x00034080; +// Clear block of broadcast signals to East +const unsigned int cm_event_broadcast_block_east_clr = 0x00034084; +// Current value of block for broadcast signals to East +const unsigned int cm_event_broadcast_block_east_value = 0x00034088; +// Control of Trace +const unsigned int cm_trace_control0 = 0x000340d0; +// Control of Trace: packet destination +const unsigned int cm_trace_control1 = 0x000340d4; +// Status of trace engine +const unsigned int cm_trace_status = 0x000340d8; +// Control of which Internal Event to Broadcast +const unsigned int cm_trace_event0 = 0x000340e0; +// Control of which Internal Event to Broadcast +const unsigned int cm_trace_event1 = 0x000340e4; +// Internal Timer Event Value. +const unsigned int cm_timer_trig_event_low_value = 0x000340f0; +// Internal Timer Event Value. +const unsigned int cm_timer_trig_event_high_value = 0x000340f4; +// Internal Timer Low part Value. +const unsigned int cm_timer_low = 0x000340f8; +// Internal Timer High part Value. +const unsigned int cm_timer_high = 0x000340fc; +// Internal event status register0 +const unsigned int cm_event_status0 = 0x00034200; +// Internal event status register1 +const unsigned int cm_event_status1 = 0x00034204; +// Internal event status register2 +const unsigned int cm_event_status2 = 0x00034208; +// Internal event status register3 +const unsigned int cm_event_status3 = 0x0003420c; +// Combo events input events +const unsigned int cm_combo_event_inputs = 0x00034400; +// Combo events input events +const unsigned int cm_combo_event_control = 0x00034404; +// Event enable for Group 0 +const unsigned int cm_event_group_0_enable = 0x00034500; +// Event enable for PC Group +const unsigned int cm_event_group_pc_enable = 0x00034504; +// Event enable for AI Engine Stall Group +const unsigned int cm_event_group_core_stall_enable = 0x00034508; +// Event enable for AI Engine Program Flow Group +const unsigned int cm_event_group_core_program_flow_enable = 0x0003450c; +// Event enable for Non Fatal Error Group +const unsigned int cm_event_group_errors0_enable = 0x00034510; +// Event enable for AI Engine Fatal Error Group +const unsigned int cm_event_group_errors1_enable = 0x00034514; +// Event enable for Stream Switch Group +const unsigned int cm_event_group_stream_switch_enable = 0x00034518; +// Event enable for Broadcast group +const unsigned int cm_event_group_broadcast_enable = 0x0003451c; +// Event enable for User group +const unsigned int cm_event_group_user_event_enable = 0x00034520; +// Tile control register +const unsigned int cm_tile_control = 0x00036030; +// Status of control packet handling +const unsigned int cm_tile_control_packet_handler_status = 0x00036034; +// Clock control for the tile +const unsigned int cm_tile_clock_control = 0x00036040; +// Stream Switch Master Configuration AI Engine 0 +const unsigned int cm_stream_switch_master_config_aie_core0 = 0x0003f000; +// Stream Switch Master Configuration AI Engine 1 +const unsigned int cm_stream_switch_master_config_aie_core1 = 0x0003f004; +// Stream Switch Master Configuration DMA 0 +const unsigned int cm_stream_switch_master_config_dma0 = 0x0003f008; +// Stream Switch Master Configuration DMA 1 +const unsigned int cm_stream_switch_master_config_dma1 = 0x0003f00c; +// Stream Switch Master Configuration AI Engine Tile Ctrl +const unsigned int cm_stream_switch_master_config_tile_ctrl = 0x0003f010; +// Stream Switch Master Configuration FIFO 0 +const unsigned int cm_stream_switch_master_config_fifo0 = 0x0003f014; +// Stream Switch Master Configuration FIFO 1 +const unsigned int cm_stream_switch_master_config_fifo1 = 0x0003f018; +// Stream Switch Master Configuration South 0 +const unsigned int cm_stream_switch_master_config_south0 = 0x0003f01c; +// Stream Switch Master Configuration South 1 +const unsigned int cm_stream_switch_master_config_south1 = 0x0003f020; +// Stream Switch Master Configuration South 2 +const unsigned int cm_stream_switch_master_config_south2 = 0x0003f024; +// Stream Switch Master Configuration South 3 +const unsigned int cm_stream_switch_master_config_south3 = 0x0003f028; +// Stream Switch Master Configuration West 0 +const unsigned int cm_stream_switch_master_config_west0 = 0x0003f02c; +// Stream Switch Master Configuration West 1 +const unsigned int cm_stream_switch_master_config_west1 = 0x0003f030; +// Stream Switch Master Configuration West 2 +const unsigned int cm_stream_switch_master_config_west2 = 0x0003f034; +// Stream Switch Master Configuration West 3 +const unsigned int cm_stream_switch_master_config_west3 = 0x0003f038; +// Stream Switch Master Configuration North 0 +const unsigned int cm_stream_switch_master_config_north0 = 0x0003f03c; +// Stream Switch Master Configuration North 1 +const unsigned int cm_stream_switch_master_config_north1 = 0x0003f040; +// Stream Switch Master Configuration North 2 +const unsigned int cm_stream_switch_master_config_north2 = 0x0003f044; +// Stream Switch Master Configuration North 3 +const unsigned int cm_stream_switch_master_config_north3 = 0x0003f048; +// Stream Switch Master Configuration North 4 +const unsigned int cm_stream_switch_master_config_north4 = 0x0003f04c; +// Stream Switch Master Configuration North 5 +const unsigned int cm_stream_switch_master_config_north5 = 0x0003f050; +// Stream Switch Master Configuration East 0 +const unsigned int cm_stream_switch_master_config_east0 = 0x0003f054; +// Stream Switch Master Configuration East 1 +const unsigned int cm_stream_switch_master_config_east1 = 0x0003f058; +// Stream Switch Master Configuration East 2 +const unsigned int cm_stream_switch_master_config_east2 = 0x0003f05c; +// Stream Switch Master Configuration East 3 +const unsigned int cm_stream_switch_master_config_east3 = 0x0003f060; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_config_aie_core0 = 0x0003f100; +// Stream Switch Slave Configuration AI Engine 1 +const unsigned int cm_stream_switch_slave_config_aie_core1 = 0x0003f104; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_config_dma_0 = 0x0003f108; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_config_dma_1 = 0x0003f10c; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_config_tile_ctrl = 0x0003f110; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_config_fifo_0 = 0x0003f114; +// Stream Switch Slave Configuration FIFO 1 +const unsigned int cm_stream_switch_slave_config_fifo_1 = 0x0003f118; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_config_south_0 = 0x0003f11c; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_config_south_1 = 0x0003f120; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_config_south_2 = 0x0003f124; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_config_south_3 = 0x0003f128; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_config_south_4 = 0x0003f12c; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_config_south_5 = 0x0003f130; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_config_west_0 = 0x0003f134; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_config_west_1 = 0x0003f138; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_config_west_2 = 0x0003f13c; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_config_west_3 = 0x0003f140; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_config_north_0 = 0x0003f144; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_config_north_1 = 0x0003f148; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_config_north_2 = 0x0003f14c; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_config_north_3 = 0x0003f150; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_config_east_0 = 0x0003f154; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_config_east_1 = 0x0003f158; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_config_east_2 = 0x0003f15c; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_config_east_3 = 0x0003f160; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_config_aie_trace = 0x0003f164; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_config_mem_trace = 0x0003f168; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot0 = 0x0003f200; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot1 = 0x0003f204; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot2 = 0x0003f208; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot3 = 0x0003f20c; +// Stream Switch Slave Configuration AI Engine 1 +const unsigned int cm_stream_switch_slave_aie_core1_slot0 = 0x0003f210; +// Stream Switch Slave Configuration AI Engine 1 +const unsigned int cm_stream_switch_slave_aie_core1_slot1 = 0x0003f214; +// Stream Switch Slave Configuration AI Engine 1 +const unsigned int cm_stream_switch_slave_aie_core1_slot2 = 0x0003f218; +// Stream Switch Slave Configuration AI Engine 1 +const unsigned int cm_stream_switch_slave_aie_core1_slot3 = 0x0003f21c; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot0 = 0x0003f220; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot1 = 0x0003f224; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot2 = 0x0003f228; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot3 = 0x0003f22c; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot0 = 0x0003f230; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot1 = 0x0003f234; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot2 = 0x0003f238; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot3 = 0x0003f23c; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot0 = 0x0003f240; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot1 = 0x0003f244; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot2 = 0x0003f248; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot3 = 0x0003f24c; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot0 = 0x0003f250; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot1 = 0x0003f254; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot2 = 0x0003f258; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot3 = 0x0003f25c; +// Stream Switch Slave Configuration FIFO 1 +const unsigned int cm_stream_switch_slave_fifo_1_slot0 = 0x0003f260; +// Stream Switch Slave Configuration FIFO 1 +const unsigned int cm_stream_switch_slave_fifo_1_slot1 = 0x0003f264; +// Stream Switch Slave Configuration FIFO 1 +const unsigned int cm_stream_switch_slave_fifo_1_slot2 = 0x0003f268; +// Stream Switch Slave Configuration FIFO 1 +const unsigned int cm_stream_switch_slave_fifo_1_slot3 = 0x0003f26c; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot0 = 0x0003f270; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot1 = 0x0003f274; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot2 = 0x0003f278; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot3 = 0x0003f27c; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot0 = 0x0003f280; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot1 = 0x0003f284; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot2 = 0x0003f288; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot3 = 0x0003f28c; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot0 = 0x0003f290; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot1 = 0x0003f294; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot2 = 0x0003f298; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot3 = 0x0003f29c; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot0 = 0x0003f2a0; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot1 = 0x0003f2a4; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot2 = 0x0003f2a8; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot3 = 0x0003f2ac; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot0 = 0x0003f2b0; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot1 = 0x0003f2b4; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot2 = 0x0003f2b8; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot3 = 0x0003f2bc; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot0 = 0x0003f2c0; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot1 = 0x0003f2c4; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot2 = 0x0003f2c8; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot3 = 0x0003f2cc; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot0 = 0x0003f2d0; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot1 = 0x0003f2d4; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot2 = 0x0003f2d8; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot3 = 0x0003f2dc; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot0 = 0x0003f2e0; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot1 = 0x0003f2e4; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot2 = 0x0003f2e8; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot3 = 0x0003f2ec; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot0 = 0x0003f2f0; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot1 = 0x0003f2f4; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot2 = 0x0003f2f8; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot3 = 0x0003f2fc; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot0 = 0x0003f300; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot1 = 0x0003f304; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot2 = 0x0003f308; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot3 = 0x0003f30c; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot0 = 0x0003f310; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot1 = 0x0003f314; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot2 = 0x0003f318; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot3 = 0x0003f31c; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot0 = 0x0003f320; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot1 = 0x0003f324; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot2 = 0x0003f328; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot3 = 0x0003f32c; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot0 = 0x0003f330; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot1 = 0x0003f334; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot2 = 0x0003f338; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot3 = 0x0003f33c; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot0 = 0x0003f340; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot1 = 0x0003f344; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot2 = 0x0003f348; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot3 = 0x0003f34c; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot0 = 0x0003f350; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot1 = 0x0003f354; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot2 = 0x0003f358; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot3 = 0x0003f35c; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot0 = 0x0003f360; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot1 = 0x0003f364; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot2 = 0x0003f368; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot3 = 0x0003f36c; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot0 = 0x0003f370; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot1 = 0x0003f374; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot2 = 0x0003f378; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot3 = 0x0003f37c; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot0 = 0x0003f380; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot1 = 0x0003f384; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot2 = 0x0003f388; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot3 = 0x0003f38c; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot0 = 0x0003f390; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot1 = 0x0003f394; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot2 = 0x0003f398; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot3 = 0x0003f39c; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot0 = 0x0003f3a0; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot1 = 0x0003f3a4; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot2 = 0x0003f3a8; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot3 = 0x0003f3ac; +// Select Stream Switch Ports for event generation +const unsigned int cm_stream_switch_event_port_selection_0 = 0x0003ff00; +// Select Stream Switch Ports for event generation +const unsigned int cm_stream_switch_event_port_selection_1 = 0x0003ff04; + +// Register definitions for MM +// ################################### +// Performance Counters Start and Stop Events +const unsigned int mm_performance_control0 = 0x00011000; +// Performance Counters Reset Events +const unsigned int mm_performance_control1 = 0x00011008; +// Performance Counter0 +const unsigned int mm_performance_counter0 = 0x00011020; +// Performance Counter1 +const unsigned int mm_performance_counter1 = 0x00011024; +// Performance Counter0 Event Value. +const unsigned int mm_performance_counter0_event_value = 0x00011080; +// Performance Counter1 Event Value. +const unsigned int mm_performance_counter1_event_value = 0x00011084; +// Inhibits check bits (parity or ECC) update to memory on writes +const unsigned int mm_checkbit_error_generation = 0x00012000; +// ECC Scrubbing Event +const unsigned int mm_ecc_scrubbing_event = 0x00012110; +// ECC Failing Address +const unsigned int mm_ecc_failing_address = 0x00012120; +// Parity Failing Address +const unsigned int mm_parity_failing_address = 0x00012124; +// Reset Control +const unsigned int mm_reset_control = 0x00013000; +// Control of Internal Timer +const unsigned int mm_timer_control = 0x00014000; +// Generate an internal event +const unsigned int mm_event_generate = 0x00014008; +// Control of which Internal Event to Broadcast0 +const unsigned int mm_event_broadcast0 = 0x00014010; +// Control of which Internal Event to Broadcast1 +const unsigned int mm_event_broadcast1 = 0x00014014; +// Control of which Internal Event to Broadcast2 +const unsigned int mm_event_broadcast2 = 0x00014018; +// Control of which Internal Event to Broadcast3 +const unsigned int mm_event_broadcast3 = 0x0001401c; +// Control of which Internal Event to Broadcast4 +const unsigned int mm_event_broadcast4 = 0x00014020; +// Control of which Internal Event to Broadcast5 +const unsigned int mm_event_broadcast5 = 0x00014024; +// Control of which Internal Event to Broadcast6 +const unsigned int mm_event_broadcast6 = 0x00014028; +// Control of which Internal Event to Broadcast7 +const unsigned int mm_event_broadcast7 = 0x0001402c; +// Control of which Internal Event to Broadcast8 +const unsigned int mm_event_broadcast8 = 0x00014030; +// Control of which Internal Event to Broadcast9 +const unsigned int mm_event_broadcast9 = 0x00014034; +// Control of which Internal Event to Broadcast10 +const unsigned int mm_event_broadcast10 = 0x00014038; +// Control of which Internal Event to Broadcast11 +const unsigned int mm_event_broadcast11 = 0x0001403c; +// Control of which Internal Event to Broadcast12 +const unsigned int mm_event_broadcast12 = 0x00014040; +// Control of which Internal Event to Broadcast13 +const unsigned int mm_event_broadcast13 = 0x00014044; +// Control of which Internal Event to Broadcast14 +const unsigned int mm_event_broadcast14 = 0x00014048; +// Control of which Internal Event to Broadcast15 +const unsigned int mm_event_broadcast15 = 0x0001404c; +// Set block of broadcast signals to South +const unsigned int mm_event_broadcast_block_south_set = 0x00014050; +// Clear block of broadcast signals to South +const unsigned int mm_event_broadcast_block_south_clr = 0x00014054; +// Current value of block for broadcast signals to South +const unsigned int mm_event_broadcast_block_south_value = 0x00014058; +// Set block of broadcast signals to West +const unsigned int mm_event_broadcast_block_west_set = 0x00014060; +// Clear block of broadcast signals to West +const unsigned int mm_event_broadcast_block_west_clr = 0x00014064; +// Current value of block for broadcast signals to West +const unsigned int mm_event_broadcast_block_west_value = 0x00014068; +// Set block of broadcast signals to North +const unsigned int mm_event_broadcast_block_north_set = 0x00014070; +// Clear block of broadcast signals to North +const unsigned int mm_event_broadcast_block_north_clr = 0x00014074; +// Current value of block for broadcast signals to North +const unsigned int mm_event_broadcast_block_north_value = 0x00014078; +// Set block of broadcast signals to East +const unsigned int mm_event_broadcast_block_east_set = 0x00014080; +// Clear block of broadcast signals to East +const unsigned int mm_event_broadcast_block_east_clr = 0x00014084; +// Current value of block for broadcast signals to East +const unsigned int mm_event_broadcast_block_east_value = 0x00014088; +// Control of Trace +const unsigned int mm_trace_control0 = 0x000140d0; +// Control of Trace packet configuration +const unsigned int mm_trace_control1 = 0x000140d4; +// Status of trace engine +const unsigned int mm_trace_status = 0x000140d8; +// Control of which Internal Event to Broadcast +const unsigned int mm_trace_event0 = 0x000140e0; +// Control of which Internal Event to Broadcast +const unsigned int mm_trace_event1 = 0x000140e4; +// Internal Timer Event Value. +const unsigned int mm_timer_trig_event_low_value = 0x000140f0; +// Internal Timer Event Value. +const unsigned int mm_timer_trig_event_high_value = 0x000140f4; +// Internal Timer Low part Value. +const unsigned int mm_timer_low = 0x000140f8; +// Internal Timer High part Value. +const unsigned int mm_timer_high = 0x000140fc; +// Define Watchpoint0 +const unsigned int mm_watchpoint0 = 0x00014100; +// Define Watchpoint1 +const unsigned int mm_watchpoint1 = 0x00014104; +// Internal event status register0 +const unsigned int mm_event_status0 = 0x00014200; +// Internal event status register1 +const unsigned int mm_event_status1 = 0x00014204; +// Internal event status register2 +const unsigned int mm_event_status2 = 0x00014208; +// Internal event status register3 +const unsigned int mm_event_status3 = 0x0001420c; +// Reserved +const unsigned int mm_reserved0 = 0x00014210; +// Reserved +const unsigned int mm_reserved1 = 0x00014214; +// Reserved +const unsigned int mm_reserved2 = 0x00014218; +// Reserved +const unsigned int mm_reserved3 = 0x0001421c; +// Combo events input events +const unsigned int mm_combo_event_inputs = 0x00014400; +// Combo events input events +const unsigned int mm_combo_event_control = 0x00014404; +// Event enable for Group 0 +const unsigned int mm_event_group_0_enable = 0x00014500; +// Event enable for Watchpoint Group +const unsigned int mm_event_group_watchpoint_enable = 0x00014504; +// Event enable for DMA Group +const unsigned int mm_event_group_dma_enable = 0x00014508; +// Event enable for Lock Group +const unsigned int mm_event_group_lock_enable = 0x0001450c; +// Event enable for Memory Conflict Group +const unsigned int mm_event_group_memory_conflict_enable = 0x00014510; +// Event enable for Error Group +const unsigned int mm_event_group_error_enable = 0x00014514; +// Event enable for Broadcast Group +const unsigned int mm_event_group_broadcast_enable = 0x00014518; +// Event enable for User Group +const unsigned int mm_event_group_user_event_enable = 0x0001451c; +// Spare register +const unsigned int mm_spare_reg = 0x00016000; +// DMA BD0 A Address and Lock +const unsigned int mm_dma_bd0_addr_a = 0x0001d000; +// DMA BD0 B Address and Lock +const unsigned int mm_dma_bd0_addr_b = 0x0001d004; +// DMA BD0 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd0_2d_x = 0x0001d008; +// DMA BD0 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd0_2d_y = 0x0001d00c; +// DMA BD0 Packet header +const unsigned int mm_dma_bd0_packet = 0x0001d010; +// DMA BD0 Interleaved state +const unsigned int mm_dma_bd0_interleaved_state = 0x0001d014; +// DMA BD0 Length, Next BD, BD Count +const unsigned int mm_dma_bd0_control = 0x0001d018; +// DMA BD1 A Address and Lock +const unsigned int mm_dma_bd1_addr_a = 0x0001d020; +// DMA BD1 B Address and Lock +const unsigned int mm_dma_bd1_addr_b = 0x0001d024; +// DMA BD1 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd1_2d_x = 0x0001d028; +// DMA BD1 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd1_2d_y = 0x0001d02c; +// DMA BD1 Dynamic packet header +const unsigned int mm_dma_bd1_packet = 0x0001d030; +// DMA BD1 Interleaved state +const unsigned int mm_dma_bd1_interleaved_state = 0x0001d034; +// DMA BD1 Length, Next BD, BD Count +const unsigned int mm_dma_bd1_control = 0x0001d038; +// DMA BD2 A Address and Lock +const unsigned int mm_dma_bd2_addr_a = 0x0001d040; +// DMA BD2 B Address and Lock +const unsigned int mm_dma_bd2_addr_b = 0x0001d044; +// DMA BD2 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd2_2d_x = 0x0001d048; +// DMA BD2 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd2_2d_y = 0x0001d04c; +// DMA BD2 Dynamic packet header +const unsigned int mm_dma_bd2_packet = 0x0001d050; +// DMA BD2 Interleaved state +const unsigned int mm_dma_bd2_interleaved_state = 0x0001d054; +// DMA BD1 Length, Next BD, BD Count +const unsigned int mm_dma_bd2_control = 0x0001d058; +// DMA BD3 A Address and Lock +const unsigned int mm_dma_bd3_addr_a = 0x0001d060; +// DMA BD3 B Address and Lock +const unsigned int mm_dma_bd3_addr_b = 0x0001d064; +// DMA BD3 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd3_2d_x = 0x0001d068; +// DMA BD3 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd3_2d_y = 0x0001d06c; +// DMA BD3 Dynamic packet header +const unsigned int mm_dma_bd3_packet = 0x0001d070; +// DMA BD3 Interleaved state +const unsigned int mm_dma_bd3_interleaved_state = 0x0001d074; +// DMA BD3 Length, Next BD, BD Count +const unsigned int mm_dma_bd3_control = 0x0001d078; +// DMA BD4 A Address and Lock +const unsigned int mm_dma_bd4_addr_a = 0x0001d080; +// DMA BD4 B Address and Lock +const unsigned int mm_dma_bd4_addr_b = 0x0001d084; +// DMA BD4 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd4_2d_x = 0x0001d088; +// DMA BD4 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd4_2d_y = 0x0001d08c; +// DMA BD4 Dynamic packet header +const unsigned int mm_dma_bd4_packet = 0x0001d090; +// DMA BD4 Interleaved state +const unsigned int mm_dma_bd4_interleaved_state = 0x0001d094; +// DMA BD4 Length, Next BD, BD Count +const unsigned int mm_dma_bd4_control = 0x0001d098; +// DMA BD5 A Address and Lock +const unsigned int mm_dma_bd5_addr_a = 0x0001d0a0; +// DMA BD5 B Address and Lock +const unsigned int mm_dma_bd5_addr_b = 0x0001d0a4; +// DMA BD5 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd5_2d_x = 0x0001d0a8; +// DMA BD5 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd5_2d_y = 0x0001d0ac; +// DMA BD5 Dynamic packet header +const unsigned int mm_dma_bd5_packet = 0x0001d0b0; +// DMA BD5 Interleaved state +const unsigned int mm_dma_bd5_interleaved_state = 0x0001d0b4; +// DMA BD5 Length, Next BD, BD Count +const unsigned int mm_dma_bd5_control = 0x0001d0b8; +// DMA BD6 A Address and Lock +const unsigned int mm_dma_bd6_addr_a = 0x0001d0c0; +// DMA BD6 B Address and Lock +const unsigned int mm_dma_bd6_addr_b = 0x0001d0c4; +// DMA BD6 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd6_2d_x = 0x0001d0c8; +// DMA BD6 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd6_2d_y = 0x0001d0cc; +// DMA BD6 Dynamic packet header +const unsigned int mm_dma_bd6_packet = 0x0001d0d0; +// DMA BD6 Interleaved state +const unsigned int mm_dma_bd6_interleaved_state = 0x0001d0d4; +// DMA BD6 Length, Next BD, BD Count +const unsigned int mm_dma_bd6_control = 0x0001d0d8; +// DMA BD7 A Address and Lock +const unsigned int mm_dma_bd7_addr_a = 0x0001d0e0; +// DMA BD7 B Address and Lock +const unsigned int mm_dma_bd7_addr_b = 0x0001d0e4; +// DMA BD7 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd7_2d_x = 0x0001d0e8; +// DMA BD7 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd7_2d_y = 0x0001d0ec; +// DMA BD7 Dynamic packet header +const unsigned int mm_dma_bd7_packet = 0x0001d0f0; +// DMA BD7 Interleaved state +const unsigned int mm_dma_bd7_interleaved_state = 0x0001d0f4; +// DMA BD7 Length, Next BD, BD Count +const unsigned int mm_dma_bd7_control = 0x0001d0f8; +// DMA BD8 A Address and Lock +const unsigned int mm_dma_bd8_addr_a = 0x0001d100; +// DMA BD8 B Address and Lock +const unsigned int mm_dma_bd8_addr_b = 0x0001d104; +// DMA BD8 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd8_2d_x = 0x0001d108; +// DMA BD8 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd8_2d_y = 0x0001d10c; +// DMA BD8 Dynamic packet header +const unsigned int mm_dma_bd8_packet = 0x0001d110; +// DMA BD8 Interleaved state +const unsigned int mm_dma_bd8_interleaved_state = 0x0001d114; +// DMA BD8 Length, Next BD, BD Count +const unsigned int mm_dma_bd8_control = 0x0001d118; +// DMA BD9 A Address and Lock +const unsigned int mm_dma_bd9_addr_a = 0x0001d120; +// DMA BD9 B Address and Lock +const unsigned int mm_dma_bd9_addr_b = 0x0001d124; +// DMA BD9 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd9_2d_x = 0x0001d128; +// DMA BD9 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd9_2d_y = 0x0001d12c; +// DMA BD9 Dynamic packet header +const unsigned int mm_dma_bd9_packet = 0x0001d130; +// DMA BD9 Interleaved state +const unsigned int mm_dma_bd9_interleaved_state = 0x0001d134; +// DMA BD9 Length, Next BD, BD Count +const unsigned int mm_dma_bd9_control = 0x0001d138; +// DMA BD10 A Address and Lock +const unsigned int mm_dma_bd10_addr_a = 0x0001d140; +// DMA BD10 B Address and Lock +const unsigned int mm_dma_bd10_addr_b = 0x0001d144; +// DMA BD10 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd10_2d_x = 0x0001d148; +// DMA BD10 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd10_2d_y = 0x0001d14c; +// DMA BD10 Dynamic packet header +const unsigned int mm_dma_bd10_packet = 0x0001d150; +// DMA BD10 Interleaved state +const unsigned int mm_dma_bd10_interleaved_state = 0x0001d154; +// DMA BD10 Length, Next BD, BD Count +const unsigned int mm_dma_bd10_control = 0x0001d158; +// DMA BD11 A Address and Lock +const unsigned int mm_dma_bd11_addr_a = 0x0001d160; +// DMA BD11 B Address and Lock +const unsigned int mm_dma_bd11_addr_b = 0x0001d164; +// DMA BD11 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd11_2d_x = 0x0001d168; +// DMA BD11 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd11_2d_y = 0x0001d16c; +// DMA BD11 Dynamic packet header +const unsigned int mm_dma_bd11_packet = 0x0001d170; +// DMA BD11 Interleaved state +const unsigned int mm_dma_bd11_interleaved_state = 0x0001d174; +// DMA BD11 Length, Next BD, BD Count +const unsigned int mm_dma_bd11_control = 0x0001d178; +// DMA BD12 A Address and Lock +const unsigned int mm_dma_bd12_addr_a = 0x0001d180; +// DMA BD12 B Address and Lock +const unsigned int mm_dma_bd12_addr_b = 0x0001d184; +// DMA BD12 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd12_2d_x = 0x0001d188; +// DMA BD12 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd12_2d_y = 0x0001d18c; +// DMA BD12 Dynamic packet header +const unsigned int mm_dma_bd12_packet = 0x0001d190; +// DMA BD12 Interleaved state +const unsigned int mm_dma_bd12_interleaved_state = 0x0001d194; +// DMA BD12 Length, Next BD, BD Count +const unsigned int mm_dma_bd12_control = 0x0001d198; +// DMA BD13 A Address and Lock +const unsigned int mm_dma_bd13_addr_a = 0x0001d1a0; +// DMA BD13 B Address and Lock +const unsigned int mm_dma_bd13_addr_b = 0x0001d1a4; +// DMA BD13 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd13_2d_x = 0x0001d1a8; +// DMA BD13 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd13_2d_y = 0x0001d1ac; +// DMA BD13 Dynamic packet header +const unsigned int mm_dma_bd13_packet = 0x0001d1b0; +// DMA BD13 Interleaved state +const unsigned int mm_dma_bd13_interleaved_state = 0x0001d1b4; +// DMA BD13 Length, Next BD, BD Count +const unsigned int mm_dma_bd13_control = 0x0001d1b8; +// DMA BD14 A Address and Lock +const unsigned int mm_dma_bd14_addr_a = 0x0001d1c0; +// DMA BD14 B Address and Lock +const unsigned int mm_dma_bd14_addr_b = 0x0001d1c4; +// DMA BD14 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd14_2d_x = 0x0001d1c8; +// DMA BD14 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd14_2d_y = 0x0001d1cc; +// DMA BD14 Dynamic packet header +const unsigned int mm_dma_bd14_packet = 0x0001d1d0; +// DMA BD14 Interleaved state +const unsigned int mm_dma_bd14_interleaved_state = 0x0001d1d4; +// DMA BD14 Length, Next BD, BD Count +const unsigned int mm_dma_bd14_control = 0x0001d1d8; +// DMA BD15 A Address and Lock +const unsigned int mm_dma_bd15_addr_a = 0x0001d1e0; +// DMA BD15 B Address and Lock +const unsigned int mm_dma_bd15_addr_b = 0x0001d1e4; +// DMA BD15 2D X Offset, Wrap, Increment +const unsigned int mm_dma_bd15_2d_x = 0x0001d1e8; +// DMA BD15 2D Y Offset, Wrap, Increment +const unsigned int mm_dma_bd15_2d_y = 0x0001d1ec; +// DMA BD15 Dynamic packet header +const unsigned int mm_dma_bd15_packet = 0x0001d1f0; +// DMA BD15 Interleaved state +const unsigned int mm_dma_bd15_interleaved_state = 0x0001d1f4; +// DMA BD15 Length, Next BD, BD Count +const unsigned int mm_dma_bd15_control = 0x0001d1f8; +// DMA Control Register S2MM Ch0 +const unsigned int mm_dma_s2mm_0_ctrl = 0x0001de00; +// DMA Control Register S2MM Ch0 +const unsigned int mm_dma_s2mm_0_start_queue = 0x0001de04; +// DMA Control Register S2MM Ch1 +const unsigned int mm_dma_s2mm_1_ctrl = 0x0001de08; +// DMA Control Register S2MM Ch1 +const unsigned int mm_dma_s2mm_1_start_queue = 0x0001de0c; +// DMA Control Register MM2S Ch0 +const unsigned int mm_dma_mm2s_0_ctrl = 0x0001de10; +// DMA Control Register MM2S Ch0 +const unsigned int mm_dma_mm2s_0_start_queue = 0x0001de14; +// DMA Control Register MM2S Ch1 +const unsigned int mm_dma_mm2s_1_ctrl = 0x0001de18; +// DMA Control Register MM2S Ch1 +const unsigned int mm_dma_mm2s_1_start_queue = 0x0001de1c; +// DMA S2MM Status Register +const unsigned int mm_dma_s2mm_status = 0x0001df00; +// DMA MM2S Status Register +const unsigned int mm_dma_mm2s_status = 0x0001df10; +// DMA FIFO Counter Register +const unsigned int mm_dma_fifo_counter = 0x0001df20; +// Lock0 Release Request with No value +const unsigned int mm_lock0_release_nv = 0x0001e000; +// Lock0 Release Request with '0' value +const unsigned int mm_lock0_release_v0 = 0x0001e020; +// Lock0 Release Request with '1' value +const unsigned int mm_lock0_release_v1 = 0x0001e030; +// Lock0 Acquire Request with No value +const unsigned int mm_lock0_acquire_nv = 0x0001e040; +// Lock0 Acquire Request with '0' value +const unsigned int mm_lock0_acquire_v0 = 0x0001e060; +// Lock0 Acquire Request with '1' value +const unsigned int mm_lock0_acquire_v1 = 0x0001e070; +// Lock1 Release Request with No value +const unsigned int mm_lock1_release_nv = 0x0001e080; +// Lock1 Release Request with '0' value +const unsigned int mm_lock1_release_v0 = 0x0001e0a0; +// Lock1 Release Request with '1' value +const unsigned int mm_lock1_release_v1 = 0x0001e0b0; +// Lock1 Acquire Request with No value +const unsigned int mm_lock1_acquire_nv = 0x0001e0c0; +// Lock1 Acquire Request with '0' value +const unsigned int mm_lock1_acquire_v0 = 0x0001e0e0; +// Lock1 Acquire Request with '1' value +const unsigned int mm_lock1_acquire_v1 = 0x0001e0f0; +// Lock2 Release Request with No value +const unsigned int mm_lock2_release_nv = 0x0001e100; +// Lock2 Release Request with '0' value +const unsigned int mm_lock2_release_v0 = 0x0001e120; +// Lock2 Release Request with '1' value +const unsigned int mm_lock2_release_v1 = 0x0001e130; +// Lock2 Acquire Request with No value +const unsigned int mm_lock2_acquire_nv = 0x0001e140; +// Lock2 Acquire Request with '0' value +const unsigned int mm_lock2_acquire_v0 = 0x0001e160; +// Lock2 Acquire Request with '1' value +const unsigned int mm_lock2_acquire_v1 = 0x0001e170; +// Lock3 Release Request with No value +const unsigned int mm_lock3_release_nv = 0x0001e180; +// Lock3 Release Request with '0' value +const unsigned int mm_lock3_release_v0 = 0x0001e1a0; +// Lock3 Release Request with '1' value +const unsigned int mm_lock3_release_v1 = 0x0001e1b0; +// Lock3 Acquire Request with No value +const unsigned int mm_lock3_acquire_nv = 0x0001e1c0; +// Lock3 Acquire Request with '0' value +const unsigned int mm_lock3_acquire_v0 = 0x0001e1e0; +// Lock3 Acquire Request with '1' value +const unsigned int mm_lock3_acquire_v1 = 0x0001e1f0; +// Lock4 Release Request with No value +const unsigned int mm_lock4_release_nv = 0x0001e200; +// Lock4 Release Request with '0' value +const unsigned int mm_lock4_release_v0 = 0x0001e220; +// Lock4 Release Request with '1' value +const unsigned int mm_lock4_release_v1 = 0x0001e230; +// Lock4 Acquire Request with No value +const unsigned int mm_lock4_acquire_nv = 0x0001e240; +// Lock4 Acquire Request with '0' value +const unsigned int mm_lock4_acquire_v0 = 0x0001e260; +// Lock4 Acquire Request with '1' value +const unsigned int mm_lock4_acquire_v1 = 0x0001e270; +// Lock5 Release Request with No value +const unsigned int mm_lock5_release_nv = 0x0001e280; +// Lock5 Release Request with '0' value +const unsigned int mm_lock5_release_v0 = 0x0001e2a0; +// Lock5 Release Request with '1' value +const unsigned int mm_lock5_release_v1 = 0x0001e2b0; +// Lock5 Acquire Request with No value +const unsigned int mm_lock5_acquire_nv = 0x0001e2c0; +// Lock5 Acquire Request with '0' value +const unsigned int mm_lock5_acquire_v0 = 0x0001e2e0; +// Lock5 Acquire Request with '1' value +const unsigned int mm_lock5_acquire_v1 = 0x0001e2f0; +// Lock6 Release Request with No value +const unsigned int mm_lock6_release_nv = 0x0001e300; +// Lock6 Release Request with '0' value +const unsigned int mm_lock6_release_v0 = 0x0001e320; +// Lock6 Release Request with '1' value +const unsigned int mm_lock6_release_v1 = 0x0001e330; +// Lock6 Acquire Request with No value +const unsigned int mm_lock6_acquire_nv = 0x0001e340; +// Lock6 Acquire Request with '0' value +const unsigned int mm_lock6_acquire_v0 = 0x0001e360; +// Lock6 Acquire Request with '1' value +const unsigned int mm_lock6_acquire_v1 = 0x0001e370; +// Lock7 Release Request with No value +const unsigned int mm_lock7_release_nv = 0x0001e380; +// Lock7 Release Request with '0' value +const unsigned int mm_lock7_release_v0 = 0x0001e3a0; +// Lock7 Release Request with '1' value +const unsigned int mm_lock7_release_v1 = 0x0001e3b0; +// Lock7 Acquire Request with No value +const unsigned int mm_lock7_acquire_nv = 0x0001e3c0; +// Lock7 Acquire Request with '0' value +const unsigned int mm_lock7_acquire_v0 = 0x0001e3e0; +// Lock7 Acquire Request with '1' value +const unsigned int mm_lock7_acquire_v1 = 0x0001e3f0; +// Lock8 Release Request with No value +const unsigned int mm_lock8_release_nv = 0x0001e400; +// Lock8 Release Request with '0' value +const unsigned int mm_lock8_release_v0 = 0x0001e420; +// Lock8 Release Request with '1' value +const unsigned int mm_lock8_release_v1 = 0x0001e430; +// Lock8 Acquire Request with No value +const unsigned int mm_lock8_acquire_nv = 0x0001e440; +// Lock8 Acquire Request with '0' value +const unsigned int mm_lock8_acquire_v0 = 0x0001e460; +// Lock8 Acquire Request with '1' value +const unsigned int mm_lock8_acquire_v1 = 0x0001e470; +// Lock9 Release Request with No value +const unsigned int mm_lock9_release_nv = 0x0001e480; +// Lock9 Release Request with '0' value +const unsigned int mm_lock9_release_v0 = 0x0001e4a0; +// Lock9 Release Request with '1' value +const unsigned int mm_lock9_release_v1 = 0x0001e4b0; +// Lock9 Acquire Request with No value +const unsigned int mm_lock9_acquire_nv = 0x0001e4c0; +// Lock9 Acquire Request with '0' value +const unsigned int mm_lock9_acquire_v0 = 0x0001e4e0; +// Lock9 Acquire Request with '1' value +const unsigned int mm_lock9_acquire_v1 = 0x0001e4f0; +// Lock10 Release Request with No value +const unsigned int mm_lock10_release_nv = 0x0001e500; +// Lock10 Release Request with '0' value +const unsigned int mm_lock10_release_v0 = 0x0001e520; +// Lock10 Release Request with '1' value +const unsigned int mm_lock10_release_v1 = 0x0001e530; +// Lock10 Acquire Request with No value +const unsigned int mm_lock10_acquire_nv = 0x0001e540; +// Lock10 Acquire Request with '0' value +const unsigned int mm_lock10_acquire_v0 = 0x0001e560; +// Lock10 Acquire Request with '1' value +const unsigned int mm_lock10_acquire_v1 = 0x0001e570; +// Lock11 Release Request with No value +const unsigned int mm_lock11_release_nv = 0x0001e580; +// Lock11 Release Request with '0' value +const unsigned int mm_lock11_release_v0 = 0x0001e5a0; +// Lock11 Release Request with '1' value +const unsigned int mm_lock11_release_v1 = 0x0001e5b0; +// Lock11 Acquire Request with No value +const unsigned int mm_lock11_acquire_nv = 0x0001e5c0; +// Lock11 Acquire Request with '0' value +const unsigned int mm_lock11_acquire_v0 = 0x0001e5e0; +// Lock11 Acquire Request with '1' value +const unsigned int mm_lock11_acquire_v1 = 0x0001e5f0; +// Lock12 Release Request with No value +const unsigned int mm_lock12_release_nv = 0x0001e600; +// Lock12 Release Request with '0' value +const unsigned int mm_lock12_release_v0 = 0x0001e620; +// Lock12 Release Request with '1' value +const unsigned int mm_lock12_release_v1 = 0x0001e630; +// Lock12 Acquire Request with No value +const unsigned int mm_lock12_acquire_nv = 0x0001e640; +// Lock12 Acquire Request with '0' value +const unsigned int mm_lock12_acquire_v0 = 0x0001e660; +// Lock12 Acquire Request with '1' value +const unsigned int mm_lock12_acquire_v1 = 0x0001e670; +// Lock13 Release Request with No value +const unsigned int mm_lock13_release_nv = 0x0001e680; +// Lock13 Release Request with '0' value +const unsigned int mm_lock13_release_v0 = 0x0001e6a0; +// Lock13 Release Request with '1' value +const unsigned int mm_lock13_release_v1 = 0x0001e6b0; +// Lock13 Acquire Request with No value +const unsigned int mm_lock13_acquire_nv = 0x0001e6c0; +// Lock13 Acquire Request with '0' value +const unsigned int mm_lock13_acquire_v0 = 0x0001e6e0; +// Lock13 Acquire Request with '1' value +const unsigned int mm_lock13_acquire_v1 = 0x0001e6f0; +// Lock14 Release Request with No value +const unsigned int mm_lock14_release_nv = 0x0001e700; +// Lock14 Release Request with '0' value +const unsigned int mm_lock14_release_v0 = 0x0001e720; +// Lock14 Release Request with '1' value +const unsigned int mm_lock14_release_v1 = 0x0001e730; +// Lock14 Acquire Request with No value +const unsigned int mm_lock14_acquire_nv = 0x0001e740; +// Lock14 Acquire Request with '0' value +const unsigned int mm_lock14_acquire_v0 = 0x0001e760; +// Lock14 Acquire Request with '1' value +const unsigned int mm_lock14_acquire_v1 = 0x0001e770; +// Lock15 Release Request with No value +const unsigned int mm_lock15_release_nv = 0x0001e780; +// Lock15 Release Request with '0' value +const unsigned int mm_lock15_release_v0 = 0x0001e7a0; +// Lock15 Release Request with '1' value +const unsigned int mm_lock15_release_v1 = 0x0001e7b0; +// Lock15 Acquire Request with No value +const unsigned int mm_lock15_acquire_nv = 0x0001e7c0; +// Lock15 Acquire Request with '0' value +const unsigned int mm_lock15_acquire_v0 = 0x0001e7e0; +// Lock15 Acquire Request with '1' value +const unsigned int mm_lock15_acquire_v1 = 0x0001e7f0; +// All Locks Acquire Status and Value +const unsigned int mm_all_lock_state_value = 0x0001ef00; +// Control for which lock values events are generated +const unsigned int mm_lock_event_value_control_0 = 0x0001ef20; +// Control for which lock values events are generated +const unsigned int mm_lock_event_value_control_1 = 0x0001ef24; + +// Register definitions for SHIM +// ################################### +// Step size between DMA BD register groups +const unsigned int shim_dma_bd_step_size = 0x14; +// Step size between DMA S2MM register groups +const unsigned int shim_dma_s2mm_step_size = 0x8; +// All Locks Acquire Status and Value +const unsigned int shim_all_lock_state_value = 0x00014f00; +// DMA BD0 Low Address +const unsigned int shim_dma_bd0_addr_low = 0x0001d000; +// DMA BD0 Buffer Length +const unsigned int shim_dma_bd0_buffer_length = 0x0001d004; +// DMA BD0 Control +const unsigned int shim_dma_bd0_control = 0x0001d008; +// DMA BD0 AXI Configuration +const unsigned int shim_dma_bd0_axi_config = 0x0001d00c; +// DMA BD0 Packet +const unsigned int shim_dma_bd0_packet = 0x0001d010; +// DMA S2MM Channel 0 Control +const unsigned int shim_dma_s2mm_0_ctrl = 0x0001d140; +// DMA S2MM Channel 0 Start Queue +const unsigned int shim_dma_s2mm_0_start_queue = 0x0001d144; +// Performance Counters 1-0 Start and Stop Events +const unsigned int shim_performance_control0 = 0x00031000; +const unsigned int shim_performance_start_stop_0_1 = 0x00031000; +// Performance Counters 1-0 Reset Events +const unsigned int shim_performance_control1 = 0x00031008; +const unsigned int shim_performance_reset_0_1 = 0x00031008; +// Performance Counter0 +const unsigned int shim_performance_counter0 = 0x00031020; +// Performance Counter1 +const unsigned int shim_performance_counter1 = 0x00031024; +// Performance Counter0 Event Value. +const unsigned int shim_performance_counter0_event_value = 0x00031080; +// Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated +const unsigned int shim_performance_counter1_event_value = 0x00031084; +// Generate an internal event +const unsigned int shim_event_generate = 0x00034008; +// Control of which Internal Event to Broadcast0 +const unsigned int shim_event_broadcast_a_0 = 0x00034010; +// Control of which Internal Event to Broadcast1 +const unsigned int shim_event_broadcast_a_1 = 0x00034014; +// Control of which Internal Event to Broadcast2 +const unsigned int shim_event_broadcast_a_2 = 0x00034018; +// Control of which Internal Event to Broadcast3 +const unsigned int shim_event_broadcast_a_3 = 0x0003401c; +// Control of which Internal Event to Broadcast4 +const unsigned int shim_event_broadcast_a_4 = 0x00034020; +// Control of which Internal Event to Broadcast5 +const unsigned int shim_event_broadcast_a_5 = 0x00034024; +// Control of which Internal Event to Broadcast6 +const unsigned int shim_event_broadcast_a_6 = 0x00034028; +// Control of which Internal Event to Broadcast7 +const unsigned int shim_event_broadcast_a_7 = 0x0003402c; +// Control of which Internal Event to Broadcast8 +const unsigned int shim_event_broadcast_a_8 = 0x00034030; +// Control of which Internal Event to Broadcast9 +const unsigned int shim_event_broadcast_a_9 = 0x00034034; +// Control of which Internal Event to Broadcast10 +const unsigned int shim_event_broadcast_a_10 = 0x00034038; +// Control of which Internal Event to Broadcast11 +const unsigned int shim_event_broadcast_a_11 = 0x0003403c; +// Control of which Internal Event to Broadcast12 +const unsigned int shim_event_broadcast_a_12 = 0x00034040; +// Control of which Internal Event to Broadcast13 +const unsigned int shim_event_broadcast_a_13 = 0x00034044; +// Control of which Internal Event to Broadcast14 +const unsigned int shim_event_broadcast_a_14 = 0x00034048; +// Control of which Internal Event to Broadcast15 +const unsigned int shim_event_broadcast_a_15 = 0x0003404c; +// Set block of broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_set = 0x00034050; +// Clear block of broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_clr = 0x00034054; +// Current value of block for broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_value = 0x00034058; +// Set block of broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_set = 0x00034060; +// Clear block of broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_clr = 0x00034064; +// Current value of block for broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_value = 0x00034068; +// Set block of broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_set = 0x00034070; +// Clear block of broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_clr = 0x00034074; +// Current value of block for broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_value = 0x00034078; +// Set block of broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_set = 0x00034080; +// Clear block of broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_clr = 0x00034084; +// Current value of block for broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_value = 0x00034088; +// Control of Trace +const unsigned int shim_trace_control0 = 0x000340d0; +// Control of Trace: packet destination +const unsigned int shim_trace_control1 = 0x000340d4; +// Status of trace engine +const unsigned int shim_trace_status = 0x000340d8; +// Control of which Internal Event to Broadcast +const unsigned int shim_trace_event0 = 0x000340e0; +// Control of which Internal Event to Broadcast +const unsigned int shim_trace_event1 = 0x000340e4; +// Internal Timer Event Value. +const unsigned int shim_timer_trig_event_low_value = 0x000340f0; +// Internal Timer Event Value. +const unsigned int shim_timer_trig_event_high_value = 0x000340f4; +// Internal Timer Low part Value. +const unsigned int shim_timer_low = 0x000340f8; +// Internal Timer High part Value. +const unsigned int shim_timer_high = 0x000340fc; +// Internal event status register0 +const unsigned int shim_event_status0 = 0x00034200; +// Internal event status register1 +const unsigned int shim_event_status1 = 0x00034204; +// Internal event status register2 +const unsigned int shim_event_status2 = 0x00034208; +// Internal event status register3 +const unsigned int shim_event_status3 = 0x0003420c; +// Combo events input events +const unsigned int shim_combo_event_inputs = 0x00034400; +// Combo events input events +const unsigned int shim_combo_event_control = 0x00034404; +// Event enable for DMA Group +const unsigned int shim_event_group_dma_enable = 0x00034504; +// Stream Switch Ports 0-3 for event generation +const unsigned int shim_stream_switch_event_port_selection_0 = 0x0003ff00; +// Stream Switch Ports 4-7 for event generation +const unsigned int shim_stream_switch_event_port_selection_1 = 0x0003ff04; + +// Register definitions for MEM +// ################################### +// NOTE: these are dummy values needed by scripts but never used +// Performance Counter0 +const unsigned int mem_performance_counter0 = 0x0; + +} // namespace aie1 + +#endif /* AIE1_REGISTERS_H_ */ diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_attributes.h b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_attributes.h new file mode 100755 index 00000000000..95f69629da7 --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_attributes.h @@ -0,0 +1,387 @@ +// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +// ####################################################################### +// Copyright (c) 2022 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#ifndef AIE2_ATTRIBUTES_H_ +#define AIE2_ATTRIBUTES_H_ + +namespace aie2 +{ + +// Version-Specific Constants +// ################################### + +// Hardware generation +// See: https://gitenterprise.xilinx.com/ai-engine/aie-rt/blob/main/driver/src/global/xaiegbl_defs.h#L46 +const unsigned int hw_gen = 2; +// Tile architecture (used to determine broadcast direction) +const char * const tile_arch = "grid"; +// Total number of rows/columns in AIE array +const unsigned int max_rows = 8; +const unsigned int max_cols = 50; +// First row of AIE tiles +// NOTE: row 0 is interface tiles, and rows 1-2 are memory tiles +const unsigned int row_offset = 3; +// Base address of AIE array +const unsigned long long aie_base = 0x20000000000; +// Tile stride (used in addressing) +const unsigned int tile_stride = 0x100000; +// AIE Clock frequency (in MHz) +const unsigned int clock_freq_mhz = 1250; +// Bit widths +const unsigned int stream_bit_width = 32; +const unsigned int cascade_bit_width = 512; +// Trace events per module/tile +const unsigned int num_trace_events = 8; +// Counters per module/tile +const unsigned int cm_num_counters = 4; +const unsigned int mm_num_counters = 2; +const unsigned int mm_num_counter_events = 2; +const unsigned int shim_num_counters = 2; +const unsigned int mem_num_counters = 4; +// Broadcast channels per module/tile +const unsigned int cm_num_broadcasts = 16; +const unsigned int mm_num_broadcasts = 16; +const unsigned int shim_num_braodcasts = 16; +const unsigned int mem_num_broadcasts = 16; +// Stream switch event ports per module/tile +const unsigned int cm_num_ss_event_ports = 8; +const unsigned int shim_num_ss_event_ports = 8; +const unsigned int mem_num_ss_event_ports = 8; +// Event status registers (i.e., sticky bits) +const unsigned int cm_num_event_status_regs = 4; +const unsigned int mm_num_event_status_regs = 4; +const unsigned int shim_num_event_status_regs = 4; +const unsigned int mem_num_event_status_regs = 6; +// Microcontrollers (uC) per interface tile +const unsigned int shim_num_uc = 0; +// BD metadata per tile +const unsigned int mm_num_bds = 16; +const unsigned int mm_num_bd_regs = 6; +const unsigned int shim_num_bds = 16; +const unsigned int shim_num_bd_regs = 9; +const unsigned int mem_num_bds = 48; +const unsigned int mem_num_bd_regs = 8; +const unsigned int mem_num_bd_s2mm_channels = 1; +const unsigned int mem_num_bd_mm2s_channels = 1; +// Locks per tile +const unsigned int mm_num_locks = 16; +const unsigned int shim_num_locks = 16; +const unsigned int mem_num_locks = 64; +// Group events +const unsigned int cm_num_group_events = 9; +const unsigned int cm_group_core_stall_index = 3; +const unsigned int cm_group_program_flow_index = 4; +const unsigned int cm_group_stream_switch_index = 7; +// Event masks +const unsigned int shim_event_mask = 0x7f; + +// Version-Specific Event IDs +// ################################### + +const unsigned int cm_event_none = 0; +const unsigned int cm_event_true = 1; +const unsigned int cm_event_perf_count_0 = 5; +const unsigned int cm_event_perf_count_1 = 6; +const unsigned int cm_event_perf_count_2 = 7; +const unsigned int cm_event_perf_count_3 = 8; +const unsigned int cm_event_combo_event_0 = 9; +const unsigned int cm_event_combo_event_1 = 10; +const unsigned int cm_event_combo_event_2 = 11; +const unsigned int cm_event_combo_event_3 = 12; +const unsigned int cm_event_group_core_stall = 22; +const unsigned int cm_event_memory_stall = 23; +const unsigned int cm_event_stream_stall = 24; +const unsigned int cm_event_cascade_stall = 25; +const unsigned int cm_event_lock_stall = 26; +const unsigned int cm_event_active = 28; +const unsigned int cm_event_disabled = 29; +const unsigned int cm_event_group_core_program_flow = 32; +const unsigned int cm_event_instr_event_0 = 33; +const unsigned int cm_event_instr_event_1 = 34; +const unsigned int cm_event_instr_call = 35; +const unsigned int cm_event_instr_return = 36; +const unsigned int cm_event_instr_vector = 37; +const unsigned int cm_event_instr_load = 38; +const unsigned int cm_event_instr_store = 39; +const unsigned int cm_event_instr_stream_get = 40; +const unsigned int cm_event_instr_stream_put = 41; +const unsigned int cm_event_instr_cascade_get = 42; +const unsigned int cm_event_instr_cascade_put = 43; +const unsigned int cm_event_fp_huge = 50; +const unsigned int cm_event_fp_tiny = 51; +const unsigned int cm_event_fp_invalid = 52; +const unsigned int cm_event_fp_infinity = 53; +const unsigned int cm_event_group_stream_switch = 73; +const unsigned int cm_event_port_idle_0 = 74; +const unsigned int cm_event_port_running_0 = 75; +const unsigned int cm_event_port_stalled_0 = 76; +const unsigned int cm_event_port_tlast_0 = 77; +const unsigned int cm_event_port_idle_1 = 78; +const unsigned int cm_event_port_running_1 = 79; +const unsigned int cm_event_port_stalled_1 = 80; +const unsigned int cm_event_port_tlast_1 = 81; +const unsigned int cm_event_port_idle_2 = 82; +const unsigned int cm_event_port_running_2 = 83; +const unsigned int cm_event_port_stalled_2 = 84; +const unsigned int cm_event_port_tlast_2 = 85; +const unsigned int cm_event_port_idle_3 = 86; +const unsigned int cm_event_port_running_3 = 87; +const unsigned int cm_event_port_stalled_3 = 88; +const unsigned int cm_event_port_tlast_3 = 89; +const unsigned int cm_event_port_idle_4 = 90; +const unsigned int cm_event_port_running_4 = 91; +const unsigned int cm_event_port_stalled_4 = 92; +const unsigned int cm_event_port_tlast_4 = 93; +const unsigned int cm_event_port_idle_5 = 94; +const unsigned int cm_event_port_running_5 = 95; +const unsigned int cm_event_port_stalled_5 = 96; +const unsigned int cm_event_port_tlast_5 = 97; +const unsigned int cm_event_port_idle_6 = 98; +const unsigned int cm_event_port_running_6 = 99; +const unsigned int cm_event_port_stalled_6 = 100; +const unsigned int cm_event_port_tlast_6 = 101; +const unsigned int cm_event_port_idle_7 = 102; +const unsigned int cm_event_port_running_7 = 103; +const unsigned int cm_event_port_stalled_7 = 104; +const unsigned int cm_event_port_tlast_7 = 105; +const unsigned int cm_event_broadcast_0 = 107; +const unsigned int cm_event_broadcast_1 = 108; +const unsigned int cm_event_broadcast_2 = 109; +const unsigned int cm_event_broadcast_3 = 110; +const unsigned int cm_event_broadcast_4 = 111; +const unsigned int cm_event_broadcast_5 = 112; +const unsigned int cm_event_broadcast_6 = 113; +const unsigned int cm_event_broadcast_7 = 114; +const unsigned int cm_event_broadcast_8 = 115; +const unsigned int cm_event_broadcast_9 = 116; +const unsigned int cm_event_broadcast_10 = 117; +const unsigned int cm_event_broadcast_11 = 118; +const unsigned int cm_event_broadcast_12 = 119; +const unsigned int cm_event_broadcast_13 = 120; +const unsigned int cm_event_broadcast_14 = 121; +const unsigned int cm_event_broadcast_15 = 122; +const unsigned int cm_event_user_event_0 = 124; +const unsigned int cm_event_user_event_1 = 125; +const unsigned int cm_event_user_event_2 = 126; +const unsigned int cm_event_user_event_3 = 127; + +const unsigned int mm_event_perf_count_0 = 5; +const unsigned int mm_event_perf_count_1 = 6; +const unsigned int mm_event_group_dma_activity = 18; +const unsigned int mm_event_dma_finish_bd_s2mm_chan0 = 23; +const unsigned int mm_event_dma_finish_bd_s2mm_chan1 = 24; +const unsigned int mm_event_dma_finish_bd_mm2s_chan0 = 25; +const unsigned int mm_event_dma_finish_bd_mm2s_chan1 = 26; +const unsigned int mm_event_dma_stall_s2mm_chan0 = 31; +const unsigned int mm_event_dma_stall_s2mm_chan1 = 32; +const unsigned int mm_event_dma_stall_mm2s_chan0 = 33; +const unsigned int mm_event_dma_stall_mm2s_chan1 = 34; +const unsigned int mm_event_dma_stream_starvation_s2mm_chan0 = 35; +const unsigned int mm_event_dma_stream_starvation_s2mm_chan1 = 36; +const unsigned int mm_event_dma_stream_backpressure_mm2s_chan0 = 37; +const unsigned int mm_event_dma_stream_backpressure_mm2s_chan1 = 38; +const unsigned int mm_event_dma_memory_backpressure_s2mm_chan0 = 39; +const unsigned int mm_event_dma_memory_backpressure_s2mm_chan1 = 40; +const unsigned int mm_event_dma_memory_starvation_mm2s_chan0 = 41; +const unsigned int mm_event_dma_memory_starvation_mm2s_chan1 = 42; +const unsigned int mm_event_group_lock = 43; +const unsigned int mm_event_group_memory_conflict = 76; +const unsigned int mm_event_group_error = 86; +const unsigned int mm_event_broadcast_14 = 121; +const unsigned int mm_event_broadcast_15 = 122; + +const unsigned int shim_event_perf_count_0 = 5; +const unsigned int shim_event_perf_count_1 = 6; +const unsigned int shim_event_combo_event_3 = 10; +const unsigned int shim_event_group_dma_activity = 13; +const unsigned int shim_event_dma_s2mm_0_start_task = 14; +const unsigned int shim_event_dma_s2mm_1_start_task = 15; +const unsigned int shim_event_dma_mm2s_0_start_task = 16; +const unsigned int shim_event_dma_mm2s_1_start_task = 17; +const unsigned int shim_event_dma_s2mm_0_finished_bd = 18; +const unsigned int shim_event_dma_s2mm_1_finished_bd = 19; +const unsigned int shim_event_dma_mm2s_0_finished_bd = 20; +const unsigned int shim_event_dma_mm2s_1_finished_bd = 21; +const unsigned int shim_event_dma_s2mm_0_finished_task = 22; +const unsigned int shim_event_dma_s2mm_1_finished_task = 23; +const unsigned int shim_event_dma_mm2s_0_finished_task = 24; +const unsigned int shim_event_dma_mm2s_1_finished_task = 25; +const unsigned int shim_event_dma_s2mm_0_stalled_lock = 26; +const unsigned int shim_event_dma_s2mm_1_stalled_lock = 27; +const unsigned int shim_event_dma_mm2s_0_stalled_lock = 28; +const unsigned int shim_event_dma_mm2s_1_stalled_lock = 29; +const unsigned int shim_event_dma_s2mm_0_stream_starvation = 30; +const unsigned int shim_event_dma_s2mm_1_stream_starvation = 31; +const unsigned int shim_event_dma_mm2s_0_stream_backpressure = 32; +const unsigned int shim_event_dma_mm2s_1_stream_backpressure = 33; +const unsigned int shim_event_dma_s2mm_0_memory_backpressure = 34; +const unsigned int shim_event_dma_s2mm_1_memory_backpressure = 35; +const unsigned int shim_event_dma_mm2s_0_memory_starvation = 36; +const unsigned int shim_event_dma_mm2s_1_memory_starvation = 37; +const unsigned int shim_event_port_idle_0 = 77; +const unsigned int shim_event_port_running_0 = 78; +const unsigned int shim_event_port_stalled_0 = 79; +const unsigned int shim_event_port_tlast_0 = 80; +const unsigned int shim_event_port_idle_1 = 81; +const unsigned int shim_event_port_running_1 = 82; +const unsigned int shim_event_port_stalled_1 = 83; +const unsigned int shim_event_port_tlast_1 = 84; +const unsigned int shim_event_port_idle_2 = 85; +const unsigned int shim_event_port_running_2 = 86; +const unsigned int shim_event_port_stalled_2 = 87; +const unsigned int shim_event_port_tlast_2 = 88; +const unsigned int shim_event_port_idle_3 = 89; +const unsigned int shim_event_port_running_3 = 90; +const unsigned int shim_event_port_stalled_3 = 91; +const unsigned int shim_event_port_tlast_3 = 92; +const unsigned int shim_event_port_idle_4 = 93; +const unsigned int shim_event_port_running_4 = 94; +const unsigned int shim_event_port_stalled_4 = 95; +const unsigned int shim_event_port_tlast_4 = 96; +const unsigned int shim_event_port_idle_5 = 97; +const unsigned int shim_event_port_running_5 = 98; +const unsigned int shim_event_port_stalled_5 = 99; +const unsigned int shim_event_port_tlast_5 = 100; +const unsigned int shim_event_port_idle_6 = 101; +const unsigned int shim_event_port_running_6 = 102; +const unsigned int shim_event_port_stalled_6 = 103; +const unsigned int shim_event_port_tlast_6 = 104; +const unsigned int shim_event_port_idle_7 = 105; +const unsigned int shim_event_port_running_7 = 106; +const unsigned int shim_event_port_stalled_7 = 107; +const unsigned int shim_event_port_tlast_7 = 108; +const unsigned int shim_event_broadcast_0 = 110; +const unsigned int shim_event_broadcast_1 = 111; +const unsigned int shim_event_broadcast_2 = 112; +const unsigned int shim_event_broadcast_3 = 113; +const unsigned int shim_event_broadcast_4 = 114; +const unsigned int shim_event_broadcast_5 = 115; +const unsigned int shim_event_broadcast_6 = 116; +const unsigned int shim_event_broadcast_7 = 117; +const unsigned int shim_event_broadcast_8 = 118; +const unsigned int shim_event_broadcast_9 = 119; +const unsigned int shim_event_broadcast_10 = 120; +const unsigned int shim_event_broadcast_11 = 121; +const unsigned int shim_event_broadcast_12 = 122; +const unsigned int shim_event_broadcast_13 = 123; +const unsigned int shim_event_broadcast_14 = 124; +const unsigned int shim_event_broadcast_15 = 125; +const unsigned int shim_event_user_event_0 = 126; +const unsigned int shim_event_user_event_1 = 127; + +const unsigned int mem_event_edge_detection_0 = 13; +const unsigned int mem_event_edge_detection_1 = 14; +const unsigned int mem_event_group_watchpoint = 15; +const unsigned int mem_event_dma_s2mm_sel0_start_task = 21; +const unsigned int mem_event_dma_s2mm_sel1_start_task = 22; +const unsigned int mem_event_dma_mm2s_sel0_start_task = 23; +const unsigned int mem_event_dma_mm2s_sel1_start_task = 24; +const unsigned int mem_event_dma_s2mm_sel0_finished_bd = 25; +const unsigned int mem_event_dma_s2mm_sel1_finished_bd = 26; +const unsigned int mem_event_dma_mm2s_sel0_finished_bd = 27; +const unsigned int mem_event_dma_mm2s_sel1_finished_bd = 28; +const unsigned int mem_event_dma_s2mm_sel0_finished_task = 29; +const unsigned int mem_event_dma_s2mm_sel1_finished_task = 30; +const unsigned int mem_event_dma_mm2s_sel0_finished_task = 31; +const unsigned int mem_event_dma_mm2s_sel1_finished_task = 32; +const unsigned int mem_event_dma_s2mm_sel0_stalled_lock = 33; +const unsigned int mem_event_dma_s2mm_sel1_stalled_lock = 34; +const unsigned int mem_event_dma_mm2s_sel0_stalled_lock = 35; +const unsigned int mem_event_dma_mm2s_sel1_stalled_lock = 36; +const unsigned int mem_event_dma_s2mm_sel0_stream_starvation = 37; +const unsigned int mem_event_dma_mm2s_sel0_stream_backpressure = 39; +const unsigned int mem_event_dma_s2mm_sel0_memory_backpressure = 41; +const unsigned int mem_event_dma_mm2s_sel0_memory_starvation = 43; +const unsigned int mem_event_dma_mm2s_sel1_memory_starvation = 44; +const unsigned int mem_event_group_lock = 45; +const unsigned int mem_event_port_idle_0 = 79; +const unsigned int mem_event_port_running_0 = 80; +const unsigned int mem_event_port_stalled_0 = 81; +const unsigned int mem_event_port_tlast_0 = 82; +const unsigned int mem_event_port_idle_1 = 83; +const unsigned int mem_event_port_running_1 = 84; +const unsigned int mem_event_port_stalled_1 = 85; +const unsigned int mem_event_port_tlast_1 = 86; +const unsigned int mem_event_port_idle_2 = 87; +const unsigned int mem_event_port_running_2 = 88; +const unsigned int mem_event_port_stalled_2 = 89; +const unsigned int mem_event_port_tlast_2 = 90; +const unsigned int mem_event_port_idle_3 = 91; +const unsigned int mem_event_port_running_3 = 92; +const unsigned int mem_event_port_stalled_3 = 93; +const unsigned int mem_event_port_tlast_3 = 94; +const unsigned int mem_event_port_idle_4 = 95; +const unsigned int mem_event_port_running_4 = 96; +const unsigned int mem_event_port_stalled_4 = 97; +const unsigned int mem_event_port_tlast_4 = 98; +const unsigned int mem_event_port_idle_5 = 99; +const unsigned int mem_event_port_running_5 = 100; +const unsigned int mem_event_port_stalled_5 = 101; +const unsigned int mem_event_port_tlast_5 = 102; +const unsigned int mem_event_port_idle_6 = 103; +const unsigned int mem_event_port_running_6 = 104; +const unsigned int mem_event_port_stalled_6 = 105; +const unsigned int mem_event_port_tlast_6 = 106; +const unsigned int mem_event_port_idle_7 = 107; +const unsigned int mem_event_port_running_7 = 108; +const unsigned int mem_event_port_stalled_7 = 109; +const unsigned int mem_event_port_tlast_7 = 110; +const unsigned int mem_event_group_memory_conflict = 111; +const unsigned int mem_event_memory_conflict_bank_0 = 112; +const unsigned int mem_event_memory_conflict_bank_1 = 113; +const unsigned int mem_event_memory_conflict_bank_2 = 114; +const unsigned int mem_event_memory_conflict_bank_3 = 115; +const unsigned int mem_event_memory_conflict_bank_4 = 116; +const unsigned int mem_event_memory_conflict_bank_5 = 117; +const unsigned int mem_event_memory_conflict_bank_6 = 118; +const unsigned int mem_event_memory_conflict_bank_7 = 119; +const unsigned int mem_event_memory_conflict_bank_8 = 120; +const unsigned int mem_event_memory_conflict_bank_9 = 121; +const unsigned int mem_event_memory_conflict_bank_10 = 122; +const unsigned int mem_event_memory_conflict_bank_11 = 123; +const unsigned int mem_event_memory_conflict_bank_12 = 124; +const unsigned int mem_event_memory_conflict_bank_13 = 125; +const unsigned int mem_event_memory_conflict_bank_14 = 126; +const unsigned int mem_event_memory_conflict_bank_15 = 127; +const unsigned int mem_event_group_errors = 128; +const unsigned int mem_event_user_event_0 = 159; +const unsigned int mem_event_user_event_1 = 160; + +// Version-Specific Port Indices +// ################################### + +const unsigned int cm_dma_channel0_port_index = 1; +const unsigned int cm_dma_channel1_port_index = 2; +const unsigned int cm_core_trace_slave_port_index = 23; +const unsigned int cm_mem_trace_slave_port_index = 24; + +const unsigned int shim_south0_slave_port_index = 2; +const unsigned int shim_south0_master_port_index = 2; +const unsigned int shim_north0_slave_port_index = 14; +const unsigned int shim_north0_master_port_index = 12; + +} // namespace aie2 + +#endif /* AIE2_ATTRIBUTES_H_ */ diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_registers.h b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_registers.h new file mode 100644 index 00000000000..337fc110baa --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2_registers.h @@ -0,0 +1,2838 @@ +// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +// ####################################################################### +// Copyright (c) 2022 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#ifndef AIE2_REGISTERS_H_ +#define AIE2_REGISTERS_H_ + +namespace aie2 +{ + +// Register definitions for AIE2 +// ################################### + +// Register definitions for CM +// ################################### +// Program Counter +const unsigned int cm_program_counter = 0x00031100; +// Performance Counters 1-0 Start and Stop Events +const unsigned int cm_performance_control0 = 0x00031500; +// Performance Counters 3-2 Start and Stop Events +const unsigned int cm_performance_control1 = 0x00031504; +// Performance Counters Reset Events +const unsigned int cm_performance_control2 = 0x00031508; +// Performance Counter0 +const unsigned int cm_performance_counter0 = 0x00031520; +// Performance Counter1 +const unsigned int cm_performance_counter1 = 0x00031524; +// Performance Counter2 +const unsigned int cm_performance_counter2 = 0x00031528; +// Performance Counter3 +const unsigned int cm_performance_counter3 = 0x0003152c; +// Performance Counter0 Event Value. +const unsigned int cm_performance_counter0_event_value = 0x00031580; +// Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated +const unsigned int cm_performance_counter1_event_value = 0x00031584; +// Performance Counter2 Event Value. When the Performance Counter2 reach this value, an event will be generated +const unsigned int cm_performance_counter2_event_value = 0x00031588; +// Performance Counter3 Event Value. When the Performance Counter3 reach this value, an event will be generated +const unsigned int cm_performance_counter3_event_value = 0x0003158c; +// Control of the AI Engine +const unsigned int cm_core_control = 0x00032000; +// The status of the AI Engine +const unsigned int cm_core_status = 0x00032004; +// Set enable events +const unsigned int cm_enable_events = 0x00032008; +// Set reset event trigger +const unsigned int cm_reset_event = 0x0003200c; +// Debug control of manual debug stall and single step count +const unsigned int cm_debug_control0 = 0x00032010; +// Debug Halt Event Control +const unsigned int cm_debug_control1 = 0x00032014; +// Debug Halt Control +const unsigned int cm_debug_control2 = 0x00032018; +// Debug Status +const unsigned int cm_debug_status = 0x0003201c; +// PC_Event0 +const unsigned int cm_pc_event0 = 0x00032020; +// PC_Event1 +const unsigned int cm_pc_event1 = 0x00032024; +// PC_Event2 +const unsigned int cm_pc_event2 = 0x00032028; +// PC_Event3 +const unsigned int cm_pc_event3 = 0x0003202c; +// Error Halt Control +const unsigned int cm_error_halt_control = 0x00032030; +// Error Halt Event +const unsigned int cm_error_halt_event = 0x00032034; +// Core Processor Bus Control +const unsigned int cm_core_processor_bus = 0x00032038; +// ECC scrubbing event +const unsigned int cm_ecc_scrubbing_event = 0x00032110; +// Control of Internal Timer +const unsigned int cm_timer_control = 0x00034000; +// Generate an internal event +const unsigned int cm_event_generate = 0x00034008; +// Control of which Internal Event to Broadcast0 +const unsigned int cm_event_broadcast0 = 0x00034010; +// Control of which Internal Event to Broadcast1 +const unsigned int cm_event_broadcast1 = 0x00034014; +// Control of which Internal Event to Broadcast2 +const unsigned int cm_event_broadcast2 = 0x00034018; +// Control of which Internal Event to Broadcast3 +const unsigned int cm_event_broadcast3 = 0x0003401c; +// Control of which Internal Event to Broadcast4 +const unsigned int cm_event_broadcast4 = 0x00034020; +// Control of which Internal Event to Broadcast5 +const unsigned int cm_event_broadcast5 = 0x00034024; +// Control of which Internal Event to Broadcast6 +const unsigned int cm_event_broadcast6 = 0x00034028; +// Control of which Internal Event to Broadcast7 +const unsigned int cm_event_broadcast7 = 0x0003402c; +// Control of which Internal Event to Broadcast8 +const unsigned int cm_event_broadcast8 = 0x00034030; +// Control of which Internal Event to Broadcast9 +const unsigned int cm_event_broadcast9 = 0x00034034; +// Control of which Internal Event to Broadcast10 +const unsigned int cm_event_broadcast10 = 0x00034038; +// Control of which Internal Event to Broadcast11 +const unsigned int cm_event_broadcast11 = 0x0003403c; +// Control of which Internal Event to Broadcast12 +const unsigned int cm_event_broadcast12 = 0x00034040; +// Control of which Internal Event to Broadcast13 +const unsigned int cm_event_broadcast13 = 0x00034044; +// Control of which Internal Event to Broadcast14 +const unsigned int cm_event_broadcast14 = 0x00034048; +// Control of which Internal Event to Broadcast15 +const unsigned int cm_event_broadcast15 = 0x0003404c; +// Set block of broadcast signals to South +const unsigned int cm_event_broadcast_block_south_set = 0x00034050; +// Clear block of broadcast signals to South +const unsigned int cm_event_broadcast_block_south_clr = 0x00034054; +// Current value of block for broadcast signals to South +const unsigned int cm_event_broadcast_block_south_value = 0x00034058; +// Set block of broadcast signals to West +const unsigned int cm_event_broadcast_block_west_set = 0x00034060; +// Clear block of broadcast signals to West +const unsigned int cm_event_broadcast_block_west_clr = 0x00034064; +// Current value of block for broadcast signals to West +const unsigned int cm_event_broadcast_block_west_value = 0x00034068; +// Set block of broadcast signals to North +const unsigned int cm_event_broadcast_block_north_set = 0x00034070; +// Clear block of broadcast signals to North +const unsigned int cm_event_broadcast_block_north_clr = 0x00034074; +// Current value of block for broadcast signals to North +const unsigned int cm_event_broadcast_block_north_value = 0x00034078; +// Set block of broadcast signals to East +const unsigned int cm_event_broadcast_block_east_set = 0x00034080; +// Clear block of broadcast signals to East +const unsigned int cm_event_broadcast_block_east_clr = 0x00034084; +// Current value of block for broadcast signals to East +const unsigned int cm_event_broadcast_block_east_value = 0x00034088; +// Control of Trace +const unsigned int cm_trace_control0 = 0x000340d0; +// Control of Trace: packet destination +const unsigned int cm_trace_control1 = 0x000340d4; +// Status of trace engine +const unsigned int cm_trace_status = 0x000340d8; +// Control of which Internal Event to Trace +const unsigned int cm_trace_event0 = 0x000340e0; +// Control of which Internal Event to Trace +const unsigned int cm_trace_event1 = 0x000340e4; +// Internal Timer Event Value. +const unsigned int cm_timer_trig_event_low_value = 0x000340f0; +// Internal Timer Event Value. +const unsigned int cm_timer_trig_event_high_value = 0x000340f4; +// Internal Timer Low part Value. +const unsigned int cm_timer_low = 0x000340f8; +// Internal Timer High part Value. +const unsigned int cm_timer_high = 0x000340fc; +// Internal event status register0 +const unsigned int cm_event_status0 = 0x00034200; +// Internal event status register1 +const unsigned int cm_event_status1 = 0x00034204; +// Internal event status register2 +const unsigned int cm_event_status2 = 0x00034208; +// Internal event status register3 +const unsigned int cm_event_status3 = 0x0003420c; +// Combo events input events +const unsigned int cm_combo_event_inputs = 0x00034400; +// Combo events input events +const unsigned int cm_combo_event_control = 0x00034404; +// Configuration for edge detection events +const unsigned int cm_edge_detection_event_control = 0x00034408; +// Event enable for Group 0 +const unsigned int cm_event_group_0_enable = 0x00034500; +// Event enable for PC Group +const unsigned int cm_event_group_pc_enable = 0x00034504; +// Event enable for AI Engine Stall Group +const unsigned int cm_event_group_core_stall_enable = 0x00034508; +// Event enable for AI Engine Program Flow Group +const unsigned int cm_event_group_core_program_flow_enable = 0x0003450c; +// Event enable for Non Fatal Error Group +const unsigned int cm_event_group_errors0_enable = 0x00034510; +// Event enable for AI Engine Fatal Error Group +const unsigned int cm_event_group_errors1_enable = 0x00034514; +// Event enable for Stream Switch Group +const unsigned int cm_event_group_stream_switch_enable = 0x00034518; +// Event enable for Broadcast group +const unsigned int cm_event_group_broadcast_enable = 0x0003451c; +// Event enable for User group +const unsigned int cm_event_group_user_event_enable = 0x00034520; +// Tile control register +const unsigned int cm_tile_control = 0x00036030; +// Control Accumulator Cascade +const unsigned int cm_accumulator_control = 0x00036060; +// Control for memory (privileged) +const unsigned int cm_memory_control = 0x00036070; +// Stream Switch Master Configuration AI Engine 0 +const unsigned int cm_stream_switch_master_config_aie_core0 = 0x0003f000; +// Stream Switch Master Configuration DMA 0 +const unsigned int cm_stream_switch_master_config_dma0 = 0x0003f004; +// Stream Switch Master Configuration DMA 1 +const unsigned int cm_stream_switch_master_config_dma1 = 0x0003f008; +// Stream Switch Master Configuration AI Engine Tile Ctrl +const unsigned int cm_stream_switch_master_config_tile_ctrl = 0x0003f00c; +// Stream Switch Master Configuration FIFO 0 +const unsigned int cm_stream_switch_master_config_fifo0 = 0x0003f010; +// Stream Switch Master Configuration South 0 +const unsigned int cm_stream_switch_master_config_south0 = 0x0003f014; +// Stream Switch Master Configuration South 1 +const unsigned int cm_stream_switch_master_config_south1 = 0x0003f018; +// Stream Switch Master Configuration South 2 +const unsigned int cm_stream_switch_master_config_south2 = 0x0003f01c; +// Stream Switch Master Configuration South 3 +const unsigned int cm_stream_switch_master_config_south3 = 0x0003f020; +// Stream Switch Master Configuration West 0 +const unsigned int cm_stream_switch_master_config_west0 = 0x0003f024; +// Stream Switch Master Configuration West 1 +const unsigned int cm_stream_switch_master_config_west1 = 0x0003f028; +// Stream Switch Master Configuration West 2 +const unsigned int cm_stream_switch_master_config_west2 = 0x0003f02c; +// Stream Switch Master Configuration West 3 +const unsigned int cm_stream_switch_master_config_west3 = 0x0003f030; +// Stream Switch Master Configuration North 0 +const unsigned int cm_stream_switch_master_config_north0 = 0x0003f034; +// Stream Switch Master Configuration North 1 +const unsigned int cm_stream_switch_master_config_north1 = 0x0003f038; +// Stream Switch Master Configuration North 2 +const unsigned int cm_stream_switch_master_config_north2 = 0x0003f03c; +// Stream Switch Master Configuration North 3 +const unsigned int cm_stream_switch_master_config_north3 = 0x0003f040; +// Stream Switch Master Configuration North 4 +const unsigned int cm_stream_switch_master_config_north4 = 0x0003f044; +// Stream Switch Master Configuration North 5 +const unsigned int cm_stream_switch_master_config_north5 = 0x0003f048; +// Stream Switch Master Configuration East 0 +const unsigned int cm_stream_switch_master_config_east0 = 0x0003f04c; +// Stream Switch Master Configuration East 1 +const unsigned int cm_stream_switch_master_config_east1 = 0x0003f050; +// Stream Switch Master Configuration East 2 +const unsigned int cm_stream_switch_master_config_east2 = 0x0003f054; +// Stream Switch Master Configuration East 3 +const unsigned int cm_stream_switch_master_config_east3 = 0x0003f058; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_config_aie_core0 = 0x0003f100; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_config_dma_0 = 0x0003f104; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_config_dma_1 = 0x0003f108; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_config_tile_ctrl = 0x0003f10c; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_config_fifo_0 = 0x0003f110; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_config_south_0 = 0x0003f114; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_config_south_1 = 0x0003f118; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_config_south_2 = 0x0003f11c; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_config_south_3 = 0x0003f120; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_config_south_4 = 0x0003f124; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_config_south_5 = 0x0003f128; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_config_west_0 = 0x0003f12c; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_config_west_1 = 0x0003f130; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_config_west_2 = 0x0003f134; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_config_west_3 = 0x0003f138; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_config_north_0 = 0x0003f13c; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_config_north_1 = 0x0003f140; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_config_north_2 = 0x0003f144; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_config_north_3 = 0x0003f148; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_config_east_0 = 0x0003f14c; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_config_east_1 = 0x0003f150; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_config_east_2 = 0x0003f154; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_config_east_3 = 0x0003f158; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_config_aie_trace = 0x0003f15c; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_config_mem_trace = 0x0003f160; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot0 = 0x0003f200; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot1 = 0x0003f204; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot2 = 0x0003f208; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot3 = 0x0003f20c; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot0 = 0x0003f210; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot1 = 0x0003f214; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot2 = 0x0003f218; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot3 = 0x0003f21c; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot0 = 0x0003f220; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot1 = 0x0003f224; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot2 = 0x0003f228; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot3 = 0x0003f22c; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot0 = 0x0003f230; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot1 = 0x0003f234; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot2 = 0x0003f238; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot3 = 0x0003f23c; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot0 = 0x0003f240; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot1 = 0x0003f244; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot2 = 0x0003f248; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot3 = 0x0003f24c; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot0 = 0x0003f250; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot1 = 0x0003f254; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot2 = 0x0003f258; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot3 = 0x0003f25c; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot0 = 0x0003f260; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot1 = 0x0003f264; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot2 = 0x0003f268; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot3 = 0x0003f26c; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot0 = 0x0003f270; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot1 = 0x0003f274; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot2 = 0x0003f278; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot3 = 0x0003f27c; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot0 = 0x0003f280; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot1 = 0x0003f284; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot2 = 0x0003f288; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot3 = 0x0003f28c; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot0 = 0x0003f290; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot1 = 0x0003f294; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot2 = 0x0003f298; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot3 = 0x0003f29c; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot0 = 0x0003f2a0; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot1 = 0x0003f2a4; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot2 = 0x0003f2a8; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot3 = 0x0003f2ac; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot0 = 0x0003f2b0; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot1 = 0x0003f2b4; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot2 = 0x0003f2b8; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot3 = 0x0003f2bc; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot0 = 0x0003f2c0; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot1 = 0x0003f2c4; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot2 = 0x0003f2c8; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot3 = 0x0003f2cc; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot0 = 0x0003f2d0; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot1 = 0x0003f2d4; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot2 = 0x0003f2d8; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot3 = 0x0003f2dc; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot0 = 0x0003f2e0; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot1 = 0x0003f2e4; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot2 = 0x0003f2e8; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot3 = 0x0003f2ec; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot0 = 0x0003f2f0; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot1 = 0x0003f2f4; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot2 = 0x0003f2f8; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot3 = 0x0003f2fc; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot0 = 0x0003f300; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot1 = 0x0003f304; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot2 = 0x0003f308; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot3 = 0x0003f30c; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot0 = 0x0003f310; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot1 = 0x0003f314; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot2 = 0x0003f318; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot3 = 0x0003f31c; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot0 = 0x0003f320; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot1 = 0x0003f324; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot2 = 0x0003f328; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot3 = 0x0003f32c; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot0 = 0x0003f330; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot1 = 0x0003f334; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot2 = 0x0003f338; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot3 = 0x0003f33c; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot0 = 0x0003f340; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot1 = 0x0003f344; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot2 = 0x0003f348; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot3 = 0x0003f34c; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot0 = 0x0003f350; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot1 = 0x0003f354; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot2 = 0x0003f358; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot3 = 0x0003f35c; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot0 = 0x0003f360; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot1 = 0x0003f364; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot2 = 0x0003f368; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot3 = 0x0003f36c; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot0 = 0x0003f370; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot1 = 0x0003f374; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot2 = 0x0003f378; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot3 = 0x0003f37c; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot0 = 0x0003f380; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot1 = 0x0003f384; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot2 = 0x0003f388; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot3 = 0x0003f38c; +// Stream Switch Deterministic Merge Arbiter:0 Slave:0,1 +const unsigned int cm_stream_switch_deterministic_merge_arb0_slave0_1 = 0x0003f800; +// Stream Switch Deterministic Merge Arbiter:0 Slave:2,3 +const unsigned int cm_stream_switch_deterministic_merge_arb0_slave2_3 = 0x0003f804; +// Stream Switch Deterministic Merge Arbiter:0 Control +const unsigned int cm_stream_switch_deterministic_merge_arb0_ctrl = 0x0003f808; +// Stream Switch Deterministic Merge Arbiter:1 Slave:0,1 +const unsigned int cm_stream_switch_deterministic_merge_arb1_slave0_1 = 0x0003f810; +// Stream Switch Deterministic Merge Arbiter:1 Slave:2,3 +const unsigned int cm_stream_switch_deterministic_merge_arb1_slave2_3 = 0x0003f814; +// Stream Switch Deterministic Merge Arbiter:1 Control +const unsigned int cm_stream_switch_deterministic_merge_arb1_ctrl = 0x0003f818; +// Select Stream Switch Ports for event generation +const unsigned int cm_stream_switch_event_port_selection_0 = 0x0003ff00; +// Select Stream Switch Ports for event generation +const unsigned int cm_stream_switch_event_port_selection_1 = 0x0003ff04; +// Status bits for Parity errors on stream switch ports +const unsigned int cm_stream_switch_parity_status = 0x0003ff10; +// Injection of Parity errors on stream switch ports +const unsigned int cm_stream_switch_parity_injection = 0x0003ff20; +// Status of control packet handling +const unsigned int cm_tile_control_packet_handler_status = 0x0003ff30; +// Status of Stream Switch Adaptive Clock Gate Status +const unsigned int cm_stream_switch_adaptive_clock_gate_status = 0x0003ff34; +// Status of Stream Switch Adaptive Clock Gate Abort Period +const unsigned int cm_stream_switch_adaptive_clock_gate_abort_period = 0x0003ff38; +// Control clock gating of modules (privileged) +const unsigned int cm_module_clock_control = 0x00060000; +// Reset of modules (privileged) +const unsigned int cm_module_reset_control = 0x00060010; + + +// Register definitions for MM +// ################################### +// Performance Counters Start and Stop Events +const unsigned int mm_performance_control0 = 0x00011000; +// Performance Counters Reset Events +const unsigned int mm_performance_control1 = 0x00011008; +// Performance Counter0 +const unsigned int mm_performance_counter0 = 0x00011020; +// Performance Counter1 +const unsigned int mm_performance_counter1 = 0x00011024; +// Performance Counter0 Event Value. +const unsigned int mm_performance_counter0_event_value = 0x00011080; +// Performance Counter1 Event Value. +const unsigned int mm_performance_counter1_event_value = 0x00011084; +// Inhibits check bits (parity or ECC) update to memory on writes +const unsigned int mm_checkbit_error_generation = 0x00012000; +// ECC Scrubbing Event +const unsigned int mm_ecc_scrubbing_event = 0x00012110; +// ECC Failing Address +const unsigned int mm_ecc_failing_address = 0x00012120; +// Parity Failing Address +const unsigned int mm_parity_failing_address = 0x00012124; +// Control of Internal Timer +const unsigned int mm_timer_control = 0x00014000; +// Generate an internal event +const unsigned int mm_event_generate = 0x00014008; +// Control of which Internal Event to Broadcast0 +const unsigned int mm_event_broadcast0 = 0x00014010; +// Control of which Internal Event to Broadcast1 +const unsigned int mm_event_broadcast1 = 0x00014014; +// Control of which Internal Event to Broadcast2 +const unsigned int mm_event_broadcast2 = 0x00014018; +// Control of which Internal Event to Broadcast3 +const unsigned int mm_event_broadcast3 = 0x0001401c; +// Control of which Internal Event to Broadcast4 +const unsigned int mm_event_broadcast4 = 0x00014020; +// Control of which Internal Event to Broadcast5 +const unsigned int mm_event_broadcast5 = 0x00014024; +// Control of which Internal Event to Broadcast6 +const unsigned int mm_event_broadcast6 = 0x00014028; +// Control of which Internal Event to Broadcast7 +const unsigned int mm_event_broadcast7 = 0x0001402c; +// Control of which Internal Event to Broadcast8 +const unsigned int mm_event_broadcast8 = 0x00014030; +// Control of which Internal Event to Broadcast9 +const unsigned int mm_event_broadcast9 = 0x00014034; +// Control of which Internal Event to Broadcast10 +const unsigned int mm_event_broadcast10 = 0x00014038; +// Control of which Internal Event to Broadcast11 +const unsigned int mm_event_broadcast11 = 0x0001403c; +// Control of which Internal Event to Broadcast12 +const unsigned int mm_event_broadcast12 = 0x00014040; +// Control of which Internal Event to Broadcast13 +const unsigned int mm_event_broadcast13 = 0x00014044; +// Control of which Internal Event to Broadcast14 +const unsigned int mm_event_broadcast14 = 0x00014048; +// Control of which Internal Event to Broadcast15 +const unsigned int mm_event_broadcast15 = 0x0001404c; +// Set block of broadcast signals to South +const unsigned int mm_event_broadcast_block_south_set = 0x00014050; +// Clear block of broadcast signals to South +const unsigned int mm_event_broadcast_block_south_clr = 0x00014054; +// Current value of block for broadcast signals to South +const unsigned int mm_event_broadcast_block_south_value = 0x00014058; +// Set block of broadcast signals to West +const unsigned int mm_event_broadcast_block_west_set = 0x00014060; +// Clear block of broadcast signals to West +const unsigned int mm_event_broadcast_block_west_clr = 0x00014064; +// Current value of block for broadcast signals to West +const unsigned int mm_event_broadcast_block_west_value = 0x00014068; +// Set block of broadcast signals to North +const unsigned int mm_event_broadcast_block_north_set = 0x00014070; +// Clear block of broadcast signals to North +const unsigned int mm_event_broadcast_block_north_clr = 0x00014074; +// Current value of block for broadcast signals to North +const unsigned int mm_event_broadcast_block_north_value = 0x00014078; +// Set block of broadcast signals to East +const unsigned int mm_event_broadcast_block_east_set = 0x00014080; +// Clear block of broadcast signals to East +const unsigned int mm_event_broadcast_block_east_clr = 0x00014084; +// Current value of block for broadcast signals to East +const unsigned int mm_event_broadcast_block_east_value = 0x00014088; +// Control of Trace +const unsigned int mm_trace_control0 = 0x000140d0; +// Control of Trace packet configuration +const unsigned int mm_trace_control1 = 0x000140d4; +// Status of trace engine +const unsigned int mm_trace_status = 0x000140d8; +// Control of which Internal Event to Trace +const unsigned int mm_trace_event0 = 0x000140e0; +// Control of which Internal Event to Trace +const unsigned int mm_trace_event1 = 0x000140e4; +// Internal Timer Event Value. +const unsigned int mm_timer_trig_event_low_value = 0x000140f0; +// Internal Timer Event Value. +const unsigned int mm_timer_trig_event_high_value = 0x000140f4; +// Internal Timer Low part Value. +const unsigned int mm_timer_low = 0x000140f8; +// Internal Timer High part Value. +const unsigned int mm_timer_high = 0x000140fc; +// Define Watchpoint0 +const unsigned int mm_watchpoint0 = 0x00014100; +// Define Watchpoint1 +const unsigned int mm_watchpoint1 = 0x00014104; +// Internal event status register0 +const unsigned int mm_event_status0 = 0x00014200; +// Internal event status register1 +const unsigned int mm_event_status1 = 0x00014204; +// Internal event status register2 +const unsigned int mm_event_status2 = 0x00014208; +// Internal event status register3 +const unsigned int mm_event_status3 = 0x0001420c; +// Reserved +const unsigned int mm_reserved0 = 0x00014210; +// Reserved +const unsigned int mm_reserved1 = 0x00014214; +// Reserved +const unsigned int mm_reserved2 = 0x00014218; +// Reserved +const unsigned int mm_reserved3 = 0x0001421c; +// Combo events input events +const unsigned int mm_combo_event_inputs = 0x00014400; +// Combo events input events +const unsigned int mm_combo_event_control = 0x00014404; +// Configuration for edge detection events +const unsigned int mm_edge_detection_event_control = 0x00014408; +// Event enable for Group 0 +const unsigned int mm_event_group_0_enable = 0x00014500; +// Event enable for Watchpoint Group +const unsigned int mm_event_group_watchpoint_enable = 0x00014504; +// Event enable for DMA Group +const unsigned int mm_event_group_dma_enable = 0x00014508; +// Event enable for Lock Group +const unsigned int mm_event_group_lock_enable = 0x0001450c; +// Event enable for Memory Conflict Group +const unsigned int mm_event_group_memory_conflict_enable = 0x00014510; +// Event enable for Error Group +const unsigned int mm_event_group_error_enable = 0x00014514; +// Event enable for Broadcast Group +const unsigned int mm_event_group_broadcast_enable = 0x00014518; +// Event enable for User Group +const unsigned int mm_event_group_user_event_enable = 0x0001451c; +// Spare register +const unsigned int mm_spare_reg = 0x00016000; +// Control for memory (privileged) +const unsigned int mm_memory_control = 0x00016010; +// DMA BD0 0 +const unsigned int mm_dma_bd0_0 = 0x0001d000; +// DMA BD0 1 +const unsigned int mm_dma_bd0_1 = 0x0001d004; +// DMA BD0 2 +const unsigned int mm_dma_bd0_2 = 0x0001d008; +// DMA BD0 3 +const unsigned int mm_dma_bd0_3 = 0x0001d00c; +// DMA BD0 4 +const unsigned int mm_dma_bd0_4 = 0x0001d010; +// DMA BD0 5 +const unsigned int mm_dma_bd0_5 = 0x0001d014; +// DMA BD1 0 +const unsigned int mm_dma_bd1_0 = 0x0001d020; +// DMA BD1 1 +const unsigned int mm_dma_bd1_1 = 0x0001d024; +// DMA BD1 2 +const unsigned int mm_dma_bd1_2 = 0x0001d028; +// DMA BD1 3 +const unsigned int mm_dma_bd1_3 = 0x0001d02c; +// DMA BD1 4 +const unsigned int mm_dma_bd1_4 = 0x0001d030; +// DMA BD1 5 +const unsigned int mm_dma_bd1_5 = 0x0001d034; +// DMA BD2 0 +const unsigned int mm_dma_bd2_0 = 0x0001d040; +// DMA BD2 1 +const unsigned int mm_dma_bd2_1 = 0x0001d044; +// DMA BD2 2 +const unsigned int mm_dma_bd2_2 = 0x0001d048; +// DMA BD2 3 +const unsigned int mm_dma_bd2_3 = 0x0001d04c; +// DMA BD2 4 +const unsigned int mm_dma_bd2_4 = 0x0001d050; +// DMA BD2 5 +const unsigned int mm_dma_bd2_5 = 0x0001d054; +// DMA BD3 0 +const unsigned int mm_dma_bd3_0 = 0x0001d060; +// DMA BD3 1 +const unsigned int mm_dma_bd3_1 = 0x0001d064; +// DMA BD3 2 +const unsigned int mm_dma_bd3_2 = 0x0001d068; +// DMA BD3 3 +const unsigned int mm_dma_bd3_3 = 0x0001d06c; +// DMA BD3 4 +const unsigned int mm_dma_bd3_4 = 0x0001d070; +// DMA BD3 5 +const unsigned int mm_dma_bd3_5 = 0x0001d074; +// DMA BD4 0 +const unsigned int mm_dma_bd4_0 = 0x0001d080; +// DMA BD4 1 +const unsigned int mm_dma_bd4_1 = 0x0001d084; +// DMA BD4 2 +const unsigned int mm_dma_bd4_2 = 0x0001d088; +// DMA BD4 3 +const unsigned int mm_dma_bd4_3 = 0x0001d08c; +// DMA BD4 4 +const unsigned int mm_dma_bd4_4 = 0x0001d090; +// DMA BD4 5 +const unsigned int mm_dma_bd4_5 = 0x0001d094; +// DMA BD5 0 +const unsigned int mm_dma_bd5_0 = 0x0001d0a0; +// DMA BD5 1 +const unsigned int mm_dma_bd5_1 = 0x0001d0a4; +// DMA BD5 2 +const unsigned int mm_dma_bd5_2 = 0x0001d0a8; +// DMA BD5 3 +const unsigned int mm_dma_bd5_3 = 0x0001d0ac; +// DMA BD5 4 +const unsigned int mm_dma_bd5_4 = 0x0001d0b0; +// DMA BD5 5 +const unsigned int mm_dma_bd5_5 = 0x0001d0b4; +// DMA BD6 0 +const unsigned int mm_dma_bd6_0 = 0x0001d0c0; +// DMA BD6 1 +const unsigned int mm_dma_bd6_1 = 0x0001d0c4; +// DMA BD6 2 +const unsigned int mm_dma_bd6_2 = 0x0001d0c8; +// DMA BD6 3 +const unsigned int mm_dma_bd6_3 = 0x0001d0cc; +// DMA BD6 4 +const unsigned int mm_dma_bd6_4 = 0x0001d0d0; +// DMA BD6 5 +const unsigned int mm_dma_bd6_5 = 0x0001d0d4; +// DMA BD7 0 +const unsigned int mm_dma_bd7_0 = 0x0001d0e0; +// DMA BD7 1 +const unsigned int mm_dma_bd7_1 = 0x0001d0e4; +// DMA BD7 2 +const unsigned int mm_dma_bd7_2 = 0x0001d0e8; +// DMA BD7 3 +const unsigned int mm_dma_bd7_3 = 0x0001d0ec; +// DMA BD7 4 +const unsigned int mm_dma_bd7_4 = 0x0001d0f0; +// DMA BD7 5 +const unsigned int mm_dma_bd7_5 = 0x0001d0f4; +// DMA BD8 0 +const unsigned int mm_dma_bd8_0 = 0x0001d100; +// DMA BD8 1 +const unsigned int mm_dma_bd8_1 = 0x0001d104; +// DMA BD8 2 +const unsigned int mm_dma_bd8_2 = 0x0001d108; +// DMA BD8 3 +const unsigned int mm_dma_bd8_3 = 0x0001d10c; +// DMA BD8 4 +const unsigned int mm_dma_bd8_4 = 0x0001d110; +// DMA BD8 5 +const unsigned int mm_dma_bd8_5 = 0x0001d114; +// DMA BD9 0 +const unsigned int mm_dma_bd9_0 = 0x0001d120; +// DMA BD9 1 +const unsigned int mm_dma_bd9_1 = 0x0001d124; +// DMA BD9 2 +const unsigned int mm_dma_bd9_2 = 0x0001d128; +// DMA BD9 3 +const unsigned int mm_dma_bd9_3 = 0x0001d12c; +// DMA BD9 4 +const unsigned int mm_dma_bd9_4 = 0x0001d130; +// DMA BD9 5 +const unsigned int mm_dma_bd9_5 = 0x0001d134; +// DMA BD10 0 +const unsigned int mm_dma_bd10_0 = 0x0001d140; +// DMA BD10 1 +const unsigned int mm_dma_bd10_1 = 0x0001d144; +// DMA BD10 2 +const unsigned int mm_dma_bd10_2 = 0x0001d148; +// DMA BD10 3 +const unsigned int mm_dma_bd10_3 = 0x0001d14c; +// DMA BD10 4 +const unsigned int mm_dma_bd10_4 = 0x0001d150; +// DMA BD10 5 +const unsigned int mm_dma_bd10_5 = 0x0001d154; +// DMA BD11 01 +const unsigned int mm_dma_bd11_0 = 0x0001d160; +// DMA BD11 1 +const unsigned int mm_dma_bd11_1 = 0x0001d164; +// DMA BD11 2 +const unsigned int mm_dma_bd11_2 = 0x0001d168; +// DMA BD11 3 +const unsigned int mm_dma_bd11_3 = 0x0001d16c; +// DMA BD11 4 +const unsigned int mm_dma_bd11_4 = 0x0001d170; +// DMA BD11 5 +const unsigned int mm_dma_bd11_5 = 0x0001d174; +// DMA BD12 01 +const unsigned int mm_dma_bd12_0 = 0x0001d180; +// DMA BD12 1 +const unsigned int mm_dma_bd12_1 = 0x0001d184; +// DMA BD12 2 +const unsigned int mm_dma_bd12_2 = 0x0001d188; +// DMA BD12 3 +const unsigned int mm_dma_bd12_3 = 0x0001d18c; +// DMA BD12 4 +const unsigned int mm_dma_bd12_4 = 0x0001d190; +// DMA BD12 5 +const unsigned int mm_dma_bd12_5 = 0x0001d194; +// DMA BD13 01 +const unsigned int mm_dma_bd13_0 = 0x0001d1a0; +// DMA BD13 1 +const unsigned int mm_dma_bd13_1 = 0x0001d1a4; +// DMA BD13 2 +const unsigned int mm_dma_bd13_2 = 0x0001d1a8; +// DMA BD13 3 +const unsigned int mm_dma_bd13_3 = 0x0001d1ac; +// DMA BD13 4 +const unsigned int mm_dma_bd13_4 = 0x0001d1b0; +// DMA BD13 5 +const unsigned int mm_dma_bd13_5 = 0x0001d1b4; +// DMA BD14 01 +const unsigned int mm_dma_bd14_0 = 0x0001d1c0; +// DMA BD14 1 +const unsigned int mm_dma_bd14_1 = 0x0001d1c4; +// DMA BD14 2 +const unsigned int mm_dma_bd14_2 = 0x0001d1c8; +// DMA BD14 3 +const unsigned int mm_dma_bd14_3 = 0x0001d1cc; +// DMA BD14 4 +const unsigned int mm_dma_bd14_4 = 0x0001d1d0; +// DMA BD14 5 +const unsigned int mm_dma_bd14_5 = 0x0001d1d4; +// DMA BD15 01 +const unsigned int mm_dma_bd15_0 = 0x0001d1e0; +// DMA BD15 1 +const unsigned int mm_dma_bd15_1 = 0x0001d1e4; +// DMA BD15 2 +const unsigned int mm_dma_bd15_2 = 0x0001d1e8; +// DMA BD15 3 +const unsigned int mm_dma_bd15_3 = 0x0001d1ec; +// DMA BD15 4 +const unsigned int mm_dma_bd15_4 = 0x0001d1f0; +// DMA BD15 5 +const unsigned int mm_dma_bd15_5 = 0x0001d1f4; +// DMA Control Register S2MM Ch0 +const unsigned int mm_dma_s2mm_0_ctrl = 0x0001de00; +// DMA Control Register S2MM Ch0 +const unsigned int mm_dma_s2mm_0_start_queue = 0x0001de04; +// DMA Control Register S2MM Ch1 +const unsigned int mm_dma_s2mm_1_ctrl = 0x0001de08; +// DMA Control Register S2MM Ch1 +const unsigned int mm_dma_s2mm_1_start_queue = 0x0001de0c; +// DMA Control Register MM2S Ch0 +const unsigned int mm_dma_mm2s_0_ctrl = 0x0001de10; +// DMA Control Register MM2S Ch0 +const unsigned int mm_dma_mm2s_0_start_queue = 0x0001de14; +// DMA Control Register MM2S Ch1 +const unsigned int mm_dma_mm2s_1_ctrl = 0x0001de18; +// DMA Control Register MM2S Ch1 +const unsigned int mm_dma_mm2s_1_start_queue = 0x0001de1c; +// DMA S2MM Status Register Ch0 +const unsigned int mm_dma_s2mm_status_0 = 0x0001df00; +// DMA S2MM Status Register Ch1 +const unsigned int mm_dma_s2mm_status_1 = 0x0001df04; +// DMA MM2S Status Register Ch0 +const unsigned int mm_dma_mm2s_status_0 = 0x0001df10; +// DMA MM2S Status Register Ch1 +const unsigned int mm_dma_mm2s_status_1 = 0x0001df14; +// DMA S2MM Current Write Count Ch0 +const unsigned int mm_dma_s2mm_current_write_count_0 = 0x0001df18; +// DMA S2MM Current Write Count Ch1 +const unsigned int mm_dma_s2mm_current_write_count_1 = 0x0001df1c; +// DMA S2MM FoT Count FIFO Pop Ch0 +const unsigned int mm_dma_s2mm_fot_count_fifo_pop_0 = 0x0001df20; +// DMA S2MM FoT Count FIFO Pop Ch1 +const unsigned int mm_dma_s2mm_fot_count_fifo_pop_1 = 0x0001df24; +// Value of lock 0 +const unsigned int mm_lock0_value = 0x0001f000; +// Value of lock 1 +const unsigned int mm_lock1_value = 0x0001f010; +// Value of lock 2 +const unsigned int mm_lock2_value = 0x0001f020; +// Value of lock 3 +const unsigned int mm_lock3_value = 0x0001f030; +// Value of lock 4 +const unsigned int mm_lock4_value = 0x0001f040; +// Value of lock 5 +const unsigned int mm_lock5_value = 0x0001f050; +// Value of lock 6 +const unsigned int mm_lock6_value = 0x0001f060; +// Value of lock 7 +const unsigned int mm_lock7_value = 0x0001f070; +// Value of lock 8 +const unsigned int mm_lock8_value = 0x0001f080; +// Value of lock 9 +const unsigned int mm_lock9_value = 0x0001f090; +// Value of lock 10 +const unsigned int mm_lock10_value = 0x0001f0a0; +// Value of lock 11 +const unsigned int mm_lock11_value = 0x0001f0b0; +// Value of lock 12 +const unsigned int mm_lock12_value = 0x0001f0c0; +// Value of lock 13 +const unsigned int mm_lock13_value = 0x0001f0d0; +// Value of lock 14 +const unsigned int mm_lock14_value = 0x0001f0e0; +// Value of lock 15 +const unsigned int mm_lock15_value = 0x0001f0f0; +// Select lock for lock event generation 0 +const unsigned int mm_locks_event_selection_0 = 0x0001f100; +// Select lock for lock event generation 1 +const unsigned int mm_locks_event_selection_1 = 0x0001f104; +// Select lock for lock event generation 2 +const unsigned int mm_locks_event_selection_2 = 0x0001f108; +// Select lock for lock event generation 3 +const unsigned int mm_locks_event_selection_3 = 0x0001f10c; +// Select lock for lock event generation 4 +const unsigned int mm_locks_event_selection_4 = 0x0001f110; +// Select lock for lock event generation 5 +const unsigned int mm_locks_event_selection_5 = 0x0001f114; +// Select lock for lock event generation 6 +const unsigned int mm_locks_event_selection_6 = 0x0001f118; +// Select lock for lock event generation 7 +const unsigned int mm_locks_event_selection_7 = 0x0001f11c; +// Status bits for lock overflow, write to clear +const unsigned int mm_locks_overflow = 0x0001f120; +// Status bits for lock underflow, write to clear +const unsigned int mm_locks_underflow = 0x0001f128; +// Lock Request. 16kB address space: = 0x40000 - = 0x43FFC, Lock_Id [13:10], Acq_Rel (9), Change_Value [8:2] +const unsigned int mm_lock_request = 0x00040000; + +// Register definitions for MEM +// ################################### +// Performance Counters 1-0 Start and Stop Events +const unsigned int mem_performance_control0 = 0x00091000; +// Performance Counters 3-2 Start and Stop Events +const unsigned int mem_performance_control1 = 0x00091004; +// Performance Counters Reset Events +const unsigned int mem_performance_control2 = 0x00091008; +// Performance Counter0 +const unsigned int mem_performance_counter0 = 0x00091020; +// Performance Counter1 +const unsigned int mem_performance_counter1 = 0x00091024; +// Performance Counter2 +const unsigned int mem_performance_counter2 = 0x00091028; +// Performance Counter3 +const unsigned int mem_performance_counter3 = 0x0009102c; +// Performance Counter0 Event Value. +const unsigned int mem_performance_counter0_event_value = 0x00091080; +// Performance Counter1 Event Value. +const unsigned int mem_performance_counter1_event_value = 0x00091084; +// Performance Counter2 Event Value. +const unsigned int mem_performance_counter2_event_value = 0x00091088; +// Performance Counter3 Event Value. +const unsigned int mem_performance_counter3_event_value = 0x0009108c; +// Inhibits ECC check bits update to memory on writes +const unsigned int mem_checkbit_error_generation = 0x00092000; +// ECC Scrubbing Event +const unsigned int mem_ecc_scrubbing_event = 0x00092110; +// ECC Failing Address +const unsigned int mem_ecc_failing_address = 0x00092120; +// Control of Internal Timer +const unsigned int mem_timer_control = 0x00094000; +// Generate an internal event +const unsigned int mem_event_generate = 0x00094008; +// Control of which Internal Event to Broadcast0 +const unsigned int mem_event_broadcast0 = 0x00094010; +// Control of which Internal Event to Broadcast1 +const unsigned int mem_event_broadcast1 = 0x00094014; +// Control of which Internal Event to Broadcast2 +const unsigned int mem_event_broadcast2 = 0x00094018; +// Control of which Internal Event to Broadcast3 +const unsigned int mem_event_broadcast3 = 0x0009401c; +// Control of which Internal Event to Broadcast4 +const unsigned int mem_event_broadcast4 = 0x00094020; +// Control of which Internal Event to Broadcast5 +const unsigned int mem_event_broadcast5 = 0x00094024; +// Control of which Internal Event to Broadcast6 +const unsigned int mem_event_broadcast6 = 0x00094028; +// Control of which Internal Event to Broadcast7 +const unsigned int mem_event_broadcast7 = 0x0009402c; +// Control of which Internal Event to Broadcast8 +const unsigned int mem_event_broadcast8 = 0x00094030; +// Control of which Internal Event to Broadcast9 +const unsigned int mem_event_broadcast9 = 0x00094034; +// Control of which Internal Event to Broadcast10 +const unsigned int mem_event_broadcast10 = 0x00094038; +// Control of which Internal Event to Broadcast11 +const unsigned int mem_event_broadcast11 = 0x0009403c; +// Control of which Internal Event to Broadcast12 +const unsigned int mem_event_broadcast12 = 0x00094040; +// Control of which Internal Event to Broadcast13 +const unsigned int mem_event_broadcast13 = 0x00094044; +// Control of which Internal Event to Broadcast14 +const unsigned int mem_event_broadcast14 = 0x00094048; +// Control of which Internal Event to Broadcast15 +const unsigned int mem_event_broadcast15 = 0x0009404c; +// Set block of broadcast signals to South +const unsigned int mem_event_broadcast_a_block_south_set = 0x00094050; +// Clear block of broadcast signals to South +const unsigned int mem_event_broadcast_a_block_south_clr = 0x00094054; +// Current value of block for broadcast signals to South +const unsigned int mem_event_broadcast_a_block_south_value = 0x00094058; +// Set block of broadcast switch A signals to West +const unsigned int mem_event_broadcast_a_block_west_set = 0x00094060; +// Clear block of broadcast switch A signals to West +const unsigned int mem_event_broadcast_a_block_west_clr = 0x00094064; +// Current value of block for broadcast switch A signals to West +const unsigned int mem_event_broadcast_a_block_west_value = 0x00094068; +// Set block of broadcast switch A signals to North +const unsigned int mem_event_broadcast_a_block_north_set = 0x00094070; +// Clear block of broadcast switch A signals to North +const unsigned int mem_event_broadcast_a_block_north_clr = 0x00094074; +// Current value of block for broadcast switch A signals to North +const unsigned int mem_event_broadcast_a_block_north_value = 0x00094078; +// Set block of broadcast switch A signals to East +const unsigned int mem_event_broadcast_a_block_east_set = 0x00094080; +// Clear block of broadcast switch A signals to East +const unsigned int mem_event_broadcast_a_block_east_clr = 0x00094084; +// Current value of block for broadcast switch A signals to East +const unsigned int mem_event_broadcast_a_block_east_value = 0x00094088; +// Set block of broadcast switch B signals to South +const unsigned int mem_event_broadcast_b_block_south_set = 0x00094090; +// Clear block of broadcast switch B signals to South +const unsigned int mem_event_broadcast_b_block_south_clr = 0x00094094; +// Current value of block for broadcast switch B signals to South +const unsigned int mem_event_broadcast_b_block_south_value = 0x00094098; +// Set block of broadcast switch B signals to West +const unsigned int mem_event_broadcast_b_block_west_set = 0x000940a0; +// Clear block of broadcast switch B signals to West +const unsigned int mem_event_broadcast_b_block_west_clr = 0x000940a4; +// Current value of block for broadcast switch B signals to West +const unsigned int mem_event_broadcast_b_block_west_value = 0x000940a8; +// Set block of broadcast switch B signals to North +const unsigned int mem_event_broadcast_b_block_north_set = 0x000940b0; +// Clear block of broadcast switch B signals to North +const unsigned int mem_event_broadcast_b_block_north_clr = 0x000940b4; +// Current value of block for broadcast switch B signals to North +const unsigned int mem_event_broadcast_b_block_north_value = 0x000940b8; +// Set block of broadcast switch B signals to East +const unsigned int mem_event_broadcast_b_block_east_set = 0x000940c0; +// Clear block of broadcast switch B signals to East +const unsigned int mem_event_broadcast_b_block_east_clr = 0x000940c4; +// Current value of block for broadcast switch B signals to East +const unsigned int mem_event_broadcast_b_block_east_value = 0x000940c8; +// Control of Trace +const unsigned int mem_trace_control0 = 0x000940d0; +// Control of Trace packet configuration +const unsigned int mem_trace_control1 = 0x000940d4; +// Status of trace engine +const unsigned int mem_trace_status = 0x000940d8; +// Control of which Internal Event to Trace +const unsigned int mem_trace_event0 = 0x000940e0; +// Control of which Internal Event to Trace +const unsigned int mem_trace_event1 = 0x000940e4; +// Internal Timer Event Value. +const unsigned int mem_timer_trig_event_low_value = 0x000940f0; +// Internal Timer Event Value. +const unsigned int mem_timer_trig_event_high_value = 0x000940f4; +// Internal Timer Low part Value. +const unsigned int mem_timer_low = 0x000940f8; +// Internal Timer High part Value. +const unsigned int mem_timer_high = 0x000940fc; +// Define Watchpoint0 +const unsigned int mem_watchpoint0 = 0x00094100; +// Define Watchpoint1 +const unsigned int mem_watchpoint1 = 0x00094104; +// Define Watchpoint2 +const unsigned int mem_watchpoint2 = 0x00094108; +// Define Watchpoint3 +const unsigned int mem_watchpoint3 = 0x0009410c; +// Internal event status register0 +const unsigned int mem_event_status0 = 0x00094200; +// Internal event status register1 +const unsigned int mem_event_status1 = 0x00094204; +// Internal event status register2 +const unsigned int mem_event_status2 = 0x00094208; +// Internal event status register3 +const unsigned int mem_event_status3 = 0x0009420c; +// Internal event status register4 +const unsigned int mem_event_status4 = 0x00094210; +// Internal event status register5 +const unsigned int mem_event_status5 = 0x00094214; +// Reserved +const unsigned int mem_reserved0 = 0x00094220; +// Reserved +const unsigned int mem_reserved1 = 0x00094224; +// Reserved +const unsigned int mem_reserved2 = 0x00094228; +// Reserved +const unsigned int mem_reserved3 = 0x0009422c; +// Combo events input events +const unsigned int mem_combo_event_inputs = 0x00094400; +// Combo events input events +const unsigned int mem_combo_event_control = 0x00094404; +// Configuration for edge detection events +const unsigned int mem_edge_detection_event_control = 0x00094408; +// Event enable for Group 0 +const unsigned int mem_event_group_0_enable = 0x00094500; +// Event enable for Watchpoint Group +const unsigned int mem_event_group_watchpoint_enable = 0x00094504; +// Event enable for DMA Group +const unsigned int mem_event_group_dma_enable = 0x00094508; +// Event enable for Lock Group +const unsigned int mem_event_group_lock_enable = 0x0009450c; +// Event enable for Stream Switch Group +const unsigned int mem_event_group_stream_switch_enable = 0x00094510; +// Event enable for Memory Conflict Group +const unsigned int mem_event_group_memory_conflict_enable = 0x00094514; +// Event enable for Error Group +const unsigned int mem_event_group_error_enable = 0x00094518; +// Event enable for Broadcast Group +const unsigned int mem_event_group_broadcast_enable = 0x0009451c; +// Event enable for User Group +const unsigned int mem_event_group_user_event_enable = 0x00094520; +// Spare register +const unsigned int mem_spare_reg = 0x00096000; +// Tile control register +const unsigned int mem_tile_control = 0x00096030; +// Trigger for CSSD +const unsigned int mem_cssd_trigger = 0x00096040; +// Control for memory (privileged) +const unsigned int mem_memory_control = 0x00096048; +// DMA BD0 +const unsigned int mem_dma_bd0_0 = 0x000a0000; +// DMA BD0 1 +const unsigned int mem_dma_bd0_1 = 0x000a0004; +// DMA BD0 2 +const unsigned int mem_dma_bd0_2 = 0x000a0008; +// DMA BD0 3 +const unsigned int mem_dma_bd0_3 = 0x000a000c; +// DMA BD0 4 +const unsigned int mem_dma_bd0_4 = 0x000a0010; +// DMA BD0 5 +const unsigned int mem_dma_bd0_5 = 0x000a0014; +// DMA BD0 6 +const unsigned int mem_dma_bd0_6 = 0x000a0018; +// DMA BD0 7 +const unsigned int mem_dma_bd0_7 = 0x000a001c; +// DMA BD1 +const unsigned int mem_dma_bd1_0 = 0x000a0020; +// DMA BD1 1 +const unsigned int mem_dma_bd1_1 = 0x000a0024; +// DMA BD1 2 +const unsigned int mem_dma_bd1_2 = 0x000a0028; +// DMA BD1 3 +const unsigned int mem_dma_bd1_3 = 0x000a002c; +// DMA BD1 4 +const unsigned int mem_dma_bd1_4 = 0x000a0030; +// DMA BD1 5 +const unsigned int mem_dma_bd1_5 = 0x000a0034; +// DMA BD1 6 +const unsigned int mem_dma_bd1_6 = 0x000a0038; +// DMA BD1 7 +const unsigned int mem_dma_bd1_7 = 0x000a003c; +// DMA BD2 +const unsigned int mem_dma_bd2_0 = 0x000a0040; +// DMA BD2 1 +const unsigned int mem_dma_bd2_1 = 0x000a0044; +// DMA BD2 2 +const unsigned int mem_dma_bd2_2 = 0x000a0048; +// DMA BD2 3 +const unsigned int mem_dma_bd2_3 = 0x000a004c; +// DMA BD2 4 +const unsigned int mem_dma_bd2_4 = 0x000a0050; +// DMA BD2 5 +const unsigned int mem_dma_bd2_5 = 0x000a0054; +// DMA BD2 6 +const unsigned int mem_dma_bd2_6 = 0x000a0058; +// DMA BD2 7 +const unsigned int mem_dma_bd2_7 = 0x000a005c; +// DMA BD3 +const unsigned int mem_dma_bd3_0 = 0x000a0060; +// DMA BD3 1 +const unsigned int mem_dma_bd3_1 = 0x000a0064; +// DMA BD3 2 +const unsigned int mem_dma_bd3_2 = 0x000a0068; +// DMA BD3 3 +const unsigned int mem_dma_bd3_3 = 0x000a006c; +// DMA BD3 4 +const unsigned int mem_dma_bd3_4 = 0x000a0070; +// DMA BD3 5 +const unsigned int mem_dma_bd3_5 = 0x000a0074; +// DMA BD3 6 +const unsigned int mem_dma_bd3_6 = 0x000a0078; +// DMA BD3 7 +const unsigned int mem_dma_bd3_7 = 0x000a007c; +// DMA BD4 +const unsigned int mem_dma_bd4_0 = 0x000a0080; +// DMA BD4 1 +const unsigned int mem_dma_bd4_1 = 0x000a0084; +// DMA BD4 2 +const unsigned int mem_dma_bd4_2 = 0x000a0088; +// DMA BD4 3 +const unsigned int mem_dma_bd4_3 = 0x000a008c; +// DMA BD4 4 +const unsigned int mem_dma_bd4_4 = 0x000a0090; +// DMA BD4 5 +const unsigned int mem_dma_bd4_5 = 0x000a0094; +// DMA BD4 6 +const unsigned int mem_dma_bd4_6 = 0x000a0098; +// DMA BD4 7 +const unsigned int mem_dma_bd4_7 = 0x000a009c; +// DMA BD5 +const unsigned int mem_dma_bd5_0 = 0x000a00a0; +// DMA BD5 1 +const unsigned int mem_dma_bd5_1 = 0x000a00a4; +// DMA BD5 2 +const unsigned int mem_dma_bd5_2 = 0x000a00a8; +// DMA BD5 3 +const unsigned int mem_dma_bd5_3 = 0x000a00ac; +// DMA BD5 4 +const unsigned int mem_dma_bd5_4 = 0x000a00b0; +// DMA BD5 5 +const unsigned int mem_dma_bd5_5 = 0x000a00b4; +// DMA BD5 6 +const unsigned int mem_dma_bd5_6 = 0x000a00b8; +// DMA BD5 7 +const unsigned int mem_dma_bd5_7 = 0x000a00bc; +// DMA BD6 +const unsigned int mem_dma_bd6_0 = 0x000a00c0; +// DMA BD6 1 +const unsigned int mem_dma_bd6_1 = 0x000a00c4; +// DMA BD6 2 +const unsigned int mem_dma_bd6_2 = 0x000a00c8; +// DMA BD6 3 +const unsigned int mem_dma_bd6_3 = 0x000a00cc; +// DMA BD6 4 +const unsigned int mem_dma_bd6_4 = 0x000a00d0; +// DMA BD6 5 +const unsigned int mem_dma_bd6_5 = 0x000a00d4; +// DMA BD6 6 +const unsigned int mem_dma_bd6_6 = 0x000a00d8; +// DMA BD6 7 +const unsigned int mem_dma_bd6_7 = 0x000a00dc; +// DMA BD7 +const unsigned int mem_dma_bd7_0 = 0x000a00e0; +// DMA BD7 1 +const unsigned int mem_dma_bd7_1 = 0x000a00e4; +// DMA BD7 2 +const unsigned int mem_dma_bd7_2 = 0x000a00e8; +// DMA BD7 3 +const unsigned int mem_dma_bd7_3 = 0x000a00ec; +// DMA BD7 4 +const unsigned int mem_dma_bd7_4 = 0x000a00f0; +// DMA BD7 5 +const unsigned int mem_dma_bd7_5 = 0x000a00f4; +// DMA BD7 6 +const unsigned int mem_dma_bd7_6 = 0x000a00f8; +// DMA BD7 7 +const unsigned int mem_dma_bd7_7 = 0x000a00fc; +// DMA BD8 +const unsigned int mem_dma_bd8_0 = 0x000a0100; +// DMA BD8 1 +const unsigned int mem_dma_bd8_1 = 0x000a0104; +// DMA BD8 2 +const unsigned int mem_dma_bd8_2 = 0x000a0108; +// DMA BD8 3 +const unsigned int mem_dma_bd8_3 = 0x000a010c; +// DMA BD8 4 +const unsigned int mem_dma_bd8_4 = 0x000a0110; +// DMA BD8 5 +const unsigned int mem_dma_bd8_5 = 0x000a0114; +// DMA BD8 6 +const unsigned int mem_dma_bd8_6 = 0x000a0118; +// DMA BD8 7 +const unsigned int mem_dma_bd8_7 = 0x000a011c; +// DMA BD9 +const unsigned int mem_dma_bd9_0 = 0x000a0120; +// DMA BD9 1 +const unsigned int mem_dma_bd9_1 = 0x000a0124; +// DMA BD9 2 +const unsigned int mem_dma_bd9_2 = 0x000a0128; +// DMA BD9 3 +const unsigned int mem_dma_bd9_3 = 0x000a012c; +// DMA BD9 4 +const unsigned int mem_dma_bd9_4 = 0x000a0130; +// DMA BD9 5 +const unsigned int mem_dma_bd9_5 = 0x000a0134; +// DMA BD9 6 +const unsigned int mem_dma_bd9_6 = 0x000a0138; +// DMA BD9 7 +const unsigned int mem_dma_bd9_7 = 0x000a013c; +// DMA BD1 +const unsigned int mem_dma_bd10_0 = 0x000a0140; +// DMA BD10 1 +const unsigned int mem_dma_bd10_1 = 0x000a0144; +// DMA BD10 2 +const unsigned int mem_dma_bd10_2 = 0x000a0148; +// DMA BD10 3 +const unsigned int mem_dma_bd10_3 = 0x000a014c; +// DMA BD10 4 +const unsigned int mem_dma_bd10_4 = 0x000a0150; +// DMA BD10 5 +const unsigned int mem_dma_bd10_5 = 0x000a0154; +// DMA BD10 6 +const unsigned int mem_dma_bd10_6 = 0x000a0158; +// DMA BD10 7 +const unsigned int mem_dma_bd10_7 = 0x000a015c; +// DMA BD11 +const unsigned int mem_dma_bd11_0 = 0x000a0160; +// DMA BD11 1 +const unsigned int mem_dma_bd11_1 = 0x000a0164; +// DMA BD11 2 +const unsigned int mem_dma_bd11_2 = 0x000a0168; +// DMA BD11 3 +const unsigned int mem_dma_bd11_3 = 0x000a016c; +// DMA BD11 4 +const unsigned int mem_dma_bd11_4 = 0x000a0170; +// DMA BD11 5 +const unsigned int mem_dma_bd11_5 = 0x000a0174; +// DMA BD11 6 +const unsigned int mem_dma_bd11_6 = 0x000a0178; +// DMA BD11 7 +const unsigned int mem_dma_bd11_7 = 0x000a017c; +// DMA BD12 +const unsigned int mem_dma_bd12_0 = 0x000a0180; +// DMA BD12 1 +const unsigned int mem_dma_bd12_1 = 0x000a0184; +// DMA BD12 2 +const unsigned int mem_dma_bd12_2 = 0x000a0188; +// DMA BD12 3 +const unsigned int mem_dma_bd12_3 = 0x000a018c; +// DMA BD12 4 +const unsigned int mem_dma_bd12_4 = 0x000a0190; +// DMA BD12 5 +const unsigned int mem_dma_bd12_5 = 0x000a0194; +// DMA BD12 6 +const unsigned int mem_dma_bd12_6 = 0x000a0198; +// DMA BD12 7 +const unsigned int mem_dma_bd12_7 = 0x000a019c; +// DMA BD13 +const unsigned int mem_dma_bd13_0 = 0x000a01a0; +// DMA BD13 1 +const unsigned int mem_dma_bd13_1 = 0x000a01a4; +// DMA BD13 2 +const unsigned int mem_dma_bd13_2 = 0x000a01a8; +// DMA BD13 3 +const unsigned int mem_dma_bd13_3 = 0x000a01ac; +// DMA BD13 4 +const unsigned int mem_dma_bd13_4 = 0x000a01b0; +// DMA BD13 5 +const unsigned int mem_dma_bd13_5 = 0x000a01b4; +// DMA BD13 6 +const unsigned int mem_dma_bd13_6 = 0x000a01b8; +// DMA BD13 7 +const unsigned int mem_dma_bd13_7 = 0x000a01bc; +// DMA BD14 +const unsigned int mem_dma_bd14_0 = 0x000a01c0; +// DMA BD14 1 +const unsigned int mem_dma_bd14_1 = 0x000a01c4; +// DMA BD14 2 +const unsigned int mem_dma_bd14_2 = 0x000a01c8; +// DMA BD14 3 +const unsigned int mem_dma_bd14_3 = 0x000a01cc; +// DMA BD14 4 +const unsigned int mem_dma_bd14_4 = 0x000a01d0; +// DMA BD14 5 +const unsigned int mem_dma_bd14_5 = 0x000a01d4; +// DMA BD14 6 +const unsigned int mem_dma_bd14_6 = 0x000a01d8; +// DMA BD14 7 +const unsigned int mem_dma_bd14_7 = 0x000a01dc; +// DMA BD15 +const unsigned int mem_dma_bd15_0 = 0x000a01e0; +// DMA BD15 1 +const unsigned int mem_dma_bd15_1 = 0x000a01e4; +// DMA BD15 2 +const unsigned int mem_dma_bd15_2 = 0x000a01e8; +// DMA BD15 3 +const unsigned int mem_dma_bd15_3 = 0x000a01ec; +// DMA BD15 4 +const unsigned int mem_dma_bd15_4 = 0x000a01f0; +// DMA BD15 5 +const unsigned int mem_dma_bd15_5 = 0x000a01f4; +// DMA BD15 6 +const unsigned int mem_dma_bd15_6 = 0x000a01f8; +// DMA BD15 7 +const unsigned int mem_dma_bd15_7 = 0x000a01fc; +// DMA BD16 +const unsigned int mem_dma_bd16_0 = 0x000a0200; +// DMA BD16 1 +const unsigned int mem_dma_bd16_1 = 0x000a0204; +// DMA BD16 2 +const unsigned int mem_dma_bd16_2 = 0x000a0208; +// DMA BD16 3 +const unsigned int mem_dma_bd16_3 = 0x000a020c; +// DMA BD16 4 +const unsigned int mem_dma_bd16_4 = 0x000a0210; +// DMA BD16 5 +const unsigned int mem_dma_bd16_5 = 0x000a0214; +// DMA BD16 6 +const unsigned int mem_dma_bd16_6 = 0x000a0218; +// DMA BD16 7 +const unsigned int mem_dma_bd16_7 = 0x000a021c; +// DMA BD17 +const unsigned int mem_dma_bd17_0 = 0x000a0220; +// DMA BD17 1 +const unsigned int mem_dma_bd17_1 = 0x000a0224; +// DMA BD17 2 +const unsigned int mem_dma_bd17_2 = 0x000a0228; +// DMA BD17 3 +const unsigned int mem_dma_bd17_3 = 0x000a022c; +// DMA BD17 4 +const unsigned int mem_dma_bd17_4 = 0x000a0230; +// DMA BD17 5 +const unsigned int mem_dma_bd17_5 = 0x000a0234; +// DMA BD17 6 +const unsigned int mem_dma_bd17_6 = 0x000a0238; +// DMA BD17 7 +const unsigned int mem_dma_bd17_7 = 0x000a023c; +// DMA BD15 +const unsigned int mem_dma_bd18_0 = 0x000a0240; +// DMA BD18 1 +const unsigned int mem_dma_bd18_1 = 0x000a0244; +// DMA BD18 2 +const unsigned int mem_dma_bd18_2 = 0x000a0248; +// DMA BD18 3 +const unsigned int mem_dma_bd18_3 = 0x000a024c; +// DMA BD18 4 +const unsigned int mem_dma_bd18_4 = 0x000a0250; +// DMA BD18 5 +const unsigned int mem_dma_bd18_5 = 0x000a0254; +// DMA BD18 6 +const unsigned int mem_dma_bd18_6 = 0x000a0258; +// DMA BD18 7 +const unsigned int mem_dma_bd18_7 = 0x000a025c; +// DMA BD19 +const unsigned int mem_dma_bd19_0 = 0x000a0260; +// DMA BD19 1 +const unsigned int mem_dma_bd19_1 = 0x000a0264; +// DMA BD19 2 +const unsigned int mem_dma_bd19_2 = 0x000a0268; +// DMA BD19 3 +const unsigned int mem_dma_bd19_3 = 0x000a026c; +// DMA BD19 4 +const unsigned int mem_dma_bd19_4 = 0x000a0270; +// DMA BD19 5 +const unsigned int mem_dma_bd19_5 = 0x000a0274; +// DMA BD19 6 +const unsigned int mem_dma_bd19_6 = 0x000a0278; +// DMA BD19 7 +const unsigned int mem_dma_bd19_7 = 0x000a027c; +// DMA BD2 +const unsigned int mem_dma_bd20_0 = 0x000a0280; +// DMA BD20 1 +const unsigned int mem_dma_bd20_1 = 0x000a0284; +// DMA BD20 2 +const unsigned int mem_dma_bd20_2 = 0x000a0288; +// DMA BD20 3 +const unsigned int mem_dma_bd20_3 = 0x000a028c; +// DMA BD20 4 +const unsigned int mem_dma_bd20_4 = 0x000a0290; +// DMA BD20 5 +const unsigned int mem_dma_bd20_5 = 0x000a0294; +// DMA BD20 6 +const unsigned int mem_dma_bd20_6 = 0x000a0298; +// DMA BD20 7 +const unsigned int mem_dma_bd20_7 = 0x000a029c; +// DMA BD21 +const unsigned int mem_dma_bd21_0 = 0x000a02a0; +// DMA BD21 1 +const unsigned int mem_dma_bd21_1 = 0x000a02a4; +// DMA BD21 2 +const unsigned int mem_dma_bd21_2 = 0x000a02a8; +// DMA BD21 3 +const unsigned int mem_dma_bd21_3 = 0x000a02ac; +// DMA BD21 4 +const unsigned int mem_dma_bd21_4 = 0x000a02b0; +// DMA BD21 5 +const unsigned int mem_dma_bd21_5 = 0x000a02b4; +// DMA BD21 6 +const unsigned int mem_dma_bd21_6 = 0x000a02b8; +// DMA BD21 7 +const unsigned int mem_dma_bd21_7 = 0x000a02bc; +// DMA BD22 +const unsigned int mem_dma_bd22_0 = 0x000a02c0; +// DMA BD22 1 +const unsigned int mem_dma_bd22_1 = 0x000a02c4; +// DMA BD22 2 +const unsigned int mem_dma_bd22_2 = 0x000a02c8; +// DMA BD22 3 +const unsigned int mem_dma_bd22_3 = 0x000a02cc; +// DMA BD22 4 +const unsigned int mem_dma_bd22_4 = 0x000a02d0; +// DMA BD22 5 +const unsigned int mem_dma_bd22_5 = 0x000a02d4; +// DMA BD22 6 +const unsigned int mem_dma_bd22_6 = 0x000a02d8; +// DMA BD22 7 +const unsigned int mem_dma_bd22_7 = 0x000a02dc; +// DMA BD23 +const unsigned int mem_dma_bd23_0 = 0x000a02e0; +// DMA BD23 1 +const unsigned int mem_dma_bd23_1 = 0x000a02e4; +// DMA BD23 2 +const unsigned int mem_dma_bd23_2 = 0x000a02e8; +// DMA BD23 3 +const unsigned int mem_dma_bd23_3 = 0x000a02ec; +// DMA BD23 4 +const unsigned int mem_dma_bd23_4 = 0x000a02f0; +// DMA BD23 5 +const unsigned int mem_dma_bd23_5 = 0x000a02f4; +// DMA BD23 6 +const unsigned int mem_dma_bd23_6 = 0x000a02f8; +// DMA BD23 7 +const unsigned int mem_dma_bd23_7 = 0x000a02fc; +// DMA BD24 +const unsigned int mem_dma_bd24_0 = 0x000a0300; +// DMA BD24 1 +const unsigned int mem_dma_bd24_1 = 0x000a0304; +// DMA BD24 2 +const unsigned int mem_dma_bd24_2 = 0x000a0308; +// DMA BD24 3 +const unsigned int mem_dma_bd24_3 = 0x000a030c; +// DMA BD24 4 +const unsigned int mem_dma_bd24_4 = 0x000a0310; +// DMA BD24 5 +const unsigned int mem_dma_bd24_5 = 0x000a0314; +// DMA BD24 6 +const unsigned int mem_dma_bd24_6 = 0x000a0318; +// DMA BD24 7 +const unsigned int mem_dma_bd24_7 = 0x000a031c; +// DMA BD25 +const unsigned int mem_dma_bd25_0 = 0x000a0320; +// DMA BD25 1 +const unsigned int mem_dma_bd25_1 = 0x000a0324; +// DMA BD25 2 +const unsigned int mem_dma_bd25_2 = 0x000a0328; +// DMA BD25 3 +const unsigned int mem_dma_bd25_3 = 0x000a032c; +// DMA BD25 4 +const unsigned int mem_dma_bd25_4 = 0x000a0330; +// DMA BD25 5 +const unsigned int mem_dma_bd25_5 = 0x000a0334; +// DMA BD25 6 +const unsigned int mem_dma_bd25_6 = 0x000a0338; +// DMA BD25 7 +const unsigned int mem_dma_bd25_7 = 0x000a033c; +// DMA BD26 +const unsigned int mem_dma_bd26_0 = 0x000a0340; +// DMA BD26 1 +const unsigned int mem_dma_bd26_1 = 0x000a0344; +// DMA BD26 2 +const unsigned int mem_dma_bd26_2 = 0x000a0348; +// DMA BD26 3 +const unsigned int mem_dma_bd26_3 = 0x000a034c; +// DMA BD26 4 +const unsigned int mem_dma_bd26_4 = 0x000a0350; +// DMA BD26 5 +const unsigned int mem_dma_bd26_5 = 0x000a0354; +// DMA BD26 6 +const unsigned int mem_dma_bd26_6 = 0x000a0358; +// DMA BD26 7 +const unsigned int mem_dma_bd26_7 = 0x000a035c; +// DMA BD27 +const unsigned int mem_dma_bd27_0 = 0x000a0360; +// DMA BD27 1 +const unsigned int mem_dma_bd27_1 = 0x000a0364; +// DMA BD27 2 +const unsigned int mem_dma_bd27_2 = 0x000a0368; +// DMA BD27 3 +const unsigned int mem_dma_bd27_3 = 0x000a036c; +// DMA BD27 4 +const unsigned int mem_dma_bd27_4 = 0x000a0370; +// DMA BD27 5 +const unsigned int mem_dma_bd27_5 = 0x000a0374; +// DMA BD27 6 +const unsigned int mem_dma_bd27_6 = 0x000a0378; +// DMA BD27 7 +const unsigned int mem_dma_bd27_7 = 0x000a037c; +// DMA BD25 +const unsigned int mem_dma_bd28_0 = 0x000a0380; +// DMA BD28 1 +const unsigned int mem_dma_bd28_1 = 0x000a0384; +// DMA BD28 2 +const unsigned int mem_dma_bd28_2 = 0x000a0388; +// DMA BD28 3 +const unsigned int mem_dma_bd28_3 = 0x000a038c; +// DMA BD28 4 +const unsigned int mem_dma_bd28_4 = 0x000a0390; +// DMA BD28 5 +const unsigned int mem_dma_bd28_5 = 0x000a0394; +// DMA BD28 6 +const unsigned int mem_dma_bd28_6 = 0x000a0398; +// DMA BD28 7 +const unsigned int mem_dma_bd28_7 = 0x000a039c; +// DMA BD29 +const unsigned int mem_dma_bd29_0 = 0x000a03a0; +// DMA BD29 1 +const unsigned int mem_dma_bd29_1 = 0x000a03a4; +// DMA BD29 2 +const unsigned int mem_dma_bd29_2 = 0x000a03a8; +// DMA BD29 3 +const unsigned int mem_dma_bd29_3 = 0x000a03ac; +// DMA BD29 4 +const unsigned int mem_dma_bd29_4 = 0x000a03b0; +// DMA BD29 5 +const unsigned int mem_dma_bd29_5 = 0x000a03b4; +// DMA BD29 6 +const unsigned int mem_dma_bd29_6 = 0x000a03b8; +// DMA BD29 7 +const unsigned int mem_dma_bd29_7 = 0x000a03bc; +// DMA BD30 +const unsigned int mem_dma_bd30_0 = 0x000a03c0; +// DMA BD30 1 +const unsigned int mem_dma_bd30_1 = 0x000a03c4; +// DMA BD30 2 +const unsigned int mem_dma_bd30_2 = 0x000a03c8; +// DMA BD30 3 +const unsigned int mem_dma_bd30_3 = 0x000a03cc; +// DMA BD30 4 +const unsigned int mem_dma_bd30_4 = 0x000a03d0; +// DMA BD30 5 +const unsigned int mem_dma_bd30_5 = 0x000a03d4; +// DMA BD30 6 +const unsigned int mem_dma_bd30_6 = 0x000a03d8; +// DMA BD30 7 +const unsigned int mem_dma_bd30_7 = 0x000a03dc; +// DMA BD31 +const unsigned int mem_dma_bd31_0 = 0x000a03e0; +// DMA BD31 1 +const unsigned int mem_dma_bd31_1 = 0x000a03e4; +// DMA BD31 2 +const unsigned int mem_dma_bd31_2 = 0x000a03e8; +// DMA BD31 3 +const unsigned int mem_dma_bd31_3 = 0x000a03ec; +// DMA BD31 4 +const unsigned int mem_dma_bd31_4 = 0x000a03f0; +// DMA BD31 5 +const unsigned int mem_dma_bd31_5 = 0x000a03f4; +// DMA BD31 6 +const unsigned int mem_dma_bd31_6 = 0x000a03f8; +// DMA BD31 7 +const unsigned int mem_dma_bd31_7 = 0x000a03fc; +// DMA BD32 +const unsigned int mem_dma_bd32_0 = 0x000a0400; +// DMA BD32 1 +const unsigned int mem_dma_bd32_1 = 0x000a0404; +// DMA BD32 2 +const unsigned int mem_dma_bd32_2 = 0x000a0408; +// DMA BD32 3 +const unsigned int mem_dma_bd32_3 = 0x000a040c; +// DMA BD32 4 +const unsigned int mem_dma_bd32_4 = 0x000a0410; +// DMA BD32 5 +const unsigned int mem_dma_bd32_5 = 0x000a0414; +// DMA BD32 6 +const unsigned int mem_dma_bd32_6 = 0x000a0418; +// DMA BD32 7 +const unsigned int mem_dma_bd32_7 = 0x000a041c; +// DMA BD33 +const unsigned int mem_dma_bd33_0 = 0x000a0420; +// DMA BD33 1 +const unsigned int mem_dma_bd33_1 = 0x000a0424; +// DMA BD33 2 +const unsigned int mem_dma_bd33_2 = 0x000a0428; +// DMA BD33 3 +const unsigned int mem_dma_bd33_3 = 0x000a042c; +// DMA BD33 4 +const unsigned int mem_dma_bd33_4 = 0x000a0430; +// DMA BD33 5 +const unsigned int mem_dma_bd33_5 = 0x000a0434; +// DMA BD33 6 +const unsigned int mem_dma_bd33_6 = 0x000a0438; +// DMA BD33 7 +const unsigned int mem_dma_bd33_7 = 0x000a043c; +// DMA BD34 +const unsigned int mem_dma_bd34_0 = 0x000a0440; +// DMA BD34 1 +const unsigned int mem_dma_bd34_1 = 0x000a0444; +// DMA BD34 2 +const unsigned int mem_dma_bd34_2 = 0x000a0448; +// DMA BD34 3 +const unsigned int mem_dma_bd34_3 = 0x000a044c; +// DMA BD34 4 +const unsigned int mem_dma_bd34_4 = 0x000a0450; +// DMA BD34 5 +const unsigned int mem_dma_bd34_5 = 0x000a0454; +// DMA BD34 6 +const unsigned int mem_dma_bd34_6 = 0x000a0458; +// DMA BD34 7 +const unsigned int mem_dma_bd34_7 = 0x000a045c; +// DMA BD35 +const unsigned int mem_dma_bd35_0 = 0x000a0460; +// DMA BD35 1 +const unsigned int mem_dma_bd35_1 = 0x000a0464; +// DMA BD35 2 +const unsigned int mem_dma_bd35_2 = 0x000a0468; +// DMA BD35 3 +const unsigned int mem_dma_bd35_3 = 0x000a046c; +// DMA BD35 4 +const unsigned int mem_dma_bd35_4 = 0x000a0470; +// DMA BD35 5 +const unsigned int mem_dma_bd35_5 = 0x000a0474; +// DMA BD35 6 +const unsigned int mem_dma_bd35_6 = 0x000a0478; +// DMA BD35 7 +const unsigned int mem_dma_bd35_7 = 0x000a047c; +// DMA BD36 +const unsigned int mem_dma_bd36_0 = 0x000a0480; +// DMA BD36 1 +const unsigned int mem_dma_bd36_1 = 0x000a0484; +// DMA BD36 2 +const unsigned int mem_dma_bd36_2 = 0x000a0488; +// DMA BD36 3 +const unsigned int mem_dma_bd36_3 = 0x000a048c; +// DMA BD36 4 +const unsigned int mem_dma_bd36_4 = 0x000a0490; +// DMA BD36 5 +const unsigned int mem_dma_bd36_5 = 0x000a0494; +// DMA BD36 6 +const unsigned int mem_dma_bd36_6 = 0x000a0498; +// DMA BD36 7 +const unsigned int mem_dma_bd36_7 = 0x000a049c; +// DMA BD37 +const unsigned int mem_dma_bd37_0 = 0x000a04a0; +// DMA BD37 1 +const unsigned int mem_dma_bd37_1 = 0x000a04a4; +// DMA BD37 2 +const unsigned int mem_dma_bd37_2 = 0x000a04a8; +// DMA BD37 3 +const unsigned int mem_dma_bd37_3 = 0x000a04ac; +// DMA BD37 4 +const unsigned int mem_dma_bd37_4 = 0x000a04b0; +// DMA BD37 5 +const unsigned int mem_dma_bd37_5 = 0x000a04b4; +// DMA BD37 6 +const unsigned int mem_dma_bd37_6 = 0x000a04b8; +// DMA BD37 7 +const unsigned int mem_dma_bd37_7 = 0x000a04bc; +// DMA BD35 +const unsigned int mem_dma_bd38_0 = 0x000a04c0; +// DMA BD38 1 +const unsigned int mem_dma_bd38_1 = 0x000a04c4; +// DMA BD38 2 +const unsigned int mem_dma_bd38_2 = 0x000a04c8; +// DMA BD38 3 +const unsigned int mem_dma_bd38_3 = 0x000a04cc; +// DMA BD38 4 +const unsigned int mem_dma_bd38_4 = 0x000a04d0; +// DMA BD38 5 +const unsigned int mem_dma_bd38_5 = 0x000a04d4; +// DMA BD38 6 +const unsigned int mem_dma_bd38_6 = 0x000a04d8; +// DMA BD38 7 +const unsigned int mem_dma_bd38_7 = 0x000a04dc; +// DMA BD39 +const unsigned int mem_dma_bd39_0 = 0x000a04e0; +// DMA BD39 1 +const unsigned int mem_dma_bd39_1 = 0x000a04e4; +// DMA BD39 2 +const unsigned int mem_dma_bd39_2 = 0x000a04e8; +// DMA BD39 3 +const unsigned int mem_dma_bd39_3 = 0x000a04ec; +// DMA BD39 4 +const unsigned int mem_dma_bd39_4 = 0x000a04f0; +// DMA BD39 5 +const unsigned int mem_dma_bd39_5 = 0x000a04f4; +// DMA BD39 6 +const unsigned int mem_dma_bd39_6 = 0x000a04f8; +// DMA BD39 7 +const unsigned int mem_dma_bd39_7 = 0x000a04fc; +// DMA BD40 +const unsigned int mem_dma_bd40_0 = 0x000a0500; +// DMA BD40 1 +const unsigned int mem_dma_bd40_1 = 0x000a0504; +// DMA BD40 2 +const unsigned int mem_dma_bd40_2 = 0x000a0508; +// DMA BD40 3 +const unsigned int mem_dma_bd40_3 = 0x000a050c; +// DMA BD40 4 +const unsigned int mem_dma_bd40_4 = 0x000a0510; +// DMA BD40 5 +const unsigned int mem_dma_bd40_5 = 0x000a0514; +// DMA BD40 6 +const unsigned int mem_dma_bd40_6 = 0x000a0518; +// DMA BD40 7 +const unsigned int mem_dma_bd40_7 = 0x000a051c; +// DMA BD41 +const unsigned int mem_dma_bd41_0 = 0x000a0520; +// DMA BD41 1 +const unsigned int mem_dma_bd41_1 = 0x000a0524; +// DMA BD41 2 +const unsigned int mem_dma_bd41_2 = 0x000a0528; +// DMA BD41 3 +const unsigned int mem_dma_bd41_3 = 0x000a052c; +// DMA BD41 4 +const unsigned int mem_dma_bd41_4 = 0x000a0530; +// DMA BD41 5 +const unsigned int mem_dma_bd41_5 = 0x000a0534; +// DMA BD41 6 +const unsigned int mem_dma_bd41_6 = 0x000a0538; +// DMA BD41 7 +const unsigned int mem_dma_bd41_7 = 0x000a053c; +// DMA BD42 +const unsigned int mem_dma_bd42_0 = 0x000a0540; +// DMA BD42 1 +const unsigned int mem_dma_bd42_1 = 0x000a0544; +// DMA BD42 2 +const unsigned int mem_dma_bd42_2 = 0x000a0548; +// DMA BD42 3 +const unsigned int mem_dma_bd42_3 = 0x000a054c; +// DMA BD42 4 +const unsigned int mem_dma_bd42_4 = 0x000a0550; +// DMA BD42 5 +const unsigned int mem_dma_bd42_5 = 0x000a0554; +// DMA BD42 6 +const unsigned int mem_dma_bd42_6 = 0x000a0558; +// DMA BD42 7 +const unsigned int mem_dma_bd42_7 = 0x000a055c; +// DMA BD43 +const unsigned int mem_dma_bd43_0 = 0x000a0560; +// DMA BD43 1 +const unsigned int mem_dma_bd43_1 = 0x000a0564; +// DMA BD43 2 +const unsigned int mem_dma_bd43_2 = 0x000a0568; +// DMA BD43 3 +const unsigned int mem_dma_bd43_3 = 0x000a056c; +// DMA BD43 4 +const unsigned int mem_dma_bd43_4 = 0x000a0570; +// DMA BD43 5 +const unsigned int mem_dma_bd43_5 = 0x000a0574; +// DMA BD43 6 +const unsigned int mem_dma_bd43_6 = 0x000a0578; +// DMA BD43 7 +const unsigned int mem_dma_bd43_7 = 0x000a057c; +// DMA BD44 +const unsigned int mem_dma_bd44_0 = 0x000a0580; +// DMA BD44 1 +const unsigned int mem_dma_bd44_1 = 0x000a0584; +// DMA BD44 2 +const unsigned int mem_dma_bd44_2 = 0x000a0588; +// DMA BD44 3 +const unsigned int mem_dma_bd44_3 = 0x000a058c; +// DMA BD44 4 +const unsigned int mem_dma_bd44_4 = 0x000a0590; +// DMA BD44 5 +const unsigned int mem_dma_bd44_5 = 0x000a0594; +// DMA BD44 6 +const unsigned int mem_dma_bd44_6 = 0x000a0598; +// DMA BD44 7 +const unsigned int mem_dma_bd44_7 = 0x000a059c; +// DMA BD45 +const unsigned int mem_dma_bd45_0 = 0x000a05a0; +// DMA BD45 1 +const unsigned int mem_dma_bd45_1 = 0x000a05a4; +// DMA BD45 2 +const unsigned int mem_dma_bd45_2 = 0x000a05a8; +// DMA BD45 3 +const unsigned int mem_dma_bd45_3 = 0x000a05ac; +// DMA BD45 4 +const unsigned int mem_dma_bd45_4 = 0x000a05b0; +// DMA BD45 5 +const unsigned int mem_dma_bd45_5 = 0x000a05b4; +// DMA BD45 6 +const unsigned int mem_dma_bd45_6 = 0x000a05b8; +// DMA BD45 7 +const unsigned int mem_dma_bd45_7 = 0x000a05bc; +// DMA BD46 +const unsigned int mem_dma_bd46_0 = 0x000a05c0; +// DMA BD46 1 +const unsigned int mem_dma_bd46_1 = 0x000a05c4; +// DMA BD46 2 +const unsigned int mem_dma_bd46_2 = 0x000a05c8; +// DMA BD46 3 +const unsigned int mem_dma_bd46_3 = 0x000a05cc; +// DMA BD46 4 +const unsigned int mem_dma_bd46_4 = 0x000a05d0; +// DMA BD46 5 +const unsigned int mem_dma_bd46_5 = 0x000a05d4; +// DMA BD46 6 +const unsigned int mem_dma_bd46_6 = 0x000a05d8; +// DMA BD46 7 +const unsigned int mem_dma_bd46_7 = 0x000a05dc; +// DMA BD47 +const unsigned int mem_dma_bd47_0 = 0x000a05e0; +// DMA BD47 1 +const unsigned int mem_dma_bd47_1 = 0x000a05e4; +// DMA BD47 2 +const unsigned int mem_dma_bd47_2 = 0x000a05e8; +// DMA BD47 3 +const unsigned int mem_dma_bd47_3 = 0x000a05ec; +// DMA BD47 4 +const unsigned int mem_dma_bd47_4 = 0x000a05f0; +// DMA BD47 5 +const unsigned int mem_dma_bd47_5 = 0x000a05f4; +// DMA BD47 6 +const unsigned int mem_dma_bd47_6 = 0x000a05f8; +// DMA BD47 7 +const unsigned int mem_dma_bd47_7 = 0x000a05fc; +// DMA Control Register S2MM Ch0 +const unsigned int mem_dma_s2mm_0_ctrl = 0x000a0600; +// DMA Control Register S2MM Ch0 start BD +const unsigned int mem_dma_s2mm_0_start_queue = 0x000a0604; +// DMA Control Register S2MM Ch1 +const unsigned int mem_dma_s2mm_1_ctrl = 0x000a0608; +// DMA Control Register S2MM Ch1 start BD +const unsigned int mem_dma_s2mm_1_start_queue = 0x000a060c; +// DMA Control Register S2MM Ch2 +const unsigned int mem_dma_s2mm_2_ctrl = 0x000a0610; +// DMA Control Register S2MM Ch2 start BD +const unsigned int mem_dma_s2mm_2_start_queue = 0x000a0614; +// DMA Control Register S2MM Ch3 +const unsigned int mem_dma_s2mm_3_ctrl = 0x000a0618; +// DMA Control Register S2MM Ch3 start BD +const unsigned int mem_dma_s2mm_3_start_queue = 0x000a061c; +// DMA Control Register S2MM Ch4 +const unsigned int mem_dma_s2mm_4_ctrl = 0x000a0620; +// DMA Control Register S2MM Ch4 start BD +const unsigned int mem_dma_s2mm_4_start_queue = 0x000a0624; +// DMA Control Register S2MM Ch5 +const unsigned int mem_dma_s2mm_5_ctrl = 0x000a0628; +// DMA Control Register S2MM Ch5 start BD +const unsigned int mem_dma_s2mm_5_start_queue = 0x000a062c; +// DMA Control Register MM2S Ch0 +const unsigned int mem_dma_mm2s_0_ctrl = 0x000a0630; +// DMA Control Register MM2S Ch0 start BD +const unsigned int mem_dma_mm2s_0_start_queue = 0x000a0634; +// DMA Control Register MM2S Ch1 +const unsigned int mem_dma_mm2s_1_ctrl = 0x000a0638; +// DMA Control Register MM2S Ch1 start BD +const unsigned int mem_dma_mm2s_1_start_queue = 0x000a063c; +// DMA Control Register MM2S Ch2 +const unsigned int mem_dma_mm2s_2_ctrl = 0x000a0640; +// DMA Control Register MM2S Ch2 start BD +const unsigned int mem_dma_mm2s_2_start_queue = 0x000a0644; +// DMA Control Register MM2S Ch3 +const unsigned int mem_dma_mm2s_3_ctrl = 0x000a0648; +// DMA Control Register MM2S Ch3 start BD +const unsigned int mem_dma_mm2s_3_start_queue = 0x000a064c; +// DMA Control Register MM2S Ch4 +const unsigned int mem_dma_mm2s_4_ctrl = 0x000a0650; +// DMA Control Register MM2S Ch4 start BD +const unsigned int mem_dma_mm2s_4_start_queue = 0x000a0654; +// DMA Control Register MM2S Ch5 +const unsigned int mem_dma_mm2s_5_ctrl = 0x000a0658; +// DMA Control Register MM2S Ch5 start BD +const unsigned int mem_dma_mm2s_5_start_queue = 0x000a065c; +// DMA S2MM Status Register Ch0 +const unsigned int mem_dma_s2mm_status_0 = 0x000a0660; +// DMA S2MM Status Register Ch1 +const unsigned int mem_dma_s2mm_status_1 = 0x000a0664; +// DMA S2MM Status Register Ch2 +const unsigned int mem_dma_s2mm_status_2 = 0x000a0668; +// DMA S2MM Status Register Ch3 +const unsigned int mem_dma_s2mm_status_3 = 0x000a066c; +// DMA S2MM Status Register Ch4 +const unsigned int mem_dma_s2mm_status_4 = 0x000a0670; +// DMA S2MM Status Register Ch5 +const unsigned int mem_dma_s2mm_status_5 = 0x000a0674; +// DMA S2MM Status Register Ch0 +const unsigned int mem_dma_mm2s_status_0 = 0x000a0680; +// DMA S2MM Status Register Ch1 +const unsigned int mem_dma_mm2s_status_1 = 0x000a0684; +// DMA S2MM Status Register Ch2 +const unsigned int mem_dma_mm2s_status_2 = 0x000a0688; +// DMA S2MM Status Register Ch3 +const unsigned int mem_dma_mm2s_status_3 = 0x000a068c; +// DMA S2MM Status Register Ch4 +const unsigned int mem_dma_mm2s_status_4 = 0x000a0690; +// DMA S2MM Status Register Ch5 +const unsigned int mem_dma_mm2s_status_5 = 0x000a0694; +// Selection of which DMA channels will generate events +const unsigned int mem_dma_event_channel_selection = 0x000a06a0; +// DMA S2MM Current Write Count Ch0 +const unsigned int mem_dma_s2mm_current_write_count_0 = 0x000a06b0; +// DMA S2MM Current Write Count Ch1 +const unsigned int mem_dma_s2mm_current_write_count_1 = 0x000a06b4; +// DMA S2MM Current Write Count Ch2 +const unsigned int mem_dma_s2mm_current_write_count_2 = 0x000a06b8; +// DMA S2MM Current Write Count Ch3 +const unsigned int mem_dma_s2mm_current_write_count_3 = 0x000a06bc; +// DMA S2MM Current Write Count Ch4 +const unsigned int mem_dma_s2mm_current_write_count_4 = 0x000a06c0; +// DMA S2MM Current Write Count Ch5 +const unsigned int mem_dma_s2mm_current_write_count_5 = 0x000a06c4; +// DMA S2MM FoT Count FIFO Pop Ch0 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_0 = 0x000a06c8; +// DMA S2MM FoT Count FIFO Pop Ch1 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_1 = 0x000a06cc; +// DMA S2MM FoT Count FIFO Pop Ch2 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_2 = 0x000a06d0; +// DMA S2MM FoT Count FIFO Pop Ch3 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_3 = 0x000a06d4; +// DMA S2MM FoT Count FIFO Pop Ch4 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_4 = 0x000a06d8; +// DMA S2MM FoT Count FIFO Pop Ch5 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_5 = 0x000a06dc; +// Stream Switch Master Configuration DMA 0 +const unsigned int mem_stream_switch_master_config_dma0 = 0x000b0000; +// Stream Switch Master Configuration DMA 1 +const unsigned int mem_stream_switch_master_config_dma1 = 0x000b0004; +// Stream Switch Master Configuration DMA 2 +const unsigned int mem_stream_switch_master_config_dma2 = 0x000b0008; +// Stream Switch Master Configuration DMA 3 +const unsigned int mem_stream_switch_master_config_dma3 = 0x000b000c; +// Stream Switch Master Configuration DMA 4 +const unsigned int mem_stream_switch_master_config_dma4 = 0x000b0010; +// Stream Switch Master Configuration DMA 5 +const unsigned int mem_stream_switch_master_config_dma5 = 0x000b0014; +// Stream Switch Master Configuration AI Engine Tile Ctrl +const unsigned int mem_stream_switch_master_config_tile_ctrl = 0x000b0018; +// Stream Switch Master Configuration South 0 +const unsigned int mem_stream_switch_master_config_south0 = 0x000b001c; +// Stream Switch Master Configuration South 1 +const unsigned int mem_stream_switch_master_config_south1 = 0x000b0020; +// Stream Switch Master Configuration South 2 +const unsigned int mem_stream_switch_master_config_south2 = 0x000b0024; +// Stream Switch Master Configuration South 3 +const unsigned int mem_stream_switch_master_config_south3 = 0x000b0028; +// Stream Switch Master Configuration North 0 +const unsigned int mem_stream_switch_master_config_north0 = 0x000b002c; +// Stream Switch Master Configuration North 1 +const unsigned int mem_stream_switch_master_config_north1 = 0x000b0030; +// Stream Switch Master Configuration North 2 +const unsigned int mem_stream_switch_master_config_north2 = 0x000b0034; +// Stream Switch Master Configuration North 3 +const unsigned int mem_stream_switch_master_config_north3 = 0x000b0038; +// Stream Switch Master Configuration North 4 +const unsigned int mem_stream_switch_master_config_north4 = 0x000b003c; +// Stream Switch Master Configuration North 5 +const unsigned int mem_stream_switch_master_config_north5 = 0x000b0040; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_config_dma_0 = 0x000b0100; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_config_dma_1 = 0x000b0104; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_config_dma_2 = 0x000b0108; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_config_dma_3 = 0x000b010c; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_config_dma_4 = 0x000b0110; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_config_dma_5 = 0x000b0114; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_config_tile_ctrl = 0x000b0118; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_config_south_0 = 0x000b011c; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_config_south_1 = 0x000b0120; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_config_south_2 = 0x000b0124; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_config_south_3 = 0x000b0128; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_config_south_4 = 0x000b012c; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_config_south_5 = 0x000b0130; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_config_north_0 = 0x000b0134; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_config_north_1 = 0x000b0138; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_config_north_2 = 0x000b013c; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_config_north_3 = 0x000b0140; +// Stream Switch Slave Configuration Trace +const unsigned int mem_stream_switch_slave_config_trace = 0x000b0144; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot0 = 0x000b0200; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot1 = 0x000b0204; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot2 = 0x000b0208; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot3 = 0x000b020c; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot0 = 0x000b0210; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot1 = 0x000b0214; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot2 = 0x000b0218; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot3 = 0x000b021c; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot0 = 0x000b0220; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot1 = 0x000b0224; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot2 = 0x000b0228; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot3 = 0x000b022c; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot0 = 0x000b0230; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot1 = 0x000b0234; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot2 = 0x000b0238; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot3 = 0x000b023c; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot0 = 0x000b0240; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot1 = 0x000b0244; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot2 = 0x000b0248; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot3 = 0x000b024c; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot0 = 0x000b0250; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot1 = 0x000b0254; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot2 = 0x000b0258; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot3 = 0x000b025c; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot0 = 0x000b0260; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot1 = 0x000b0264; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot2 = 0x000b0268; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot3 = 0x000b026c; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot0 = 0x000b0270; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot1 = 0x000b0274; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot2 = 0x000b0278; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot3 = 0x000b027c; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot0 = 0x000b0280; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot1 = 0x000b0284; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot2 = 0x000b0288; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot3 = 0x000b028c; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot0 = 0x000b0290; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot1 = 0x000b0294; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot2 = 0x000b0298; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot3 = 0x000b029c; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot0 = 0x000b02a0; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot1 = 0x000b02a4; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot2 = 0x000b02a8; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot3 = 0x000b02ac; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot0 = 0x000b02b0; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot1 = 0x000b02b4; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot2 = 0x000b02b8; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot3 = 0x000b02bc; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot0 = 0x000b02c0; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot1 = 0x000b02c4; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot2 = 0x000b02c8; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot3 = 0x000b02cc; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot0 = 0x000b02d0; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot1 = 0x000b02d4; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot2 = 0x000b02d8; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot3 = 0x000b02dc; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot0 = 0x000b02e0; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot1 = 0x000b02e4; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot2 = 0x000b02e8; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot3 = 0x000b02ec; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot0 = 0x000b02f0; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot1 = 0x000b02f4; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot2 = 0x000b02f8; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot3 = 0x000b02fc; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot0 = 0x000b0300; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot1 = 0x000b0304; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot2 = 0x000b0308; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot3 = 0x000b030c; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot0 = 0x000b0310; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot1 = 0x000b0314; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot2 = 0x000b0318; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot3 = 0x000b031c; +// Stream Switch Deterministic Merge Arbiter:0 Slave:0,1 +const unsigned int mem_stream_switch_deterministic_merge_arb0_slave0_1 = 0x000b0800; +// Stream Switch Deterministic Merge Arbiter:0 Slave:2,3 +const unsigned int mem_stream_switch_deterministic_merge_arb0_slave2_3 = 0x000b0804; +// Stream Switch Deterministic Merge Arbiter:0 Control +const unsigned int mem_stream_switch_deterministic_merge_arb0_ctrl = 0x000b0808; +// Stream Switch Deterministic Merge Arbiter:1 Slave:0,1 +const unsigned int mem_stream_switch_deterministic_merge_arb1_slave0_1 = 0x000b0810; +// Stream Switch Deterministic Merge Arbiter:1 Slave:2,3 +const unsigned int mem_stream_switch_deterministic_merge_arb1_slave2_3 = 0x000b0814; +// Stream Switch Deterministic Merge Arbiter:1 Control +const unsigned int mem_stream_switch_deterministic_merge_arb1_ctrl = 0x000b0818; +// Select Stream Switch Ports for event generation +const unsigned int mem_stream_switch_event_port_selection_0 = 0x000b0f00; +// Select Stream Switch Ports for event generation +const unsigned int mem_stream_switch_event_port_selection_1 = 0x000b0f04; +// Status bits for Parity errors on stream switch ports +const unsigned int mem_stream_switch_parity_status = 0x000b0f10; +// Injection of Parity errors on stream switch ports +const unsigned int mem_stream_switch_parity_injection = 0x000b0f20; +// Status of control packet handling +const unsigned int mem_tile_control_packet_handler_status = 0x000b0f30; +// Status of Stream Switch Adaptive Clock Gate +const unsigned int mem_stream_switch_adaptive_clock_gate_status = 0x000b0f34; +// Status of Stream Switch Adaptive Clock Gate Abort Period +const unsigned int mem_stream_switch_adaptive_clock_gate_abort_period = 0x000b0f38; +// Value of lock 0 +const unsigned int mem_lock0_value = 0x000c0000; +// Value of lock 1 +const unsigned int mem_lock1_value = 0x000c0010; +// Value of lock 2 +const unsigned int mem_lock2_value = 0x000c0020; +// Value of lock 3 +const unsigned int mem_lock3_value = 0x000c0030; +// Value of lock 4 +const unsigned int mem_lock4_value = 0x000c0040; +// Value of lock 5 +const unsigned int mem_lock5_value = 0x000c0050; +// Value of lock 6 +const unsigned int mem_lock6_value = 0x000c0060; +// Value of lock 7 +const unsigned int mem_lock7_value = 0x000c0070; +// Value of lock 8 +const unsigned int mem_lock8_value = 0x000c0080; +// Value of lock 9 +const unsigned int mem_lock9_value = 0x000c0090; +// Value of lock 10 +const unsigned int mem_lock10_value = 0x000c00a0; +// Value of lock 11 +const unsigned int mem_lock11_value = 0x000c00b0; +// Value of lock 12 +const unsigned int mem_lock12_value = 0x000c00c0; +// Value of lock 13 +const unsigned int mem_lock13_value = 0x000c00d0; +// Value of lock 14 +const unsigned int mem_lock14_value = 0x000c00e0; +// Value of lock 15 +const unsigned int mem_lock15_value = 0x000c00f0; +// Value of lock 16 +const unsigned int mem_lock16_value = 0x000c0100; +// Value of lock 17 +const unsigned int mem_lock17_value = 0x000c0110; +// Value of lock 18 +const unsigned int mem_lock18_value = 0x000c0120; +// Value of lock 19 +const unsigned int mem_lock19_value = 0x000c0130; +// Value of lock 20 +const unsigned int mem_lock20_value = 0x000c0140; +// Value of lock 21 +const unsigned int mem_lock21_value = 0x000c0150; +// Value of lock 22 +const unsigned int mem_lock22_value = 0x000c0160; +// Value of lock 23 +const unsigned int mem_lock23_value = 0x000c0170; +// Value of lock 24 +const unsigned int mem_lock24_value = 0x000c0180; +// Value of lock 25 +const unsigned int mem_lock25_value = 0x000c0190; +// Value of lock 26 +const unsigned int mem_lock26_value = 0x000c01a0; +// Value of lock 27 +const unsigned int mem_lock27_value = 0x000c01b0; +// Value of lock 28 +const unsigned int mem_lock28_value = 0x000c01c0; +// Value of lock 29 +const unsigned int mem_lock29_value = 0x000c01d0; +// Value of lock 30 +const unsigned int mem_lock30_value = 0x000c01e0; +// Value of lock 31 +const unsigned int mem_lock31_value = 0x000c01f0; +// Value of lock 32 +const unsigned int mem_lock32_value = 0x000c0200; +// Value of lock 33 +const unsigned int mem_lock33_value = 0x000c0210; +// Value of lock 34 +const unsigned int mem_lock34_value = 0x000c0220; +// Value of lock 35 +const unsigned int mem_lock35_value = 0x000c0230; +// Value of lock 36 +const unsigned int mem_lock36_value = 0x000c0240; +// Value of lock 37 +const unsigned int mem_lock37_value = 0x000c0250; +// Value of lock 38 +const unsigned int mem_lock38_value = 0x000c0260; +// Value of lock 39 +const unsigned int mem_lock39_value = 0x000c0270; +// Value of lock 40 +const unsigned int mem_lock40_value = 0x000c0280; +// Value of lock 41 +const unsigned int mem_lock41_value = 0x000c0290; +// Value of lock 42 +const unsigned int mem_lock42_value = 0x000c02a0; +// Value of lock 43 +const unsigned int mem_lock43_value = 0x000c02b0; +// Value of lock 44 +const unsigned int mem_lock44_value = 0x000c02c0; +// Value of lock 45 +const unsigned int mem_lock45_value = 0x000c02d0; +// Value of lock 46 +const unsigned int mem_lock46_value = 0x000c02e0; +// Value of lock 47 +const unsigned int mem_lock47_value = 0x000c02f0; +// Value of lock 48 +const unsigned int mem_lock48_value = 0x000c0300; +// Value of lock 49 +const unsigned int mem_lock49_value = 0x000c0310; +// Value of lock 50 +const unsigned int mem_lock50_value = 0x000c0320; +// Value of lock 51 +const unsigned int mem_lock51_value = 0x000c0330; +// Value of lock 52 +const unsigned int mem_lock52_value = 0x000c0340; +// Value of lock 53 +const unsigned int mem_lock53_value = 0x000c0350; +// Value of lock 54 +const unsigned int mem_lock54_value = 0x000c0360; +// Value of lock 55 +const unsigned int mem_lock55_value = 0x000c0370; +// Value of lock 56 +const unsigned int mem_lock56_value = 0x000c0380; +// Value of lock 57 +const unsigned int mem_lock57_value = 0x000c0390; +// Value of lock 58 +const unsigned int mem_lock58_value = 0x000c03a0; +// Value of lock 59 +const unsigned int mem_lock59_value = 0x000c03b0; +// Value of lock 60 +const unsigned int mem_lock60_value = 0x000c03c0; +// Value of lock 61 +const unsigned int mem_lock61_value = 0x000c03d0; +// Value of lock 62 +const unsigned int mem_lock62_value = 0x000c03e0; +// Value of lock 63 +const unsigned int mem_lock63_value = 0x000c03f0; +// Select lock for lock event generation 0 +const unsigned int mem_locks_event_selection_0 = 0x000c0400; +// Select lock for lock event generation 1 +const unsigned int mem_locks_event_selection_1 = 0x000c0404; +// Select lock for lock event generation 2 +const unsigned int mem_locks_event_selection_2 = 0x000c0408; +// Select lock for lock event generation 3 +const unsigned int mem_locks_event_selection_3 = 0x000c040c; +// Select lock for lock event generation 4 +const unsigned int mem_locks_event_selection_4 = 0x000c0410; +// Select lock for lock event generation 5 +const unsigned int mem_locks_event_selection_5 = 0x000c0414; +// Select lock for lock event generation 6 +const unsigned int mem_locks_event_selection_6 = 0x000c0418; +// Select lock for lock event generation 7 +const unsigned int mem_locks_event_selection_7 = 0x000c041c; +// Status bits for lock overflow, write to clear +const unsigned int mem_locks_overflow_0 = 0x000c0420; +// Status bits for lock overflow, write to clear +const unsigned int mem_locks_overflow_1 = 0x000c0424; +// Status bits for lock underflow, write to clear +const unsigned int mem_locks_underflow_0 = 0x000c0428; +// Status bits for lock underflow, write to clear +const unsigned int mem_locks_underflow_1 = 0x000c042c; +// Lock Request. 65kB address space: = 0xD0000 - = 0xDFFFC, Lock_Id [15:10], Acq_Rel (9), Change_Value [8:2] +const unsigned int mem_lock_request = 0x000d0000; +// Control clock gating of modules (privileged) +const unsigned int mem_module_clock_control = 0x000fff00; +// Reset of modules (privileged) +const unsigned int mem_module_reset_control = 0x000fff10; + +// Register definitions for SHIM +// ################################### +// Step size between lock registers +const unsigned int shim_lock_step_size = 0x10; +// Step size between DMA BD register groups +const unsigned int shim_dma_bd_step_size = 0x20; +// Step size between DMA S2MM register groups +const unsigned int shim_dma_s2mm_step_size = 0x8; +// Value of lock 0 +const unsigned int shim_lock0_value = 0x00014000; +// Value of lock 1 +const unsigned int shim_lock1_value = 0x00014010; +// Value of lock 2 +const unsigned int shim_lock2_value = 0x00014020; +// Value of lock 3 +const unsigned int shim_lock3_value = 0x00014030; +// Value of lock 4 +const unsigned int shim_lock4_value = 0x00014040; +// Value of lock 5 +const unsigned int shim_lock5_value = 0x00014050; +// Value of lock 6 +const unsigned int shim_lock6_value = 0x00014060; +// Value of lock 7 +const unsigned int shim_lock7_value = 0x00014070; +// Value of lock 8 +const unsigned int shim_lock8_value = 0x00014080; +// Value of lock 9 +const unsigned int shim_lock9_value = 0x00014090; +// Value of lock 10 +const unsigned int shim_lock10_value = 0x000140a0; +// Value of lock 11 +const unsigned int shim_lock11_value = 0x000140b0; +// Value of lock 12 +const unsigned int shim_lock12_value = 0x000140c0; +// Value of lock 13 +const unsigned int shim_lock13_value = 0x000140d0; +// Value of lock 14 +const unsigned int shim_lock14_value = 0x000140e0; +// Value of lock 15 +const unsigned int shim_lock15_value = 0x000140f0; +// DMA BD0 Config Register 0 +const unsigned int shim_dma_bd0_0 = 0x0001d000; +// DMA BD0 Config Register 1 +const unsigned int shim_dma_bd0_1 = 0x0001d004; +// DMA BD0 Config Register 2 +const unsigned int shim_dma_bd0_2 = 0x0001d008; +// DMA BD0 Config Register 3 +const unsigned int shim_dma_bd0_3 = 0x0001d00c; +// DMA BD0 Config Register 4 +const unsigned int shim_dma_bd0_4 = 0x0001d010; +// DMA BD0 Config Register 5 +const unsigned int shim_dma_bd0_5 = 0x0001d014; +// DMA BD0 Config Register 6 +const unsigned int shim_dma_bd0_6 = 0x0001d018; +// DMA BD0 Config Register 7 +const unsigned int shim_dma_bd0_7 = 0x0001d01c; +// DMA BD1 Config Register 0 +const unsigned int shim_dma_bd1_0 = 0x0001d020; +// DMA BD1 Config Register 1 +const unsigned int shim_dma_bd1_1 = 0x0001d024; +// DMA BD1 Config Register 2 +const unsigned int shim_dma_bd1_2 = 0x0001d028; +// DMA BD1 Config Register 3 +const unsigned int shim_dma_bd1_3 = 0x0001d02c; +// DMA BD1 Config Register 4 +const unsigned int shim_dma_bd1_4 = 0x0001d030; +// DMA BD1 Config Register 5 +const unsigned int shim_dma_bd1_5 = 0x0001d034; +// DMA BD1 Config Register 6 +const unsigned int shim_dma_bd1_6 = 0x0001d038; +// DMA BD1 Config Register 7 +const unsigned int shim_dma_bd1_7 = 0x0001d03c; +// DMA BD2 Config Register 0 +const unsigned int shim_dma_bd2_0 = 0x0001d040; +// DMA BD2 Config Register 1 +const unsigned int shim_dma_bd2_1 = 0x0001d044; +// DMA BD2 Config Register 2 +const unsigned int shim_dma_bd2_2 = 0x0001d048; +// DMA BD2 Config Register 3 +const unsigned int shim_dma_bd2_3 = 0x0001d04c; +// DMA BD2 Config Register 4 +const unsigned int shim_dma_bd2_4 = 0x0001d050; +// DMA BD2 Config Register 5 +const unsigned int shim_dma_bd2_5 = 0x0001d054; +// DMA BD2 Config Register 6 +const unsigned int shim_dma_bd2_6 = 0x0001d058; +// DMA BD2 Config Register 7 +const unsigned int shim_dma_bd2_7 = 0x0001d05c; +// DMA BD3 Config Register 0 +const unsigned int shim_dma_bd3_0 = 0x0001d060; +// DMA BD3 Config Register 1 +const unsigned int shim_dma_bd3_1 = 0x0001d064; +// DMA BD3 Config Register 2 +const unsigned int shim_dma_bd3_2 = 0x0001d068; +// DMA BD3 Config Register 3 +const unsigned int shim_dma_bd3_3 = 0x0001d06c; +// DMA BD3 Config Register 4 +const unsigned int shim_dma_bd3_4 = 0x0001d070; +// DMA BD3 Config Register 5 +const unsigned int shim_dma_bd3_5 = 0x0001d074; +// DMA BD3 Config Register 6 +const unsigned int shim_dma_bd3_6 = 0x0001d078; +// DMA BD3 Config Register 7 +const unsigned int shim_dma_bd3_7 = 0x0001d07c; +// DMA BD4 Config Register 0 +const unsigned int shim_dma_bd4_0 = 0x0001d080; +// DMA BD4 Config Register 1 +const unsigned int shim_dma_bd4_1 = 0x0001d084; +// DMA BD4 Config Register 2 +const unsigned int shim_dma_bd4_2 = 0x0001d088; +// DMA BD4 Config Register 3 +const unsigned int shim_dma_bd4_3 = 0x0001d08c; +// DMA BD4 Config Register 4 +const unsigned int shim_dma_bd4_4 = 0x0001d090; +// DMA BD4 Config Register 5 +const unsigned int shim_dma_bd4_5 = 0x0001d094; +// DMA BD4 Config Register 6 +const unsigned int shim_dma_bd4_6 = 0x0001d098; +// DMA BD4 Config Register 7 +const unsigned int shim_dma_bd4_7 = 0x0001d09c; +// DMA BD5 Config Register 0 +const unsigned int shim_dma_bd5_0 = 0x0001d0a0; +// DMA BD5 Config Register 1 +const unsigned int shim_dma_bd5_1 = 0x0001d0a4; +// DMA BD5 Config Register 2 +const unsigned int shim_dma_bd5_2 = 0x0001d0a8; +// DMA BD5 Config Register 3 +const unsigned int shim_dma_bd5_3 = 0x0001d0ac; +// DMA BD5 Config Register 4 +const unsigned int shim_dma_bd5_4 = 0x0001d0b0; +// DMA BD5 Config Register 5 +const unsigned int shim_dma_bd5_5 = 0x0001d0b4; +// DMA BD5 Config Register 6 +const unsigned int shim_dma_bd5_6 = 0x0001d0b8; +// DMA BD5 Config Register 7 +const unsigned int shim_dma_bd5_7 = 0x0001d0bc; +// DMA BD6 Config Register 0 +const unsigned int shim_dma_bd6_0 = 0x0001d0c0; +// DMA BD6 Config Register 1 +const unsigned int shim_dma_bd6_1 = 0x0001d0c4; +// DMA BD6 Config Register 2 +const unsigned int shim_dma_bd6_2 = 0x0001d0c8; +// DMA BD6 Config Register 3 +const unsigned int shim_dma_bd6_3 = 0x0001d0cc; +// DMA BD6 Config Register 4 +const unsigned int shim_dma_bd6_4 = 0x0001d0d0; +// DMA BD6 Config Register 5 +const unsigned int shim_dma_bd6_5 = 0x0001d0d4; +// DMA BD6 Config Register 6 +const unsigned int shim_dma_bd6_6 = 0x0001d0d8; +// DMA BD6 Config Register 7 +const unsigned int shim_dma_bd6_7 = 0x0001d0dc; +// DMA BD7 Config Register 0 +const unsigned int shim_dma_bd7_0 = 0x0001d0e0; +// DMA BD7 Config Register 1 +const unsigned int shim_dma_bd7_1 = 0x0001d0e4; +// DMA BD7 Config Register 2 +const unsigned int shim_dma_bd7_2 = 0x0001d0e8; +// DMA BD7 Config Register 3 +const unsigned int shim_dma_bd7_3 = 0x0001d0ec; +// DMA BD7 Config Register 4 +const unsigned int shim_dma_bd7_4 = 0x0001d0f0; +// DMA BD7 Config Register 5 +const unsigned int shim_dma_bd7_5 = 0x0001d0f4; +// DMA BD7 Config Register 6 +const unsigned int shim_dma_bd7_6 = 0x0001d0f8; +// DMA BD7 Config Register 7 +const unsigned int shim_dma_bd7_7 = 0x0001d0fc; +// DMA BD8 Config Register 0 +const unsigned int shim_dma_bd8_0 = 0x0001d100; +// DMA BD8 Config Register 1 +const unsigned int shim_dma_bd8_1 = 0x0001d104; +// DMA BD8 Config Register 2 +const unsigned int shim_dma_bd8_2 = 0x0001d108; +// DMA BD8 Config Register 3 +const unsigned int shim_dma_bd8_3 = 0x0001d10c; +// DMA BD8 Config Register 4 +const unsigned int shim_dma_bd8_4 = 0x0001d110; +// DMA BD8 Config Register 5 +const unsigned int shim_dma_bd8_5 = 0x0001d114; +// DMA BD8 Config Register 6 +const unsigned int shim_dma_bd8_6 = 0x0001d118; +// DMA BD8 Config Register 7 +const unsigned int shim_dma_bd8_7 = 0x0001d11c; +// DMA BD9 Config Register 0 +const unsigned int shim_dma_bd9_0 = 0x0001d120; +// DMA BD9 Config Register 1 +const unsigned int shim_dma_bd9_1 = 0x0001d124; +// DMA BD9 Config Register 2 +const unsigned int shim_dma_bd9_2 = 0x0001d128; +// DMA BD9 Config Register 3 +const unsigned int shim_dma_bd9_3 = 0x0001d12c; +// DMA BD9 Config Register 4 +const unsigned int shim_dma_bd9_4 = 0x0001d130; +// DMA BD9 Config Register 5 +const unsigned int shim_dma_bd9_5 = 0x0001d134; +// DMA BD9 Config Register 6 +const unsigned int shim_dma_bd9_6 = 0x0001d138; +// DMA BD9 Config Register 7 +const unsigned int shim_dma_bd9_7 = 0x0001d13c; +// DMA BD10 Config Register 0 +const unsigned int shim_dma_bd10_0 = 0x0001d140; +// DMA BD10 Config Register 1 +const unsigned int shim_dma_bd10_1 = 0x0001d144; +// DMA BD10 Config Register 2 +const unsigned int shim_dma_bd10_2 = 0x0001d148; +// DMA BD10 Config Register 3 +const unsigned int shim_dma_bd10_3 = 0x0001d14c; +// DMA BD10 Config Register 4 +const unsigned int shim_dma_bd10_4 = 0x0001d150; +// DMA BD10 Config Register 5 +const unsigned int shim_dma_bd10_5 = 0x0001d154; +// DMA BD10 Config Register 6 +const unsigned int shim_dma_bd10_6 = 0x0001d158; +// DMA BD10 Config Register 7 +const unsigned int shim_dma_bd10_7 = 0x0001d15c; +// DMA BD11 Config Register 0 +const unsigned int shim_dma_bd11_0 = 0x0001d160; +// DMA BD11 Config Register 1 +const unsigned int shim_dma_bd11_1 = 0x0001d164; +// DMA BD11 Config Register 2 +const unsigned int shim_dma_bd11_2 = 0x0001d168; +// DMA BD11 Config Register 3 +const unsigned int shim_dma_bd11_3 = 0x0001d16c; +// DMA BD11 Config Register 4 +const unsigned int shim_dma_bd11_4 = 0x0001d170; +// DMA BD11 Config Register 5 +const unsigned int shim_dma_bd11_5 = 0x0001d174; +// DMA BD11 Config Register 6 +const unsigned int shim_dma_bd11_6 = 0x0001d178; +// DMA BD11 Config Register 7 +const unsigned int shim_dma_bd11_7 = 0x0001d17c; +// DMA BD12 Config Register 0 +const unsigned int shim_dma_bd12_0 = 0x0001d180; +// DMA BD12 Config Register 1 +const unsigned int shim_dma_bd12_1 = 0x0001d184; +// DMA BD12 Config Register 2 +const unsigned int shim_dma_bd12_2 = 0x0001d188; +// DMA BD12 Config Register 3 +const unsigned int shim_dma_bd12_3 = 0x0001d18c; +// DMA BD12 Config Register 4 +const unsigned int shim_dma_bd12_4 = 0x0001d190; +// DMA BD12 Config Register 5 +const unsigned int shim_dma_bd12_5 = 0x0001d194; +// DMA BD12 Config Register 6 +const unsigned int shim_dma_bd12_6 = 0x0001d198; +// DMA BD12 Config Register 7 +const unsigned int shim_dma_bd12_7 = 0x0001d19c; +// DMA BD13 Config Register 0 +const unsigned int shim_dma_bd13_0 = 0x0001d1a0; +// DMA BD13 Config Register 1 +const unsigned int shim_dma_bd13_1 = 0x0001d1a4; +// DMA BD13 Config Register 2 +const unsigned int shim_dma_bd13_2 = 0x0001d1a8; +// DMA BD13 Config Register 3 +const unsigned int shim_dma_bd13_3 = 0x0001d1ac; +// DMA BD13 Config Register 4 +const unsigned int shim_dma_bd13_4 = 0x0001d1b0; +// DMA BD13 Config Register 5 +const unsigned int shim_dma_bd13_5 = 0x0001d1b4; +// DMA BD13 Config Register 6 +const unsigned int shim_dma_bd13_6 = 0x0001d1b8; +// DMA BD13 Config Register 7 +const unsigned int shim_dma_bd13_7 = 0x0001d1bc; +// DMA BD14 Config Register 0 +const unsigned int shim_dma_bd14_0 = 0x0001d1c0; +// DMA BD14 Config Register 1 +const unsigned int shim_dma_bd14_1 = 0x0001d1c4; +// DMA BD14 Config Register 2 +const unsigned int shim_dma_bd14_2 = 0x0001d1c8; +// DMA BD14 Config Register 3 +const unsigned int shim_dma_bd14_3 = 0x0001d1cc; +// DMA BD14 Config Register 4 +const unsigned int shim_dma_bd14_4 = 0x0001d1d0; +// DMA BD14 Config Register 5 +const unsigned int shim_dma_bd14_5 = 0x0001d1d4; +// DMA BD14 Config Register 6 +const unsigned int shim_dma_bd14_6 = 0x0001d1d8; +// DMA BD14 Config Register 7 +const unsigned int shim_dma_bd14_7 = 0x0001d1dc; +// DMA BD15 Config Register 0 +const unsigned int shim_dma_bd15_0 = 0x0001d1e0; +// DMA BD15 Config Register 1 +const unsigned int shim_dma_bd15_1 = 0x0001d1e4; +// DMA BD15 Config Register 2 +const unsigned int shim_dma_bd15_2 = 0x0001d1e8; +// DMA BD15 Config Register 3 +const unsigned int shim_dma_bd15_3 = 0x0001d1ec; +// DMA BD15 Config Register 4 +const unsigned int shim_dma_bd15_4 = 0x0001d1f0; +// DMA BD15 Config Register 5 +const unsigned int shim_dma_bd15_5 = 0x0001d1f4; +// DMA BD15 Config Register 6 +const unsigned int shim_dma_bd15_6 = 0x0001d1f8; +// DMA BD15 Config Register 7 +const unsigned int shim_dma_bd15_7 = 0x0001d1fc; +// DMA S2MM Channel 0 Control +const unsigned int shim_dma_s2mm_0_ctrl = 0x0001d200; +// DMA S2MM Channel 0 Start Queue +const unsigned int shim_dma_s2mm_0_task_queue = 0x0001d204; +// DMA S2MM Channel 0 Status +const unsigned int shim_dma_s2mm_status_0 = 0x0001d220; +// DMA S2MM Channel 1 Status +const unsigned int shim_dma_s2mm_status_1 = 0x0001d224; +// DMA MM2S Channel 0 Status +const unsigned int shim_dma_mm2s_status_0 = 0x0001d228; +// DMA MM2S Channel 1 Status +const unsigned int shim_dma_mm2s_status_1 = 0x0001d22c; +// Performance Counters 1-0 Start and Stop Event +const unsigned int shim_performance_control0 = 0x00031000; +const unsigned int shim_performance_start_stop_0_1 = 0x00031000; +// Performance Counters Reset Events +const unsigned int shim_performance_control1 = 0x00031008; +const unsigned int shim_performance_reset_0_1 = 0x00031008; +// Performance Counter0 +const unsigned int shim_performance_counter0 = 0x00031020; +// Performance Counter1 +const unsigned int shim_performance_counter1 = 0x00031024; +// Performance Counter0 Event Value. +const unsigned int shim_performance_counter0_event_value = 0x00031080; +// Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated +const unsigned int shim_performance_counter1_event_value = 0x00031084; +// Generate an internal event +const unsigned int shim_event_generate = 0x00034008; +// Control of which Internal Event to Broadcast0 +const unsigned int shim_event_broadcast_a_0 = 0x00034010; +// Control of which Internal Event to Broadcast1 +const unsigned int shim_event_broadcast_a_1 = 0x00034014; +// Control of which Internal Event to Broadcast2 +const unsigned int shim_event_broadcast_a_2 = 0x00034018; +// Control of which Internal Event to Broadcast3 +const unsigned int shim_event_broadcast_a_3 = 0x0003401c; +// Control of which Internal Event to Broadcast4 +const unsigned int shim_event_broadcast_a_4 = 0x00034020; +// Control of which Internal Event to Broadcast5 +const unsigned int shim_event_broadcast_a_5 = 0x00034024; +// Control of which Internal Event to Broadcast6 +const unsigned int shim_event_broadcast_a_6 = 0x00034028; +// Control of which Internal Event to Broadcast7 +const unsigned int shim_event_broadcast_a_7 = 0x0003402c; +// Control of which Internal Event to Broadcast8 +const unsigned int shim_event_broadcast_a_8 = 0x00034030; +// Control of which Internal Event to Broadcast9 +const unsigned int shim_event_broadcast_a_9 = 0x00034034; +// Control of which Internal Event to Broadcast10 +const unsigned int shim_event_broadcast_a_10 = 0x00034038; +// Control of which Internal Event to Broadcast11 +const unsigned int shim_event_broadcast_a_11 = 0x0003403c; +// Control of which Internal Event to Broadcast12 +const unsigned int shim_event_broadcast_a_12 = 0x00034040; +// Control of which Internal Event to Broadcast13 +const unsigned int shim_event_broadcast_a_13 = 0x00034044; +// Control of which Internal Event to Broadcast14 +const unsigned int shim_event_broadcast_a_14 = 0x00034048; +// Control of which Internal Event to Broadcast15 +const unsigned int shim_event_broadcast_a_15 = 0x0003404c; +// Set block of broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_set = 0x00034050; +// Clear block of broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_clr = 0x00034054; +// Current value of block for broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_value = 0x00034058; +// Set block of broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_set = 0x00034060; +// Clear block of broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_clr = 0x00034064; +// Current value of block for broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_value = 0x00034068; +// Set block of broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_set = 0x00034070; +// Clear block of broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_clr = 0x00034074; +// Current value of block for broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_value = 0x00034078; +// Set block of broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_set = 0x00034080; +// Clear block of broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_clr = 0x00034084; +// Current value of block for broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_value = 0x00034088; +// Control of Trace +const unsigned int shim_trace_control0 = 0x000340d0; +// Control of Trace: packet destination +const unsigned int shim_trace_control1 = 0x000340d4; +// Status of trace engine +const unsigned int shim_trace_status = 0x000340d8; +// Control of which Internal Event to Broadcast +const unsigned int shim_trace_event0 = 0x000340e0; +// Control of which Internal Event to Broadcast +const unsigned int shim_trace_event1 = 0x000340e4; +// Internal Timer Event Value. +const unsigned int shim_timer_trig_event_low_value = 0x000340f0; +// Internal Timer Event Value. +const unsigned int shim_timer_trig_event_high_value = 0x000340f4; +// Internal Timer Low part Value. +const unsigned int shim_timer_low = 0x000340f8; +// Internal Timer High part Value. +const unsigned int shim_timer_high = 0x000340fc; +// Internal event status register0 +const unsigned int shim_event_status0 = 0x00034200; +// Internal event status register1 +const unsigned int shim_event_status1 = 0x00034204; +// Internal event status register2 +const unsigned int shim_event_status2 = 0x00034208; +// Internal event status register3 +const unsigned int shim_event_status3 = 0x0003420c; +// Combo events input events +const unsigned int shim_combo_event_inputs = 0x00034400; +// Combo events input events +const unsigned int shim_combo_event_control = 0x00034404; +// Event enable for DMA Group +const unsigned int shim_event_group_dma_enable = 0x00034504; +// Stream Switch Ports 0-3 for event generation +const unsigned int shim_stream_switch_event_port_selection_0 = 0x0003ff00; +// Stream Switch Ports 4-7 for event generation +const unsigned int shim_stream_switch_event_port_selection_1 = 0x0003ff04; + +} // namespace aie2 + +#endif /* AIE2_REGISTERS_H_ */ diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_attributes.h b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_attributes.h new file mode 100755 index 00000000000..1ba872920dd --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_attributes.h @@ -0,0 +1,510 @@ +// ####################################################################### +// Copyright (c) 2024 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#ifndef AIE2PS_ATTRIBUTES_H_ +#define AIE2PS_ATTRIBUTES_H_ + +namespace aie2ps +{ + +// Version-Specific Constants +// ################################### + +// Hardware generation +// See: https://gitenterprise.xilinx.com/ai-engine/aie-rt/blob/main/driver/src/global/xaiegbl_defs.h#L46 +const unsigned int hw_gen = 5; +// Tile architecture (used to determine broadcast direction) +const char * const tile_arch = "grid"; +// Total number of rows/columns in AIE array +// Note: See section 3.12 of AIE2ps arch spec +const unsigned int max_rows = 14; +const unsigned int max_cols = 60; +// First row of AIE tiles +// NOTE: row 0 is interface tiles, and rows 1-2 are memory tiles +const unsigned int row_offset = 3; +// Base address of AIE array +const unsigned long long aie_base = 0x20000000000; +// Tile stride (used in addressing) +const unsigned int tile_stride = 0x100000; +// AIE Clock frequency (in MHz) +const unsigned int clock_freq_mhz = 1250; +// Bit widths +const unsigned int stream_bit_width = 64; +const unsigned int cascade_bit_width = 512; +// Trace events per module/tile +const unsigned int num_trace_events = 8; +// Counters per module/tile +const unsigned int cm_num_counters = 4; +const unsigned int mm_num_counters = 4; +const unsigned int mm_num_counter_events = 2; +const unsigned int shim_num_counters = 6; +const unsigned int mem_num_counters = 6; +const unsigned int uc_num_event_counters = 5; +const unsigned int uc_num_latency_counters = 1; +// Broadcast channels per module/tile +const unsigned int cm_num_broadcasts = 16; +const unsigned int mm_num_broadcasts = 16; +const unsigned int shim_num_braodcasts = 16; +const unsigned int mem_num_broadcasts = 16; +// Stream switch event ports per module/tile +const unsigned int cm_num_ss_event_ports = 8; +const unsigned int shim_num_ss_event_ports = 8; +const unsigned int mem_num_ss_event_ports = 8; +// Event status registers (i.e., sticky bits) +const unsigned int cm_num_event_status_regs = 4; +const unsigned int mm_num_event_status_regs = 4; +const unsigned int shim_num_event_status_regs = 8; +const unsigned int mem_num_event_status_regs = 6; +// Microcontrollers (uC) per interface tile +const unsigned int shim_num_uc = 1; +// BD metadata per tile +const unsigned int mm_num_bds = 16; +const unsigned int mm_num_bd_regs = 6; +const unsigned int shim_num_bds = 16; +const unsigned int shim_num_bd_regs = 9; +const unsigned int mem_num_bds = 48; +const unsigned int mem_num_bd_regs = 8; +const unsigned int mem_num_bd_s2mm_channels = 1; +const unsigned int mem_num_bd_mm2s_channels = 1; +// Locks per tile +const unsigned int mm_num_locks = 16; +const unsigned int shim_num_locks = 16; +const unsigned int mem_num_locks = 64; +// Group events +const unsigned int cm_num_group_events = 9; +const unsigned int cm_group_core_stall_index = 3; +const unsigned int cm_group_program_flow_index = 4; +const unsigned int cm_group_stream_switch_index = 7; +// Event masks +const unsigned int shim_event_mask = 0xff; + +// Version-Specific Event IDs +// ################################### + +// AIE tile core modules +const unsigned int cm_event_none = 0; +const unsigned int cm_event_true = 1; +const unsigned int cm_event_perf_count_0 = 5; +const unsigned int cm_event_perf_count_1 = 6; +const unsigned int cm_event_perf_count_2 = 7; +const unsigned int cm_event_perf_count_3 = 8; +const unsigned int cm_event_combo_event_0 = 9; +const unsigned int cm_event_combo_event_1 = 10; +const unsigned int cm_event_combo_event_2 = 11; +const unsigned int cm_event_combo_event_3 = 12; +const unsigned int cm_event_group_core_stall = 22; +const unsigned int cm_event_memory_stall = 23; +const unsigned int cm_event_stream_stall = 24; +const unsigned int cm_event_cascade_stall = 25; +const unsigned int cm_event_lock_stall = 26; +const unsigned int cm_event_active = 28; +const unsigned int cm_event_disabled = 29; +const unsigned int cm_event_group_core_program_flow = 32; +const unsigned int cm_event_instr_event_0 = 33; +const unsigned int cm_event_instr_event_1 = 34; +const unsigned int cm_event_instr_call = 35; +const unsigned int cm_event_instr_return = 36; +const unsigned int cm_event_instr_vector = 37; +const unsigned int cm_event_instr_load = 38; +const unsigned int cm_event_instr_store = 39; +const unsigned int cm_event_instr_stream_get = 40; +const unsigned int cm_event_instr_stream_put = 41; +const unsigned int cm_event_instr_cascade_get = 42; +const unsigned int cm_event_instr_cascade_put = 43; +const unsigned int cm_event_fp_huge = 50; +const unsigned int cm_event_fp_tiny = 51; +const unsigned int cm_event_fp_invalid = 52; +const unsigned int cm_event_fp_infinity = 53; +const unsigned int cm_event_group_stream_switch = 73; +const unsigned int cm_event_port_idle_0 = 74; +const unsigned int cm_event_port_running_0 = 75; +const unsigned int cm_event_port_stalled_0 = 76; +const unsigned int cm_event_port_tlast_0 = 77; +const unsigned int cm_event_port_idle_1 = 78; +const unsigned int cm_event_port_running_1 = 79; +const unsigned int cm_event_port_stalled_1 = 80; +const unsigned int cm_event_port_tlast_1 = 81; +const unsigned int cm_event_port_idle_2 = 82; +const unsigned int cm_event_port_running_2 = 83; +const unsigned int cm_event_port_stalled_2 = 84; +const unsigned int cm_event_port_tlast_2 = 85; +const unsigned int cm_event_port_idle_3 = 86; +const unsigned int cm_event_port_running_3 = 87; +const unsigned int cm_event_port_stalled_3 = 88; +const unsigned int cm_event_port_tlast_3 = 89; +const unsigned int cm_event_port_idle_4 = 90; +const unsigned int cm_event_port_running_4 = 91; +const unsigned int cm_event_port_stalled_4 = 92; +const unsigned int cm_event_port_tlast_4 = 93; +const unsigned int cm_event_port_idle_5 = 94; +const unsigned int cm_event_port_running_5 = 95; +const unsigned int cm_event_port_stalled_5 = 96; +const unsigned int cm_event_port_tlast_5 = 97; +const unsigned int cm_event_port_idle_6 = 98; +const unsigned int cm_event_port_running_6 = 99; +const unsigned int cm_event_port_stalled_6 = 100; +const unsigned int cm_event_port_tlast_6 = 101; +const unsigned int cm_event_port_idle_7 = 102; +const unsigned int cm_event_port_running_7 = 103; +const unsigned int cm_event_port_stalled_7 = 104; +const unsigned int cm_event_port_tlast_7 = 105; +const unsigned int cm_event_broadcast_0 = 107; +const unsigned int cm_event_broadcast_1 = 108; +const unsigned int cm_event_broadcast_2 = 109; +const unsigned int cm_event_broadcast_3 = 110; +const unsigned int cm_event_broadcast_4 = 111; +const unsigned int cm_event_broadcast_5 = 112; +const unsigned int cm_event_broadcast_6 = 113; +const unsigned int cm_event_broadcast_7 = 114; +const unsigned int cm_event_broadcast_8 = 115; +const unsigned int cm_event_broadcast_9 = 116; +const unsigned int cm_event_broadcast_10 = 117; +const unsigned int cm_event_broadcast_11 = 118; +const unsigned int cm_event_broadcast_12 = 119; +const unsigned int cm_event_broadcast_13 = 120; +const unsigned int cm_event_broadcast_14 = 121; +const unsigned int cm_event_broadcast_15 = 122; +const unsigned int cm_event_user_event_0 = 124; +const unsigned int cm_event_user_event_1 = 125; +const unsigned int cm_event_user_event_2 = 126; +const unsigned int cm_event_user_event_3 = 127; + +// AIE tile memory modules +const unsigned int mm_event_perf_count_0 = 5; +const unsigned int mm_event_perf_count_1 = 6; +const unsigned int mm_event_group_dma_activity = 18; +const unsigned int mm_event_dma_finish_bd_s2mm_chan0 = 23; +const unsigned int mm_event_dma_finish_bd_s2mm_chan1 = 24; +const unsigned int mm_event_dma_finish_bd_mm2s_chan0 = 25; +const unsigned int mm_event_dma_finish_bd_mm2s_chan1 = 26; +const unsigned int mm_event_dma_stall_s2mm_chan0 = 31; +const unsigned int mm_event_dma_stall_s2mm_chan1 = 32; +const unsigned int mm_event_dma_stall_mm2s_chan0 = 33; +const unsigned int mm_event_dma_stall_mm2s_chan1 = 34; +const unsigned int mm_event_dma_stream_starvation_s2mm_chan0 = 35; +const unsigned int mm_event_dma_stream_starvation_s2mm_chan1 = 36; +const unsigned int mm_event_dma_stream_backpressure_mm2s_chan0 = 37; +const unsigned int mm_event_dma_stream_backpressure_mm2s_chan1 = 38; +const unsigned int mm_event_dma_memory_backpressure_s2mm_chan0 = 39; +const unsigned int mm_event_dma_memory_backpressure_s2mm_chan1 = 40; +const unsigned int mm_event_dma_memory_starvation_mm2s_chan0 = 41; +const unsigned int mm_event_dma_memory_starvation_mm2s_chan1 = 42; +const unsigned int mm_event_group_lock = 43; +const unsigned int mm_event_group_memory_conflict = 76; +const unsigned int mm_event_group_error = 86; +const unsigned int mm_event_broadcast_14 = 121; +const unsigned int mm_event_broadcast_15 = 122; + +// Interface tiles - general +const unsigned int shim_event_perf_count_0 = 5; +const unsigned int shim_event_perf_count_1 = 6; +const unsigned int shim_event_combo_event_3 = 10; +const unsigned int shim_event_group_dma_activity = 13; +const unsigned int shim_event_dma_s2mm_0_start_task = 14; +const unsigned int shim_event_dma_s2mm_1_start_task = 15; +const unsigned int shim_event_dma_mm2s_0_start_task = 16; +const unsigned int shim_event_dma_mm2s_1_start_task = 17; +const unsigned int shim_event_dma_s2mm_0_finished_bd = 18; +const unsigned int shim_event_dma_s2mm_1_finished_bd = 19; +const unsigned int shim_event_dma_mm2s_0_finished_bd = 20; +const unsigned int shim_event_dma_mm2s_1_finished_bd = 21; +const unsigned int shim_event_dma_s2mm_0_finished_task = 22; +const unsigned int shim_event_dma_s2mm_1_finished_task = 23; +const unsigned int shim_event_dma_mm2s_0_finished_task = 24; +const unsigned int shim_event_dma_mm2s_1_finished_task = 25; +const unsigned int shim_event_dma_s2mm_0_stalled_lock = 26; +const unsigned int shim_event_dma_s2mm_1_stalled_lock = 27; +const unsigned int shim_event_dma_mm2s_0_stalled_lock = 28; +const unsigned int shim_event_dma_mm2s_1_stalled_lock = 29; +const unsigned int shim_event_dma_s2mm_0_stream_starvation = 30; +const unsigned int shim_event_dma_s2mm_1_stream_starvation = 31; +const unsigned int shim_event_dma_mm2s_0_stream_backpressure = 32; +const unsigned int shim_event_dma_mm2s_1_stream_backpressure = 33; +const unsigned int shim_event_dma_s2mm_0_memory_backpressure = 34; +const unsigned int shim_event_dma_s2mm_1_memory_backpressure = 35; +const unsigned int shim_event_dma_mm2s_0_memory_starvation = 36; +const unsigned int shim_event_dma_mm2s_1_memory_starvation = 37; +const unsigned int shim_event_port_idle_0 = 133; +const unsigned int shim_event_port_running_0 = 134; +const unsigned int shim_event_port_stalled_0 = 135; +const unsigned int shim_event_port_tlast_0 = 136; +const unsigned int shim_event_port_idle_1 = 137; +const unsigned int shim_event_port_running_1 = 138; +const unsigned int shim_event_port_stalled_1 = 139; +const unsigned int shim_event_port_tlast_1 = 140; +const unsigned int shim_event_port_idle_2 = 141; +const unsigned int shim_event_port_running_2 = 142; +const unsigned int shim_event_port_stalled_2 = 143; +const unsigned int shim_event_port_tlast_2 = 144; +const unsigned int shim_event_port_idle_3 = 145; +const unsigned int shim_event_port_running_3 = 146; +const unsigned int shim_event_port_stalled_3 = 147; +const unsigned int shim_event_port_tlast_3 = 148; +const unsigned int shim_event_port_idle_4 = 149; +const unsigned int shim_event_port_running_4 = 150; +const unsigned int shim_event_port_stalled_4 = 151; +const unsigned int shim_event_port_tlast_4 = 152; +const unsigned int shim_event_port_idle_5 = 153; +const unsigned int shim_event_port_running_5 = 154; +const unsigned int shim_event_port_stalled_5 = 155; +const unsigned int shim_event_port_tlast_5 = 156; +const unsigned int shim_event_port_idle_6 = 157; +const unsigned int shim_event_port_running_6 = 158; +const unsigned int shim_event_port_stalled_6 = 159; +const unsigned int shim_event_port_tlast_6 = 160; +const unsigned int shim_event_port_idle_7 = 161; +const unsigned int shim_event_port_running_7 = 162; +const unsigned int shim_event_port_stalled_7 = 163; +const unsigned int shim_event_port_tlast_7 = 164; +const unsigned int shim_event_broadcast_0 = 166; +const unsigned int shim_event_broadcast_1 = 167; +const unsigned int shim_event_broadcast_2 = 168; +const unsigned int shim_event_broadcast_3 = 169; +const unsigned int shim_event_broadcast_4 = 170; +const unsigned int shim_event_broadcast_5 = 171; +const unsigned int shim_event_broadcast_6 = 172; +const unsigned int shim_event_broadcast_7 = 173; +const unsigned int shim_event_broadcast_8 = 174; +const unsigned int shim_event_broadcast_9 = 175; +const unsigned int shim_event_broadcast_10 = 176; +const unsigned int shim_event_broadcast_11 = 177; +const unsigned int shim_event_broadcast_12 = 178; +const unsigned int shim_event_broadcast_13 = 179; +const unsigned int shim_event_broadcast_14 = 180; +const unsigned int shim_event_broadcast_15 = 181; +const unsigned int shim_event_user_event_0 = 182; +const unsigned int shim_event_user_event_1 = 183; + +// Interface tiles - uC specific +const unsigned int shim_event_dma_dm2mm_start_task = 185; +const unsigned int shim_event_dma_mm2dm_start_task = 186; +const unsigned int shim_event_dma_dm2mm_finished_bd = 187; +const unsigned int shim_event_dma_mm2dm_finished_bd = 188; +const unsigned int shim_event_dma_dm2mm_finished_task = 189; +const unsigned int shim_event_dma_mm2dm_finished_task = 190; +const unsigned int shim_event_dma_dm2mm_local_memory_starvation = 191; +const unsigned int shim_event_dma_dm2mm_remote_memory_backpressure = 192; +const unsigned int shim_event_dma_mm2dm_local_memory_backpressure = 193; +const unsigned int shim_event_dma_mm2dm_remote_memory_starvation = 194; +const unsigned int shim_event_group_uc_module_errors = 195; +const unsigned int shim_event_axi_mm_uc_core_master_decode_error = 196; +const unsigned int shim_event_axi_mm_uc_dma_master_decode_error = 197; +const unsigned int shim_event_axi_mm_uc_core_master_slave_error = 198; +const unsigned int shim_event_axi_mm_uc_dma_master_slave_error = 199; +const unsigned int shim_event_shim_event_dma_dm2mm_error = 200; +const unsigned int shim_event_shim_event_dma_mm2dm_error = 201; +const unsigned int shim_event_shim_event_pm_ecc_error_1bit = 202; +const unsigned int shim_event_pm_ecc_error_2bit = 203; +const unsigned int shim_event_private_dm_ecc_error_1bit = 204; +const unsigned int shim_event_private_dm_ecc_error_2bit = 205; +const unsigned int shim_event_shared_dm_ecc_error_1bit = 206; +const unsigned int shim_event_shared_dm_ecc_error_2bit = 207; +const unsigned int shim_event_group_uc_core_streams = 208; +const unsigned int shim_event_axis_master_idle = 209; +const unsigned int shim_event_axis_master_running = 210; +const unsigned int shim_event_axis_master_stalled = 211; +const unsigned int shim_event_axis_master_tlast = 212; +const unsigned int shim_event_axis_slave_idle = 213; +const unsigned int shim_event_axis_slave_running = 214; +const unsigned int shim_event_axis_slave_stalled = 215; +const unsigned int shim_event_axis_slave_tlast = 216; +const unsigned int shim_event_group_uc_core_program_flow = 217; +const unsigned int shim_event_uc_core_sleep = 218; +const unsigned int shim_event_uc_core_interrupt = 219; +const unsigned int shim_event_uc_core_debug_sys_rst = 220; +const unsigned int shim_event_uc_core_debug_wakeup = 221; +const unsigned int shim_event_uc_core_timer1_interrupt = 222; +const unsigned int shim_event_uc_core_timer2_interrupt = 223; +const unsigned int shim_event_uc_core_timer3_interrupt = 224; +const unsigned int shim_event_uc_core_timer4_interrupt = 225; +const unsigned int shim_event_uc_core_reg_write = 226; +const unsigned int shim_event_uc_core_exception_taken = 227; +const unsigned int shim_event_uc_core_jump_taken = 228; +const unsigned int shim_event_uc_core_jump_hit = 229; +const unsigned int shim_event_uc_core_data_read = 230; +const unsigned int shim_event_uc_core_data_write = 231; +const unsigned int shim_event_uc_core_pipeline_halted_debug = 232; +const unsigned int shim_event_uc_core_stream_get = 233; +const unsigned int shim_event_uc_core_stream_put = 234; + +// MicroBlaze Debug Module (MDM) +const unsigned int uc_event_valid_instruction = 0; +const unsigned int uc_event_load_word = 1; +const unsigned int uc_event_load_halfword = 2; +const unsigned int uc_event_load_byte = 3; +const unsigned int uc_event_store_word = 4; +const unsigned int uc_event_store_halfword = 5; +const unsigned int uc_event_store_byte = 6; +const unsigned int uc_event_unconditional_branch = 7; +const unsigned int uc_event_taken_conditional_branch = 8; +const unsigned int uc_event_not_taken_conditional_branch = 9; +const unsigned int uc_event_load_execution_r1 = 16; +const unsigned int uc_event_store_execution_r1 = 17; +const unsigned int uc_event_logical_execution = 18; +const unsigned int uc_event_arithmetic_execution = 19; +const unsigned int uc_event_multiply_execution = 20; +const unsigned int uc_event_barrel_shift_execution = 21; +const unsigned int uc_event_shift_execution = 22; +const unsigned int uc_event_exception = 23; +const unsigned int uc_event_interrupt = 24; +const unsigned int uc_event_pipeline_stall_operand_fetch = 25; +const unsigned int uc_event_pipeline_stall_execute = 26; +const unsigned int uc_event_pipeline_stall_memory = 27; +const unsigned int uc_event_integer_divide = 28; +const unsigned int uc_event_floating_point = 29; +const unsigned int uc_event_clock_cycles = 30; +const unsigned int uc_event_immediate = 31; +const unsigned int uc_event_pattern_compare = 32; +const unsigned int uc_event_sign_extend = 33; +const unsigned int uc_event_machine_status = 36; +const unsigned int uc_event_unconditional_branch_delay = 37; +const unsigned int uc_event_taken_conditional_branch_delay = 38; +const unsigned int uc_event_not_taken_conditional_branch_delay = 39; +const unsigned int uc_event_delay_slot = 40; +const unsigned int uc_event_load_execution = 41; +const unsigned int uc_event_store_execution = 42; +const unsigned int uc_event_mmu_data_access = 43; +const unsigned int uc_event_conditional_branch = 44; +const unsigned int uc_event_branch = 45; +const unsigned int uc_event_mmu_exception = 48; +const unsigned int uc_event_mmu_instruction_exception = 49; +const unsigned int uc_event_mmu_data_exception = 50; +const unsigned int uc_event_pipeline_stall = 51; +const unsigned int uc_event_mmu_side_access = 53; +const unsigned int uc_event_mmu_instruction_hit = 54; +const unsigned int uc_event_mmu_data_hit = 55; +const unsigned int uc_event_mmu_unified_hit = 56; +// The events below can be used with either event or latency counters +const unsigned int uc_event_interrupt_latency = 57; +const unsigned int uc_event_mmu_lookup_latency = 61; +const unsigned int uc_event_peripheral_data_read = 62; +const unsigned int uc_event_peripheral_data_write = 63; + +// Memory tiles +const unsigned int mem_event_edge_detection_0 = 13; +const unsigned int mem_event_edge_detection_1 = 14; +const unsigned int mem_event_group_watchpoint = 15; +const unsigned int mem_event_dma_s2mm_sel0_start_task = 21; +const unsigned int mem_event_dma_s2mm_sel1_start_task = 22; +const unsigned int mem_event_dma_mm2s_sel0_start_task = 23; +const unsigned int mem_event_dma_mm2s_sel1_start_task = 24; +const unsigned int mem_event_dma_s2mm_sel0_finished_bd = 25; +const unsigned int mem_event_dma_s2mm_sel1_finished_bd = 26; +const unsigned int mem_event_dma_mm2s_sel0_finished_bd = 27; +const unsigned int mem_event_dma_mm2s_sel1_finished_bd = 28; +const unsigned int mem_event_dma_s2mm_sel0_finished_task = 29; +const unsigned int mem_event_dma_s2mm_sel1_finished_task = 30; +const unsigned int mem_event_dma_mm2s_sel0_finished_task = 31; +const unsigned int mem_event_dma_mm2s_sel1_finished_task = 32; +const unsigned int mem_event_dma_s2mm_sel0_stalled_lock = 33; +const unsigned int mem_event_dma_s2mm_sel1_stalled_lock = 34; +const unsigned int mem_event_dma_mm2s_sel0_stalled_lock = 35; +const unsigned int mem_event_dma_mm2s_sel1_stalled_lock = 36; +const unsigned int mem_event_dma_s2mm_sel0_stream_starvation = 37; +const unsigned int mem_event_dma_mm2s_sel0_stream_backpressure = 39; +const unsigned int mem_event_dma_s2mm_sel0_memory_backpressure = 41; +const unsigned int mem_event_dma_mm2s_sel0_memory_starvation = 43; +const unsigned int mem_event_dma_mm2s_sel1_memory_starvation = 44; +const unsigned int mem_event_group_lock = 45; +const unsigned int mem_event_port_idle_0 = 79; +const unsigned int mem_event_port_running_0 = 80; +const unsigned int mem_event_port_stalled_0 = 81; +const unsigned int mem_event_port_tlast_0 = 82; +const unsigned int mem_event_port_idle_1 = 83; +const unsigned int mem_event_port_running_1 = 84; +const unsigned int mem_event_port_stalled_1 = 85; +const unsigned int mem_event_port_tlast_1 = 86; +const unsigned int mem_event_port_idle_2 = 87; +const unsigned int mem_event_port_running_2 = 88; +const unsigned int mem_event_port_stalled_2 = 89; +const unsigned int mem_event_port_tlast_2 = 90; +const unsigned int mem_event_port_idle_3 = 91; +const unsigned int mem_event_port_running_3 = 92; +const unsigned int mem_event_port_stalled_3 = 93; +const unsigned int mem_event_port_tlast_3 = 94; +const unsigned int mem_event_port_idle_4 = 95; +const unsigned int mem_event_port_running_4 = 96; +const unsigned int mem_event_port_stalled_4 = 97; +const unsigned int mem_event_port_tlast_4 = 98; +const unsigned int mem_event_port_idle_5 = 99; +const unsigned int mem_event_port_running_5 = 100; +const unsigned int mem_event_port_stalled_5 = 101; +const unsigned int mem_event_port_tlast_5 = 102; +const unsigned int mem_event_port_idle_6 = 103; +const unsigned int mem_event_port_running_6 = 104; +const unsigned int mem_event_port_stalled_6 = 105; +const unsigned int mem_event_port_tlast_6 = 106; +const unsigned int mem_event_port_idle_7 = 107; +const unsigned int mem_event_port_running_7 = 108; +const unsigned int mem_event_port_stalled_7 = 109; +const unsigned int mem_event_port_tlast_7 = 110; +const unsigned int mem_event_group_memory_conflict = 111; +const unsigned int mem_event_memory_conflict_bank_0 = 112; +const unsigned int mem_event_memory_conflict_bank_1 = 113; +const unsigned int mem_event_memory_conflict_bank_2 = 114; +const unsigned int mem_event_memory_conflict_bank_3 = 115; +const unsigned int mem_event_memory_conflict_bank_4 = 116; +const unsigned int mem_event_memory_conflict_bank_5 = 117; +const unsigned int mem_event_memory_conflict_bank_6 = 118; +const unsigned int mem_event_memory_conflict_bank_7 = 119; +const unsigned int mem_event_memory_conflict_bank_8 = 120; +const unsigned int mem_event_memory_conflict_bank_9 = 121; +const unsigned int mem_event_memory_conflict_bank_10 = 122; +const unsigned int mem_event_memory_conflict_bank_11 = 123; +const unsigned int mem_event_memory_conflict_bank_12 = 124; +const unsigned int mem_event_memory_conflict_bank_13 = 125; +const unsigned int mem_event_memory_conflict_bank_14 = 126; +const unsigned int mem_event_memory_conflict_bank_15 = 127; +const unsigned int mem_event_group_errors = 128; +const unsigned int mem_event_user_event_0 = 159; +const unsigned int mem_event_user_event_1 = 160; + +// Version-Specific Port Indices +// ################################### + +const unsigned int cm_dma_channel0_port_index = 1; +const unsigned int cm_dma_channel1_port_index = 2; +const unsigned int cm_core_trace_slave_port_index = 23; +const unsigned int cm_mem_trace_slave_port_index = 24; + +const unsigned int shim_south0_slave_port_index = 2; +const unsigned int shim_south0_master_port_index = 2; +const unsigned int shim_north0_slave_port_index = 14; +const unsigned int shim_north0_master_port_index = 12; + +// Bit Definitions in Key Registers +// ################################### + +const unsigned int uc_mdm_pccmdr_clear_bit = 4; +const unsigned int uc_mdm_pccmdr_start_bit = 3; +const unsigned int uc_mdm_pccmdr_stop_bit = 2; +const unsigned int uc_mdm_pccmdr_sample_bit = 1; +const unsigned int uc_mdm_pccmdr_reset_bit = 0; +const unsigned int uc_mdm_pcsr_overflow_bit = 1; +const unsigned int uc_mdm_pcsr_full_bit = 0; +const unsigned int uc_mdm_pcdrr_latency_reads = 4; + +} // namespace aie2ps + +#endif /* AIE2PS_ATTRIBUTES_H_ */ diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h new file mode 100644 index 00000000000..425b72212fc --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h @@ -0,0 +1,3663 @@ +// ####################################################################### +// Copyright (c) 2024 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ####################################################################### + +#ifndef AIE2PS_REGISTERS_H_ +#define AIE2PS_REGISTERS_H_ + +namespace aie2ps +{ + +// Register definitions for AIE2PS +// ################################### + +// Register definitions for core module +// #################################### +// Accumulator BMLL0 Part 1 +const unsigned int cm_core_bmll0_part1 = 0x00030000; +// Accumulator BMLL0 Part 2 +const unsigned int cm_core_bmll0_part2 = 0x00030010; +// Accumulator BMLL0 Part 3 +const unsigned int cm_core_bmll0_part3 = 0x00030020; +// Accumulator BMLL0 Part 4 +const unsigned int cm_core_bmll0_part4 = 0x00030030; +// Accumulator BMLH0 Part 1 +const unsigned int cm_core_bmlh0_part1 = 0x00030040; +// Accumulator BMLH0 Part 2 +const unsigned int cm_core_bmlh0_part2 = 0x00030050; +// Accumulator BMLH0 Part 3 +const unsigned int cm_core_bmlh0_part3 = 0x00030060; +// Accumulator BMLH0 Part 4 +const unsigned int cm_core_bmlh0_part4 = 0x00030070; +// Accumulator BMHL0 Part 1 +const unsigned int cm_core_bmhl0_part1 = 0x00030080; +// Accumulator BMHL0 Part 2 +const unsigned int cm_core_bmhl0_part2 = 0x00030090; +// Accumulator BMHL0 Part 3 +const unsigned int cm_core_bmhl0_part3 = 0x000300a0; +// Accumulator BMLH0 Part 4 +const unsigned int cm_core_bmhl0_part4 = 0x000300b0; +// Accumulator BMHH0 Part 1 +const unsigned int cm_core_bmhh0_part1 = 0x000300c0; +// Accumulator BMHH0 Part 2 +const unsigned int cm_core_bmhh0_part2 = 0x000300d0; +// Accumulator BMHH0 Part 3 +const unsigned int cm_core_bmhh0_part3 = 0x000300e0; +// Accumulator BMLH0 Part 4 +const unsigned int cm_core_bmhh0_part4 = 0x000300f0; +// Accumulator BMLL1 Part 1 +const unsigned int cm_core_bmll1_part1 = 0x00030100; +// Accumulator BMLL1 Part 2 +const unsigned int cm_core_bmll1_part2 = 0x00030110; +// Accumulator BMLL1 Part 3 +const unsigned int cm_core_bmll1_part3 = 0x00030120; +// Accumulator BMLL1 Part 4 +const unsigned int cm_core_bmll1_part4 = 0x00030130; +// Accumulator BMLH1 Part 1 +const unsigned int cm_core_bmlh1_part1 = 0x00030140; +// Accumulator BMLH1 Part 2 +const unsigned int cm_core_bmlh1_part2 = 0x00030150; +// Accumulator BMLH1 Part 3 +const unsigned int cm_core_bmlh1_part3 = 0x00030160; +// Accumulator BMLH1 Part 4 +const unsigned int cm_core_bmlh1_part4 = 0x00030170; +// Accumulator BMHL1 Part 1 +const unsigned int cm_core_bmhl1_part1 = 0x00030180; +// Accumulator BMHL1 Part 2 +const unsigned int cm_core_bmhl1_part2 = 0x00030190; +// Accumulator BMHL1 Part 3 +const unsigned int cm_core_bmhl1_part3 = 0x000301a0; +// Accumulator BMLH1 Part 4 +const unsigned int cm_core_bmhl1_part4 = 0x000301b0; +// Accumulator BMHH1 Part 1 +const unsigned int cm_core_bmhh1_part1 = 0x000301c0; +// Accumulator BMHH1 Part 2 +const unsigned int cm_core_bmhh1_part2 = 0x000301d0; +// Accumulator BMHH1 Part 3 +const unsigned int cm_core_bmhh1_part3 = 0x000301e0; +// Accumulator BMLH1 Part 4 +const unsigned int cm_core_bmhh1_part4 = 0x000301f0; +// Accumulator BMLL2 Part 1 +const unsigned int cm_core_bmll2_part1 = 0x00030200; +// Accumulator BMLL2 Part 2 +const unsigned int cm_core_bmll2_part2 = 0x00030210; +// Accumulator BMLL2 Part 3 +const unsigned int cm_core_bmll2_part3 = 0x00030220; +// Accumulator BMLL2 Part 4 +const unsigned int cm_core_bmll2_part4 = 0x00030230; +// Accumulator BMLH2 Part 1 +const unsigned int cm_core_bmlh2_part1 = 0x00030240; +// Accumulator BMLH2 Part 2 +const unsigned int cm_core_bmlh2_part2 = 0x00030250; +// Accumulator BMLH2 Part 3 +const unsigned int cm_core_bmlh2_part3 = 0x00030260; +// Accumulator BMLH2 Part 4 +const unsigned int cm_core_bmlh2_part4 = 0x00030270; +// Accumulator BMHL2 Part 1 +const unsigned int cm_core_bmhl2_part1 = 0x00030280; +// Accumulator BMHL2 Part 2 +const unsigned int cm_core_bmhl2_part2 = 0x00030290; +// Accumulator BMHL2 Part 3 +const unsigned int cm_core_bmhl2_part3 = 0x000302a0; +// Accumulator BMLH2 Part 4 +const unsigned int cm_core_bmhl2_part4 = 0x000302b0; +// Accumulator BMHH2 Part 1 +const unsigned int cm_core_bmhh2_part1 = 0x000302c0; +// Accumulator BMHH2 Part 2 +const unsigned int cm_core_bmhh2_part2 = 0x000302d0; +// Accumulator BMHH2 Part 3 +const unsigned int cm_core_bmhh2_part3 = 0x000302e0; +// Accumulator BMLH2 Part 4 +const unsigned int cm_core_bmhh2_part4 = 0x000302f0; +// Accumulator BMLL3 Part 1 +const unsigned int cm_core_bmll3_part1 = 0x00030300; +// Accumulator BMLL3 Part 2 +const unsigned int cm_core_bmll3_part2 = 0x00030310; +// Accumulator BMLL3 Part 3 +const unsigned int cm_core_bmll3_part3 = 0x00030320; +// Accumulator BMLL3 Part 4 +const unsigned int cm_core_bmll3_part4 = 0x00030330; +// Accumulator BMLH3 Part 1 +const unsigned int cm_core_bmlh3_part1 = 0x00030340; +// Accumulator BMLH3 Part 2 +const unsigned int cm_core_bmlh3_part2 = 0x00030350; +// Accumulator BMLH3 Part 3 +const unsigned int cm_core_bmlh3_part3 = 0x00030360; +// Accumulator BMLH3 Part 4 +const unsigned int cm_core_bmlh3_part4 = 0x00030370; +// Accumulator BMHL3 Part 1 +const unsigned int cm_core_bmhl3_part1 = 0x00030380; +// Accumulator BMHL3 Part 2 +const unsigned int cm_core_bmhl3_part2 = 0x00030390; +// Accumulator BMHL3 Part 3 +const unsigned int cm_core_bmhl3_part3 = 0x000303a0; +// Accumulator BMLH3 Part 4 +const unsigned int cm_core_bmhl3_part4 = 0x000303b0; +// Accumulator BMHH3 Part 1 +const unsigned int cm_core_bmhh3_part1 = 0x000303c0; +// Accumulator BMHH3 Part 2 +const unsigned int cm_core_bmhh3_part2 = 0x000303d0; +// Accumulator BMHH3 Part 3 +const unsigned int cm_core_bmhh3_part3 = 0x000303e0; +// Accumulator BMLH3 Part 4 +const unsigned int cm_core_bmhh3_part4 = 0x000303f0; +// Accumulator BMLL4 Part 1 +const unsigned int cm_core_bmll4_part1 = 0x00030400; +// Accumulator BMLL4 Part 2 +const unsigned int cm_core_bmll4_part2 = 0x00030410; +// Accumulator BMLL4 Part 3 +const unsigned int cm_core_bmll4_part3 = 0x00030420; +// Accumulator BMLL4 Part 4 +const unsigned int cm_core_bmll4_part4 = 0x00030430; +// Accumulator BMLH4 Part 1 +const unsigned int cm_core_bmlh4_part1 = 0x00030440; +// Accumulator BMLH4 Part 2 +const unsigned int cm_core_bmlh4_part2 = 0x00030450; +// Accumulator BMLH4 Part 3 +const unsigned int cm_core_bmlh4_part3 = 0x00030460; +// Accumulator BMLH4 Part 4 +const unsigned int cm_core_bmlh4_part4 = 0x00030470; +// Accumulator BMHL4 Part 1 +const unsigned int cm_core_bmhl4_part1 = 0x00030480; +// Accumulator BMHL4 Part 2 +const unsigned int cm_core_bmhl4_part2 = 0x00030490; +// Accumulator BMHL4 Part 3 +const unsigned int cm_core_bmhl4_part3 = 0x000304a0; +// Accumulator BMLH4 Part 4 +const unsigned int cm_core_bmhl4_part4 = 0x000304b0; +// Accumulator BMHH4 Part 1 +const unsigned int cm_core_bmhh4_part1 = 0x000304c0; +// Accumulator BMHH4 Part 2 +const unsigned int cm_core_bmhh4_part2 = 0x000304d0; +// Accumulator BMHH4 Part 3 +const unsigned int cm_core_bmhh4_part3 = 0x000304e0; +// Accumulator BMLH4 Part 4 +const unsigned int cm_core_bmhh4_part4 = 0x000304f0; +// Accumulator BMLL5 Part 1 +const unsigned int cm_core_bmll5_part1 = 0x00030500; +// Accumulator BMLL5 Part 2 +const unsigned int cm_core_bmll5_part2 = 0x00030510; +// Accumulator BMLL5 Part 3 +const unsigned int cm_core_bmll5_part3 = 0x00030520; +// Accumulator BMLL5 Part 4 +const unsigned int cm_core_bmll5_part4 = 0x00030530; +// Accumulator BMLH5 Part 1 +const unsigned int cm_core_bmlh5_part1 = 0x00030540; +// Accumulator BMLH5 Part 2 +const unsigned int cm_core_bmlh5_part2 = 0x00030550; +// Accumulator BMLH5 Part 3 +const unsigned int cm_core_bmlh5_part3 = 0x00030560; +// Accumulator BMLH5 Part 4 +const unsigned int cm_core_bmlh5_part4 = 0x00030570; +// Accumulator BMHL5 Part 1 +const unsigned int cm_core_bmhl5_part1 = 0x00030580; +// Accumulator BMHL5 Part 2 +const unsigned int cm_core_bmhl5_part2 = 0x00030590; +// Accumulator BMHL5 Part 3 +const unsigned int cm_core_bmhl5_part3 = 0x000305a0; +// Accumulator BMLH5 Part 4 +const unsigned int cm_core_bmhl5_part4 = 0x000305b0; +// Accumulator BMHH5 Part 1 +const unsigned int cm_core_bmhh5_part1 = 0x000305c0; +// Accumulator BMHH5 Part 2 +const unsigned int cm_core_bmhh5_part2 = 0x000305d0; +// Accumulator BMHH5 Part 3 +const unsigned int cm_core_bmhh5_part3 = 0x000305e0; +// Accumulator BMLH5 Part 4 +const unsigned int cm_core_bmhh5_part4 = 0x000305f0; +// Accumulator BMLL6 Part 1 +const unsigned int cm_core_bmll6_part1 = 0x00030600; +// Accumulator BMLL6 Part 2 +const unsigned int cm_core_bmll6_part2 = 0x00030610; +// Accumulator BMLL6 Part 3 +const unsigned int cm_core_bmll6_part3 = 0x00030620; +// Accumulator BMLL6 Part 4 +const unsigned int cm_core_bmll6_part4 = 0x00030630; +// Accumulator BMLH6 Part 1 +const unsigned int cm_core_bmlh6_part1 = 0x00030640; +// Accumulator BMLH6 Part 2 +const unsigned int cm_core_bmlh6_part2 = 0x00030650; +// Accumulator BMLH6 Part 3 +const unsigned int cm_core_bmlh6_part3 = 0x00030660; +// Accumulator BMLH6 Part 4 +const unsigned int cm_core_bmlh6_part4 = 0x00030670; +// Accumulator BMHL6 Part 1 +const unsigned int cm_core_bmhl6_part1 = 0x00030680; +// Accumulator BMHL6 Part 2 +const unsigned int cm_core_bmhl6_part2 = 0x00030690; +// Accumulator BMHL6 Part 3 +const unsigned int cm_core_bmhl6_part3 = 0x000306a0; +// Accumulator BMLH6 Part 4 +const unsigned int cm_core_bmhl6_part4 = 0x000306b0; +// Accumulator BMHH6 Part 1 +const unsigned int cm_core_bmhh6_part1 = 0x000306c0; +// Accumulator BMHH6 Part 2 +const unsigned int cm_core_bmhh6_part2 = 0x000306d0; +// Accumulator BMHH6 Part 3 +const unsigned int cm_core_bmhh6_part3 = 0x000306e0; +// Accumulator BMLH6 Part 4 +const unsigned int cm_core_bmhh6_part4 = 0x000306f0; +// Accumulator BMLL7 Part 1 +const unsigned int cm_core_bmll7_part1 = 0x00030700; +// Accumulator BMLL7 Part 2 +const unsigned int cm_core_bmll7_part2 = 0x00030710; +// Accumulator BMLL7 Part 3 +const unsigned int cm_core_bmll7_part3 = 0x00030720; +// Accumulator BMLL7 Part 4 +const unsigned int cm_core_bmll7_part4 = 0x00030730; +// Accumulator BMLH7 Part 1 +const unsigned int cm_core_bmlh7_part1 = 0x00030740; +// Accumulator BMLH7 Part 2 +const unsigned int cm_core_bmlh7_part2 = 0x00030750; +// Accumulator BMLH7 Part 3 +const unsigned int cm_core_bmlh7_part3 = 0x00030760; +// Accumulator BMLH7 Part 4 +const unsigned int cm_core_bmlh7_part4 = 0x00030770; +// Accumulator BMHL7 Part 1 +const unsigned int cm_core_bmhl7_part1 = 0x00030780; +// Accumulator BMHL7 Part 2 +const unsigned int cm_core_bmhl7_part2 = 0x00030790; +// Accumulator BMHL7 Part 3 +const unsigned int cm_core_bmhl7_part3 = 0x000307a0; +// Accumulator BMLH7 Part 4 +const unsigned int cm_core_bmhl7_part4 = 0x000307b0; +// Accumulator BMHH7 Part 1 +const unsigned int cm_core_bmhh7_part1 = 0x000307c0; +// Accumulator BMHH7 Part 2 +const unsigned int cm_core_bmhh7_part2 = 0x000307d0; +// Accumulator BMHH7 Part 3 +const unsigned int cm_core_bmhh7_part3 = 0x000307e0; +// Accumulator BMLH7 Part 4 +const unsigned int cm_core_bmhh7_part4 = 0x000307f0; +// Vector register X0 Part 1 +const unsigned int cm_core_x0_part1 = 0x00031800; +// Vector register X0 Part 2 +const unsigned int cm_core_x0_part2 = 0x00031810; +// Vector register X0 Part 3 +const unsigned int cm_core_x0_part3 = 0x00031820; +// Vector register X0 Part 4 +const unsigned int cm_core_x0_part4 = 0x00031830; +// Vector register X1 Part 1 +const unsigned int cm_core_x1_part1 = 0x00031840; +// Vector register X1 Part 2 +const unsigned int cm_core_x1_part2 = 0x00031850; +// Vector register X1 Part 3 +const unsigned int cm_core_x1_part3 = 0x00031860; +// Vector register X1 Part 4 +const unsigned int cm_core_x1_part4 = 0x00031870; +// Vector register X2 Part 1 +const unsigned int cm_core_x2_part1 = 0x00031880; +// Vector register X2 Part 2 +const unsigned int cm_core_x2_part2 = 0x00031890; +// Vector register X2 Part 3 +const unsigned int cm_core_x2_part3 = 0x000318a0; +// Vector register X2 Part 4 +const unsigned int cm_core_x2_part4 = 0x000318b0; +// Vector register X3 Part 1 +const unsigned int cm_core_x3_part1 = 0x000318c0; +// Vector register X3 Part 2 +const unsigned int cm_core_x3_part2 = 0x000318d0; +// Vector register X3 Part 3 +const unsigned int cm_core_x3_part3 = 0x000318e0; +// Vector register X3 Part 4 +const unsigned int cm_core_x3_part4 = 0x000318f0; +// Vector register X4 Part 1 +const unsigned int cm_core_x4_part1 = 0x00031900; +// Vector register X4 Part 2 +const unsigned int cm_core_x4_part2 = 0x00031910; +// Vector register X4 Part 3 +const unsigned int cm_core_x4_part3 = 0x00031920; +// Vector register X4 Part 4 +const unsigned int cm_core_x4_part4 = 0x00031930; +// Vector register X5 Part 1 +const unsigned int cm_core_x5_part1 = 0x00031940; +// Vector register X5 Part 2 +const unsigned int cm_core_x5_part2 = 0x00031950; +// Vector register X5 Part 3 +const unsigned int cm_core_x5_part3 = 0x00031960; +// Vector register X5 Part 4 +const unsigned int cm_core_x5_part4 = 0x00031970; +// Vector register X6 Part 1 +const unsigned int cm_core_x6_part1 = 0x00031980; +// Vector register X6 Part 2 +const unsigned int cm_core_x6_part2 = 0x00031990; +// Vector register X6 Part 3 +const unsigned int cm_core_x6_part3 = 0x000319a0; +// Vector register X6 Part 4 +const unsigned int cm_core_x6_part4 = 0x000319b0; +// Vector register X7 Part 1 +const unsigned int cm_core_x7_part1 = 0x000319c0; +// Vector register X7 Part 2 +const unsigned int cm_core_x7_part2 = 0x000319d0; +// Vector register X7 Part 3 +const unsigned int cm_core_x7_part3 = 0x000319e0; +// Vector register X7 Part 4 +const unsigned int cm_core_x7_part4 = 0x000319f0; +// Vector register X8 Part 1 +const unsigned int cm_core_x8_part1 = 0x00031a00; +// Vector register X8 Part 2 +const unsigned int cm_core_x8_part2 = 0x00031a10; +// Vector register X8 Part 3 +const unsigned int cm_core_x8_part3 = 0x00031a20; +// Vector register X8 Part 4 +const unsigned int cm_core_x8_part4 = 0x00031a30; +// Vector register X9 Part 1 +const unsigned int cm_core_x9_part1 = 0x00031a40; +// Vector register X9 Part 2 +const unsigned int cm_core_x9_part2 = 0x00031a50; +// Vector register X9 Part 3 +const unsigned int cm_core_x9_part3 = 0x00031a60; +// Vector register X9 Part 4 +const unsigned int cm_core_x9_part4 = 0x00031a70; +// Vector register X10 Part 1 +const unsigned int cm_core_x10_part1 = 0x00031a80; +// Vector register X10 Part 2 +const unsigned int cm_core_x10_part2 = 0x00031a90; +// Vector register X10 Part 3 +const unsigned int cm_core_x10_part3 = 0x00031aa0; +// Vector register X10 Part 4 +const unsigned int cm_core_x10_part4 = 0x00031ab0; +// Vector register X11 Part 1 +const unsigned int cm_core_x11_part1 = 0x00031ac0; +// Vector register X11 Part 2 +const unsigned int cm_core_x11_part2 = 0x00031ad0; +// Vector register X11 Part 3 +const unsigned int cm_core_x11_part3 = 0x00031ae0; +// Vector register X11 Part 4 +const unsigned int cm_core_x11_part4 = 0x00031af0; +// LDFIFOL0 Part 1 +const unsigned int cm_core_ldfifol0_part1 = 0x00032400; +// LDFIFOL0 Part 2 +const unsigned int cm_core_ldfifol0_part2 = 0x00032410; +// LDFIFOL0 Part 3 +const unsigned int cm_core_ldfifol0_part3 = 0x00032420; +// LDFIFOL0 Part 4 +const unsigned int cm_core_ldfifol0_part4 = 0x00032430; +// LDFIFOH0 Part 1 +const unsigned int cm_core_ldfifoh0_part1 = 0x00032440; +// LDFIFOH0 Part 2 +const unsigned int cm_core_ldfifoh0_part2 = 0x00032450; +// LDFIFOH0 Part 3 +const unsigned int cm_core_ldfifoh0_part3 = 0x00032460; +// LDFIFOH0 Part 4 +const unsigned int cm_core_ldfifoh0_part4 = 0x00032470; +// LDFIFOL1 Part 1 +const unsigned int cm_core_ldfifol1_part1 = 0x00032480; +// LDFIFOL1 Part 2 +const unsigned int cm_core_ldfifol1_part2 = 0x00032490; +// LDFIFOL1 Part 3 +const unsigned int cm_core_ldfifol1_part3 = 0x000324a0; +// LDFIFOL1 Part 4 +const unsigned int cm_core_ldfifol1_part4 = 0x000324b0; +// LDFIFOH1 Part 1 +const unsigned int cm_core_ldfifoh1_part1 = 0x000324c0; +// LDFIFOH1 Part 2 +const unsigned int cm_core_ldfifoh1_part2 = 0x000324d0; +// LDFIFOH1 Part 3 +const unsigned int cm_core_ldfifoh1_part3 = 0x000324e0; +// LDFIFOH1 Part 4 +const unsigned int cm_core_ldfifoh1_part4 = 0x000324f0; +// STFIFOL Part 1 +const unsigned int cm_core_stfifol_part1 = 0x00032500; +// STFIFOL Part 2 +const unsigned int cm_core_stfifol_part2 = 0x00032510; +// STFIFOL Part 3 +const unsigned int cm_core_stfifol_part3 = 0x00032520; +// STFIFOL Part 4 +const unsigned int cm_core_stfifol_part4 = 0x00032530; +// STFIFOH Part 1 +const unsigned int cm_core_stfifoh_part1 = 0x00032540; +// STFIFOH Part 2 +const unsigned int cm_core_stfifoh_part2 = 0x00032550; +// STFIFOH Part 3 +const unsigned int cm_core_stfifoh_part3 = 0x00032560; +// STFIFOH Part 4 +const unsigned int cm_core_stfifoh_part4 = 0x00032570; +// FIFOXTRA Part 1 +const unsigned int cm_core_fifoxtra_part1 = 0x00032580; +// FIFOXTRA Part 2 +const unsigned int cm_core_fifoxtra_part2 = 0x00032590; +// FIFOXTRA Part 3 +const unsigned int cm_core_fifoxtra_part3 = 0x000325a0; +// FIFOXTRA Part 4 +const unsigned int cm_core_fifoxtra_part4 = 0x000325b0; +// Combined exponent register EG0 +const unsigned int cm_core_eg0 = 0x00032600; +// Combined exponent register EG1 +const unsigned int cm_core_eg1 = 0x00032610; +// Combined exponent register EG2 +const unsigned int cm_core_eg2 = 0x00032620; +// Combined exponent register EG3 +const unsigned int cm_core_eg3 = 0x00032630; +// Combined exponent register EG4 +const unsigned int cm_core_eg4 = 0x00032640; +// Combined exponent register EG5 +const unsigned int cm_core_eg5 = 0x00032650; +// Combined exponent register EG6 +const unsigned int cm_core_eg6 = 0x00032660; +// Combined exponent register EG7 +const unsigned int cm_core_eg7 = 0x00032670; +// Combined exponent register EG8 +const unsigned int cm_core_eg8 = 0x00032680; +// Combined exponent register EG9 +const unsigned int cm_core_eg9 = 0x00032690; +// Combined exponent register EG10 +const unsigned int cm_core_eg10 = 0x000326a0; +// Combined exponent register EG11 +const unsigned int cm_core_eg11 = 0x000326b0; +// Mantissa msb register F0 +const unsigned int cm_core_f0 = 0x00032700; +// Mantissa msb register F1 +const unsigned int cm_core_f1 = 0x00032710; +// Mantissa msb register F2 +const unsigned int cm_core_f2 = 0x00032720; +// Mantissa msb register F3 +const unsigned int cm_core_f3 = 0x00032730; +// Mantissa msb register F4 +const unsigned int cm_core_f4 = 0x00032740; +// Mantissa msb register F5 +const unsigned int cm_core_f5 = 0x00032750; +// Mantissa msb register F6 +const unsigned int cm_core_f6 = 0x00032760; +// Mantissa msb register F7 +const unsigned int cm_core_f7 = 0x00032770; +// Mantissa msb register F8 +const unsigned int cm_core_f8 = 0x00032780; +// Mantissa msb register F9 +const unsigned int cm_core_f9 = 0x00032790; +// Mantissa msb register F10 +const unsigned int cm_core_f10 = 0x000327a0; +// Mantissa msb register F11 +const unsigned int cm_core_f11 = 0x000327b0; +// R0 register +const unsigned int cm_core_r0 = 0x00032800; +// R1 register +const unsigned int cm_core_r1 = 0x00032810; +// R2 register +const unsigned int cm_core_r2 = 0x00032820; +// R3 register +const unsigned int cm_core_r3 = 0x00032830; +// R4 register +const unsigned int cm_core_r4 = 0x00032840; +// R5 register +const unsigned int cm_core_r5 = 0x00032850; +// R6 register +const unsigned int cm_core_r6 = 0x00032860; +// R7 register +const unsigned int cm_core_r7 = 0x00032870; +// R8 register +const unsigned int cm_core_r8 = 0x00032880; +// R9 register +const unsigned int cm_core_r9 = 0x00032890; +// R10 register +const unsigned int cm_core_r10 = 0x000328a0; +// R11 register +const unsigned int cm_core_r11 = 0x000328b0; +// R12 register +const unsigned int cm_core_r12 = 0x000328c0; +// R13 register +const unsigned int cm_core_r13 = 0x000328d0; +// R14 register +const unsigned int cm_core_r14 = 0x000328e0; +// R15 register +const unsigned int cm_core_r15 = 0x000328f0; +// R16 register +const unsigned int cm_core_r16 = 0x00032900; +// R17 register +const unsigned int cm_core_r17 = 0x00032910; +// R18 register +const unsigned int cm_core_r18 = 0x00032920; +// R19 register +const unsigned int cm_core_r19 = 0x00032930; +// R20 register +const unsigned int cm_core_r20 = 0x00032940; +// R21 register +const unsigned int cm_core_r21 = 0x00032950; +// R22 register +const unsigned int cm_core_r22 = 0x00032960; +// R23 register +const unsigned int cm_core_r23 = 0x00032970; +// R24 register +const unsigned int cm_core_r24 = 0x00032980; +// R25 register +const unsigned int cm_core_r25 = 0x00032990; +// R26 register +const unsigned int cm_core_r26 = 0x000329a0; +// R27 register +const unsigned int cm_core_r27 = 0x000329b0; +// R28 register +const unsigned int cm_core_r28 = 0x000329c0; +// R29 register +const unsigned int cm_core_r29 = 0x000329d0; +// R30 register +const unsigned int cm_core_r30 = 0x000329e0; +// R31 register +const unsigned int cm_core_r31 = 0x000329f0; +// Modifier register M0 +const unsigned int cm_core_m0 = 0x00032a00; +// Modifier register M1 +const unsigned int cm_core_m1 = 0x00032a10; +// Modifier register M2 +const unsigned int cm_core_m2 = 0x00032a20; +// Modifier register M3 +const unsigned int cm_core_m3 = 0x00032a30; +// Modifier register M4 +const unsigned int cm_core_m4 = 0x00032a40; +// Modifier register M5 +const unsigned int cm_core_m5 = 0x00032a50; +// Modifier register M6 +const unsigned int cm_core_m6 = 0x00032a60; +// Modifier register M7 +const unsigned int cm_core_m7 = 0x00032a70; +// Size register DN0 +const unsigned int cm_core_dn0 = 0x00032a80; +// Size register DN1 +const unsigned int cm_core_dn1 = 0x00032a90; +// Size register DN2 +const unsigned int cm_core_dn2 = 0x00032aa0; +// Size register DN3 +const unsigned int cm_core_dn3 = 0x00032ab0; +// Size register DN4 +const unsigned int cm_core_dn4 = 0x00032ac0; +// Size register DN5 +const unsigned int cm_core_dn5 = 0x00032ad0; +// Size register DN6 +const unsigned int cm_core_dn6 = 0x00032ae0; +// Size register DN7 +const unsigned int cm_core_dn7 = 0x00032af0; +// Step register DJ0 +const unsigned int cm_core_dj0 = 0x00032b00; +// Step register DJ1 +const unsigned int cm_core_dj1 = 0x00032b10; +// Step register DJ2 +const unsigned int cm_core_dj2 = 0x00032b20; +// Step register DJ3 +const unsigned int cm_core_dj3 = 0x00032b30; +// Step register DJ4 +const unsigned int cm_core_dj4 = 0x00032b40; +// Step register DJ5 +const unsigned int cm_core_dj5 = 0x00032b50; +// Step register DJ6 +const unsigned int cm_core_dj6 = 0x00032b60; +// Step register DJ7 +const unsigned int cm_core_dj7 = 0x00032b70; +// Count register DC0 +const unsigned int cm_core_dc0 = 0x00032b80; +// Count register DC1 +const unsigned int cm_core_dc1 = 0x00032b90; +// Count register DC2 +const unsigned int cm_core_dc2 = 0x00032ba0; +// Count register DC3 +const unsigned int cm_core_dc3 = 0x00032bb0; +// Count register DC4 +const unsigned int cm_core_dc4 = 0x00032bc0; +// Count register DC5 +const unsigned int cm_core_dc5 = 0x00032bd0; +// Count register DC6 +const unsigned int cm_core_dc6 = 0x00032be0; +// Count register DC7 +const unsigned int cm_core_dc7 = 0x00032bf0; +// Pointer register P0 +const unsigned int cm_core_p0 = 0x00032c00; +// Pointer register P1 +const unsigned int cm_core_p1 = 0x00032c10; +// Pointer register P2 +const unsigned int cm_core_p2 = 0x00032c20; +// Pointer register P3 +const unsigned int cm_core_p3 = 0x00032c30; +// Pointer register P4 +const unsigned int cm_core_p4 = 0x00032c40; +// Pointer register P5 +const unsigned int cm_core_p5 = 0x00032c50; +// Pointer register P6 +const unsigned int cm_core_p6 = 0x00032c60; +// Pointer register P7 +const unsigned int cm_core_p7 = 0x00032c70; +// Shift register S0 +const unsigned int cm_core_s0 = 0x00032c80; +// Shift register S1 +const unsigned int cm_core_s1 = 0x00032c90; +// Shift register S2 +const unsigned int cm_core_s2 = 0x00032ca0; +// Shift register S3 +const unsigned int cm_core_s3 = 0x00032cb0; +// Program counter register PC +const unsigned int cm_core_pc = 0x00032d00; +const unsigned int cm_program_counter = 0x00032d00; +// PM fetch counter register FC +const unsigned int cm_core_fc = 0x00032d10; +// Stack pointer register SP +const unsigned int cm_core_sp = 0x00032d20; +// Link register LR +const unsigned int cm_core_lr = 0x00032d30; +// Loop start register LS +const unsigned int cm_core_ls = 0x00032d40; +// Loop end register LE +const unsigned int cm_core_le = 0x00032d50; +// Loop count register LC +const unsigned int cm_core_lc = 0x00032d60; +// Loop count register LCI +const unsigned int cm_core_lci = 0x00032d70; +// Control register CR1 +const unsigned int cm_core_cr1 = 0x00032d80; +// Control register CR2 +const unsigned int cm_core_cr2 = 0x00032d90; +// Control register CR3 +const unsigned int cm_core_cr3 = 0x00032da0; +// Status register SR1 +const unsigned int cm_core_sr1 = 0x00032dc0; +// Status register SR2 +const unsigned int cm_core_sr2 = 0x00032dd0; +// Control of Internal Timer +const unsigned int cm_timer_control = 0x00034000; +// Generate an internal event +const unsigned int cm_event_generate = 0x00034008; +// Control of which Internal Event to Broadcast0 +const unsigned int cm_event_broadcast0 = 0x00034010; +// Control of which Internal Event to Broadcast1 +const unsigned int cm_event_broadcast1 = 0x00034014; +// Control of which Internal Event to Broadcast2 +const unsigned int cm_event_broadcast2 = 0x00034018; +// Control of which Internal Event to Broadcast3 +const unsigned int cm_event_broadcast3 = 0x0003401c; +// Control of which Internal Event to Broadcast4 +const unsigned int cm_event_broadcast4 = 0x00034020; +// Control of which Internal Event to Broadcast5 +const unsigned int cm_event_broadcast5 = 0x00034024; +// Control of which Internal Event to Broadcast6 +const unsigned int cm_event_broadcast6 = 0x00034028; +// Control of which Internal Event to Broadcast7 +const unsigned int cm_event_broadcast7 = 0x0003402c; +// Control of which Internal Event to Broadcast8 +const unsigned int cm_event_broadcast8 = 0x00034030; +// Control of which Internal Event to Broadcast9 +const unsigned int cm_event_broadcast9 = 0x00034034; +// Control of which Internal Event to Broadcast10 +const unsigned int cm_event_broadcast10 = 0x00034038; +// Control of which Internal Event to Broadcast11 +const unsigned int cm_event_broadcast11 = 0x0003403c; +// Control of which Internal Event to Broadcast12 +const unsigned int cm_event_broadcast12 = 0x00034040; +// Control of which Internal Event to Broadcast13 +const unsigned int cm_event_broadcast13 = 0x00034044; +// Control of which Internal Event to Broadcast14 +const unsigned int cm_event_broadcast14 = 0x00034048; +// Control of which Internal Event to Broadcast15 +const unsigned int cm_event_broadcast15 = 0x0003404c; +// Set block of broadcast signals to South +const unsigned int cm_event_broadcast_block_south_set = 0x00034050; +// Clear block of broadcast signals to South +const unsigned int cm_event_broadcast_block_south_clr = 0x00034054; +// Current value of block for broadcast signals to South +const unsigned int cm_event_broadcast_block_south_value = 0x00034058; +// Set block of broadcast signals to West +const unsigned int cm_event_broadcast_block_west_set = 0x00034060; +// Clear block of broadcast signals to West +const unsigned int cm_event_broadcast_block_west_clr = 0x00034064; +// Current value of block for broadcast signals to West +const unsigned int cm_event_broadcast_block_west_value = 0x00034068; +// Set block of broadcast signals to North +const unsigned int cm_event_broadcast_block_north_set = 0x00034070; +// Clear block of broadcast signals to North +const unsigned int cm_event_broadcast_block_north_clr = 0x00034074; +// Current value of block for broadcast signals to North +const unsigned int cm_event_broadcast_block_north_value = 0x00034078; +// Set block of broadcast signals to East +const unsigned int cm_event_broadcast_block_east_set = 0x00034080; +// Clear block of broadcast signals to East +const unsigned int cm_event_broadcast_block_east_clr = 0x00034084; +// Current value of block for broadcast signals to East +const unsigned int cm_event_broadcast_block_east_value = 0x00034088; +// Control of Trace +const unsigned int cm_trace_control0 = 0x000340d0; +// Control of Trace: packet destination +const unsigned int cm_trace_control1 = 0x000340d4; +// Status of trace engine +const unsigned int cm_trace_status = 0x000340d8; +// Control of which Internal Event to Trace +const unsigned int cm_trace_event0 = 0x000340e0; +// Control of which Internal Event to Trace +const unsigned int cm_trace_event1 = 0x000340e4; +// Internal Timer Event Value. +const unsigned int cm_timer_trig_event_low_value = 0x000340f0; +// Internal Timer Event Value. +const unsigned int cm_timer_trig_event_high_value = 0x000340f4; +// Internal Timer Low part Value. +const unsigned int cm_timer_low = 0x000340f8; +// Internal Timer High part Value. +const unsigned int cm_timer_high = 0x000340fc; +// Internal event status register0 +const unsigned int cm_event_status0 = 0x00034200; +// Internal event status register1 +const unsigned int cm_event_status1 = 0x00034204; +// Internal event status register2 +const unsigned int cm_event_status2 = 0x00034208; +// Internal event status register3 +const unsigned int cm_event_status3 = 0x0003420c; +// Combo events input events +const unsigned int cm_combo_event_inputs = 0x00034400; +// Combo events input events +const unsigned int cm_combo_event_control = 0x00034404; +// Configuration for edge detection events +const unsigned int cm_edge_detection_event_control = 0x00034408; +// Event enable for Group 0 +const unsigned int cm_event_group_0_enable = 0x00034500; +// Event enable for PC Group +const unsigned int cm_event_group_pc_enable = 0x00034504; +// Event enable for AI Engine Stall Group +const unsigned int cm_event_group_core_stall_enable = 0x00034508; +// Event enable for AI Engine Program Flow Group +const unsigned int cm_event_group_core_program_flow_enable = 0x0003450c; +// Event enable for Non Fatal Error Group +const unsigned int cm_event_group_errors0_enable = 0x00034510; +// Event enable for AI Engine Fatal Error Group +const unsigned int cm_event_group_errors1_enable = 0x00034514; +// Event enable for Stream Switch Group +const unsigned int cm_event_group_stream_switch_enable = 0x00034518; +// Event enable for Broadcast group +const unsigned int cm_event_group_broadcast_enable = 0x0003451c; +// Event enable for User group +const unsigned int cm_event_group_user_event_enable = 0x00034520; +// Control Accumulator Cascade +const unsigned int cm_accumulator_control = 0x00036060; +// Control for memory (privileged) +const unsigned int cm_memory_control = 0x00036070; +// Performance Counters 1-0 Start and Stop Event +const unsigned int cm_performance_control0 = 0x00037500; +// Performance Counters 3-2 Start and Stop Event +const unsigned int cm_performance_control1 = 0x00037504; +// Performance Counters Reset Events +const unsigned int cm_performance_control2 = 0x00037508; +// Performance Counter0 +const unsigned int cm_performance_counter0 = 0x00037520; +// Performance Counter1 +const unsigned int cm_performance_counter1 = 0x00037524; +// Performance Counter2 +const unsigned int cm_performance_counter2 = 0x00037528; +// Performance Counter3 +const unsigned int cm_performance_counter3 = 0x0003752c; +// Performance Counter0 Event Value. +const unsigned int cm_performance_counter0_event_value = 0x00037580; +// Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated +const unsigned int cm_performance_counter1_event_value = 0x00037584; +// Performance Counter2 Event Value. When the Performance Counter2 reach this value, an event will be generated +const unsigned int cm_performance_counter2_event_value = 0x00037588; +// Performance Counter3 Event Value. When the Performance Counter3 reach this value, an event will be generated +const unsigned int cm_performance_counter3_event_value = 0x0003758c; +// Control of the AI Engine +const unsigned int cm_core_control = 0x00038000; +// The status of the AI Engine +const unsigned int cm_core_status = 0x00038004; +// Set reset event trigger +const unsigned int cm_enable_events = 0x00038008; +// Set reset event trigger +const unsigned int cm_reset_event = 0x0003800c; +// Debug control of manual debug stall and single step count +const unsigned int cm_debug_control0 = 0x00038010; +// Debug Halt Event Control +const unsigned int cm_debug_control1 = 0x00038014; +// Debug Halt Control +const unsigned int cm_debug_control2 = 0x00038018; +// Debug Status +const unsigned int cm_debug_status = 0x0003801c; +// PC_Event0 +const unsigned int cm_pc_event0 = 0x00038020; +// PC_Event1 +const unsigned int cm_pc_event1 = 0x00038024; +// PC_Event2 +const unsigned int cm_pc_event2 = 0x00038028; +// PC_Event3 +const unsigned int cm_pc_event3 = 0x0003802c; +// Error Halt Control +const unsigned int cm_error_halt_control = 0x00038030; +// Error Halt Event +const unsigned int cm_error_halt_event = 0x00038034; +// Core Processor Bus Control +const unsigned int cm_core_processor_bus = 0x00038038; +// ECC scrubbing event +const unsigned int cm_ecc_scrubbing_event = 0x00038110; +// Stream Switch Master Configuration AI Engine 0 +const unsigned int cm_stream_switch_master_config_aie_core0 = 0x0003f000; +// Stream Switch Master Configuration DMA 0 +const unsigned int cm_stream_switch_master_config_dma0 = 0x0003f004; +// Stream Switch Master Configuration DMA 1 +const unsigned int cm_stream_switch_master_config_dma1 = 0x0003f008; +// Stream Switch Master Configuration AI Engine Tile Ctrl +const unsigned int cm_stream_switch_master_config_tile_ctrl = 0x0003f00c; +// Stream Switch Master Configuration FIFO 0 +const unsigned int cm_stream_switch_master_config_fifo0 = 0x0003f010; +// Stream Switch Master Configuration South 0 +const unsigned int cm_stream_switch_master_config_south0 = 0x0003f014; +// Stream Switch Master Configuration South 1 +const unsigned int cm_stream_switch_master_config_south1 = 0x0003f018; +// Stream Switch Master Configuration South 2 +const unsigned int cm_stream_switch_master_config_south2 = 0x0003f01c; +// Stream Switch Master Configuration South 3 +const unsigned int cm_stream_switch_master_config_south3 = 0x0003f020; +// Stream Switch Master Configuration West 0 +const unsigned int cm_stream_switch_master_config_west0 = 0x0003f024; +// Stream Switch Master Configuration West 1 +const unsigned int cm_stream_switch_master_config_west1 = 0x0003f028; +// Stream Switch Master Configuration West 2 +const unsigned int cm_stream_switch_master_config_west2 = 0x0003f02c; +// Stream Switch Master Configuration West 3 +const unsigned int cm_stream_switch_master_config_west3 = 0x0003f030; +// Stream Switch Master Configuration North 0 +const unsigned int cm_stream_switch_master_config_north0 = 0x0003f034; +// Stream Switch Master Configuration North 1 +const unsigned int cm_stream_switch_master_config_north1 = 0x0003f038; +// Stream Switch Master Configuration North 2 +const unsigned int cm_stream_switch_master_config_north2 = 0x0003f03c; +// Stream Switch Master Configuration North 3 +const unsigned int cm_stream_switch_master_config_north3 = 0x0003f040; +// Stream Switch Master Configuration North 4 +const unsigned int cm_stream_switch_master_config_north4 = 0x0003f044; +// Stream Switch Master Configuration North 5 +const unsigned int cm_stream_switch_master_config_north5 = 0x0003f048; +// Stream Switch Master Configuration East 0 +const unsigned int cm_stream_switch_master_config_east0 = 0x0003f04c; +// Stream Switch Master Configuration East 1 +const unsigned int cm_stream_switch_master_config_east1 = 0x0003f050; +// Stream Switch Master Configuration East 2 +const unsigned int cm_stream_switch_master_config_east2 = 0x0003f054; +// Stream Switch Master Configuration East 3 +const unsigned int cm_stream_switch_master_config_east3 = 0x0003f058; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_config_aie_core0 = 0x0003f100; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_config_dma_0 = 0x0003f104; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_config_dma_1 = 0x0003f108; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_config_tile_ctrl = 0x0003f10c; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_config_fifo_0 = 0x0003f110; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_config_south_0 = 0x0003f114; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_config_south_1 = 0x0003f118; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_config_south_2 = 0x0003f11c; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_config_south_3 = 0x0003f120; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_config_south_4 = 0x0003f124; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_config_south_5 = 0x0003f128; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_config_west_0 = 0x0003f12c; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_config_west_1 = 0x0003f130; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_config_west_2 = 0x0003f134; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_config_west_3 = 0x0003f138; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_config_north_0 = 0x0003f13c; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_config_north_1 = 0x0003f140; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_config_north_2 = 0x0003f144; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_config_north_3 = 0x0003f148; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_config_east_0 = 0x0003f14c; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_config_east_1 = 0x0003f150; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_config_east_2 = 0x0003f154; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_config_east_3 = 0x0003f158; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_config_aie_trace = 0x0003f15c; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_config_mem_trace = 0x0003f160; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot0 = 0x0003f200; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot1 = 0x0003f204; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot2 = 0x0003f208; +// Stream Switch Slave Configuration AI Engine 0 +const unsigned int cm_stream_switch_slave_aie_core0_slot3 = 0x0003f20c; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot0 = 0x0003f210; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot1 = 0x0003f214; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot2 = 0x0003f218; +// Stream Switch Slave Configuration DMA 0 +const unsigned int cm_stream_switch_slave_dma_0_slot3 = 0x0003f21c; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot0 = 0x0003f220; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot1 = 0x0003f224; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot2 = 0x0003f228; +// Stream Switch Slave Configuration DMA 1 +const unsigned int cm_stream_switch_slave_dma_1_slot3 = 0x0003f22c; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot0 = 0x0003f230; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot1 = 0x0003f234; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot2 = 0x0003f238; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int cm_stream_switch_slave_tile_ctrl_slot3 = 0x0003f23c; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot0 = 0x0003f240; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot1 = 0x0003f244; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot2 = 0x0003f248; +// Stream Switch Slave Configuration FIFO 0 +const unsigned int cm_stream_switch_slave_fifo_0_slot3 = 0x0003f24c; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot0 = 0x0003f250; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot1 = 0x0003f254; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot2 = 0x0003f258; +// Stream Switch Slave Configuration South 0 +const unsigned int cm_stream_switch_slave_south_0_slot3 = 0x0003f25c; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot0 = 0x0003f260; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot1 = 0x0003f264; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot2 = 0x0003f268; +// Stream Switch Slave Configuration South 1 +const unsigned int cm_stream_switch_slave_south_1_slot3 = 0x0003f26c; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot0 = 0x0003f270; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot1 = 0x0003f274; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot2 = 0x0003f278; +// Stream Switch Slave Configuration South 2 +const unsigned int cm_stream_switch_slave_south_2_slot3 = 0x0003f27c; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot0 = 0x0003f280; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot1 = 0x0003f284; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot2 = 0x0003f288; +// Stream Switch Slave Configuration South 3 +const unsigned int cm_stream_switch_slave_south_3_slot3 = 0x0003f28c; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot0 = 0x0003f290; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot1 = 0x0003f294; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot2 = 0x0003f298; +// Stream Switch Slave Configuration South 4 +const unsigned int cm_stream_switch_slave_south_4_slot3 = 0x0003f29c; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot0 = 0x0003f2a0; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot1 = 0x0003f2a4; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot2 = 0x0003f2a8; +// Stream Switch Slave Configuration South 5 +const unsigned int cm_stream_switch_slave_south_5_slot3 = 0x0003f2ac; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot0 = 0x0003f2b0; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot1 = 0x0003f2b4; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot2 = 0x0003f2b8; +// Stream Switch Slave Configuration West 0 +const unsigned int cm_stream_switch_slave_west_0_slot3 = 0x0003f2bc; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot0 = 0x0003f2c0; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot1 = 0x0003f2c4; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot2 = 0x0003f2c8; +// Stream Switch Slave Configuration West 1 +const unsigned int cm_stream_switch_slave_west_1_slot3 = 0x0003f2cc; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot0 = 0x0003f2d0; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot1 = 0x0003f2d4; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot2 = 0x0003f2d8; +// Stream Switch Slave Configuration West 2 +const unsigned int cm_stream_switch_slave_west_2_slot3 = 0x0003f2dc; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot0 = 0x0003f2e0; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot1 = 0x0003f2e4; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot2 = 0x0003f2e8; +// Stream Switch Slave Configuration West 3 +const unsigned int cm_stream_switch_slave_west_3_slot3 = 0x0003f2ec; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot0 = 0x0003f2f0; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot1 = 0x0003f2f4; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot2 = 0x0003f2f8; +// Stream Switch Slave Configuration North 0 +const unsigned int cm_stream_switch_slave_north_0_slot3 = 0x0003f2fc; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot0 = 0x0003f300; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot1 = 0x0003f304; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot2 = 0x0003f308; +// Stream Switch Slave Configuration North 1 +const unsigned int cm_stream_switch_slave_north_1_slot3 = 0x0003f30c; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot0 = 0x0003f310; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot1 = 0x0003f314; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot2 = 0x0003f318; +// Stream Switch Slave Configuration North 2 +const unsigned int cm_stream_switch_slave_north_2_slot3 = 0x0003f31c; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot0 = 0x0003f320; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot1 = 0x0003f324; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot2 = 0x0003f328; +// Stream Switch Slave Configuration North 3 +const unsigned int cm_stream_switch_slave_north_3_slot3 = 0x0003f32c; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot0 = 0x0003f330; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot1 = 0x0003f334; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot2 = 0x0003f338; +// Stream Switch Slave Configuration East 0 +const unsigned int cm_stream_switch_slave_east_0_slot3 = 0x0003f33c; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot0 = 0x0003f340; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot1 = 0x0003f344; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot2 = 0x0003f348; +// Stream Switch Slave Configuration East 1 +const unsigned int cm_stream_switch_slave_east_1_slot3 = 0x0003f34c; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot0 = 0x0003f350; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot1 = 0x0003f354; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot2 = 0x0003f358; +// Stream Switch Slave Configuration East 2 +const unsigned int cm_stream_switch_slave_east_2_slot3 = 0x0003f35c; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot0 = 0x0003f360; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot1 = 0x0003f364; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot2 = 0x0003f368; +// Stream Switch Slave Configuration East 3 +const unsigned int cm_stream_switch_slave_east_3_slot3 = 0x0003f36c; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot0 = 0x0003f370; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot1 = 0x0003f374; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot2 = 0x0003f378; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int cm_stream_switch_slave_aie_trace_slot3 = 0x0003f37c; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot0 = 0x0003f380; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot1 = 0x0003f384; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot2 = 0x0003f388; +// Stream Switch Slave Configuration Mem Trace +const unsigned int cm_stream_switch_slave_mem_trace_slot3 = 0x0003f38c; +// Stream Switch Deterministic Merge Arbiter:0 Slave:0,1 +const unsigned int cm_stream_switch_deterministic_merge_arb0_slave0_1 = 0x0003f800; +// Stream Switch Deterministic Merge Arbiter:0 Slave:2,3 +const unsigned int cm_stream_switch_deterministic_merge_arb0_slave2_3 = 0x0003f804; +// Stream Switch Deterministic Merge Arbiter:0 Control +const unsigned int cm_stream_switch_deterministic_merge_arb0_ctrl = 0x0003f808; +// Stream Switch Deterministic Merge Arbiter:1 Slave:0,1 +const unsigned int cm_stream_switch_deterministic_merge_arb1_slave0_1 = 0x0003f810; +// Stream Switch Deterministic Merge Arbiter:1 Slave:2,3 +const unsigned int cm_stream_switch_deterministic_merge_arb1_slave2_3 = 0x0003f814; +// Stream Switch Deterministic Merge Arbiter:1 Control +const unsigned int cm_stream_switch_deterministic_merge_arb1_ctrl = 0x0003f818; +// Select Stream Switch Ports for event generation +const unsigned int cm_stream_switch_event_port_selection_0 = 0x0003ff00; +// Select Stream Switch Ports for event generation +const unsigned int cm_stream_switch_event_port_selection_1 = 0x0003ff04; +// Status bits for Parity errors on stream switch ports (error on lower OR upper 32-bit word) +const unsigned int cm_stream_switch_parity_status = 0x0003ff10; +// Injection of Parity errors on stream switch ports (privileged) +const unsigned int cm_stream_switch_parity_injection = 0x0003ff20; +// Status of control packet handling +const unsigned int cm_tile_control_packet_handler_status = 0x0003ff30; +// Defeaured this generation. Status of Stream Switch Adaptive Clock Gate Status +const unsigned int cm_stream_switch_adaptive_clock_gate_status = 0x0003ff34; +// Defeaured this generation. Set Stream Switch Adaptive Clock Gate Abort Period +const unsigned int cm_stream_switch_adaptive_clock_gate_abort_period = 0x0003ff38; +// Control clock gating of modules (privileged) +const unsigned int cm_module_clock_control = 0x00060000; +// Tile control register (Isolation) +const unsigned int cm_tile_control = 0x00060020; + +// Register definitions for memory module +// ###################################### +// Performance Counters 1-0 Start and Stop Event +const unsigned int mm_performance_control0 = 0x00011000; +// Performance Counters 1-0 Reset Event +const unsigned int mm_performance_control1 = 0x00011008; +// Performance Counters 3-2 Start and Stop Event +const unsigned int mm_performance_control2 = 0x0001100c; +// Performance Counters 3-2 Reset Events +const unsigned int mm_performance_control3 = 0x00011010; +// Performance Counter0 +const unsigned int mm_performance_counter0 = 0x00011020; +// Performance Counter1 +const unsigned int mm_performance_counter1 = 0x00011024; +// Performance Counter2 +const unsigned int mm_performance_counter2 = 0x00011028; +// Performance Counter3 +const unsigned int mm_performance_counter3 = 0x0001102c; +// Performance Counter0 Event Value. +const unsigned int mm_performance_counter0_event_value = 0x00011080; +// Performance Counter1 Event Value. +const unsigned int mm_performance_counter1_event_value = 0x00011084; +// Control of Internal Timer +const unsigned int mm_timer_control = 0x00014000; +// Generate an internal event +const unsigned int mm_event_generate = 0x00014008; +// Control of which Internal Event to Broadcast0 +const unsigned int mm_event_broadcast0 = 0x00014010; +// Control of which Internal Event to Broadcast1 +const unsigned int mm_event_broadcast1 = 0x00014014; +// Control of which Internal Event to Broadcast2 +const unsigned int mm_event_broadcast2 = 0x00014018; +// Control of which Internal Event to Broadcast3 +const unsigned int mm_event_broadcast3 = 0x0001401c; +// Control of which Internal Event to Broadcast4 +const unsigned int mm_event_broadcast4 = 0x00014020; +// Control of which Internal Event to Broadcast5 +const unsigned int mm_event_broadcast5 = 0x00014024; +// Control of which Internal Event to Broadcast6 +const unsigned int mm_event_broadcast6 = 0x00014028; +// Control of which Internal Event to Broadcast7 +const unsigned int mm_event_broadcast7 = 0x0001402c; +// Control of which Internal Event to Broadcast8 +const unsigned int mm_event_broadcast8 = 0x00014030; +// Control of which Internal Event to Broadcast9 +const unsigned int mm_event_broadcast9 = 0x00014034; +// Control of which Internal Event to Broadcast10 +const unsigned int mm_event_broadcast10 = 0x00014038; +// Control of which Internal Event to Broadcast11 +const unsigned int mm_event_broadcast11 = 0x0001403c; +// Control of which Internal Event to Broadcast12 +const unsigned int mm_event_broadcast12 = 0x00014040; +// Control of which Internal Event to Broadcast13 +const unsigned int mm_event_broadcast13 = 0x00014044; +// Control of which Internal Event to Broadcast14 +const unsigned int mm_event_broadcast14 = 0x00014048; +// Control of which Internal Event to Broadcast15 +const unsigned int mm_event_broadcast15 = 0x0001404c; +// Set block of broadcast signals to South +const unsigned int mm_event_broadcast_block_south_set = 0x00014050; +// Clear block of broadcast signals to South +const unsigned int mm_event_broadcast_block_south_clr = 0x00014054; +// Current value of block for broadcast signals to South +const unsigned int mm_event_broadcast_block_south_value = 0x00014058; +// Set block of broadcast signals to West +const unsigned int mm_event_broadcast_block_west_set = 0x00014060; +// Clear block of broadcast signals to West +const unsigned int mm_event_broadcast_block_west_clr = 0x00014064; +// Current value of block for broadcast signals to West +const unsigned int mm_event_broadcast_block_west_value = 0x00014068; +// Set block of broadcast signals to North +const unsigned int mm_event_broadcast_block_north_set = 0x00014070; +// Clear block of broadcast signals to North +const unsigned int mm_event_broadcast_block_north_clr = 0x00014074; +// Current value of block for broadcast signals to North +const unsigned int mm_event_broadcast_block_north_value = 0x00014078; +// Set block of broadcast signals to East +const unsigned int mm_event_broadcast_block_east_set = 0x00014080; +// Clear block of broadcast signals to East +const unsigned int mm_event_broadcast_block_east_clr = 0x00014084; +// Current value of block for broadcast signals to East +const unsigned int mm_event_broadcast_block_east_value = 0x00014088; +// Control of Trace +const unsigned int mm_trace_control0 = 0x000140d0; +// Control of Trace: packet configuration +const unsigned int mm_trace_control1 = 0x000140d4; +// Status of trace engine +const unsigned int mm_trace_status = 0x000140d8; +// Control of which Internal Event to Trace +const unsigned int mm_trace_event0 = 0x000140e0; +// Control of which Internal Event to Trace +const unsigned int mm_trace_event1 = 0x000140e4; +// Internal Timer Event Value. +const unsigned int mm_timer_trig_event_low_value = 0x000140f0; +// Internal Timer Event Value. +const unsigned int mm_timer_trig_event_high_value = 0x000140f4; +// Internal Timer Low part Value. +const unsigned int mm_timer_low = 0x000140f8; +// Internal Timer High part Value. +const unsigned int mm_timer_high = 0x000140fc; +// Define Watchpoint0 +const unsigned int mm_watchpoint0 = 0x00014100; +// Define Watchpoint1 +const unsigned int mm_watchpoint1 = 0x00014104; +// Internal event status register0 +const unsigned int mm_event_status0 = 0x00014200; +// Internal event status register1 +const unsigned int mm_event_status1 = 0x00014204; +// Internal event status register2 +const unsigned int mm_event_status2 = 0x00014208; +// Internal event status register3 +const unsigned int mm_event_status3 = 0x0001420c; +// Combo events input events +const unsigned int mm_combo_event_inputs = 0x00014400; +// Combo events input events +const unsigned int mm_combo_event_control = 0x00014404; +// Configuration for edge detection events +const unsigned int mm_edge_detection_event_control = 0x00014408; +// Event enable for Group 0 +const unsigned int mm_event_group_0_enable = 0x00014500; +// Event enable for Watchpoint Group +const unsigned int mm_event_group_watchpoint_enable = 0x00014504; +// Event enable for DMA Group +const unsigned int mm_event_group_dma_enable = 0x00014508; +// Event enable for Lock Group +const unsigned int mm_event_group_lock_enable = 0x0001450c; +// Event enable for Memory Conflict Group +const unsigned int mm_event_group_memory_conflict_enable = 0x00014510; +// Event enable for Error Group +const unsigned int mm_event_group_error_enable = 0x00014514; +// Event enable for Broadcast Group +const unsigned int mm_event_group_broadcast_enable = 0x00014518; +// Event enable for User Group +const unsigned int mm_event_group_user_event_enable = 0x0001451c; +// Control for memory (privileged) +const unsigned int mm_memory_control = 0x00016010; +// DMA BD0 0 +const unsigned int mm_dma_bd0_0 = 0x0001d000; +// DMA BD0 1 +const unsigned int mm_dma_bd0_1 = 0x0001d004; +// DMA BD0 2 +const unsigned int mm_dma_bd0_2 = 0x0001d008; +// DMA BD0 3 +const unsigned int mm_dma_bd0_3 = 0x0001d00c; +// DMA BD0 4 +const unsigned int mm_dma_bd0_4 = 0x0001d010; +// DMA BD0 5 +const unsigned int mm_dma_bd0_5 = 0x0001d014; +// DMA BD1 0 +const unsigned int mm_dma_bd1_0 = 0x0001d020; +// DMA BD1 1 +const unsigned int mm_dma_bd1_1 = 0x0001d024; +// DMA BD1 2 +const unsigned int mm_dma_bd1_2 = 0x0001d028; +// DMA BD1 3 +const unsigned int mm_dma_bd1_3 = 0x0001d02c; +// DMA BD1 4 +const unsigned int mm_dma_bd1_4 = 0x0001d030; +// DMA BD1 5 +const unsigned int mm_dma_bd1_5 = 0x0001d034; +// DMA BD2 0 +const unsigned int mm_dma_bd2_0 = 0x0001d040; +// DMA BD2 1 +const unsigned int mm_dma_bd2_1 = 0x0001d044; +// DMA BD2 2 +const unsigned int mm_dma_bd2_2 = 0x0001d048; +// DMA BD2 3 +const unsigned int mm_dma_bd2_3 = 0x0001d04c; +// DMA BD2 4 +const unsigned int mm_dma_bd2_4 = 0x0001d050; +// DMA BD2 5 +const unsigned int mm_dma_bd2_5 = 0x0001d054; +// DMA BD3 0 +const unsigned int mm_dma_bd3_0 = 0x0001d060; +// DMA BD3 1 +const unsigned int mm_dma_bd3_1 = 0x0001d064; +// DMA BD3 2 +const unsigned int mm_dma_bd3_2 = 0x0001d068; +// DMA BD3 3 +const unsigned int mm_dma_bd3_3 = 0x0001d06c; +// DMA BD3 4 +const unsigned int mm_dma_bd3_4 = 0x0001d070; +// DMA BD3 5 +const unsigned int mm_dma_bd3_5 = 0x0001d074; +// DMA BD4 0 +const unsigned int mm_dma_bd4_0 = 0x0001d080; +// DMA BD4 1 +const unsigned int mm_dma_bd4_1 = 0x0001d084; +// DMA BD4 2 +const unsigned int mm_dma_bd4_2 = 0x0001d088; +// DMA BD4 3 +const unsigned int mm_dma_bd4_3 = 0x0001d08c; +// DMA BD4 4 +const unsigned int mm_dma_bd4_4 = 0x0001d090; +// DMA BD4 5 +const unsigned int mm_dma_bd4_5 = 0x0001d094; +// DMA BD5 0 +const unsigned int mm_dma_bd5_0 = 0x0001d0a0; +// DMA BD5 1 +const unsigned int mm_dma_bd5_1 = 0x0001d0a4; +// DMA BD5 2 +const unsigned int mm_dma_bd5_2 = 0x0001d0a8; +// DMA BD5 3 +const unsigned int mm_dma_bd5_3 = 0x0001d0ac; +// DMA BD5 4 +const unsigned int mm_dma_bd5_4 = 0x0001d0b0; +// DMA BD5 5 +const unsigned int mm_dma_bd5_5 = 0x0001d0b4; +// DMA BD6 0 +const unsigned int mm_dma_bd6_0 = 0x0001d0c0; +// DMA BD6 1 +const unsigned int mm_dma_bd6_1 = 0x0001d0c4; +// DMA BD6 2 +const unsigned int mm_dma_bd6_2 = 0x0001d0c8; +// DMA BD6 3 +const unsigned int mm_dma_bd6_3 = 0x0001d0cc; +// DMA BD6 4 +const unsigned int mm_dma_bd6_4 = 0x0001d0d0; +// DMA BD6 5 +const unsigned int mm_dma_bd6_5 = 0x0001d0d4; +// DMA BD7 0 +const unsigned int mm_dma_bd7_0 = 0x0001d0e0; +// DMA BD7 1 +const unsigned int mm_dma_bd7_1 = 0x0001d0e4; +// DMA BD7 2 +const unsigned int mm_dma_bd7_2 = 0x0001d0e8; +// DMA BD7 3 +const unsigned int mm_dma_bd7_3 = 0x0001d0ec; +// DMA BD7 4 +const unsigned int mm_dma_bd7_4 = 0x0001d0f0; +// DMA BD7 5 +const unsigned int mm_dma_bd7_5 = 0x0001d0f4; +// DMA BD8 0 +const unsigned int mm_dma_bd8_0 = 0x0001d100; +// DMA BD8 1 +const unsigned int mm_dma_bd8_1 = 0x0001d104; +// DMA BD8 2 +const unsigned int mm_dma_bd8_2 = 0x0001d108; +// DMA BD8 3 +const unsigned int mm_dma_bd8_3 = 0x0001d10c; +// DMA BD8 4 +const unsigned int mm_dma_bd8_4 = 0x0001d110; +// DMA BD8 5 +const unsigned int mm_dma_bd8_5 = 0x0001d114; +// DMA BD9 0 +const unsigned int mm_dma_bd9_0 = 0x0001d120; +// DMA BD9 1 +const unsigned int mm_dma_bd9_1 = 0x0001d124; +// DMA BD9 2 +const unsigned int mm_dma_bd9_2 = 0x0001d128; +// DMA BD9 3 +const unsigned int mm_dma_bd9_3 = 0x0001d12c; +// DMA BD9 4 +const unsigned int mm_dma_bd9_4 = 0x0001d130; +// DMA BD9 5 +const unsigned int mm_dma_bd9_5 = 0x0001d134; +// DMA BD10 0 +const unsigned int mm_dma_bd10_0 = 0x0001d140; +// DMA BD10 1 +const unsigned int mm_dma_bd10_1 = 0x0001d144; +// DMA BD10 2 +const unsigned int mm_dma_bd10_2 = 0x0001d148; +// DMA BD10 3 +const unsigned int mm_dma_bd10_3 = 0x0001d14c; +// DMA BD10 4 +const unsigned int mm_dma_bd10_4 = 0x0001d150; +// DMA BD10 5 +const unsigned int mm_dma_bd10_5 = 0x0001d154; +// DMA BD11 0 +const unsigned int mm_dma_bd11_0 = 0x0001d160; +// DMA BD11 1 +const unsigned int mm_dma_bd11_1 = 0x0001d164; +// DMA BD11 2 +const unsigned int mm_dma_bd11_2 = 0x0001d168; +// DMA BD11 3 +const unsigned int mm_dma_bd11_3 = 0x0001d16c; +// DMA BD11 4 +const unsigned int mm_dma_bd11_4 = 0x0001d170; +// DMA BD11 5 +const unsigned int mm_dma_bd11_5 = 0x0001d174; +// DMA BD12 0 +const unsigned int mm_dma_bd12_0 = 0x0001d180; +// DMA BD12 1 +const unsigned int mm_dma_bd12_1 = 0x0001d184; +// DMA BD12 2 +const unsigned int mm_dma_bd12_2 = 0x0001d188; +// DMA BD12 3 +const unsigned int mm_dma_bd12_3 = 0x0001d18c; +// DMA BD12 4 +const unsigned int mm_dma_bd12_4 = 0x0001d190; +// DMA BD12 5 +const unsigned int mm_dma_bd12_5 = 0x0001d194; +// DMA BD13 0 +const unsigned int mm_dma_bd13_0 = 0x0001d1a0; +// DMA BD13 1 +const unsigned int mm_dma_bd13_1 = 0x0001d1a4; +// DMA BD13 2 +const unsigned int mm_dma_bd13_2 = 0x0001d1a8; +// DMA BD13 3 +const unsigned int mm_dma_bd13_3 = 0x0001d1ac; +// DMA BD13 4 +const unsigned int mm_dma_bd13_4 = 0x0001d1b0; +// DMA BD13 5 +const unsigned int mm_dma_bd13_5 = 0x0001d1b4; +// DMA BD14 0 +const unsigned int mm_dma_bd14_0 = 0x0001d1c0; +// DMA BD14 1 +const unsigned int mm_dma_bd14_1 = 0x0001d1c4; +// DMA BD14 2 +const unsigned int mm_dma_bd14_2 = 0x0001d1c8; +// DMA BD14 3 +const unsigned int mm_dma_bd14_3 = 0x0001d1cc; +// DMA BD14 4 +const unsigned int mm_dma_bd14_4 = 0x0001d1d0; +// DMA BD14 5 +const unsigned int mm_dma_bd14_5 = 0x0001d1d4; +// DMA BD15 0 +const unsigned int mm_dma_bd15_0 = 0x0001d1e0; +// DMA BD15 1 +const unsigned int mm_dma_bd15_1 = 0x0001d1e4; +// DMA BD15 2 +const unsigned int mm_dma_bd15_2 = 0x0001d1e8; +// DMA BD15 3 +const unsigned int mm_dma_bd15_3 = 0x0001d1ec; +// DMA BD15 4 +const unsigned int mm_dma_bd15_4 = 0x0001d1f0; +// DMA BD15 5 +const unsigned int mm_dma_bd15_5 = 0x0001d1f4; +// DMA Control Register S2MM Ch0 +const unsigned int mm_dma_s2mm_0_ctrl = 0x0001de00; +// DMA Control Register S2MM Ch0 +const unsigned int mm_dma_s2mm_0_start_queue = 0x0001de04; +// DMA Control Register S2MM Ch1 +const unsigned int mm_dma_s2mm_1_ctrl = 0x0001de08; +// DMA Control Register S2MM Ch1 +const unsigned int mm_dma_s2mm_1_start_queue = 0x0001de0c; +// DMA Control Register MM2S Ch0 +const unsigned int mm_dma_mm2s_0_ctrl = 0x0001de10; +// DMA Control Register MM2S Ch0 +const unsigned int mm_dma_mm2s_0_start_queue = 0x0001de14; +// DMA Control Register MM2S Ch1 +const unsigned int mm_dma_mm2s_1_ctrl = 0x0001de18; +// DMA Control Register MM2S Ch1 +const unsigned int mm_dma_mm2s_1_start_queue = 0x0001de1c; +// DMA S2MM Status Register Ch0 +const unsigned int mm_dma_s2mm_status_0 = 0x0001df00; +// DMA S2MM Status Register Ch1 +const unsigned int mm_dma_s2mm_status_1 = 0x0001df04; +// DMA MM2S Status Register Ch0 +const unsigned int mm_dma_mm2s_status_0 = 0x0001df10; +// DMA MM2S Status Register Ch1 +const unsigned int mm_dma_mm2s_status_1 = 0x0001df14; +// DMA S2MM Current Write Count Ch0 +const unsigned int mm_dma_s2mm_current_write_count_0 = 0x0001df18; +// DMA S2MM Current Write Count Ch1 +const unsigned int mm_dma_s2mm_current_write_count_1 = 0x0001df1c; +// DMA S2MM FoT Count FIFO Pop Ch0 +const unsigned int mm_dma_s2mm_fot_count_fifo_pop_0 = 0x0001df20; +// DMA S2MM FoT Count FIFO Pop Ch1 +const unsigned int mm_dma_s2mm_fot_count_fifo_pop_1 = 0x0001df24; +// Value of lock 0 +const unsigned int mm_lock0_value = 0x0001f000; +// Value of lock 1 +const unsigned int mm_lock1_value = 0x0001f010; +// Value of lock 2 +const unsigned int mm_lock2_value = 0x0001f020; +// Value of lock 3 +const unsigned int mm_lock3_value = 0x0001f030; +// Value of lock 4 +const unsigned int mm_lock4_value = 0x0001f040; +// Value of lock 5 +const unsigned int mm_lock5_value = 0x0001f050; +// Value of lock 6 +const unsigned int mm_lock6_value = 0x0001f060; +// Value of lock 7 +const unsigned int mm_lock7_value = 0x0001f070; +// Value of lock 8 +const unsigned int mm_lock8_value = 0x0001f080; +// Value of lock 9 +const unsigned int mm_lock9_value = 0x0001f090; +// Value of lock 10 +const unsigned int mm_lock10_value = 0x0001f0a0; +// Value of lock 11 +const unsigned int mm_lock11_value = 0x0001f0b0; +// Value of lock 12 +const unsigned int mm_lock12_value = 0x0001f0c0; +// Value of lock 13 +const unsigned int mm_lock13_value = 0x0001f0d0; +// Value of lock 14 +const unsigned int mm_lock14_value = 0x0001f0e0; +// Value of lock 15 +const unsigned int mm_lock15_value = 0x0001f0f0; +// Select lock for lock event generation 0 +const unsigned int mm_locks_event_selection_0 = 0x0001f100; +// Select lock for lock event generation 1 +const unsigned int mm_locks_event_selection_1 = 0x0001f104; +// Select lock for lock event generation 2 +const unsigned int mm_locks_event_selection_2 = 0x0001f108; +// Select lock for lock event generation 3 +const unsigned int mm_locks_event_selection_3 = 0x0001f10c; +// Select lock for lock event generation 4 +const unsigned int mm_locks_event_selection_4 = 0x0001f110; +// Select lock for lock event generation 5 +const unsigned int mm_locks_event_selection_5 = 0x0001f114; +// Select lock for lock event generation 6 +const unsigned int mm_locks_event_selection_6 = 0x0001f118; +// Select lock for lock event generation 7 +const unsigned int mm_locks_event_selection_7 = 0x0001f11c; +// Status bits for lock overflow, write to clear +const unsigned int mm_locks_overflow = 0x0001f120; +// Status bits for lock underflow, write to clear +const unsigned int mm_locks_underflow = 0x0001f128; +// Lock Request. 16kB address space: 0x40000 - 0x43FFC, Lock_Id [13:10], Acq_Rel (9), Change_Value [8:2] +const unsigned int mm_lock_request = 0x00040000; + +// Register definitions for memory tile +// #################################### +// Performance Counters 1-0 Start and Stop Event +const unsigned int mem_performance_control0 = 0x00091000; +// Performance Counters 3-2 Start and Stop Event +const unsigned int mem_performance_control1 = 0x00091004; +// Performance Counters 3-0 Reset Event +const unsigned int mem_performance_control2 = 0x00091008; +// Performance Counters 5-4 Start and Stop Event +const unsigned int mem_performance_control3 = 0x0009100c; +// Performance Counters 5-4 Reset Event +const unsigned int mem_performance_control4 = 0x00091010; +// Performance Counter0 +const unsigned int mem_performance_counter0 = 0x00091020; +// Performance Counter1 +const unsigned int mem_performance_counter1 = 0x00091024; +// Performance Counter2 +const unsigned int mem_performance_counter2 = 0x00091028; +// Performance Counter3 +const unsigned int mem_performance_counter3 = 0x0009102c; +// Performance Counter4 +const unsigned int mem_performance_counter4 = 0x00091030; +// Performance Counter5 +const unsigned int mem_performance_counter5 = 0x00091034; +// Performance Counter0 Event Value. +const unsigned int mem_performance_counter0_event_value = 0x00091080; +// Performance Counter1 Event Value. +const unsigned int mem_performance_counter1_event_value = 0x00091084; +// Performance Counter2 Event Value. +const unsigned int mem_performance_counter2_event_value = 0x00091088; +// Performance Counter3 Event Value. +const unsigned int mem_performance_counter3_event_value = 0x0009108c; +// Control of Internal Timer +const unsigned int mem_timer_control = 0x00094000; +// Generate an internal event +const unsigned int mem_event_generate = 0x00094008; +// Control of which Internal Event to Broadcast0 +const unsigned int mem_event_broadcast0 = 0x00094010; +// Control of which Internal Event to Broadcast1 +const unsigned int mem_event_broadcast1 = 0x00094014; +// Control of which Internal Event to Broadcast2 +const unsigned int mem_event_broadcast2 = 0x00094018; +// Control of which Internal Event to Broadcast3 +const unsigned int mem_event_broadcast3 = 0x0009401c; +// Control of which Internal Event to Broadcast4 +const unsigned int mem_event_broadcast4 = 0x00094020; +// Control of which Internal Event to Broadcast5 +const unsigned int mem_event_broadcast5 = 0x00094024; +// Control of which Internal Event to Broadcast6 +const unsigned int mem_event_broadcast6 = 0x00094028; +// Control of which Internal Event to Broadcast7 +const unsigned int mem_event_broadcast7 = 0x0009402c; +// Control of which Internal Event to Broadcast8 +const unsigned int mem_event_broadcast8 = 0x00094030; +// Control of which Internal Event to Broadcast9 +const unsigned int mem_event_broadcast9 = 0x00094034; +// Control of which Internal Event to Broadcast10 +const unsigned int mem_event_broadcast10 = 0x00094038; +// Control of which Internal Event to Broadcast11 +const unsigned int mem_event_broadcast11 = 0x0009403c; +// Control of which Internal Event to Broadcast12 +const unsigned int mem_event_broadcast12 = 0x00094040; +// Control of which Internal Event to Broadcast13 +const unsigned int mem_event_broadcast13 = 0x00094044; +// Control of which Internal Event to Broadcast14 +const unsigned int mem_event_broadcast14 = 0x00094048; +// Control of which Internal Event to Broadcast15 +const unsigned int mem_event_broadcast15 = 0x0009404c; +// Set block of broadcast signals to South +const unsigned int mem_event_broadcast_a_block_south_set = 0x00094050; +// Clear block of broadcast signals to South +const unsigned int mem_event_broadcast_a_block_south_clr = 0x00094054; +// Current value of block for broadcast signals to South +const unsigned int mem_event_broadcast_a_block_south_value = 0x00094058; +// Set block of broadcast switch A signals to West +const unsigned int mem_event_broadcast_a_block_west_set = 0x00094060; +// Clear block of broadcast switch A signals to West +const unsigned int mem_event_broadcast_a_block_west_clr = 0x00094064; +// Current value of block for broadcast switch A signals to West +const unsigned int mem_event_broadcast_a_block_west_value = 0x00094068; +// Set block of broadcast switch A signals to North +const unsigned int mem_event_broadcast_a_block_north_set = 0x00094070; +// Clear block of broadcast switch A signals to North +const unsigned int mem_event_broadcast_a_block_north_clr = 0x00094074; +// Current value of block for broadcast switch A signals to North +const unsigned int mem_event_broadcast_a_block_north_value = 0x00094078; +// Set block of broadcast switch A signals to East +const unsigned int mem_event_broadcast_a_block_east_set = 0x00094080; +// Clear block of broadcast switch A signals to East +const unsigned int mem_event_broadcast_a_block_east_clr = 0x00094084; +// Current value of block for broadcast switch A signals to East +const unsigned int mem_event_broadcast_a_block_east_value = 0x00094088; +// Set block of broadcast switch B signals to South +const unsigned int mem_event_broadcast_b_block_south_set = 0x00094090; +// Clear block of broadcast switch B signals to South +const unsigned int mem_event_broadcast_b_block_south_clr = 0x00094094; +// Current value of block for broadcast switch B signals to South +const unsigned int mem_event_broadcast_b_block_south_value = 0x00094098; +// Set block of broadcast switch B signals to West +const unsigned int mem_event_broadcast_b_block_west_set = 0x000940a0; +// Clear block of broadcast switch B signals to West +const unsigned int mem_event_broadcast_b_block_west_clr = 0x000940a4; +// Current value of block for broadcast switch B signals to West +const unsigned int mem_event_broadcast_b_block_west_value = 0x000940a8; +// Set block of broadcast switch B signals to North +const unsigned int mem_event_broadcast_b_block_north_set = 0x000940b0; +// Clear block of broadcast switch B signals to North +const unsigned int mem_event_broadcast_b_block_north_clr = 0x000940b4; +// Current value of block for broadcast switch B signals to North +const unsigned int mem_event_broadcast_b_block_north_value = 0x000940b8; +// Set block of broadcast switch B signals to East +const unsigned int mem_event_broadcast_b_block_east_set = 0x000940c0; +// Clear block of broadcast switch B signals to East +const unsigned int mem_event_broadcast_b_block_east_clr = 0x000940c4; +// Current value of block for broadcast switch B signals to East +const unsigned int mem_event_broadcast_b_block_east_value = 0x000940c8; +// Control of Trace +const unsigned int mem_trace_control0 = 0x000940d0; +// Control of Trace: packet configuration +const unsigned int mem_trace_control1 = 0x000940d4; +// Status of trace engine +const unsigned int mem_trace_status = 0x000940d8; +// Control of which Internal Event to Trace +const unsigned int mem_trace_event0 = 0x000940e0; +// Control of which Internal Event to Trace +const unsigned int mem_trace_event1 = 0x000940e4; +// Internal Timer Event Value. +const unsigned int mem_timer_trig_event_low_value = 0x000940f0; +// Internal Timer Event Value. +const unsigned int mem_timer_trig_event_high_value = 0x000940f4; +// Internal Timer Low part Value. +const unsigned int mem_timer_low = 0x000940f8; +// Internal Timer High part Value. +const unsigned int mem_timer_high = 0x000940fc; +// Define Watchpoint0 +const unsigned int mem_watchpoint0 = 0x00094100; +// Define Watchpoint1 +const unsigned int mem_watchpoint1 = 0x00094104; +// Define Watchpoint2 +const unsigned int mem_watchpoint2 = 0x00094108; +// Define Watchpoint3 +const unsigned int mem_watchpoint3 = 0x0009410c; +// Internal event status register0 +const unsigned int mem_event_status0 = 0x00094200; +// Internal event status register1 +const unsigned int mem_event_status1 = 0x00094204; +// Internal event status register2 +const unsigned int mem_event_status2 = 0x00094208; +// Internal event status register3 +const unsigned int mem_event_status3 = 0x0009420c; +// Internal event status register4 +const unsigned int mem_event_status4 = 0x00094210; +// Internal event status register5 +const unsigned int mem_event_status5 = 0x00094214; +// Combo events input events +const unsigned int mem_combo_event_inputs = 0x00094400; +// Combo events input events +const unsigned int mem_combo_event_control = 0x00094404; +// Configuration for edge detection events +const unsigned int mem_edge_detection_event_control = 0x00094408; +// Event enable for Group 0 +const unsigned int mem_event_group_0_enable = 0x00094500; +// Event enable for Watchpoint Group +const unsigned int mem_event_group_watchpoint_enable = 0x00094504; +// Event enable for DMA Group +const unsigned int mem_event_group_dma_enable = 0x00094508; +// Event enable for Lock Group +const unsigned int mem_event_group_lock_enable = 0x0009450c; +// Event enable for Stream Switch Group +const unsigned int mem_event_group_stream_switch_enable = 0x00094510; +// Event enable for Memory Conflict Group +const unsigned int mem_event_group_memory_conflict_enable = 0x00094514; +// Event enable for Error Group +const unsigned int mem_event_group_error_enable = 0x00094518; +// Event enable for Broadcast Group +const unsigned int mem_event_group_broadcast_enable = 0x0009451c; +// Event enable for User Group +const unsigned int mem_event_group_user_event_enable = 0x00094520; +// Control for memory (privileged) +const unsigned int mem_memory_control = 0x00096048; +// DMA BD0 0 +const unsigned int mem_dma_bd0_0 = 0x000a0000; +// DMA BD0 1 +const unsigned int mem_dma_bd0_1 = 0x000a0004; +// DMA BD0 2 +const unsigned int mem_dma_bd0_2 = 0x000a0008; +// DMA BD0 3 +const unsigned int mem_dma_bd0_3 = 0x000a000c; +// DMA BD0 4 +const unsigned int mem_dma_bd0_4 = 0x000a0010; +// DMA BD0 5 +const unsigned int mem_dma_bd0_5 = 0x000a0014; +// DMA BD0 6 +const unsigned int mem_dma_bd0_6 = 0x000a0018; +// DMA BD0 7 +const unsigned int mem_dma_bd0_7 = 0x000a001c; +// DMA BD1 0 +const unsigned int mem_dma_bd1_0 = 0x000a0020; +// DMA BD1 1 +const unsigned int mem_dma_bd1_1 = 0x000a0024; +// DMA BD1 2 +const unsigned int mem_dma_bd1_2 = 0x000a0028; +// DMA BD1 3 +const unsigned int mem_dma_bd1_3 = 0x000a002c; +// DMA BD1 4 +const unsigned int mem_dma_bd1_4 = 0x000a0030; +// DMA BD1 5 +const unsigned int mem_dma_bd1_5 = 0x000a0034; +// DMA BD1 6 +const unsigned int mem_dma_bd1_6 = 0x000a0038; +// DMA BD1 7 +const unsigned int mem_dma_bd1_7 = 0x000a003c; +// DMA BD2 0 +const unsigned int mem_dma_bd2_0 = 0x000a0040; +// DMA BD2 1 +const unsigned int mem_dma_bd2_1 = 0x000a0044; +// DMA BD2 2 +const unsigned int mem_dma_bd2_2 = 0x000a0048; +// DMA BD2 3 +const unsigned int mem_dma_bd2_3 = 0x000a004c; +// DMA BD2 4 +const unsigned int mem_dma_bd2_4 = 0x000a0050; +// DMA BD2 5 +const unsigned int mem_dma_bd2_5 = 0x000a0054; +// DMA BD2 6 +const unsigned int mem_dma_bd2_6 = 0x000a0058; +// DMA BD2 7 +const unsigned int mem_dma_bd2_7 = 0x000a005c; +// DMA BD3 0 +const unsigned int mem_dma_bd3_0 = 0x000a0060; +// DMA BD3 1 +const unsigned int mem_dma_bd3_1 = 0x000a0064; +// DMA BD3 2 +const unsigned int mem_dma_bd3_2 = 0x000a0068; +// DMA BD3 3 +const unsigned int mem_dma_bd3_3 = 0x000a006c; +// DMA BD3 4 +const unsigned int mem_dma_bd3_4 = 0x000a0070; +// DMA BD3 5 +const unsigned int mem_dma_bd3_5 = 0x000a0074; +// DMA BD3 6 +const unsigned int mem_dma_bd3_6 = 0x000a0078; +// DMA BD3 7 +const unsigned int mem_dma_bd3_7 = 0x000a007c; +// DMA BD4 0 +const unsigned int mem_dma_bd4_0 = 0x000a0080; +// DMA BD4 1 +const unsigned int mem_dma_bd4_1 = 0x000a0084; +// DMA BD4 2 +const unsigned int mem_dma_bd4_2 = 0x000a0088; +// DMA BD4 3 +const unsigned int mem_dma_bd4_3 = 0x000a008c; +// DMA BD4 4 +const unsigned int mem_dma_bd4_4 = 0x000a0090; +// DMA BD4 5 +const unsigned int mem_dma_bd4_5 = 0x000a0094; +// DMA BD4 6 +const unsigned int mem_dma_bd4_6 = 0x000a0098; +// DMA BD4 7 +const unsigned int mem_dma_bd4_7 = 0x000a009c; +// DMA BD5 0 +const unsigned int mem_dma_bd5_0 = 0x000a00a0; +// DMA BD5 1 +const unsigned int mem_dma_bd5_1 = 0x000a00a4; +// DMA BD5 2 +const unsigned int mem_dma_bd5_2 = 0x000a00a8; +// DMA BD5 3 +const unsigned int mem_dma_bd5_3 = 0x000a00ac; +// DMA BD5 4 +const unsigned int mem_dma_bd5_4 = 0x000a00b0; +// DMA BD5 5 +const unsigned int mem_dma_bd5_5 = 0x000a00b4; +// DMA BD5 6 +const unsigned int mem_dma_bd5_6 = 0x000a00b8; +// DMA BD5 7 +const unsigned int mem_dma_bd5_7 = 0x000a00bc; +// DMA BD6 0 +const unsigned int mem_dma_bd6_0 = 0x000a00c0; +// DMA BD6 1 +const unsigned int mem_dma_bd6_1 = 0x000a00c4; +// DMA BD6 2 +const unsigned int mem_dma_bd6_2 = 0x000a00c8; +// DMA BD6 3 +const unsigned int mem_dma_bd6_3 = 0x000a00cc; +// DMA BD6 4 +const unsigned int mem_dma_bd6_4 = 0x000a00d0; +// DMA BD6 5 +const unsigned int mem_dma_bd6_5 = 0x000a00d4; +// DMA BD6 6 +const unsigned int mem_dma_bd6_6 = 0x000a00d8; +// DMA BD6 7 +const unsigned int mem_dma_bd6_7 = 0x000a00dc; +// DMA BD7 0 +const unsigned int mem_dma_bd7_0 = 0x000a00e0; +// DMA BD7 1 +const unsigned int mem_dma_bd7_1 = 0x000a00e4; +// DMA BD7 2 +const unsigned int mem_dma_bd7_2 = 0x000a00e8; +// DMA BD7 3 +const unsigned int mem_dma_bd7_3 = 0x000a00ec; +// DMA BD7 4 +const unsigned int mem_dma_bd7_4 = 0x000a00f0; +// DMA BD7 5 +const unsigned int mem_dma_bd7_5 = 0x000a00f4; +// DMA BD7 6 +const unsigned int mem_dma_bd7_6 = 0x000a00f8; +// DMA BD7 7 +const unsigned int mem_dma_bd7_7 = 0x000a00fc; +// DMA BD8 0 +const unsigned int mem_dma_bd8_0 = 0x000a0100; +// DMA BD8 1 +const unsigned int mem_dma_bd8_1 = 0x000a0104; +// DMA BD8 2 +const unsigned int mem_dma_bd8_2 = 0x000a0108; +// DMA BD8 3 +const unsigned int mem_dma_bd8_3 = 0x000a010c; +// DMA BD8 4 +const unsigned int mem_dma_bd8_4 = 0x000a0110; +// DMA BD8 5 +const unsigned int mem_dma_bd8_5 = 0x000a0114; +// DMA BD8 6 +const unsigned int mem_dma_bd8_6 = 0x000a0118; +// DMA BD8 7 +const unsigned int mem_dma_bd8_7 = 0x000a011c; +// DMA BD9 0 +const unsigned int mem_dma_bd9_0 = 0x000a0120; +// DMA BD9 1 +const unsigned int mem_dma_bd9_1 = 0x000a0124; +// DMA BD9 2 +const unsigned int mem_dma_bd9_2 = 0x000a0128; +// DMA BD9 3 +const unsigned int mem_dma_bd9_3 = 0x000a012c; +// DMA BD9 4 +const unsigned int mem_dma_bd9_4 = 0x000a0130; +// DMA BD9 5 +const unsigned int mem_dma_bd9_5 = 0x000a0134; +// DMA BD9 6 +const unsigned int mem_dma_bd9_6 = 0x000a0138; +// DMA BD9 7 +const unsigned int mem_dma_bd9_7 = 0x000a013c; +// DMA BD10 0 +const unsigned int mem_dma_bd10_0 = 0x000a0140; +// DMA BD10 1 +const unsigned int mem_dma_bd10_1 = 0x000a0144; +// DMA BD10 2 +const unsigned int mem_dma_bd10_2 = 0x000a0148; +// DMA BD10 3 +const unsigned int mem_dma_bd10_3 = 0x000a014c; +// DMA BD10 4 +const unsigned int mem_dma_bd10_4 = 0x000a0150; +// DMA BD10 5 +const unsigned int mem_dma_bd10_5 = 0x000a0154; +// DMA BD10 6 +const unsigned int mem_dma_bd10_6 = 0x000a0158; +// DMA BD10 7 +const unsigned int mem_dma_bd10_7 = 0x000a015c; +// DMA BD11 0 +const unsigned int mem_dma_bd11_0 = 0x000a0160; +// DMA BD11 1 +const unsigned int mem_dma_bd11_1 = 0x000a0164; +// DMA BD11 2 +const unsigned int mem_dma_bd11_2 = 0x000a0168; +// DMA BD11 3 +const unsigned int mem_dma_bd11_3 = 0x000a016c; +// DMA BD11 4 +const unsigned int mem_dma_bd11_4 = 0x000a0170; +// DMA BD11 5 +const unsigned int mem_dma_bd11_5 = 0x000a0174; +// DMA BD11 6 +const unsigned int mem_dma_bd11_6 = 0x000a0178; +// DMA BD11 7 +const unsigned int mem_dma_bd11_7 = 0x000a017c; +// DMA BD12 0 +const unsigned int mem_dma_bd12_0 = 0x000a0180; +// DMA BD12 1 +const unsigned int mem_dma_bd12_1 = 0x000a0184; +// DMA BD12 2 +const unsigned int mem_dma_bd12_2 = 0x000a0188; +// DMA BD12 3 +const unsigned int mem_dma_bd12_3 = 0x000a018c; +// DMA BD12 4 +const unsigned int mem_dma_bd12_4 = 0x000a0190; +// DMA BD12 5 +const unsigned int mem_dma_bd12_5 = 0x000a0194; +// DMA BD12 6 +const unsigned int mem_dma_bd12_6 = 0x000a0198; +// DMA BD12 7 +const unsigned int mem_dma_bd12_7 = 0x000a019c; +// DMA BD13 0 +const unsigned int mem_dma_bd13_0 = 0x000a01a0; +// DMA BD13 1 +const unsigned int mem_dma_bd13_1 = 0x000a01a4; +// DMA BD13 2 +const unsigned int mem_dma_bd13_2 = 0x000a01a8; +// DMA BD13 3 +const unsigned int mem_dma_bd13_3 = 0x000a01ac; +// DMA BD13 4 +const unsigned int mem_dma_bd13_4 = 0x000a01b0; +// DMA BD13 5 +const unsigned int mem_dma_bd13_5 = 0x000a01b4; +// DMA BD13 6 +const unsigned int mem_dma_bd13_6 = 0x000a01b8; +// DMA BD13 7 +const unsigned int mem_dma_bd13_7 = 0x000a01bc; +// DMA BD14 0 +const unsigned int mem_dma_bd14_0 = 0x000a01c0; +// DMA BD14 1 +const unsigned int mem_dma_bd14_1 = 0x000a01c4; +// DMA BD14 2 +const unsigned int mem_dma_bd14_2 = 0x000a01c8; +// DMA BD14 3 +const unsigned int mem_dma_bd14_3 = 0x000a01cc; +// DMA BD14 4 +const unsigned int mem_dma_bd14_4 = 0x000a01d0; +// DMA BD14 5 +const unsigned int mem_dma_bd14_5 = 0x000a01d4; +// DMA BD14 6 +const unsigned int mem_dma_bd14_6 = 0x000a01d8; +// DMA BD14 7 +const unsigned int mem_dma_bd14_7 = 0x000a01dc; +// DMA BD15 0 +const unsigned int mem_dma_bd15_0 = 0x000a01e0; +// DMA BD15 1 +const unsigned int mem_dma_bd15_1 = 0x000a01e4; +// DMA BD15 2 +const unsigned int mem_dma_bd15_2 = 0x000a01e8; +// DMA BD15 3 +const unsigned int mem_dma_bd15_3 = 0x000a01ec; +// DMA BD15 4 +const unsigned int mem_dma_bd15_4 = 0x000a01f0; +// DMA BD15 5 +const unsigned int mem_dma_bd15_5 = 0x000a01f4; +// DMA BD15 6 +const unsigned int mem_dma_bd15_6 = 0x000a01f8; +// DMA BD15 7 +const unsigned int mem_dma_bd15_7 = 0x000a01fc; +// DMA BD16 0 +const unsigned int mem_dma_bd16_0 = 0x000a0200; +// DMA BD16 1 +const unsigned int mem_dma_bd16_1 = 0x000a0204; +// DMA BD16 2 +const unsigned int mem_dma_bd16_2 = 0x000a0208; +// DMA BD16 3 +const unsigned int mem_dma_bd16_3 = 0x000a020c; +// DMA BD16 4 +const unsigned int mem_dma_bd16_4 = 0x000a0210; +// DMA BD16 5 +const unsigned int mem_dma_bd16_5 = 0x000a0214; +// DMA BD16 6 +const unsigned int mem_dma_bd16_6 = 0x000a0218; +// DMA BD16 7 +const unsigned int mem_dma_bd16_7 = 0x000a021c; +// DMA BD17 0 +const unsigned int mem_dma_bd17_0 = 0x000a0220; +// DMA BD17 1 +const unsigned int mem_dma_bd17_1 = 0x000a0224; +// DMA BD17 2 +const unsigned int mem_dma_bd17_2 = 0x000a0228; +// DMA BD17 3 +const unsigned int mem_dma_bd17_3 = 0x000a022c; +// DMA BD17 4 +const unsigned int mem_dma_bd17_4 = 0x000a0230; +// DMA BD17 5 +const unsigned int mem_dma_bd17_5 = 0x000a0234; +// DMA BD17 6 +const unsigned int mem_dma_bd17_6 = 0x000a0238; +// DMA BD17 7 +const unsigned int mem_dma_bd17_7 = 0x000a023c; +// DMA BD18 0 +const unsigned int mem_dma_bd18_0 = 0x000a0240; +// DMA BD18 1 +const unsigned int mem_dma_bd18_1 = 0x000a0244; +// DMA BD18 2 +const unsigned int mem_dma_bd18_2 = 0x000a0248; +// DMA BD18 3 +const unsigned int mem_dma_bd18_3 = 0x000a024c; +// DMA BD18 4 +const unsigned int mem_dma_bd18_4 = 0x000a0250; +// DMA BD18 5 +const unsigned int mem_dma_bd18_5 = 0x000a0254; +// DMA BD18 6 +const unsigned int mem_dma_bd18_6 = 0x000a0258; +// DMA BD18 7 +const unsigned int mem_dma_bd18_7 = 0x000a025c; +// DMA BD19 0 +const unsigned int mem_dma_bd19_0 = 0x000a0260; +// DMA BD19 1 +const unsigned int mem_dma_bd19_1 = 0x000a0264; +// DMA BD19 2 +const unsigned int mem_dma_bd19_2 = 0x000a0268; +// DMA BD19 3 +const unsigned int mem_dma_bd19_3 = 0x000a026c; +// DMA BD19 4 +const unsigned int mem_dma_bd19_4 = 0x000a0270; +// DMA BD19 5 +const unsigned int mem_dma_bd19_5 = 0x000a0274; +// DMA BD19 6 +const unsigned int mem_dma_bd19_6 = 0x000a0278; +// DMA BD19 7 +const unsigned int mem_dma_bd19_7 = 0x000a027c; +// DMA BD20 0 +const unsigned int mem_dma_bd20_0 = 0x000a0280; +// DMA BD20 1 +const unsigned int mem_dma_bd20_1 = 0x000a0284; +// DMA BD20 2 +const unsigned int mem_dma_bd20_2 = 0x000a0288; +// DMA BD20 3 +const unsigned int mem_dma_bd20_3 = 0x000a028c; +// DMA BD20 4 +const unsigned int mem_dma_bd20_4 = 0x000a0290; +// DMA BD20 5 +const unsigned int mem_dma_bd20_5 = 0x000a0294; +// DMA BD20 6 +const unsigned int mem_dma_bd20_6 = 0x000a0298; +// DMA BD20 7 +const unsigned int mem_dma_bd20_7 = 0x000a029c; +// DMA BD21 0 +const unsigned int mem_dma_bd21_0 = 0x000a02a0; +// DMA BD21 1 +const unsigned int mem_dma_bd21_1 = 0x000a02a4; +// DMA BD21 2 +const unsigned int mem_dma_bd21_2 = 0x000a02a8; +// DMA BD21 3 +const unsigned int mem_dma_bd21_3 = 0x000a02ac; +// DMA BD21 4 +const unsigned int mem_dma_bd21_4 = 0x000a02b0; +// DMA BD21 5 +const unsigned int mem_dma_bd21_5 = 0x000a02b4; +// DMA BD21 6 +const unsigned int mem_dma_bd21_6 = 0x000a02b8; +// DMA BD21 7 +const unsigned int mem_dma_bd21_7 = 0x000a02bc; +// DMA BD22 0 +const unsigned int mem_dma_bd22_0 = 0x000a02c0; +// DMA BD22 1 +const unsigned int mem_dma_bd22_1 = 0x000a02c4; +// DMA BD22 2 +const unsigned int mem_dma_bd22_2 = 0x000a02c8; +// DMA BD22 3 +const unsigned int mem_dma_bd22_3 = 0x000a02cc; +// DMA BD22 4 +const unsigned int mem_dma_bd22_4 = 0x000a02d0; +// DMA BD22 5 +const unsigned int mem_dma_bd22_5 = 0x000a02d4; +// DMA BD22 6 +const unsigned int mem_dma_bd22_6 = 0x000a02d8; +// DMA BD22 7 +const unsigned int mem_dma_bd22_7 = 0x000a02dc; +// DMA BD23 0 +const unsigned int mem_dma_bd23_0 = 0x000a02e0; +// DMA BD23 1 +const unsigned int mem_dma_bd23_1 = 0x000a02e4; +// DMA BD23 2 +const unsigned int mem_dma_bd23_2 = 0x000a02e8; +// DMA BD23 3 +const unsigned int mem_dma_bd23_3 = 0x000a02ec; +// DMA BD23 4 +const unsigned int mem_dma_bd23_4 = 0x000a02f0; +// DMA BD23 5 +const unsigned int mem_dma_bd23_5 = 0x000a02f4; +// DMA BD23 6 +const unsigned int mem_dma_bd23_6 = 0x000a02f8; +// DMA BD23 7 +const unsigned int mem_dma_bd23_7 = 0x000a02fc; +// DMA BD24 0 +const unsigned int mem_dma_bd24_0 = 0x000a0300; +// DMA BD24 1 +const unsigned int mem_dma_bd24_1 = 0x000a0304; +// DMA BD24 2 +const unsigned int mem_dma_bd24_2 = 0x000a0308; +// DMA BD24 3 +const unsigned int mem_dma_bd24_3 = 0x000a030c; +// DMA BD24 4 +const unsigned int mem_dma_bd24_4 = 0x000a0310; +// DMA BD24 5 +const unsigned int mem_dma_bd24_5 = 0x000a0314; +// DMA BD24 6 +const unsigned int mem_dma_bd24_6 = 0x000a0318; +// DMA BD24 7 +const unsigned int mem_dma_bd24_7 = 0x000a031c; +// DMA BD25 0 +const unsigned int mem_dma_bd25_0 = 0x000a0320; +// DMA BD25 1 +const unsigned int mem_dma_bd25_1 = 0x000a0324; +// DMA BD25 2 +const unsigned int mem_dma_bd25_2 = 0x000a0328; +// DMA BD25 3 +const unsigned int mem_dma_bd25_3 = 0x000a032c; +// DMA BD25 4 +const unsigned int mem_dma_bd25_4 = 0x000a0330; +// DMA BD25 5 +const unsigned int mem_dma_bd25_5 = 0x000a0334; +// DMA BD25 6 +const unsigned int mem_dma_bd25_6 = 0x000a0338; +// DMA BD25 7 +const unsigned int mem_dma_bd25_7 = 0x000a033c; +// DMA BD26 0 +const unsigned int mem_dma_bd26_0 = 0x000a0340; +// DMA BD26 1 +const unsigned int mem_dma_bd26_1 = 0x000a0344; +// DMA BD26 2 +const unsigned int mem_dma_bd26_2 = 0x000a0348; +// DMA BD26 3 +const unsigned int mem_dma_bd26_3 = 0x000a034c; +// DMA BD26 4 +const unsigned int mem_dma_bd26_4 = 0x000a0350; +// DMA BD26 5 +const unsigned int mem_dma_bd26_5 = 0x000a0354; +// DMA BD26 6 +const unsigned int mem_dma_bd26_6 = 0x000a0358; +// DMA BD26 7 +const unsigned int mem_dma_bd26_7 = 0x000a035c; +// DMA BD27 0 +const unsigned int mem_dma_bd27_0 = 0x000a0360; +// DMA BD27 1 +const unsigned int mem_dma_bd27_1 = 0x000a0364; +// DMA BD27 2 +const unsigned int mem_dma_bd27_2 = 0x000a0368; +// DMA BD27 3 +const unsigned int mem_dma_bd27_3 = 0x000a036c; +// DMA BD27 4 +const unsigned int mem_dma_bd27_4 = 0x000a0370; +// DMA BD27 5 +const unsigned int mem_dma_bd27_5 = 0x000a0374; +// DMA BD27 6 +const unsigned int mem_dma_bd27_6 = 0x000a0378; +// DMA BD27 7 +const unsigned int mem_dma_bd27_7 = 0x000a037c; +// DMA BD28 0 +const unsigned int mem_dma_bd28_0 = 0x000a0380; +// DMA BD28 1 +const unsigned int mem_dma_bd28_1 = 0x000a0384; +// DMA BD28 2 +const unsigned int mem_dma_bd28_2 = 0x000a0388; +// DMA BD28 3 +const unsigned int mem_dma_bd28_3 = 0x000a038c; +// DMA BD28 4 +const unsigned int mem_dma_bd28_4 = 0x000a0390; +// DMA BD28 5 +const unsigned int mem_dma_bd28_5 = 0x000a0394; +// DMA BD28 6 +const unsigned int mem_dma_bd28_6 = 0x000a0398; +// DMA BD28 7 +const unsigned int mem_dma_bd28_7 = 0x000a039c; +// DMA BD29 0 +const unsigned int mem_dma_bd29_0 = 0x000a03a0; +// DMA BD29 1 +const unsigned int mem_dma_bd29_1 = 0x000a03a4; +// DMA BD29 2 +const unsigned int mem_dma_bd29_2 = 0x000a03a8; +// DMA BD29 3 +const unsigned int mem_dma_bd29_3 = 0x000a03ac; +// DMA BD29 4 +const unsigned int mem_dma_bd29_4 = 0x000a03b0; +// DMA BD29 5 +const unsigned int mem_dma_bd29_5 = 0x000a03b4; +// DMA BD29 6 +const unsigned int mem_dma_bd29_6 = 0x000a03b8; +// DMA BD29 7 +const unsigned int mem_dma_bd29_7 = 0x000a03bc; +// DMA BD30 0 +const unsigned int mem_dma_bd30_0 = 0x000a03c0; +// DMA BD30 1 +const unsigned int mem_dma_bd30_1 = 0x000a03c4; +// DMA BD30 2 +const unsigned int mem_dma_bd30_2 = 0x000a03c8; +// DMA BD30 3 +const unsigned int mem_dma_bd30_3 = 0x000a03cc; +// DMA BD30 4 +const unsigned int mem_dma_bd30_4 = 0x000a03d0; +// DMA BD30 5 +const unsigned int mem_dma_bd30_5 = 0x000a03d4; +// DMA BD30 6 +const unsigned int mem_dma_bd30_6 = 0x000a03d8; +// DMA BD30 7 +const unsigned int mem_dma_bd30_7 = 0x000a03dc; +// DMA BD31 0 +const unsigned int mem_dma_bd31_0 = 0x000a03e0; +// DMA BD31 1 +const unsigned int mem_dma_bd31_1 = 0x000a03e4; +// DMA BD31 2 +const unsigned int mem_dma_bd31_2 = 0x000a03e8; +// DMA BD31 3 +const unsigned int mem_dma_bd31_3 = 0x000a03ec; +// DMA BD31 4 +const unsigned int mem_dma_bd31_4 = 0x000a03f0; +// DMA BD31 5 +const unsigned int mem_dma_bd31_5 = 0x000a03f4; +// DMA BD31 6 +const unsigned int mem_dma_bd31_6 = 0x000a03f8; +// DMA BD31 7 +const unsigned int mem_dma_bd31_7 = 0x000a03fc; +// DMA BD32 0 +const unsigned int mem_dma_bd32_0 = 0x000a0400; +// DMA BD32 1 +const unsigned int mem_dma_bd32_1 = 0x000a0404; +// DMA BD32 2 +const unsigned int mem_dma_bd32_2 = 0x000a0408; +// DMA BD32 3 +const unsigned int mem_dma_bd32_3 = 0x000a040c; +// DMA BD32 4 +const unsigned int mem_dma_bd32_4 = 0x000a0410; +// DMA BD32 5 +const unsigned int mem_dma_bd32_5 = 0x000a0414; +// DMA BD32 6 +const unsigned int mem_dma_bd32_6 = 0x000a0418; +// DMA BD32 7 +const unsigned int mem_dma_bd32_7 = 0x000a041c; +// DMA BD33 0 +const unsigned int mem_dma_bd33_0 = 0x000a0420; +// DMA BD33 1 +const unsigned int mem_dma_bd33_1 = 0x000a0424; +// DMA BD33 2 +const unsigned int mem_dma_bd33_2 = 0x000a0428; +// DMA BD33 3 +const unsigned int mem_dma_bd33_3 = 0x000a042c; +// DMA BD33 4 +const unsigned int mem_dma_bd33_4 = 0x000a0430; +// DMA BD33 5 +const unsigned int mem_dma_bd33_5 = 0x000a0434; +// DMA BD33 6 +const unsigned int mem_dma_bd33_6 = 0x000a0438; +// DMA BD33 7 +const unsigned int mem_dma_bd33_7 = 0x000a043c; +// DMA BD34 0 +const unsigned int mem_dma_bd34_0 = 0x000a0440; +// DMA BD34 1 +const unsigned int mem_dma_bd34_1 = 0x000a0444; +// DMA BD34 2 +const unsigned int mem_dma_bd34_2 = 0x000a0448; +// DMA BD34 3 +const unsigned int mem_dma_bd34_3 = 0x000a044c; +// DMA BD34 4 +const unsigned int mem_dma_bd34_4 = 0x000a0450; +// DMA BD34 5 +const unsigned int mem_dma_bd34_5 = 0x000a0454; +// DMA BD34 6 +const unsigned int mem_dma_bd34_6 = 0x000a0458; +// DMA BD34 7 +const unsigned int mem_dma_bd34_7 = 0x000a045c; +// DMA BD35 0 +const unsigned int mem_dma_bd35_0 = 0x000a0460; +// DMA BD35 1 +const unsigned int mem_dma_bd35_1 = 0x000a0464; +// DMA BD35 2 +const unsigned int mem_dma_bd35_2 = 0x000a0468; +// DMA BD35 3 +const unsigned int mem_dma_bd35_3 = 0x000a046c; +// DMA BD35 4 +const unsigned int mem_dma_bd35_4 = 0x000a0470; +// DMA BD35 5 +const unsigned int mem_dma_bd35_5 = 0x000a0474; +// DMA BD35 6 +const unsigned int mem_dma_bd35_6 = 0x000a0478; +// DMA BD35 7 +const unsigned int mem_dma_bd35_7 = 0x000a047c; +// DMA BD36 0 +const unsigned int mem_dma_bd36_0 = 0x000a0480; +// DMA BD36 1 +const unsigned int mem_dma_bd36_1 = 0x000a0484; +// DMA BD36 2 +const unsigned int mem_dma_bd36_2 = 0x000a0488; +// DMA BD36 3 +const unsigned int mem_dma_bd36_3 = 0x000a048c; +// DMA BD36 4 +const unsigned int mem_dma_bd36_4 = 0x000a0490; +// DMA BD36 5 +const unsigned int mem_dma_bd36_5 = 0x000a0494; +// DMA BD36 6 +const unsigned int mem_dma_bd36_6 = 0x000a0498; +// DMA BD36 7 +const unsigned int mem_dma_bd36_7 = 0x000a049c; +// DMA BD37 0 +const unsigned int mem_dma_bd37_0 = 0x000a04a0; +// DMA BD37 1 +const unsigned int mem_dma_bd37_1 = 0x000a04a4; +// DMA BD37 2 +const unsigned int mem_dma_bd37_2 = 0x000a04a8; +// DMA BD37 3 +const unsigned int mem_dma_bd37_3 = 0x000a04ac; +// DMA BD37 4 +const unsigned int mem_dma_bd37_4 = 0x000a04b0; +// DMA BD37 5 +const unsigned int mem_dma_bd37_5 = 0x000a04b4; +// DMA BD37 6 +const unsigned int mem_dma_bd37_6 = 0x000a04b8; +// DMA BD37 7 +const unsigned int mem_dma_bd37_7 = 0x000a04bc; +// DMA BD38 0 +const unsigned int mem_dma_bd38_0 = 0x000a04c0; +// DMA BD38 1 +const unsigned int mem_dma_bd38_1 = 0x000a04c4; +// DMA BD38 2 +const unsigned int mem_dma_bd38_2 = 0x000a04c8; +// DMA BD38 3 +const unsigned int mem_dma_bd38_3 = 0x000a04cc; +// DMA BD38 4 +const unsigned int mem_dma_bd38_4 = 0x000a04d0; +// DMA BD38 5 +const unsigned int mem_dma_bd38_5 = 0x000a04d4; +// DMA BD38 6 +const unsigned int mem_dma_bd38_6 = 0x000a04d8; +// DMA BD38 7 +const unsigned int mem_dma_bd38_7 = 0x000a04dc; +// DMA BD39 0 +const unsigned int mem_dma_bd39_0 = 0x000a04e0; +// DMA BD39 1 +const unsigned int mem_dma_bd39_1 = 0x000a04e4; +// DMA BD39 2 +const unsigned int mem_dma_bd39_2 = 0x000a04e8; +// DMA BD39 3 +const unsigned int mem_dma_bd39_3 = 0x000a04ec; +// DMA BD39 4 +const unsigned int mem_dma_bd39_4 = 0x000a04f0; +// DMA BD39 5 +const unsigned int mem_dma_bd39_5 = 0x000a04f4; +// DMA BD39 6 +const unsigned int mem_dma_bd39_6 = 0x000a04f8; +// DMA BD39 7 +const unsigned int mem_dma_bd39_7 = 0x000a04fc; +// DMA BD40 0 +const unsigned int mem_dma_bd40_0 = 0x000a0500; +// DMA BD40 1 +const unsigned int mem_dma_bd40_1 = 0x000a0504; +// DMA BD40 2 +const unsigned int mem_dma_bd40_2 = 0x000a0508; +// DMA BD40 3 +const unsigned int mem_dma_bd40_3 = 0x000a050c; +// DMA BD40 4 +const unsigned int mem_dma_bd40_4 = 0x000a0510; +// DMA BD40 5 +const unsigned int mem_dma_bd40_5 = 0x000a0514; +// DMA BD40 6 +const unsigned int mem_dma_bd40_6 = 0x000a0518; +// DMA BD40 7 +const unsigned int mem_dma_bd40_7 = 0x000a051c; +// DMA BD41 0 +const unsigned int mem_dma_bd41_0 = 0x000a0520; +// DMA BD41 1 +const unsigned int mem_dma_bd41_1 = 0x000a0524; +// DMA BD41 2 +const unsigned int mem_dma_bd41_2 = 0x000a0528; +// DMA BD41 3 +const unsigned int mem_dma_bd41_3 = 0x000a052c; +// DMA BD41 4 +const unsigned int mem_dma_bd41_4 = 0x000a0530; +// DMA BD41 5 +const unsigned int mem_dma_bd41_5 = 0x000a0534; +// DMA BD41 6 +const unsigned int mem_dma_bd41_6 = 0x000a0538; +// DMA BD41 7 +const unsigned int mem_dma_bd41_7 = 0x000a053c; +// DMA BD42 0 +const unsigned int mem_dma_bd42_0 = 0x000a0540; +// DMA BD42 1 +const unsigned int mem_dma_bd42_1 = 0x000a0544; +// DMA BD42 2 +const unsigned int mem_dma_bd42_2 = 0x000a0548; +// DMA BD42 3 +const unsigned int mem_dma_bd42_3 = 0x000a054c; +// DMA BD42 4 +const unsigned int mem_dma_bd42_4 = 0x000a0550; +// DMA BD42 5 +const unsigned int mem_dma_bd42_5 = 0x000a0554; +// DMA BD42 6 +const unsigned int mem_dma_bd42_6 = 0x000a0558; +// DMA BD42 7 +const unsigned int mem_dma_bd42_7 = 0x000a055c; +// DMA BD43 0 +const unsigned int mem_dma_bd43_0 = 0x000a0560; +// DMA BD43 1 +const unsigned int mem_dma_bd43_1 = 0x000a0564; +// DMA BD43 2 +const unsigned int mem_dma_bd43_2 = 0x000a0568; +// DMA BD43 3 +const unsigned int mem_dma_bd43_3 = 0x000a056c; +// DMA BD43 4 +const unsigned int mem_dma_bd43_4 = 0x000a0570; +// DMA BD43 5 +const unsigned int mem_dma_bd43_5 = 0x000a0574; +// DMA BD43 6 +const unsigned int mem_dma_bd43_6 = 0x000a0578; +// DMA BD43 7 +const unsigned int mem_dma_bd43_7 = 0x000a057c; +// DMA BD44 0 +const unsigned int mem_dma_bd44_0 = 0x000a0580; +// DMA BD44 1 +const unsigned int mem_dma_bd44_1 = 0x000a0584; +// DMA BD44 2 +const unsigned int mem_dma_bd44_2 = 0x000a0588; +// DMA BD44 3 +const unsigned int mem_dma_bd44_3 = 0x000a058c; +// DMA BD44 4 +const unsigned int mem_dma_bd44_4 = 0x000a0590; +// DMA BD44 5 +const unsigned int mem_dma_bd44_5 = 0x000a0594; +// DMA BD44 6 +const unsigned int mem_dma_bd44_6 = 0x000a0598; +// DMA BD44 7 +const unsigned int mem_dma_bd44_7 = 0x000a059c; +// DMA BD45 0 +const unsigned int mem_dma_bd45_0 = 0x000a05a0; +// DMA BD45 1 +const unsigned int mem_dma_bd45_1 = 0x000a05a4; +// DMA BD45 2 +const unsigned int mem_dma_bd45_2 = 0x000a05a8; +// DMA BD45 3 +const unsigned int mem_dma_bd45_3 = 0x000a05ac; +// DMA BD45 4 +const unsigned int mem_dma_bd45_4 = 0x000a05b0; +// DMA BD45 5 +const unsigned int mem_dma_bd45_5 = 0x000a05b4; +// DMA BD45 6 +const unsigned int mem_dma_bd45_6 = 0x000a05b8; +// DMA BD45 7 +const unsigned int mem_dma_bd45_7 = 0x000a05bc; +// DMA BD46 0 +const unsigned int mem_dma_bd46_0 = 0x000a05c0; +// DMA BD46 1 +const unsigned int mem_dma_bd46_1 = 0x000a05c4; +// DMA BD46 2 +const unsigned int mem_dma_bd46_2 = 0x000a05c8; +// DMA BD46 3 +const unsigned int mem_dma_bd46_3 = 0x000a05cc; +// DMA BD46 4 +const unsigned int mem_dma_bd46_4 = 0x000a05d0; +// DMA BD46 5 +const unsigned int mem_dma_bd46_5 = 0x000a05d4; +// DMA BD46 6 +const unsigned int mem_dma_bd46_6 = 0x000a05d8; +// DMA BD46 7 +const unsigned int mem_dma_bd46_7 = 0x000a05dc; +// DMA BD47 0 +const unsigned int mem_dma_bd47_0 = 0x000a05e0; +// DMA BD47 1 +const unsigned int mem_dma_bd47_1 = 0x000a05e4; +// DMA BD47 2 +const unsigned int mem_dma_bd47_2 = 0x000a05e8; +// DMA BD47 3 +const unsigned int mem_dma_bd47_3 = 0x000a05ec; +// DMA BD47 4 +const unsigned int mem_dma_bd47_4 = 0x000a05f0; +// DMA BD47 5 +const unsigned int mem_dma_bd47_5 = 0x000a05f4; +// DMA BD47 6 +const unsigned int mem_dma_bd47_6 = 0x000a05f8; +// DMA BD47 7 +const unsigned int mem_dma_bd47_7 = 0x000a05fc; +// DMA Control Register S2MM Ch0 +const unsigned int mem_dma_s2mm_0_ctrl = 0x000a0600; +// DMA Control Register S2MM Ch0 start BD +const unsigned int mem_dma_s2mm_0_start_queue = 0x000a0604; +// DMA Control Register S2MM Ch1 +const unsigned int mem_dma_s2mm_1_ctrl = 0x000a0608; +// DMA Control Register S2MM Ch1 start BD +const unsigned int mem_dma_s2mm_1_start_queue = 0x000a060c; +// DMA Control Register S2MM Ch2 +const unsigned int mem_dma_s2mm_2_ctrl = 0x000a0610; +// DMA Control Register S2MM Ch2 start BD +const unsigned int mem_dma_s2mm_2_start_queue = 0x000a0614; +// DMA Control Register S2MM Ch3 +const unsigned int mem_dma_s2mm_3_ctrl = 0x000a0618; +// DMA Control Register S2MM Ch3 start BD +const unsigned int mem_dma_s2mm_3_start_queue = 0x000a061c; +// DMA Control Register S2MM Ch4 +const unsigned int mem_dma_s2mm_4_ctrl = 0x000a0620; +// DMA Control Register S2MM Ch4 start BD +const unsigned int mem_dma_s2mm_4_start_queue = 0x000a0624; +// DMA Control Register S2MM Ch5 +const unsigned int mem_dma_s2mm_5_ctrl = 0x000a0628; +// DMA Control Register S2MM Ch5 start BD +const unsigned int mem_dma_s2mm_5_start_queue = 0x000a062c; +// DMA Control Register MM2S Ch0 +const unsigned int mem_dma_mm2s_0_ctrl = 0x000a0630; +// DMA Control Register MM2S Ch0 start BD +const unsigned int mem_dma_mm2s_0_start_queue = 0x000a0634; +// DMA Control Register MM2S Ch1 +const unsigned int mem_dma_mm2s_1_ctrl = 0x000a0638; +// DMA Control Register MM2S Ch1 start BD +const unsigned int mem_dma_mm2s_1_start_queue = 0x000a063c; +// DMA Control Register MM2S Ch2 +const unsigned int mem_dma_mm2s_2_ctrl = 0x000a0640; +// DMA Control Register MM2S Ch2 start BD +const unsigned int mem_dma_mm2s_2_start_queue = 0x000a0644; +// DMA Control Register MM2S Ch3 +const unsigned int mem_dma_mm2s_3_ctrl = 0x000a0648; +// DMA Control Register MM2S Ch3 start BD +const unsigned int mem_dma_mm2s_3_start_queue = 0x000a064c; +// DMA Control Register MM2S Ch4 +const unsigned int mem_dma_mm2s_4_ctrl = 0x000a0650; +// DMA Control Register MM2S Ch4 start BD +const unsigned int mem_dma_mm2s_4_start_queue = 0x000a0654; +// DMA Control Register MM2S Ch5 +const unsigned int mem_dma_mm2s_5_ctrl = 0x000a0658; +// DMA Control Register MM2S Ch5 start BD +const unsigned int mem_dma_mm2s_5_start_queue = 0x000a065c; +// DMA S2MM Status Register Ch0 +const unsigned int mem_dma_s2mm_status_0 = 0x000a0660; +// DMA S2MM Status Register Ch1 +const unsigned int mem_dma_s2mm_status_1 = 0x000a0664; +// DMA S2MM Status Register Ch2 +const unsigned int mem_dma_s2mm_status_2 = 0x000a0668; +// DMA S2MM Status Register Ch3 +const unsigned int mem_dma_s2mm_status_3 = 0x000a066c; +// DMA S2MM Status Register Ch4 +const unsigned int mem_dma_s2mm_status_4 = 0x000a0670; +// DMA S2MM Status Register Ch5 +const unsigned int mem_dma_s2mm_status_5 = 0x000a0674; +// DMA MM2S Status Register Ch0 +const unsigned int mem_dma_mm2s_status_0 = 0x000a0680; +// DMA MM2S Status Register Ch1 +const unsigned int mem_dma_mm2s_status_1 = 0x000a0684; +// DMA MM2S Status Register Ch2 +const unsigned int mem_dma_mm2s_status_2 = 0x000a0688; +// DMA MM2S Status Register Ch3 +const unsigned int mem_dma_mm2s_status_3 = 0x000a068c; +// DMA MM2S Status Register Ch4 +const unsigned int mem_dma_mm2s_status_4 = 0x000a0690; +// DMA MM2S Status Register Ch5 +const unsigned int mem_dma_mm2s_status_5 = 0x000a0694; +// Selection of which DMA channels will generate events +const unsigned int mem_dma_event_channel_selection = 0x000a06a0; +// DMA S2MM Current Write Count Ch0 +const unsigned int mem_dma_s2mm_current_write_count_0 = 0x000a06b0; +// DMA S2MM Current Write Count Ch1 +const unsigned int mem_dma_s2mm_current_write_count_1 = 0x000a06b4; +// DMA S2MM Current Write Count Ch2 +const unsigned int mem_dma_s2mm_current_write_count_2 = 0x000a06b8; +// DMA S2MM Current Write Count Ch3 +const unsigned int mem_dma_s2mm_current_write_count_3 = 0x000a06bc; +// DMA S2MM Current Write Count Ch4 +const unsigned int mem_dma_s2mm_current_write_count_4 = 0x000a06c0; +// DMA S2MM Current Write Count Ch5 +const unsigned int mem_dma_s2mm_current_write_count_5 = 0x000a06c4; +// DMA S2MM FoT Count FIFO Pop Ch0 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_0 = 0x000a06c8; +// DMA S2MM FoT Count FIFO Pop Ch1 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_1 = 0x000a06cc; +// DMA S2MM FoT Count FIFO Pop Ch2 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_2 = 0x000a06d0; +// DMA S2MM FoT Count FIFO Pop Ch3 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_3 = 0x000a06d4; +// DMA S2MM FoT Count FIFO Pop Ch4 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_4 = 0x000a06d8; +// DMA S2MM FoT Count FIFO Pop Ch5 +const unsigned int mem_dma_s2mm_fot_count_fifo_pop_5 = 0x000a06dc; +// DMA MM2S 0 Constant Pad Value +const unsigned int mem_dma_mm2s_0_constant_pad_value = 0x000a06e0; +// DMA MM2S 1 Constant Pad Value +const unsigned int mem_dma_mm2s_1_constant_pad_value = 0x000a06e4; +// DMA MM2S 2 Constant Pad Value +const unsigned int mem_dma_mm2s_2_constant_pad_value = 0x000a06e8; +// DMA MM2S 3 Constant Pad Value +const unsigned int mem_dma_mm2s_3_constant_pad_value = 0x000a06ec; +// DMA MM2S 4 Constant Pad Value +const unsigned int mem_dma_mm2s_4_constant_pad_value = 0x000a06f0; +// DMA MM2S 5 Constant Pad Value +const unsigned int mem_dma_mm2s_5_constant_pad_value = 0x000a06f4; +// Stream Switch Master Configuration DMA 0 +const unsigned int mem_stream_switch_master_config_dma0 = 0x000b0000; +// Stream Switch Master Configuration DMA 1 +const unsigned int mem_stream_switch_master_config_dma1 = 0x000b0004; +// Stream Switch Master Configuration DMA 2 +const unsigned int mem_stream_switch_master_config_dma2 = 0x000b0008; +// Stream Switch Master Configuration DMA 3 +const unsigned int mem_stream_switch_master_config_dma3 = 0x000b000c; +// Stream Switch Master Configuration DMA 4 +const unsigned int mem_stream_switch_master_config_dma4 = 0x000b0010; +// Stream Switch Master Configuration DMA 5 +const unsigned int mem_stream_switch_master_config_dma5 = 0x000b0014; +// Stream Switch Master Configuration AI Engine Tile Ctrl +const unsigned int mem_stream_switch_master_config_tile_ctrl = 0x000b0018; +// Stream Switch Master Configuration South 0 +const unsigned int mem_stream_switch_master_config_south0 = 0x000b001c; +// Stream Switch Master Configuration South 1 +const unsigned int mem_stream_switch_master_config_south1 = 0x000b0020; +// Stream Switch Master Configuration South 2 +const unsigned int mem_stream_switch_master_config_south2 = 0x000b0024; +// Stream Switch Master Configuration South 3 +const unsigned int mem_stream_switch_master_config_south3 = 0x000b0028; +// Stream Switch Master Configuration North 0 +const unsigned int mem_stream_switch_master_config_north0 = 0x000b002c; +// Stream Switch Master Configuration North 1 +const unsigned int mem_stream_switch_master_config_north1 = 0x000b0030; +// Stream Switch Master Configuration North 2 +const unsigned int mem_stream_switch_master_config_north2 = 0x000b0034; +// Stream Switch Master Configuration North 3 +const unsigned int mem_stream_switch_master_config_north3 = 0x000b0038; +// Stream Switch Master Configuration North 4 +const unsigned int mem_stream_switch_master_config_north4 = 0x000b003c; +// Stream Switch Master Configuration North 5 +const unsigned int mem_stream_switch_master_config_north5 = 0x000b0040; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_config_dma_0 = 0x000b0100; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_config_dma_1 = 0x000b0104; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_config_dma_2 = 0x000b0108; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_config_dma_3 = 0x000b010c; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_config_dma_4 = 0x000b0110; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_config_dma_5 = 0x000b0114; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_config_tile_ctrl = 0x000b0118; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_config_south_0 = 0x000b011c; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_config_south_1 = 0x000b0120; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_config_south_2 = 0x000b0124; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_config_south_3 = 0x000b0128; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_config_south_4 = 0x000b012c; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_config_south_5 = 0x000b0130; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_config_north_0 = 0x000b0134; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_config_north_1 = 0x000b0138; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_config_north_2 = 0x000b013c; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_config_north_3 = 0x000b0140; +// Stream Switch Slave Configuration Trace +const unsigned int mem_stream_switch_slave_config_trace = 0x000b0144; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot0 = 0x000b0200; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot1 = 0x000b0204; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot2 = 0x000b0208; +// Stream Switch Slave Configuration DMA 0 +const unsigned int mem_stream_switch_slave_dma_0_slot3 = 0x000b020c; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot0 = 0x000b0210; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot1 = 0x000b0214; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot2 = 0x000b0218; +// Stream Switch Slave Configuration DMA 1 +const unsigned int mem_stream_switch_slave_dma_1_slot3 = 0x000b021c; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot0 = 0x000b0220; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot1 = 0x000b0224; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot2 = 0x000b0228; +// Stream Switch Slave Configuration DMA 2 +const unsigned int mem_stream_switch_slave_dma_2_slot3 = 0x000b022c; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot0 = 0x000b0230; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot1 = 0x000b0234; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot2 = 0x000b0238; +// Stream Switch Slave Configuration DMA 3 +const unsigned int mem_stream_switch_slave_dma_3_slot3 = 0x000b023c; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot0 = 0x000b0240; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot1 = 0x000b0244; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot2 = 0x000b0248; +// Stream Switch Slave Configuration DMA 4 +const unsigned int mem_stream_switch_slave_dma_4_slot3 = 0x000b024c; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot0 = 0x000b0250; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot1 = 0x000b0254; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot2 = 0x000b0258; +// Stream Switch Slave Configuration DMA 5 +const unsigned int mem_stream_switch_slave_dma_5_slot3 = 0x000b025c; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot0 = 0x000b0260; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot1 = 0x000b0264; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot2 = 0x000b0268; +// Stream Switch Slave Configuration Tile Ctrl +const unsigned int mem_stream_switch_slave_tile_ctrl_slot3 = 0x000b026c; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot0 = 0x000b0270; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot1 = 0x000b0274; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot2 = 0x000b0278; +// Stream Switch Slave Configuration South 0 +const unsigned int mem_stream_switch_slave_south_0_slot3 = 0x000b027c; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot0 = 0x000b0280; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot1 = 0x000b0284; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot2 = 0x000b0288; +// Stream Switch Slave Configuration South 1 +const unsigned int mem_stream_switch_slave_south_1_slot3 = 0x000b028c; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot0 = 0x000b0290; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot1 = 0x000b0294; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot2 = 0x000b0298; +// Stream Switch Slave Configuration South 2 +const unsigned int mem_stream_switch_slave_south_2_slot3 = 0x000b029c; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot0 = 0x000b02a0; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot1 = 0x000b02a4; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot2 = 0x000b02a8; +// Stream Switch Slave Configuration South 3 +const unsigned int mem_stream_switch_slave_south_3_slot3 = 0x000b02ac; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot0 = 0x000b02b0; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot1 = 0x000b02b4; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot2 = 0x000b02b8; +// Stream Switch Slave Configuration South 4 +const unsigned int mem_stream_switch_slave_south_4_slot3 = 0x000b02bc; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot0 = 0x000b02c0; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot1 = 0x000b02c4; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot2 = 0x000b02c8; +// Stream Switch Slave Configuration South 5 +const unsigned int mem_stream_switch_slave_south_5_slot3 = 0x000b02cc; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot0 = 0x000b02d0; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot1 = 0x000b02d4; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot2 = 0x000b02d8; +// Stream Switch Slave Configuration North 0 +const unsigned int mem_stream_switch_slave_north_0_slot3 = 0x000b02dc; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot0 = 0x000b02e0; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot1 = 0x000b02e4; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot2 = 0x000b02e8; +// Stream Switch Slave Configuration North 1 +const unsigned int mem_stream_switch_slave_north_1_slot3 = 0x000b02ec; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot0 = 0x000b02f0; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot1 = 0x000b02f4; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot2 = 0x000b02f8; +// Stream Switch Slave Configuration North 2 +const unsigned int mem_stream_switch_slave_north_2_slot3 = 0x000b02fc; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot0 = 0x000b0300; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot1 = 0x000b0304; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot2 = 0x000b0308; +// Stream Switch Slave Configuration North 3 +const unsigned int mem_stream_switch_slave_north_3_slot3 = 0x000b030c; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot0 = 0x000b0310; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot1 = 0x000b0314; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot2 = 0x000b0318; +// Stream Switch Slave Configuration AI Engine Trace +const unsigned int mem_stream_switch_slave_trace_slot3 = 0x000b031c; +// Stream Switch Deterministic Merge Arbiter:0 Slave:0,1 +const unsigned int mem_stream_switch_deterministic_merge_arb0_slave0_1 = 0x000b0800; +// Stream Switch Deterministic Merge Arbiter:0 Slave:2,3 +const unsigned int mem_stream_switch_deterministic_merge_arb0_slave2_3 = 0x000b0804; +// Stream Switch Deterministic Merge Arbiter:0 Control +const unsigned int mem_stream_switch_deterministic_merge_arb0_ctrl = 0x000b0808; +// Stream Switch Deterministic Merge Arbiter:1 Slave:0,1 +const unsigned int mem_stream_switch_deterministic_merge_arb1_slave0_1 = 0x000b0810; +// Stream Switch Deterministic Merge Arbiter:1 Slave:2,3 +const unsigned int mem_stream_switch_deterministic_merge_arb1_slave2_3 = 0x000b0814; +// Stream Switch Deterministic Merge Arbiter:1 Control +const unsigned int mem_stream_switch_deterministic_merge_arb1_ctrl = 0x000b0818; +// Select Stream Switch Ports for event generation +const unsigned int mem_stream_switch_event_port_selection_0 = 0x000b0f00; +// Select Stream Switch Ports for event generation +const unsigned int mem_stream_switch_event_port_selection_1 = 0x000b0f04; +// Status bits for Parity errors on stream switch ports (error on lower OR upper 32-bit word) +const unsigned int mem_stream_switch_parity_status = 0x000b0f10; +// Injection of Parity errors on stream switch ports (privileged) +const unsigned int mem_stream_switch_parity_injection = 0x000b0f20; +// Status of control packet handling +const unsigned int mem_tile_control_packet_handler_status = 0x000b0f30; +// Defeatured this generation. Status of Stream Switch Adaptive Clock Gate +const unsigned int mem_stream_switch_adaptive_clock_gate_status = 0x000b0f34; +// Defeatured this generation. Status of Stream Switch Adaptive Clock Gate Abort Period +const unsigned int mem_stream_switch_adaptive_clock_gate_abort_period = 0x000b0f38; +// Value of lock 0 +const unsigned int mem_lock0_value = 0x000c0000; +// Value of lock 1 +const unsigned int mem_lock1_value = 0x000c0010; +// Value of lock 2 +const unsigned int mem_lock2_value = 0x000c0020; +// Value of lock 3 +const unsigned int mem_lock3_value = 0x000c0030; +// Value of lock 4 +const unsigned int mem_lock4_value = 0x000c0040; +// Value of lock 5 +const unsigned int mem_lock5_value = 0x000c0050; +// Value of lock 6 +const unsigned int mem_lock6_value = 0x000c0060; +// Value of lock 7 +const unsigned int mem_lock7_value = 0x000c0070; +// Value of lock 8 +const unsigned int mem_lock8_value = 0x000c0080; +// Value of lock 9 +const unsigned int mem_lock9_value = 0x000c0090; +// Value of lock 10 +const unsigned int mem_lock10_value = 0x000c00a0; +// Value of lock 11 +const unsigned int mem_lock11_value = 0x000c00b0; +// Value of lock 12 +const unsigned int mem_lock12_value = 0x000c00c0; +// Value of lock 13 +const unsigned int mem_lock13_value = 0x000c00d0; +// Value of lock 14 +const unsigned int mem_lock14_value = 0x000c00e0; +// Value of lock 15 +const unsigned int mem_lock15_value = 0x000c00f0; +// Value of lock 16 +const unsigned int mem_lock16_value = 0x000c0100; +// Value of lock 17 +const unsigned int mem_lock17_value = 0x000c0110; +// Value of lock 18 +const unsigned int mem_lock18_value = 0x000c0120; +// Value of lock 19 +const unsigned int mem_lock19_value = 0x000c0130; +// Value of lock 20 +const unsigned int mem_lock20_value = 0x000c0140; +// Value of lock 21 +const unsigned int mem_lock21_value = 0x000c0150; +// Value of lock 22 +const unsigned int mem_lock22_value = 0x000c0160; +// Value of lock 23 +const unsigned int mem_lock23_value = 0x000c0170; +// Value of lock 24 +const unsigned int mem_lock24_value = 0x000c0180; +// Value of lock 25 +const unsigned int mem_lock25_value = 0x000c0190; +// Value of lock 26 +const unsigned int mem_lock26_value = 0x000c01a0; +// Value of lock 27 +const unsigned int mem_lock27_value = 0x000c01b0; +// Value of lock 28 +const unsigned int mem_lock28_value = 0x000c01c0; +// Value of lock 29 +const unsigned int mem_lock29_value = 0x000c01d0; +// Value of lock 30 +const unsigned int mem_lock30_value = 0x000c01e0; +// Value of lock 31 +const unsigned int mem_lock31_value = 0x000c01f0; +// Value of lock 32 +const unsigned int mem_lock32_value = 0x000c0200; +// Value of lock 33 +const unsigned int mem_lock33_value = 0x000c0210; +// Value of lock 34 +const unsigned int mem_lock34_value = 0x000c0220; +// Value of lock 35 +const unsigned int mem_lock35_value = 0x000c0230; +// Value of lock 36 +const unsigned int mem_lock36_value = 0x000c0240; +// Value of lock 37 +const unsigned int mem_lock37_value = 0x000c0250; +// Value of lock 38 +const unsigned int mem_lock38_value = 0x000c0260; +// Value of lock 39 +const unsigned int mem_lock39_value = 0x000c0270; +// Value of lock 40 +const unsigned int mem_lock40_value = 0x000c0280; +// Value of lock 41 +const unsigned int mem_lock41_value = 0x000c0290; +// Value of lock 42 +const unsigned int mem_lock42_value = 0x000c02a0; +// Value of lock 43 +const unsigned int mem_lock43_value = 0x000c02b0; +// Value of lock 44 +const unsigned int mem_lock44_value = 0x000c02c0; +// Value of lock 45 +const unsigned int mem_lock45_value = 0x000c02d0; +// Value of lock 46 +const unsigned int mem_lock46_value = 0x000c02e0; +// Value of lock 47 +const unsigned int mem_lock47_value = 0x000c02f0; +// Value of lock 48 +const unsigned int mem_lock48_value = 0x000c0300; +// Value of lock 49 +const unsigned int mem_lock49_value = 0x000c0310; +// Value of lock 50 +const unsigned int mem_lock50_value = 0x000c0320; +// Value of lock 51 +const unsigned int mem_lock51_value = 0x000c0330; +// Value of lock 52 +const unsigned int mem_lock52_value = 0x000c0340; +// Value of lock 53 +const unsigned int mem_lock53_value = 0x000c0350; +// Value of lock 54 +const unsigned int mem_lock54_value = 0x000c0360; +// Value of lock 55 +const unsigned int mem_lock55_value = 0x000c0370; +// Value of lock 56 +const unsigned int mem_lock56_value = 0x000c0380; +// Value of lock 57 +const unsigned int mem_lock57_value = 0x000c0390; +// Value of lock 58 +const unsigned int mem_lock58_value = 0x000c03a0; +// Value of lock 59 +const unsigned int mem_lock59_value = 0x000c03b0; +// Value of lock 60 +const unsigned int mem_lock60_value = 0x000c03c0; +// Value of lock 61 +const unsigned int mem_lock61_value = 0x000c03d0; +// Value of lock 62 +const unsigned int mem_lock62_value = 0x000c03e0; +// Value of lock 63 +const unsigned int mem_lock63_value = 0x000c03f0; +// Select lock for lock event generation 0 +const unsigned int mem_locks_event_selection_0 = 0x000c0400; +// Select lock for lock event generation 1 +const unsigned int mem_locks_event_selection_1 = 0x000c0404; +// Select lock for lock event generation 2 +const unsigned int mem_locks_event_selection_2 = 0x000c0408; +// Select lock for lock event generation 3 +const unsigned int mem_locks_event_selection_3 = 0x000c040c; +// Select lock for lock event generation 4 +const unsigned int mem_locks_event_selection_4 = 0x000c0410; +// Select lock for lock event generation 5 +const unsigned int mem_locks_event_selection_5 = 0x000c0414; +// Select lock for lock event generation 6 +const unsigned int mem_locks_event_selection_6 = 0x000c0418; +// Select lock for lock event generation 7 +const unsigned int mem_locks_event_selection_7 = 0x000c041c; +// Status bits for lock overflow, write to clear +const unsigned int mem_locks_overflow_0 = 0x000c0420; +// Status bits for lock overflow, write to clear +const unsigned int mem_locks_overflow_1 = 0x000c0424; +// Status bits for lock underflow, write to clear +const unsigned int mem_locks_underflow_0 = 0x000c0428; +// Status bits for lock underflow, write to clear +const unsigned int mem_locks_underflow_1 = 0x000c042c; +// Lock Request. 65kB address space: 0xD0000 - 0xDFFFC, Lock_Id [15:10], Acq_Rel (9), Change_Value [8:2] +const unsigned int mem_lock_request = 0x000d0000; +// Control clock gating of modules (privileged) +const unsigned int mem_module_clock_control = 0x000fff00; +// Tile control register (Isolation) +const unsigned int mem_tile_control = 0x000fff20; + +// Register definitions for interface tile +// ####################################### +// Step size between lock registers +const unsigned int shim_lock_step_size = 0x10; +// Step size between DMA BD register groups +const unsigned int shim_dma_bd_step_size = 0x20; +// Step size between DMA S2MM register groups +const unsigned int shim_dma_s2mm_step_size = 0x8; +// Value of lock 0 +const unsigned int shim_lock0_value = 0x00000000; +// Value of lock 1 +const unsigned int shim_lock1_value = 0x00000010; +// Value of lock 2 +const unsigned int shim_lock2_value = 0x00000020; +// Value of lock 3 +const unsigned int shim_lock3_value = 0x00000030; +// Value of lock 4 +const unsigned int shim_lock4_value = 0x00000040; +// Value of lock 5 +const unsigned int shim_lock5_value = 0x00000050; +// Value of lock 6 +const unsigned int shim_lock6_value = 0x00000060; +// Value of lock 7 +const unsigned int shim_lock7_value = 0x00000070; +// Value of lock 8 +const unsigned int shim_lock8_value = 0x00000080; +// Value of lock 9 +const unsigned int shim_lock9_value = 0x00000090; +// Value of lock 10 +const unsigned int shim_lock10_value = 0x000000a0; +// Value of lock 11 +const unsigned int shim_lock11_value = 0x000000b0; +// Value of lock 12 +const unsigned int shim_lock12_value = 0x000000c0; +// Value of lock 13 +const unsigned int shim_lock13_value = 0x000000d0; +// Value of lock 14 +const unsigned int shim_lock14_value = 0x000000e0; +// Value of lock 15 +const unsigned int shim_lock15_value = 0x000000f0; +// Select lock for lock event generation 0 +const unsigned int shim_locks_event_selection_0 = 0x00000100; +// Select lock for lock event generation 1 +const unsigned int shim_locks_event_selection_1 = 0x00000104; +// Select lock for lock event generation 2 +const unsigned int shim_locks_event_selection_2 = 0x00000108; +// Select lock for lock event generation 3 +const unsigned int shim_locks_event_selection_3 = 0x0000010c; +// Select lock for lock event generation 4 +const unsigned int shim_locks_event_selection_4 = 0x00000110; +// Select lock for lock event generation 5 +const unsigned int shim_locks_event_selection_5 = 0x00000114; +// Status bits for lock overflow, write to clear +const unsigned int shim_locks_overflow = 0x00000120; +// Status bits for lock underflow, write to clear +const unsigned int shim_locks_underflow = 0x00000128; +// Interrupt controller 2nd level mask (IMR) (noc_module_0 Only) +const unsigned int shim_interrupt_controller_2nd_level_mask = 0x00001000; +// Interrupt controller 2nd level enable interrupt (IER) (noc_module_0 Only) +const unsigned int shim_interrupt_controller_2nd_level_enable = 0x00001004; +// Interrupt controller 2nd level disable interrupt (IDR) (noc_module_0 Only) +const unsigned int shim_interrupt_controller_2nd_level_disable = 0x00001008; +// Interrupt controller 2nd level status register (ISR) (noc_module_0 Only) +const unsigned int shim_interrupt_controller_2nd_level_status = 0x0000100c; +// Interrupt controller 2nd level interrupt (privileged) (noc_module_0 Only) +const unsigned int shim_interrupt_controller_2nd_level_interrupt = 0x00001010; +// AXI-MM NSU Bridge configuration (privileged) (only valid in noc_module_0 instance and shim tiles with NSU connection) +const unsigned int shim_me_aximm_config = 0x00002100; +// Configuration of multiplexer of tile input streams +const unsigned int shim_mux_config = 0x00002104; +// Configuration of demultiplexer of tile output streams +const unsigned int shim_demux_config = 0x00002108; +// AXI-MM outstanding transactions monitor +const unsigned int shim_axi_mm_outstanding_transactions = 0x00002120; +// SMID bits (privileged) +const unsigned int shim_smid = 0x00003000; +// DMA BD0 0 +const unsigned int shim_dma_bd0_0 = 0x00009000; +// DMA BD0 1 +const unsigned int shim_dma_bd0_1 = 0x00009004; +// DMA BD0 2 +const unsigned int shim_dma_bd0_2 = 0x00009008; +// DMA BD0 3 +const unsigned int shim_dma_bd0_3 = 0x0000900c; +// DMA BD0 4 +const unsigned int shim_dma_bd0_4 = 0x00009010; +// DMA BD0 5 +const unsigned int shim_dma_bd0_5 = 0x00009014; +// DMA BD0 6 +const unsigned int shim_dma_bd0_6 = 0x00009018; +// DMA BD0 7 +const unsigned int shim_dma_bd0_7 = 0x0000901c; +// DMA BD0 8 +const unsigned int shim_dma_bd0_8 = 0x00009020; +// DMA BD1 0 +const unsigned int shim_dma_bd1_0 = 0x00009030; +// DMA BD1 1 +const unsigned int shim_dma_bd1_1 = 0x00009034; +// DMA BD1 2 +const unsigned int shim_dma_bd1_2 = 0x00009038; +// DMA BD1 3 +const unsigned int shim_dma_bd1_3 = 0x0000903c; +// DMA BD1 4 +const unsigned int shim_dma_bd1_4 = 0x00009040; +// DMA BD1 5 +const unsigned int shim_dma_bd1_5 = 0x00009044; +// DMA BD1 6 +const unsigned int shim_dma_bd1_6 = 0x00009048; +// DMA BD1 7 +const unsigned int shim_dma_bd1_7 = 0x0000904c; +// DMA BD1 8 +const unsigned int shim_dma_bd1_8 = 0x00009050; +// DMA BD2 0 +const unsigned int shim_dma_bd2_0 = 0x00009060; +// DMA BD2 1 +const unsigned int shim_dma_bd2_1 = 0x00009064; +// DMA BD2 2 +const unsigned int shim_dma_bd2_2 = 0x00009068; +// DMA BD2 3 +const unsigned int shim_dma_bd2_3 = 0x0000906c; +// DMA BD2 4 +const unsigned int shim_dma_bd2_4 = 0x00009070; +// DMA BD2 5 +const unsigned int shim_dma_bd2_5 = 0x00009074; +// DMA BD2 6 +const unsigned int shim_dma_bd2_6 = 0x00009078; +// DMA BD2 7 +const unsigned int shim_dma_bd2_7 = 0x0000907c; +// DMA BD2 8 +const unsigned int shim_dma_bd2_8 = 0x00009080; +// DMA BD3 0 +const unsigned int shim_dma_bd3_0 = 0x00009090; +// DMA BD3 1 +const unsigned int shim_dma_bd3_1 = 0x00009094; +// DMA BD3 2 +const unsigned int shim_dma_bd3_2 = 0x00009098; +// DMA BD3 3 +const unsigned int shim_dma_bd3_3 = 0x0000909c; +// DMA BD3 4 +const unsigned int shim_dma_bd3_4 = 0x000090a0; +// DMA BD3 5 +const unsigned int shim_dma_bd3_5 = 0x000090a4; +// DMA BD3 6 +const unsigned int shim_dma_bd3_6 = 0x000090a8; +// DMA BD3 7 +const unsigned int shim_dma_bd3_7 = 0x000090ac; +// DMA BD3 8 +const unsigned int shim_dma_bd3_8 = 0x000090b0; +// DMA BD4 0 +const unsigned int shim_dma_bd4_0 = 0x000090c0; +// DMA BD4 1 +const unsigned int shim_dma_bd4_1 = 0x000090c4; +// DMA BD4 2 +const unsigned int shim_dma_bd4_2 = 0x000090c8; +// DMA BD4 3 +const unsigned int shim_dma_bd4_3 = 0x000090cc; +// DMA BD4 4 +const unsigned int shim_dma_bd4_4 = 0x000090d0; +// DMA BD4 5 +const unsigned int shim_dma_bd4_5 = 0x000090d4; +// DMA BD4 6 +const unsigned int shim_dma_bd4_6 = 0x000090d8; +// DMA BD4 7 +const unsigned int shim_dma_bd4_7 = 0x000090dc; +// DMA BD4 8 +const unsigned int shim_dma_bd4_8 = 0x000090e0; +// DMA BD5 0 +const unsigned int shim_dma_bd5_0 = 0x000090f0; +// DMA BD5 1 +const unsigned int shim_dma_bd5_1 = 0x000090f4; +// DMA BD5 2 +const unsigned int shim_dma_bd5_2 = 0x000090f8; +// DMA BD5 3 +const unsigned int shim_dma_bd5_3 = 0x000090fc; +// DMA BD5 4 +const unsigned int shim_dma_bd5_4 = 0x00009100; +// DMA BD5 5 +const unsigned int shim_dma_bd5_5 = 0x00009104; +// DMA BD5 6 +const unsigned int shim_dma_bd5_6 = 0x00009108; +// DMA BD5 7 +const unsigned int shim_dma_bd5_7 = 0x0000910c; +// DMA BD5 8 +const unsigned int shim_dma_bd5_8 = 0x00009110; +// DMA BD6 0 +const unsigned int shim_dma_bd6_0 = 0x00009120; +// DMA BD6 1 +const unsigned int shim_dma_bd6_1 = 0x00009124; +// DMA BD6 2 +const unsigned int shim_dma_bd6_2 = 0x00009128; +// DMA BD6 3 +const unsigned int shim_dma_bd6_3 = 0x0000912c; +// DMA BD6 4 +const unsigned int shim_dma_bd6_4 = 0x00009130; +// DMA BD6 5 +const unsigned int shim_dma_bd6_5 = 0x00009134; +// DMA BD6 6 +const unsigned int shim_dma_bd6_6 = 0x00009138; +// DMA BD6 7 +const unsigned int shim_dma_bd6_7 = 0x0000913c; +// DMA BD6 8 +const unsigned int shim_dma_bd6_8 = 0x00009140; +// DMA BD7 0 +const unsigned int shim_dma_bd7_0 = 0x00009150; +// DMA BD7 1 +const unsigned int shim_dma_bd7_1 = 0x00009154; +// DMA BD7 2 +const unsigned int shim_dma_bd7_2 = 0x00009158; +// DMA BD7 3 +const unsigned int shim_dma_bd7_3 = 0x0000915c; +// DMA BD7 4 +const unsigned int shim_dma_bd7_4 = 0x00009160; +// DMA BD7 5 +const unsigned int shim_dma_bd7_5 = 0x00009164; +// DMA BD7 6 +const unsigned int shim_dma_bd7_6 = 0x00009168; +// DMA BD7 7 +const unsigned int shim_dma_bd7_7 = 0x0000916c; +// DMA BD7 8 +const unsigned int shim_dma_bd7_8 = 0x00009170; +// DMA BD8 0 +const unsigned int shim_dma_bd8_0 = 0x00009180; +// DMA BD8 1 +const unsigned int shim_dma_bd8_1 = 0x00009184; +// DMA BD8 2 +const unsigned int shim_dma_bd8_2 = 0x00009188; +// DMA BD8 3 +const unsigned int shim_dma_bd8_3 = 0x0000918c; +// DMA BD8 4 +const unsigned int shim_dma_bd8_4 = 0x00009190; +// DMA BD8 5 +const unsigned int shim_dma_bd8_5 = 0x00009194; +// DMA BD8 6 +const unsigned int shim_dma_bd8_6 = 0x00009198; +// DMA BD8 7 +const unsigned int shim_dma_bd8_7 = 0x0000919c; +// DMA BD8 8 +const unsigned int shim_dma_bd8_8 = 0x000091a0; +// DMA BD9 0 +const unsigned int shim_dma_bd9_0 = 0x000091b0; +// DMA BD9 1 +const unsigned int shim_dma_bd9_1 = 0x000091b4; +// DMA BD9 2 +const unsigned int shim_dma_bd9_2 = 0x000091b8; +// DMA BD9 3 +const unsigned int shim_dma_bd9_3 = 0x000091bc; +// DMA BD9 4 +const unsigned int shim_dma_bd9_4 = 0x000091c0; +// DMA BD9 5 +const unsigned int shim_dma_bd9_5 = 0x000091c4; +// DMA BD9 6 +const unsigned int shim_dma_bd9_6 = 0x000091c8; +// DMA BD9 7 +const unsigned int shim_dma_bd9_7 = 0x000091cc; +// DMA BD9 8 +const unsigned int shim_dma_bd9_8 = 0x000091d0; +// DMA BD10 0 +const unsigned int shim_dma_bd10_0 = 0x000091e0; +// DMA BD10 1 +const unsigned int shim_dma_bd10_1 = 0x000091e4; +// DMA BD10 2 +const unsigned int shim_dma_bd10_2 = 0x000091e8; +// DMA BD10 3 +const unsigned int shim_dma_bd10_3 = 0x000091ec; +// DMA BD10 4 +const unsigned int shim_dma_bd10_4 = 0x000091f0; +// DMA BD10 5 +const unsigned int shim_dma_bd10_5 = 0x000091f4; +// DMA BD10 6 +const unsigned int shim_dma_bd10_6 = 0x000091f8; +// DMA BD10 7 +const unsigned int shim_dma_bd10_7 = 0x000091fc; +// DMA BD10 8 +const unsigned int shim_dma_bd10_8 = 0x00009200; +// DMA BD11 0 +const unsigned int shim_dma_bd11_0 = 0x00009210; +// DMA BD11 1 +const unsigned int shim_dma_bd11_1 = 0x00009214; +// DMA BD11 2 +const unsigned int shim_dma_bd11_2 = 0x00009218; +// DMA BD11 3 +const unsigned int shim_dma_bd11_3 = 0x0000921c; +// DMA BD11 4 +const unsigned int shim_dma_bd11_4 = 0x00009220; +// DMA BD11 5 +const unsigned int shim_dma_bd11_5 = 0x00009224; +// DMA BD11 6 +const unsigned int shim_dma_bd11_6 = 0x00009228; +// DMA BD11 7 +const unsigned int shim_dma_bd11_7 = 0x0000922c; +// DMA BD11 8 +const unsigned int shim_dma_bd11_8 = 0x00009230; +// DMA BD12 0 +const unsigned int shim_dma_bd12_0 = 0x00009240; +// DMA BD12 1 +const unsigned int shim_dma_bd12_1 = 0x00009244; +// DMA BD12 2 +const unsigned int shim_dma_bd12_2 = 0x00009248; +// DMA BD12 3 +const unsigned int shim_dma_bd12_3 = 0x0000924c; +// DMA BD12 4 +const unsigned int shim_dma_bd12_4 = 0x00009250; +// DMA BD12 5 +const unsigned int shim_dma_bd12_5 = 0x00009254; +// DMA BD12 6 +const unsigned int shim_dma_bd12_6 = 0x00009258; +// DMA BD12 7 +const unsigned int shim_dma_bd12_7 = 0x0000925c; +// DMA BD12 8 +const unsigned int shim_dma_bd12_8 = 0x00009260; +// DMA BD13 0 +const unsigned int shim_dma_bd13_0 = 0x00009270; +// DMA BD13 1 +const unsigned int shim_dma_bd13_1 = 0x00009274; +// DMA BD13 2 +const unsigned int shim_dma_bd13_2 = 0x00009278; +// DMA BD13 3 +const unsigned int shim_dma_bd13_3 = 0x0000927c; +// DMA BD13 4 +const unsigned int shim_dma_bd13_4 = 0x00009280; +// DMA BD13 5 +const unsigned int shim_dma_bd13_5 = 0x00009284; +// DMA BD13 6 +const unsigned int shim_dma_bd13_6 = 0x00009288; +// DMA BD13 7 +const unsigned int shim_dma_bd13_7 = 0x0000928c; +// DMA BD13 8 +const unsigned int shim_dma_bd13_8 = 0x00009290; +// DMA BD14 0 +const unsigned int shim_dma_bd14_0 = 0x000092a0; +// DMA BD14 1 +const unsigned int shim_dma_bd14_1 = 0x000092a4; +// DMA BD14 2 +const unsigned int shim_dma_bd14_2 = 0x000092a8; +// DMA BD14 3 +const unsigned int shim_dma_bd14_3 = 0x000092ac; +// DMA BD14 4 +const unsigned int shim_dma_bd14_4 = 0x000092b0; +// DMA BD14 5 +const unsigned int shim_dma_bd14_5 = 0x000092b4; +// DMA BD14 6 +const unsigned int shim_dma_bd14_6 = 0x000092b8; +// DMA BD14 7 +const unsigned int shim_dma_bd14_7 = 0x000092bc; +// DMA BD14 8 +const unsigned int shim_dma_bd14_8 = 0x000092c0; +// DMA BD15 0 +const unsigned int shim_dma_bd15_0 = 0x000092d0; +// DMA BD15 1 +const unsigned int shim_dma_bd15_1 = 0x000092d4; +// DMA BD15 2 +const unsigned int shim_dma_bd15_2 = 0x000092d8; +// DMA BD15 3 +const unsigned int shim_dma_bd15_3 = 0x000092dc; +// DMA BD15 4 +const unsigned int shim_dma_bd15_4 = 0x000092e0; +// DMA BD15 5 +const unsigned int shim_dma_bd15_5 = 0x000092e4; +// DMA BD15 6 +const unsigned int shim_dma_bd15_6 = 0x000092e8; +// DMA BD15 7 +const unsigned int shim_dma_bd15_7 = 0x000092ec; +// DMA BD15 8 +const unsigned int shim_dma_bd15_8 = 0x000092f0; +// DMA Control Register S2MM Ch0 +const unsigned int shim_dma_s2mm_0_ctrl = 0x00009300; +// DMA Task Queue Insertion S2MM Ch0 (4-deep) +const unsigned int shim_dma_s2mm_0_task_queue = 0x00009304; +// DMA Control Register S2MM Ch1 +const unsigned int shim_dma_s2mm_1_ctrl = 0x00009308; +// DMA Task Queue Insertion S2MM Ch1 (4-deep) +const unsigned int shim_dma_s2mm_1_task_queue = 0x0000930c; +// DMA Control Register MM2S Ch0 +const unsigned int shim_dma_mm2s_0_ctrl = 0x00009310; +// DMA Task Queue Insertion MM2S Ch0 (16-deep) +const unsigned int shim_dma_mm2s_0_task_queue = 0x00009314; +// DMA Control Register MM2S Ch1 +const unsigned int shim_dma_mm2s_1_ctrl = 0x00009318; +// DMA Task Queue Insertion MM2S Ch1 (16-deep) +const unsigned int shim_dma_mm2s_1_task_queue = 0x0000931c; +// DMA S2MM Status Register Ch0 +const unsigned int shim_dma_s2mm_status_0 = 0x00009320; +// DMA S2MM Status Register Ch1 +const unsigned int shim_dma_s2mm_status_1 = 0x00009324; +// DMA MM2S Status Register Ch0 +const unsigned int shim_dma_mm2s_status_0 = 0x00009328; +// DMA MM2S Status Register Ch1 +const unsigned int shim_dma_mm2s_status_1 = 0x0000932c; +// DMA S2MM Current Write Count Ch0 +const unsigned int shim_dma_s2mm_current_write_count_0 = 0x00009330; +// DMA S2MM Current Write Count Ch1 +const unsigned int shim_dma_s2mm_current_write_count_1 = 0x00009334; +// DMA S2MM FoT Count FIFO Pop Ch0 +const unsigned int shim_dma_s2mm_fot_count_fifo_pop_0 = 0x00009338; +// DMA S2MM FoT Count FIFO Pop Ch1 +const unsigned int shim_dma_s2mm_fot_count_fifo_pop_1 = 0x0000933c; +// DMA MM2S Response FIFO Parity Error Injection Ch0 (privileged) +const unsigned int shim_dma_mm2s_0_response_fifo_parity_error_injection = 0x00009340; +// DMA MM2S Response FIFO Parity Error Injection Ch1 (privileged) +const unsigned int shim_dma_mm2s_1_response_fifo_parity_error_injection = 0x00009344; +// DMA Pause (privileged) +const unsigned int shim_dma_pause = 0x00009348; +// Lock Request. 16kB address space: 0xC000 - 0xFFFC, Lock_Id [13:10], Acq_Rel (9), Change_Value [8:2] +const unsigned int shim_lock_request = 0x0000c000; +// Performance Counters 1-0 Start and Stop Events +const unsigned int shim_performance_control0 = 0x00031000; +const unsigned int shim_performance_start_stop_0_1 = 0x00031000; +// Performance Counters 1-0 Reset Events +const unsigned int shim_performance_control1 = 0x00031008; +const unsigned int shim_performance_reset_0_1 = 0x00031008; +// Performance Counters 3-2 Start and Stop Events +const unsigned int shim_performance_control2 = 0x0003100C; +const unsigned int shim_performance_start_stop_2_3 = 0x0003100C; +// Performance Counters 3-2 Reset Events +const unsigned int shim_performance_control3 = 0x00031010; +const unsigned int shim_performance_reset_2_3 = 0x00031010; +// Performance Counters 5-4 Start and Stop Events +const unsigned int shim_performance_control4 = 0x00031014; +const unsigned int shim_performance_start_stop_4_5 = 0x00031014; +// Performance Counters 5-4 Reset Events +const unsigned int shim_performance_control5 = 0x00031018; +const unsigned int shim_performance_reset_4_5 = 0x00031018; +// Performance Counter0 +const unsigned int shim_performance_counter0 = 0x00031020; +// Performance Counter1 +const unsigned int shim_performance_counter1 = 0x00031024; +// Performance Counter2 +const unsigned int shim_performance_counter2 = 0x00031028; +// Performance Counter3 +const unsigned int shim_performance_counter3 = 0x0003102C; +// Performance Counter4 +const unsigned int shim_performance_counter4 = 0x00031030; +// Performance Counter5 +const unsigned int shim_performance_counter5 = 0x00031034; +// Performance Counter0 Event Value. +const unsigned int shim_performance_counter0_event_value = 0x00031080; +// Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated +const unsigned int shim_performance_counter1_event_value = 0x00031084; +// Generate an internal event +const unsigned int shim_event_generate = 0x00034008; +// Control of which Internal Event to Broadcast0 +const unsigned int shim_event_broadcast_a_0 = 0x00034010; +// Control of which Internal Event to Broadcast1 +const unsigned int shim_event_broadcast_a_1 = 0x00034014; +// Control of which Internal Event to Broadcast2 +const unsigned int shim_event_broadcast_a_2 = 0x00034018; +// Control of which Internal Event to Broadcast3 +const unsigned int shim_event_broadcast_a_3 = 0x0003401c; +// Control of which Internal Event to Broadcast4 +const unsigned int shim_event_broadcast_a_4 = 0x00034020; +// Control of which Internal Event to Broadcast5 +const unsigned int shim_event_broadcast_a_5 = 0x00034024; +// Control of which Internal Event to Broadcast6 +const unsigned int shim_event_broadcast_a_6 = 0x00034028; +// Control of which Internal Event to Broadcast7 +const unsigned int shim_event_broadcast_a_7 = 0x0003402c; +// Control of which Internal Event to Broadcast8 +const unsigned int shim_event_broadcast_a_8 = 0x00034030; +// Control of which Internal Event to Broadcast9 +const unsigned int shim_event_broadcast_a_9 = 0x00034034; +// Control of which Internal Event to Broadcast10 +const unsigned int shim_event_broadcast_a_10 = 0x00034038; +// Control of which Internal Event to Broadcast11 +const unsigned int shim_event_broadcast_a_11 = 0x0003403c; +// Control of which Internal Event to Broadcast12 +const unsigned int shim_event_broadcast_a_12 = 0x00034040; +// Control of which Internal Event to Broadcast13 +const unsigned int shim_event_broadcast_a_13 = 0x00034044; +// Control of which Internal Event to Broadcast14 +const unsigned int shim_event_broadcast_a_14 = 0x00034048; +// Control of which Internal Event to Broadcast15 +const unsigned int shim_event_broadcast_a_15 = 0x0003404c; +// Set block of broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_set = 0x00034050; +// Clear block of broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_clr = 0x00034054; +// Current value of block for broadcast signals to South +const unsigned int shim_event_broadcast_a_block_south_value = 0x00034058; +// Set block of broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_set = 0x00034060; +// Clear block of broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_clr = 0x00034064; +// Current value of block for broadcast signals to West +const unsigned int shim_event_broadcast_a_block_west_value = 0x00034068; +// Set block of broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_set = 0x00034070; +// Clear block of broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_clr = 0x00034074; +// Current value of block for broadcast signals to North +const unsigned int shim_event_broadcast_a_block_north_value = 0x00034078; +// Set block of broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_set = 0x00034080; +// Clear block of broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_clr = 0x00034084; +// Current value of block for broadcast signals to East +const unsigned int shim_event_broadcast_a_block_east_value = 0x00034088; +// Control of Trace +const unsigned int shim_trace_control0 = 0x000340d0; +// Control of Trace: packet destination +const unsigned int shim_trace_control1 = 0x000340d4; +// Status of trace engine +const unsigned int shim_trace_status = 0x000340d8; +// Control of which Internal Event to Broadcast +const unsigned int shim_trace_event0 = 0x000340e0; +// Control of which Internal Event to Broadcast +const unsigned int shim_trace_event1 = 0x000340e4; +// Internal Timer Event Value. +const unsigned int shim_timer_trig_event_low_value = 0x000340f0; +// Internal Timer Event Value. +const unsigned int shim_timer_trig_event_high_value = 0x000340f4; +// Internal Timer Low part Value. +const unsigned int shim_timer_low = 0x000340f8; +// Internal Timer High part Value. +const unsigned int shim_timer_high = 0x000340fc; +// Internal event status register0 +const unsigned int shim_event_status0 = 0x00034200; +// Internal event status register1 +const unsigned int shim_event_status1 = 0x00034204; +// Internal event status register2 +const unsigned int shim_event_status2 = 0x00034208; +// Internal event status register3 +const unsigned int shim_event_status3 = 0x0003420c; +// Combo events input events +const unsigned int shim_combo_event_inputs = 0x00034400; +// Combo events input events +const unsigned int shim_combo_event_control = 0x00034404; +// Event enable for DMA Group +const unsigned int shim_event_group_dma_enable = 0x00034504; +// Stream Switch Ports 0-3 for event generation +const unsigned int shim_stream_switch_event_port_selection_0 = 0x0003ff00; +// Stream Switch Ports 4-7 for event generation +const unsigned int shim_stream_switch_event_port_selection_1 = 0x0003ff04; + +// Register definitions for NPI +// ################################### +// Interrupt Status Register +const unsigned int npi_me_isr = 0x00000030; +// Interrupt Trigger Register +const unsigned int npi_me_itr = 0x00000034; +// Interrupt Mask Register +const unsigned int npi_me_imr0 = 0x00000038; +// Interrupte Enable Register +const unsigned int npi_me_ier0 = 0x0000003c; +// Interrupt Disable Register +const unsigned int npi_me_idr0 = 0x00000040; +// Interrupt Mask Register +const unsigned int npi_me_imr1 = 0x00000044; +// Interrupte Enable Register +const unsigned int npi_me_ier1 = 0x00000048; +// Interrupt Disable Register +const unsigned int npi_me_idr1 = 0x0000004c; +// Interrupt Mask Register +const unsigned int npi_me_imr2 = 0x00000050; +// Interrupte Enable Register +const unsigned int npi_me_ier2 = 0x00000054; +// Interrupt Disable Register +const unsigned int npi_me_idr2 = 0x00000058; +// Interrupt Mask Register +const unsigned int npi_me_imr3 = 0x0000005c; +// Interrupte Enable Register +const unsigned int npi_me_ier3 = 0x00000060; +// Interrupt Disable Register +const unsigned int npi_me_idr3 = 0x00000064; +// Interrupt Offset Register +const unsigned int npi_me_ior = 0x0000006c; +// Tells the status of the PLLs. Note: All Status Registers have no predefined Reset value. The value shown in reset is a typical value that will be read after reset. The actual value read can differ from this. +const unsigned int npi_me_pll_status = 0x0000010c; +// ME secure register +const unsigned int npi_me_secure_reg = 0x00000208; + +// Register definitions for UC +// ################################### +// Base address of uC module +const unsigned int uc_base_address = 0x00000000; +// Debug register access control and status +const unsigned int uc_mdm_dbg_ctrl_status = 0x000b0010; +// Debug register access data +const unsigned int uc_mdm_dbg_data = 0x000b0014; +// Debug register access lock +const unsigned int uc_mdm_dbg_lock = 0x000b0018; +// Microblaze Performance Counter Control +const unsigned int uc_mdm_pcctrlr = 0x000b5440; +// Microblaze Performance Counter Command +const unsigned int uc_mdm_pccmdr = 0x000b5480; +// Microblaze Performance Counter Status +const unsigned int uc_mdm_pcsr = 0x000b54c0; +// Microblaze Performance Counter Data Read +const unsigned int uc_mdm_pcdrr = 0x000b5580; +// Microblaze Performance Counter Data Write +const unsigned int uc_mdm_pcwr = 0x000b55c0; +// uC-Core status bits +const unsigned int uc_core_status = 0x000c0000; +// uC-Core control bits +const unsigned int uc_core_control = 0x000c0004; +// uC-Core external interrupts sticky bits +const unsigned int uc_core_interrupt_status = 0x000c0008; +// AXI-MM address offset +const unsigned int uc_module_aximm_offset = 0x000c0020; +// AXI-MM outstanding transactions monitors +const unsigned int uc_module_axi_mm_outstanding_transactions = 0x000c0024; +// Control of memory zeroization (privileged) +const unsigned int uc_memory_zeroization = 0x000c0030; +// Control of uC-PM, uC-Private-DM and uC-Core debug port privileged status (privileged) +const unsigned int uc_memory_privileged = 0x000c0034; +// uC-DM ECC scrubbing period (privileged) +const unsigned int uc_memory_dm_ecc_scrubbing_period = 0x000c0038; +// Inhibits ECC check bits update to uC-DM on writes (privileged) +const unsigned int uc_memory_dm_ecc_error_generation = 0x000c003c; +// MM2DM DMA Status +const unsigned int uc_dma_dm2mm_status = 0x000c0100; +// MM2DM DMA Control +const unsigned int uc_dma_dm2mm_control = 0x000c0104; +// MM2DM DMA External AXI Control +const unsigned int uc_dma_dm2mm_axi_control = 0x000c0108; +// DM2MM DMA Status +const unsigned int uc_dma_mm2dm_status = 0x000c0110; +// DM2MM DMA Control +const unsigned int uc_dma_mm2dm_control = 0x000c0114; +// DM2MM DMA External AXI Control +const unsigned int uc_dma_mm2dm_axi_control = 0x000c0118; +// DMA Pause (privileged) +const unsigned int uc_dma_pause = 0x000c0120; + +} // namespace aie2ps + +#endif /* AIE2PS_REGISTERS_H_ */ \ No newline at end of file diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/util/aie_debug_util.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/util/aie_debug_util.cpp new file mode 100644 index 00000000000..e69de29bb2d diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/util/aie_debug_util.h b/src/runtime_src/xdp/profile/plugin/aie_debug/util/aie_debug_util.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.cpp b/src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.cpp new file mode 100755 index 00000000000..8454d224284 --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.cpp @@ -0,0 +1,184 @@ +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#define XDP_PLUGIN_SOURCE + +#include "xdp/profile/plugin/aie_debug/ve2/aie_debug.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_metadata.h" +#include "xdp/profile/plugin/aie_debug/generations/aie1_attributes.h" +#include "xdp/profile/plugin/aie_debug/generations/aie1_registers.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2_attributes.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2_registers.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2ps_attributes.h" +#include "xdp/profile/plugin/aie_debug/generations/aie2ps_registers.h" + +#include +#include +#include + +#include "shim/shim.h" +#include "core/common/message.h" +#include "core/common/time.h" +#include "core/include/xrt/xrt_kernel.h" +//#include "core/common/api/bo_int.h" +//#include "core/common/api/hw_context_int.h" +#include "core/common/config_reader.h" +#include "core/include/experimental/xrt-next.h" + +#include "xdp/profile/database/static_info/aie_util.h" +#include "xdp/profile/database/database.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/plugin/vp_base/info.h" + +namespace { + static void* fetchAieDevInst(void* devHandle) + { + auto drv = aiarm::shim::handleCheck(devHandle); + if (!drv) + return nullptr ; + auto aieArray = drv->get_aie_array(); + if (!aieArray) + return nullptr; + return aieArray->get_dev(); + } + + static void* allocateAieDevice(void* devHandle) + { + auto aieDevInst = static_cast(fetchAieDevInst(devHandle)); + if (!aieDevInst) + return nullptr; + return new xaiefal::XAieDev(aieDevInst, false); + } + + static void deallocateAieDevice(void* aieDevice) + { + auto object = static_cast(aieDevice); + if (object != nullptr) + delete object; + } +} // end anonymous namespace + +namespace xdp { + using severity_level = xrt_core::message::severity_level; + using tile_type = xdp::tile_type; + using module_type = xdp::module_type; + + /**************************************************************************** + * Edge constructor + ***************************************************************************/ + AieDebug_VE2Impl::AieDebug_VE2Impl(VPDatabase* database, std::shared_ptr metadata) + : AieDebugImpl(database, metadata) + { + // Nothing to do + } + + /**************************************************************************** + * Edge destructor + ***************************************************************************/ + AieDebug_VE2Impl::~AieDebug_VE2Impl() { + // Nothing to do + } + + /**************************************************************************** + * Poll all registers + ***************************************************************************/ + void AieDebug_VE2Impl::poll(const uint64_t deviceID, void* handle) + { + xrt_core::message::send(severity_level::debug, "XRT", "Calling AIE Poll."); + + if (!(db->getStaticInfo().isDeviceReady(deviceID))) { + xrt_core::message::send(severity_level::debug, "XRT", + "Device is not ready, so no debug polling will occur."); + return; + } + + XAie_DevInst* aieDevInst = + static_cast(db->getStaticInfo().getAieDevInst(fetchAieDevInst, handle)); + if (!aieDevInst) { + xrt_core::message::send(severity_level::debug, "XRT", + "AIE device instance is not available, so no debug polling will occur."); + return; + } + + for (auto& tileAddr : debugTileMap) { + tileAddr.second->readValues(aieDevInst); + tileAddr.second->printValues(deviceID, db); + } + } + + /**************************************************************************** + * Update device + ***************************************************************************/ + void AieDebug_VE2Impl::updateDevice() + { + // Do nothing for now + } + + /**************************************************************************** + * Compile list of registers to read + ***************************************************************************/ + void AieDebug_VE2Impl::updateAIEDevice(void* handle) + { + if (!xrt_core::config::get_aie_debug()) + return; + XAie_DevInst* aieDevInst = + static_cast(db->getStaticInfo().getAieDevInst(fetchAieDevInst, handle)); + + std::unique_ptr debugPlugin; + auto regValues = metadata->getRegisterValues(); + + // Traverse all module types + int counterId = 0; + for (int module = 0; module < metadata->getNumModules(); ++module) { + auto configMetrics = metadata->getConfigMetricsVec(module); + if (configMetrics.empty()) + continue; + + module_type mod = metadata->getModuleType(module); + auto name = moduleTypes.at(mod); + + // List of registers to read for current module + auto& Regs = regValues[mod]; + if (Regs.empty()) + continue; + + if (aie::isDebugVerbosity()) { + std::stringstream msg; + msg << "AIE Debug monitoring tiles of type " << name << ":\n"; + for (auto& tileMetric : configMetrics) + msg << +tileMetric.first.col << "," << +tileMetric.first.row << " "; + xrt_core::message::send(severity_level::debug, "XRT", msg.str()); + } + + // Traverse all active and/or requested tiles + for (auto& tileMetric : configMetrics) { + //auto& metricSet = tileMetric.second; + auto tile = tileMetric.first; + auto tileOffset = XAie_GetTileAddr(aieDevInst, tile.row, tile.col); + + // Traverse all registers within tile + for (auto& regAddr : Regs) { + if (debugTileMap.find(tile) == debugTileMap.end()) + debugTileMap[tile] = std::make_unique(tile.col, tile.row, tileOffset); + + auto regName = metadata->lookupRegisterName(regAddr); + debugTileMap[tile]->addOffsetName(regAddr, regName); + } + } + } + } + +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.h b/src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.h new file mode 100755 index 00000000000..ddd3a820b41 --- /dev/null +++ b/src/runtime_src/xdp/profile/plugin/aie_debug/ve2/aie_debug.h @@ -0,0 +1,75 @@ +/** + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_H +#define AIE_DEBUG_H + +#include +#include + +#include "xdp/profile/plugin/aie_debug/aie_debug_impl.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/database/static_info/filetypes/base_filetype_impl.h" +#include "xdp/profile/plugin/vp_base/vp_base_plugin.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_plugin.h" + +#include "core/edge/common/aie_parser.h" +#include "xaiefal/xaiefal.hpp" + +extern "C" { + #include + #include +} + +namespace xdp { + class VE2ReadableTile; + + class AieDebug_VE2Impl : public AieDebugImpl { + public: + AieDebug_VE2Impl(VPDatabase* database, std::shared_ptr metadata); + ~AieDebug_VE2Impl(); + void updateDevice(); + void updateAIEDevice(void* handle); + void poll(const uint64_t index, void* handle); + + private: + + std::map> debugAddresses; + std::map> debugTileMap; + const std::vector falModuleTypes = { + XAIE_CORE_MOD, XAIE_MEM_MOD, XAIE_PL_MOD, XAIE_MEM_MOD}; + }; + + class VE2ReadableTile: public BaseReadableTile { + public: + VE2ReadableTile(uint8_t c, uint8_t r, uint64_t to) { + col = c; + row = r; + tileOffset = to; + } + + void readValues(XAie_DevInst* aieDevInst) { + for (auto& offset : relativeOffsets) { + uint32_t val = 0; + XAie_Read32(aieDevInst, offset + tileOffset, &val); + values.push_back(val); + } + } +}; + +} // end namespace xdp + +#endif diff --git a/src/runtime_src/xdp/profile/plugin/aie_profile/CMakeLists.txt b/src/runtime_src/xdp/profile/plugin/aie_profile/CMakeLists.txt index 57936864f35..3425eff152a 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_profile/CMakeLists.txt +++ b/src/runtime_src/xdp/profile/plugin/aie_profile/CMakeLists.txt @@ -4,7 +4,7 @@ # ==================================================================== # This builds the AIE Profile plugin. It is currently built -# on both Edge, x86, client and ve2 platforms that support AIE. +# on Edge, x86, Client, and VE2 platforms that support AIE. # ==================================================================== if (XDP_VE2_BUILD_CMAKE STREQUAL "yes") diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.cpp b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.cpp new file mode 100644 index 00000000000..47b8bbe5418 --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.cpp @@ -0,0 +1,105 @@ +/** + * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +#include +#include "xdp/profile/writer/aie_debug/aie_debug_writer.h" +#include "xdp/profile/database/database.h" +#include "xdp/profile/database/static_info/aie_constructs.h" +#include "xdp/profile/database/static_info/aie_util.h" +#include "xdp/profile/database/dynamic_event_database.h" +#include "xdp/profile/plugin/vp_base/utility.h" + +namespace xdp { + AIEDebugWriter::AIEDebugWriter(const char* fileName, const char* deviceName, uint64_t deviceIndex) + : VPWriter(fileName), mDeviceName(deviceName), mDeviceIndex(deviceIndex), mHeaderWritten(false) + { + mIsWritten = false; + } + + void AIEDebugWriter::writeHeader() + { + float fileVersion = 1.0; + + // Report HW generation to inform analysis how to interpret register addresses + auto aieGeneration = (db->getStaticInfo()).getAIEGeneration(mDeviceIndex); + + fout << "HEADER"<<"\n"; + fout << "File Version: " << fileVersion << "\n"; + fout << "Target device: " << mDeviceName << "\n"; + fout << "Hardware generation: " << static_cast(aieGeneration) << "\n"; + } + + void AIEDebugWriter::writerDataColumnHeader() + { + fout << "Register Values" << "\n"; + fout << "Column" << "," + << "Row" << "," + << "Register Name" << "," + << "Bit Range" << "," + << "Field Name" << "," + << "Value" << "\n"; + } + + bool AIEDebugWriter::write(bool /*openNewFile*/) + { + if (mIsWritten) + return true; + mIsWritten = true; + + if (!mHeaderWritten) { + this->writeHeader(); + this->writerDataColumnHeader(); + this->mHeaderWritten = true; + } + + // Getting all samples from database + std::vector samples = + db->getDynamicInfo().moveAIEDebugSamples(mDeviceIndex); + + // Create register interpreter for current AIE generation + auto aieGeneration = (db->getStaticInfo()).getAIEGeneration(mDeviceIndex); + std::unique_ptr regInterp = std::make_unique(mDeviceIndex, aieGeneration); + + for (auto& sample : samples) { + // Print out full 32-bit values (for debug purposes) + fout << +sample.col << "," + << +sample.row << "," + << sample.name << "," + << "31:0" << "," + << "full" << "," + << "0x" << std::hex << sample.value + << std::dec << "\n"; + + // Parse all fields from register value + auto regInfoVec = regInterp->registerInfo(sample.name, sample.offset, sample.value); + + // Report all fields + for (auto& rInfo : regInfoVec) { + if (rInfo.field_name == "") + continue; + + fout << +sample.col << "," + << +sample.row << "," + << sample.name << "," + << rInfo.bit_range << "," + << rInfo.field_name << "," + << rInfo.subval << "\n"; + } + } + + fout.flush(); + return true; + } +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.h b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.h new file mode 100644 index 00000000000..508753bc8e0 --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer.h @@ -0,0 +1,44 @@ +/** + * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +#ifndef AIE_DEBUG_WRITER_DOT_H +#define AIE_DEBUG_WRITER_DOT_H + +#include "xdp/profile/writer/vp_base/vp_writer.h" +#include "xdp/profile/plugin/aie_debug/aie_debug_plugin.h" +#include "xdp/profile/writer/aie_debug/register_interpreter.h" +#include + +namespace xdp { +class AIEDebugWriter : public VPWriter + { +public: + AIEDebugWriter(const char* fileName, const char* deviceName, uint64_t deviceIndex); + ~AIEDebugWriter()=default; + + void writeHeader(); + void writerDataColumnHeader(); + virtual bool write(bool openNewFile = true); + + private: + bool mIsWritten; + std::string mDeviceName; + uint64_t mDeviceIndex; + bool mHeaderWritten; + void* mHandle; + }; +} // end namespace xdp + +#endif diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie1_metadata.cpp b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie1_metadata.cpp new file mode 100644 index 00000000000..e31dddf44e9 --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie1_metadata.cpp @@ -0,0 +1,1491 @@ +// ####################################################################### +// Copyright (c) 2024 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#include "xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h" + +namespace xdp { + +/************************************************************************************* + * AIE1 Registers + *************************************************************************************/ +void AIE1WriterUsedRegisters::populateRegDataMap() { + regDataMap["cm_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["cm_core_cb0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cb7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_ch0"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch1"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch2"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch3"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch4"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch5"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch6"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_ch7"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl0"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl1"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl2"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl3"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl4"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl5"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl6"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cl7"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_cs0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_cs7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_control"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_control"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["cm_core_fc"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_lc"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_le"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_lr"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_ls"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_mc0"].push_back(RegData("Carry", "0", 0, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("SS0_tlast", "1", 1, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("UPS_sat", "10", 10, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("reserved", "15:11", 11, 0x1F)); + regDataMap["cm_core_mc0"].push_back(RegData("SS1_tlast", "2", 2, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("Floating_Add_exceptions", "23:16", 16, 0xFF)); + regDataMap["cm_core_mc0"].push_back(RegData("WSS0_tlast", "3", 3, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("Floating_Mul_exceptions", "31:24", 24, 0xFF)); + regDataMap["cm_core_mc0"].push_back(RegData("WSS1_tlast", "4", 4, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("SS0_nb_sc", "5", 5, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("SS1_nb_sc", "6", 6, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("MS0_nb_sc", "7", 7, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("MS1_nb_sc", "8", 8, 0x1)); + regDataMap["cm_core_mc0"].push_back(RegData("SRS_sat", "9", 9, 0x1)); + regDataMap["cm_core_mc1"].push_back(RegData("Fx2fl_Cnv_exceptions", "15:8", 8, 0xFF)); + regDataMap["cm_core_mc1"].push_back(RegData("Fl2Fx_Cnv_exceptions", "23:16", 16, 0xFF)); + regDataMap["cm_core_mc1"].push_back(RegData("reserved", "31:24", 24, 0xFF)); + regDataMap["cm_core_mc1"].push_back(RegData("Nlf_exceptions", "7:0", 0, 0xFF)); + regDataMap["cm_core_md0"].push_back(RegData("Saturation_Select", "0", 0, 0x1)); + regDataMap["cm_core_md0"].push_back(RegData("mdMS", "11:10", 10, 0x3)); + regDataMap["cm_core_md0"].push_back(RegData("reserved", "15:12", 12, 0xF)); + regDataMap["cm_core_md0"].push_back(RegData("Floating_Add_Mask", "23:16", 16, 0xFF)); + regDataMap["cm_core_md0"].push_back(RegData("Floating_Mul_Mask", "31:24", 24, 0xFF)); + regDataMap["cm_core_md0"].push_back(RegData("Round_Mode_Select", "3:1", 1, 0x7)); + regDataMap["cm_core_md0"].push_back(RegData("Radix_select", "6:4", 4, 0x7)); + regDataMap["cm_core_md0"].push_back(RegData("Symmetric_Saturation_Select", "7", 7, 0x1)); + regDataMap["cm_core_md0"].push_back(RegData("mdSS", "9:8", 8, 0x3)); + regDataMap["cm_core_md1"].push_back(RegData("Floating_Fixed_to_Float_Mask", "15:8", 8, 0xFF)); + regDataMap["cm_core_md1"].push_back(RegData("Floating_Float_to_Fixed_Mask", "23:16", 16, 0xFF)); + regDataMap["cm_core_md1"].push_back(RegData("reserved", "31:24", 24, 0xFF)); + regDataMap["cm_core_md1"].push_back(RegData("Floating_Non_Linear_Mask", "7:0", 0, 0xFF)); + regDataMap["cm_core_p0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_pc"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_r0"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r1"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r10"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r11"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r12"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r13"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r14"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r15"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r2"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r3"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r4"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r5"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r6"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r7"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r8"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r9"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_s0"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s1"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s2"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s3"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s4"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s5"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s6"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_s7"].push_back(RegData("Register_Value", "7:0", 0, 0xFF)); + regDataMap["cm_core_sp"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_status"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_SS0", "10", 10, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_SS1", "11", 11, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_MS0", "12", 12, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_MS1", "13", 13, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Cascade_Stall_SCD", "14", 14, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Cascade_Stall_MCD", "15", 15, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Debug_Halt", "16", 16, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("ECC_Error_Stall", "17", 17, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("ECC_Scrubbing_Stall", "18", 18, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Error_Halt", "19", 19, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_S", "2", 2, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("reserved", "20", 20, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_W", "3", 3, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_N", "4", 4, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_E", "5", 5, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_S", "6", 6, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_W", "7", 7, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_N", "8", 8, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_E", "9", 9, 0x1)); + regDataMap["cm_debug_control0"].push_back(RegData("Debug_Halt_Bit", "0", 0, 0x1)); + regDataMap["cm_debug_control0"].push_back(RegData("Single_Step_Count", "5:2", 2, 0xF)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_SingleStep_Core_Event", "14:8", 8, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Halt_Core_Event0", "22:16", 16, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Halt_Core_Event1", "30:24", 24, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Resume_Core_Event", "6:0", 0, 0x7F)); + regDataMap["cm_debug_control2"].push_back(RegData("PC_Event_Halt", "0", 0, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Memory_Stall_Halt", "1", 1, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Lock_Stall_Halt", "2", 2, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Stream_Stall_Halt", "3", 3, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_halted", "0", 0, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("PC_Event_halted", "1", 1, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Memory_Stall_Halted", "2", 2, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Lock_Stall_Halted", "3", 3, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Stream_stall_Halted", "4", 4, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_Event0_Halted", "5", 5, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_Event1_Halted", "6", 6, 0x1)); + regDataMap["cm_ecc_control"].push_back(RegData("Stall_Core_Control", "0", 0, 0x1)); + regDataMap["cm_ecc_control"].push_back(RegData("Unstall_Core", "1", 1, 0x1)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("Access_Type", "14", 14, 0x1)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("Clear_failing_address", "15", 15, 0x1)); + regDataMap["cm_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_number", "6:0", 0, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Disable_Event", "14:8", 8, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Disable_Event_occurred", "15", 15, 0x1)); + regDataMap["cm_enable_events"].push_back(RegData("Enable_Event", "6:0", 0, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Enable_Event_occurred", "7", 7, 0x1)); + regDataMap["cm_error_halt_control"].push_back(RegData("Error_Halt", "0", 0, 0x1)); + regDataMap["cm_error_halt_event"].push_back(RegData("Error_Halt_Core_Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast0"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast1"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast10"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast11"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast12"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast13"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast14"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast15"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast2"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast3"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast4"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast5"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast6"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast7"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast8"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast9"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt0", "2", 2, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt1", "3", 3, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt2", "4", 4, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt3", "5", 5, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_0", "6", 6, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_1", "7", 7, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_2", "8", 8, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_3", "9", 9, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_0", "0", 0, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_1", "1", 1, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_10", "10", 10, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_11", "11", 11, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_12", "12", 12, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_13", "13", 13, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_14", "14", 14, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_15", "15", 15, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_2", "2", 2, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_3", "3", 3, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_4", "4", 4, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_5", "5", 5, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_6", "6", 6, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_7", "7", 7, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_8", "8", 8, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_9", "9", 9, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Event_0", "0", 0, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Event_1", "1", 1, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Cascade_Put", "10", 10, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Lock_Acquire_req", "11", 11, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Lock_Release_req", "12", 12, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Call", "2", 2, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Return", "3", 3, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Vector", "4", 4, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Load", "5", 5, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Store", "6", 6, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Stream_Get", "7", 7, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Stream_Put", "8", 8, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Cascade_Get", "9", 9, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Memory_Stall", "0", 0, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Stream_Stall", "1", 1, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Cascade_Stall", "2", 2, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Lock_Stall", "3", 3, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Debug", "4", 4, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Active", "5", 5, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Disable", "6", 6, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("ECC_Scrubbing_Stall", "7", 7, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("ECC_Error_Stall", "8", 8, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("SRS_Saturate", "0", 0, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("UPS_Saturate", "1", 1, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("AXI_MM_Slave_Error", "10", 10, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instruction_Decompression_Error", "11", 11, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("DM_address_out_of_range", "12", 12, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_Scrub_Corrected", "13", 13, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_Scrub_2bit", "14", 14, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_1bit", "15", 15, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_2bit", "16", 16, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_address_out_of_range", "17", 17, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("DM_access_to_Unavailable", "18", 18, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Lock_Access_to_Unavailable", "19", 19, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Overflow", "2", 2, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instr_Warning", "20", 20, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instr_Error", "21", 21, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Underflow", "3", 3, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Invalid", "4", 4, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Div_by_Zero", "5", 5, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("TLAST_in_WSS_words_0_2", "6", 6, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_Reg_Access_Failure", "7", 7, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "8", 8, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Control_Pkt_Error", "9", 9, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("SRS_Saturate", "0", 0, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("UPS_Saturate", "1", 1, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("AXI_MM_Slave_Error", "10", 10, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instruction_Decompression_Error", "11", 11, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("DM_address_out_of_range", "12", 12, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_Scrub_Corrected", "13", 13, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_Scrub_2bit", "14", 14, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_1bit", "15", 15, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_2bit", "16", 16, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_address_out_of_range", "17", 17, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("DM_access_to_Unavailable", "18", 18, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Lock_Access_to_Unavailable", "19", 19, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Overflow", "2", 2, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instr_Warning", "20", 20, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instr_Error", "21", 21, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Underflow", "3", 3, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Invalid", "4", 4, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Div_by_Zero", "5", 5, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("TLAST_in_WSS_words_0_2", "6", 6, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_Reg_Access_Failure", "7", 7, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "8", 8, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Control_Pkt_Error", "9", 9, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_0", "0", 0, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_1", "1", 1, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_2", "2", 2, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_3", "3", 3, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_Range_0_1", "4", 4, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_Range_2_3", "5", 5, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["cm_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_pc_event0"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event1"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event2"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event2"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event3"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event3"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter0_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter1"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter1_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter2"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter2_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter3"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter3_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_ctrl0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_ctrl0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_ctrl0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_ctrl0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_ctrl1"].push_back(RegData("Cnt2_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_ctrl1"].push_back(RegData("Cnt3_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_ctrl1"].push_back(RegData("Cnt3_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_ctrl1"].push_back(RegData("Cnt2_Start_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_ctrl2"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_ctrl2"].push_back(RegData("Cnt2_Reset_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_ctrl2"].push_back(RegData("Cnt3_Reset_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_ctrl2"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["cm_reserved0"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_reserved1"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_reserved2"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_reserved3"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_reset_event"].push_back(RegData("Reset_Event", "6:0", 0, 0x7F)); + regDataMap["cm_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["cm_stream_switch_master_config_dma0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_dma0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_dma0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_dma0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_dma1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_dma1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_dma1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_dma1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_east0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_east0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_east0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_east0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_east1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_east1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_east1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_east1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_east2"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_east2"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_east2"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_east2"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_east3"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_east3"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_east3"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_east3"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_fifo0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_fifo0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_fifo0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_fifo0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_fifo1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_fifo1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_fifo1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_fifo1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_me_core0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_me_core0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_me_core0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_me_core0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_me_core1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_me_core1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_me_core1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_me_core1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_north0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_north0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_north0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_north0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_north1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_north1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_north1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_north1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_north2"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_north2"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_north2"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_north2"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_north3"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_north3"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_north3"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_north3"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_north4"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_north4"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_north4"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_north4"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_north5"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_north5"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_north5"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_north5"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_south0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_south0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_south0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_south0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_south1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_south1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_south1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_south1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_south2"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_south2"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_south2"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_south2"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_south3"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_south3"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_south3"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_south3"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_tile_ctrl"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_tile_ctrl"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_tile_ctrl"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_tile_ctrl"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_west0"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_west0"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_west0"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_west0"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_west1"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_west1"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_west1"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_west1"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_west2"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_west2"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_west2"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_west2"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_stream_switch_master_config_west3"].push_back(RegData("Packet_Enable", "30", 30, 0x1)); + regDataMap["cm_stream_switch_master_config_west3"].push_back(RegData("Master_Enable", "31", 31, 0x1)); + regDataMap["cm_stream_switch_master_config_west3"].push_back(RegData("Configuration", "6:0", 0, 0x7F)); + regDataMap["cm_stream_switch_master_config_west3"].push_back(RegData("Drop_Header", "7", 7, 0x1)); + regDataMap["cm_tile_clock_control"].push_back(RegData("Clock_Buffer_Enable", "0", 0, 0x1)); + regDataMap["cm_tile_clock_control"].push_back(RegData("Next_Tile_Clock_Enable", "1", 1, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["cm_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["cm_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["cm_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_trace_control0"].push_back(RegData("Mode", "1:0", 0, 0x3)); + regDataMap["cm_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["cm_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["cm_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["cm_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock0_State", "0", 0, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock0_Value", "1", 1, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock5_State", "10", 10, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock5_Value", "11", 11, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock6_State", "12", 12, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock6_Value", "13", 13, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock7_State", "14", 14, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock7_Value", "15", 15, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock8_State", "16", 16, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock8_Value", "17", 17, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock9_State", "18", 18, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock9_Value", "19", 19, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock1_State", "2", 2, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock10_State", "20", 20, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock10_Value", "21", 21, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock11_State", "22", 22, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock11_Value", "23", 23, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock12_State", "24", 24, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock12_Value", "25", 25, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock13_State", "26", 26, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock13_Value", "27", 27, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock14_State", "28", 28, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock14_Value", "29", 29, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock1_Value", "3", 3, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock15_State", "30", 30, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock15_Value", "31", 31, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock2_State", "4", 4, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock2_Value", "5", 5, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock3_State", "6", 6, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock3_Value", "7", 7, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock4_State", "8", 8, 0x1)); + regDataMap["mm_all_lock_state_value"].push_back(RegData("Lock4_Value", "9", 9, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane0", "0", 0, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane1", "1", 1, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane2", "2", 2, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane3", "3", 3, 0x1)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["mm_dma_fifo_counter"].push_back(RegData("Counter0", "12:0", 0, 0x1FFF)); + regDataMap["mm_dma_fifo_counter"].push_back(RegData("Counter1", "28:16", 16, 0x1FFF)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Start_Queue_Size_1", "11:9", 9, 0x7)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Cur_BD_0", "19:16", 16, 0xF)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Stat0", "1:0", 0, 0x3)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Cur_BD_1", "23:20", 20, 0xF)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Start_Queue_Overflow_0", "28", 28, 0x1)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Start_Queue_Overflow_1", "29", 29, 0x1)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Stat1", "3:2", 2, 0x3)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Lock_stalled0", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Lock_stalled1", "5", 5, 0x1)); + regDataMap["mm_dma_mm2s_status"].push_back(RegData("Start_Queue_Size_0", "8:6", 6, 0x7)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Start_Queue_Size_1", "11:9", 9, 0x7)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Cur_BD_0", "19:16", 16, 0xF)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Stat0", "1:0", 0, 0x3)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Cur_BD_1", "23:20", 20, 0xF)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Start_Queue_Overflow_0", "28", 28, 0x1)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Start_Queue_Overflow_1", "29", 29, 0x1)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Stat1", "3:2", 2, 0x3)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Lock_stalled0", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Lock_stalled1", "5", 5, 0x1)); + regDataMap["mm_dma_s2mm_status"].push_back(RegData("Start_Queue_Size_0", "8:6", 6, 0x7)); + regDataMap["mm_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "13:0", 0, 0x3FFF)); + regDataMap["mm_ecc_failing_address"].push_back(RegData("Valid", "15", 15, 0x1)); + regDataMap["mm_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_number", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast0"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast1"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast10"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast11"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast12"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast13"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast14"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast15"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast2"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast3"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast4"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast5"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast6"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast7"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast8"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast9"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Perf_Cnt0_Event", "2", 2, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Perf_Cnt1_Event", "3", 3, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_0", "4", 4, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_1", "5", 5, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_2", "6", 6, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_3", "7", 7, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_0", "0", 0, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_1", "1", 1, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_10", "10", 10, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_11", "11", 11, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_12", "12", 12, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_13", "13", 13, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_14", "14", 14, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_15", "15", 15, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_2", "2", 2, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_3", "3", 3, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_4", "4", 4, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_5", "5", 5, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_6", "6", 6, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_7", "7", 7, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_8", "8", 8, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_9", "9", 9, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_start_BD", "0", 0, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_start_BD", "1", 1, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_go_to_idle", "10", 10, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_go_to_idle", "11", 11, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_memory_conflict", "16", 16, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_memory_conflict", "17", 17, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_memory_conflict", "18", 18, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_memory_conflict", "19", 19, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_start_BD", "2", 2, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_start_BD", "3", 3, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_go_to_idle", "8", 8, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_go_to_idle", "9", 9, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_Corrected", "0", 0, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_2bit", "1", 1, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_S2MM_0_Error", "10", 10, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_S2MM_1_Error", "11", 11, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_MM2S_0_Error", "12", 12, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_MM2S_1_Error", "13", 13, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_1bit", "2", 2, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_2bit", "3", 3, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_2", "4", 4, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_3", "5", 5, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_4", "6", 6, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_5", "7", 7, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_6", "8", 8, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_7", "9", 9, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_0_Acquired", "0", 0, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_0_Release", "1", 1, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_5_Acquired", "10", 10, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_5_Release", "11", 11, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_6_Acquired", "12", 12, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_6_Release", "13", 13, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_7_Acquired", "14", 14, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_7_Release", "15", 15, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_8_Acquired", "16", 16, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_8_Release", "17", 17, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_9_Acquired", "18", 18, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_9_Release", "19", 19, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_1_Acquired", "2", 2, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_10_Acquired", "20", 20, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_10_Release", "21", 21, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_11_Acquired", "22", 22, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_11_Release", "23", 23, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_12_Acquired", "24", 24, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_12_Release", "25", 25, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_13_Acquired", "26", 26, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_13_Release", "27", 27, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_14_Acquired", "28", 28, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_14_Release", "29", 29, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_1_Release", "3", 3, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_15_Acquired", "30", 30, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_15_Release", "31", 31, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_2_Acquired", "4", 4, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_2_Release", "5", 5, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_3_Acquired", "6", 6, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_3_Release", "7", 7, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_4_Acquired", "8", 8, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_4_Release", "9", 9, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_0", "0", 0, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_1", "1", 1, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_2", "2", 2, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_3", "3", 3, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_4", "4", 4, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_5", "5", 5, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_6", "6", 6, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_7", "7", 7, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["mm_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_0", "0", 0, 0x1)); + regDataMap["mm_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_1", "1", 1, 0x1)); + regDataMap["mm_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_lock0_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock0_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock0_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock0_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock0_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock0_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock10_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock10_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock10_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock10_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock10_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock10_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock11_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock11_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock11_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock11_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock11_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock11_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock12_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock12_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock12_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock12_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock12_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock12_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock13_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock13_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock13_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock13_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock13_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock13_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock14_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock14_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock14_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock14_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock14_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock14_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock15_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock15_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock15_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock15_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock15_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock15_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock1_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock1_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock1_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock1_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock1_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock1_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock2_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock2_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock2_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock2_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock2_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock2_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock3_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock3_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock3_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock3_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock3_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock3_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock4_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock4_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock4_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock4_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock4_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock4_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock5_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock5_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock5_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock5_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock5_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock5_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock6_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock6_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock6_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock6_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock6_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock6_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock7_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock7_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock7_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock7_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock7_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock7_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock8_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock8_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock8_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock8_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock8_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock8_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock9_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock9_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock9_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["mm_lock9_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock9_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock9_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_2_Release", "11:10", 10, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_3_Acquired", "13:12", 12, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_3_Release", "15:14", 14, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_4_Acquired", "17:16", 16, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_4_Release", "19:18", 18, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_0_Acquired", "1:0", 0, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_5_Acquired", "21:20", 20, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_5_Release", "23:22", 22, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_6_Acquired", "25:24", 24, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_6_Release", "27:26", 26, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_7_Acquired", "29:28", 28, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_7_Release", "31:30", 30, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_0_Release", "3:2", 2, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_1_Acquired", "5:4", 4, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_1_Release", "7:6", 6, 0x3)); + regDataMap["mm_lock_event_value_control_0"].push_back(RegData("Lock_2_Acquired", "9:8", 8, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_10_Release", "11:10", 10, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_11_Acquired", "13:12", 12, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_11_Release", "15:14", 14, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_12_Acquired", "17:16", 16, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_12_Release", "19:18", 18, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_8_Acquired", "1:0", 0, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_13_Acquired", "21:20", 20, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_13_Release", "23:22", 22, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_14_Acquired", "25:24", 24, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_14_Release", "27:26", 26, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_15_Acquired", "29:28", 28, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_15_Release", "31:30", 30, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_8_Release", "3:2", 2, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_9_Acquired", "5:4", 4, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_9_Release", "7:6", 6, 0x3)); + regDataMap["mm_lock_event_value_control_1"].push_back(RegData("Lock_10_Acquired", "9:8", 8, 0x3)); + regDataMap["mm_parity_failing_address"].push_back(RegData("Parity_Error_Detection_Address", "14:0", 0, 0x7FFF)); + regDataMap["mm_parity_failing_address"].push_back(RegData("Valid", "15", 15, 0x1)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_control1"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control1"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter0_event_value"].push_back(RegData("Counter0_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter1"].push_back(RegData("Counter1_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter1_event_value"].push_back(RegData("Counter1_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved0"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved1"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved2"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved3"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reset_control"].push_back(RegData("DMA_reset", "0", 0, 0x1)); + regDataMap["mm_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["mm_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["mm_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["mm_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["mm_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["mm_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mm_watchpoint0"].push_back(RegData("Address", "14:4", 4, 0x7FF)); + regDataMap["mm_watchpoint0"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mm_watchpoint0"].push_back(RegData("South_Access", "24", 24, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("West_Access", "25", 25, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("North_Access", "26", 26, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("East_Access", "27", 27, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("DMA_Access", "28", 28, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("AXI_Access", "29", 29, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("Write_Access", "30", 30, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("Read_Access", "31", 31, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Address", "14:4", 4, 0x7FF)); + regDataMap["mm_watchpoint1"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mm_watchpoint1"].push_back(RegData("South_Access", "24", 24, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("West_Access", "25", 25, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("North_Access", "26", 26, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("East_Access", "27", 27, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("DMA_Access", "28", 28, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("AXI_Access", "29", 29, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Write_Access", "30", 30, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Read_Access", "31", 31, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock0_State", "0", 0, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock0_Value", "1", 1, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock5_State", "10", 10, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock5_Value", "11", 11, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock6_State", "12", 12, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock6_Value", "13", 13, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock7_State", "14", 14, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock7_Value", "15", 15, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock8_State", "16", 16, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock8_Value", "17", 17, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock9_State", "18", 18, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock9_Value", "19", 19, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock1_State", "2", 2, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock10_State", "20", 20, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock10_Value", "21", 21, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock11_State", "22", 22, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock11_Value", "23", 23, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock12_State", "24", 24, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock12_Value", "25", 25, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock13_State", "26", 26, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock13_Value", "27", 27, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock14_State", "28", 28, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock14_Value", "29", 29, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock1_Value", "3", 3, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock15_State", "30", 30, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock15_Value", "31", 31, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock2_State", "4", 4, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock2_Value", "5", 5, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock3_State", "6", 6, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock3_Value", "7", 7, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock4_State", "8", 8, 0x1)); + regDataMap["shim_all_lock_state_value"].push_back(RegData("Lock4_Value", "9", 9, 0x1)); + regDataMap["shim_bisr_cache_ctrl"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_ctrl"].push_back(RegData("Clear", "4", 4, 0x1)); + regDataMap["shim_bisr_cache_data0"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data1"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data2"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data3"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_status"].push_back(RegData("Done", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_status"].push_back(RegData("Pass", "1", 1, 0x1)); + regDataMap["shim_bisr_test_data0"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data1"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data2"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data3"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("Control_Pkt_Error", "0", 0, 0x1)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_0_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_1_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Start_Queue_Size_1", "11:9", 9, 0x7)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Cur_BD_0", "19:16", 16, 0xF)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Status0", "1:0", 0, 0x3)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Cur_BD_1", "23:20", 20, 0xF)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("AXI_MM_Decode_Error_0", "24", 24, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("AXI_MM_Decode_Error_1", "25", 25, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("AXI_MM_Slave_Error_0", "26", 26, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("AXI_MM_Slave_Error_1", "27", 27, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Start_Queue_Overflow_0", "28", 28, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Start_Queue_Overflow_1", "29", 29, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Status1", "3:2", 2, 0x3)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Stalled0", "4", 4, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Stalled1", "5", 5, 0x1)); + regDataMap["shim_dma_mm2s_status"].push_back(RegData("Start_Queue_Size_0", "8:6", 6, 0x7)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_0_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_1_start_queue"].push_back(RegData("Start_BD", "3:0", 0, 0xF)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Start_Queue_Size_1", "11:9", 9, 0x7)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Cur_BD_0", "19:16", 16, 0xF)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Status0", "1:0", 0, 0x3)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Cur_BD_1", "23:20", 20, 0xF)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("AXI_MM_Decode_Error_0", "24", 24, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("AXI_MM_Decode_Error_1", "25", 25, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("AXI_MM_Slave_Error_0", "26", 26, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("AXI_MM_Slave_Error_1", "27", 27, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Start_Queue_Overflow_0", "28", 28, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Start_Queue_Overflow_1", "29", 29, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Status1", "3:2", 2, 0x3)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Stalled0", "4", 4, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Stalled1", "5", 5, 0x1)); + regDataMap["shim_dma_s2mm_status"].push_back(RegData("Start_Queue_Size_0", "8:6", 6, 0x7)); + regDataMap["shim_demux_config"].push_back(RegData("South5", "11:10", 10, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South2", "5:4", 4, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South3", "7:6", 6, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South4", "9:8", 8, 0x3)); + regDataMap["shim_event_broadcast0_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast10_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast11_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast12_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast13_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast14_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast15_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast1_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast2_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast3_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast4_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast5_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast6_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast7_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast8_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast9_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast_a_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Perf_Cnt0", "2", 2, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Perf_Cnt1", "3", 3, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_0", "4", 4, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_1", "5", 5, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_2", "6", 6, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_3", "7", 7, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_0", "0", 0, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_1", "1", 1, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_10", "10", 10, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_11", "11", 11, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_12", "12", 12, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_13", "13", 13, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_14", "14", 14, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_15", "15", 15, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_2", "2", 2, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_3", "3", 3, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_4", "4", 4, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_5", "5", 5, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_6", "6", 6, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_7", "7", 7, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_8", "8", 8, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_9", "9", 9, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_start_BD", "0", 0, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_start_BD", "1", 1, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_go_to_idle", "10", 10, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_go_to_idle", "11", 11, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_start_BD", "2", 2, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_start_BD", "3", 3, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_go_to_idle", "8", 8, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_go_to_idle", "9", 9, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Slave_Tile_Error", "0", 0, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("Control_Pkt_Error", "1", 1, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_MM2S_1_Error", "10", 10, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Decode_NSU_Error", "2", 2, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Slave_NSU_Error", "3", 3, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Unsupported_Traffic", "4", 4, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Unsecure_Access_in_Secure_Mode", "5", 5, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Byte_Strobe_Error", "6", 6, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_S2MM_0_Error", "7", 7, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_S2MM_1_Error", "8", 8, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_MM2S_0_Error", "9", 9, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_0_Acquired", "0", 0, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_0_Release", "1", 1, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_5_Acquired", "10", 10, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_5_Release", "11", 11, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_6_Acquired", "12", 12, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_6_Release", "13", 13, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_7_Acquired", "14", 14, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_7_Release", "15", 15, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_8_Acquired", "16", 16, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_8_Release", "17", 17, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_9_Acquired", "18", 18, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_9_Release", "19", 19, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_1_Acquired", "2", 2, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_10_Acquired", "20", 20, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_10_Release", "21", 21, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_11_Acquired", "22", 22, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_11_Release", "23", 23, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_12_Acquired", "24", 24, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_12_Release", "25", 25, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_13_Acquired", "26", 26, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_13_Release", "27", 27, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_14_Acquired", "28", 28, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_14_Release", "29", 29, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_1_Release", "3", 3, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_15_Acquired", "30", 30, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_15_Release", "31", 31, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_2_Acquired", "4", 4, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_2_Release", "5", 5, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_3_Acquired", "6", 6, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_3_Release", "7", 7, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_4_Acquired", "8", 8, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_4_Release", "9", 9, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["shim_event_group_user_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["shim_event_group_user_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["shim_event_group_user_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["shim_event_group_user_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["shim_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_clear"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_clear"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_disable_a"].push_back(RegData("Disable_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_disable_b"].push_back(RegData("Disable_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_enable_a"].push_back(RegData("Enable_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_enable_b"].push_back(RegData("Enable_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event1", "14:8", 8, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event2", "22:16", 16, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event3", "30:24", 24, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event0", "6:0", 0, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event1", "14:8", 8, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event2", "22:16", 16, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event3", "30:24", 24, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event0", "6:0", 0, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_no_a"].push_back(RegData("Irq_no_A", "3:0", 0, 0xF)); + regDataMap["shim_interrupt_controller_1st_level_irq_no_b"].push_back(RegData("Irq_no_B", "3:0", 0, 0xF)); + regDataMap["shim_interrupt_controller_1st_level_mask_a"].push_back(RegData("IRQ_Mask_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_mask_b"].push_back(RegData("IRQ_Mask_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_status_a"].push_back(RegData("Status_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_status_b"].push_back(RegData("Status_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_disable"].push_back(RegData("Disable_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_enable"].push_back(RegData("Enable_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_interrupt"].push_back(RegData("NoC_Interrupt", "1:0", 0, 0x3)); + regDataMap["shim_interrupt_controller_2nd_level_mask"].push_back(RegData("IRQ_Mask_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_status"].push_back(RegData("Status_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_lock0_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock0_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock0_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock0_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock0_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock0_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock10_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock10_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock10_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock10_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock10_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock10_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock11_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock11_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock11_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock11_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock11_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock11_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock12_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock12_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock12_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock12_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock12_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock12_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock13_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock13_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock13_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock13_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock13_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock13_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock14_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock14_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock14_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock14_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock14_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock14_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock15_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock15_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock15_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock15_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock15_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock15_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock1_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock1_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock1_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock1_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock1_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock1_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock2_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock2_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock2_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock2_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock2_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock2_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock3_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock3_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock3_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock3_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock3_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock3_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock4_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock4_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock4_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock4_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock4_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock4_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock5_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock5_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock5_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock5_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock5_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock5_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock6_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock6_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock6_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock6_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock6_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock6_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock7_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock7_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock7_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock7_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock7_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock7_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock8_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock8_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock8_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock8_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock8_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock8_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock9_acquire_nv"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock9_acquire_v0"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock9_acquire_v1"].push_back(RegData("Acquire_Done", "0", 0, 0x1)); + regDataMap["shim_lock9_release_nv"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock9_release_v0"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock9_release_v1"].push_back(RegData("Release_Done", "0", 0, 0x1)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_2_Release", "11:10", 10, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_3_Acquired", "13:12", 12, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_3_Release", "15:14", 14, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_4_Acquired", "17:16", 16, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_4_Release", "19:18", 18, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_0_Acquired", "1:0", 0, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_5_Acquired", "21:20", 20, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_5_Release", "23:22", 22, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_6_Acquired", "25:24", 24, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_6_Release", "27:26", 26, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_7_Acquired", "29:28", 28, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_7_Release", "31:30", 30, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_0_Release", "3:2", 2, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_1_Acquired", "5:4", 4, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_1_Release", "7:6", 6, 0x3)); + regDataMap["shim_lock_event_value_control_0"].push_back(RegData("Lock_2_Acquired", "9:8", 8, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_10_Release", "11:10", 10, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_11_Acquired", "13:12", 12, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_11_Release", "15:14", 14, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_12_Acquired", "17:16", 16, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_12_Release", "19:18", 18, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_8_Acquired", "1:0", 0, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_13_Acquired", "21:20", 20, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_13_Release", "23:22", 22, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_14_Acquired", "25:24", 24, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_14_Release", "27:26", 26, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_15_Acquired", "29:28", 28, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_15_Release", "31:30", 30, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_8_Release", "3:2", 2, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_9_Acquired", "5:4", 4, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_9_Release", "7:6", 6, 0x3)); + regDataMap["shim_lock_event_value_control_1"].push_back(RegData("Lock_10_Acquired", "9:8", 8, 0x3)); + regDataMap["shim_me_aximm_config"].push_back(RegData("Master_Sel", "0", 0, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("Slave_Sel", "1", 1, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("SLVERR_Block", "2", 2, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("DECERR_Block", "3", 3, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("reserved", "4", 4, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("reserved", "5", 5, 0x1)); + regDataMap["shim_me_shim_reset_enable"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_me_tile_column_reset"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_mux_config"].push_back(RegData("South3", "11:10", 10, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South6", "13:12", 12, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South7", "15:14", 14, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South2", "9:8", 8, 0x3)); + regDataMap["shim_noc_interface_me_to_noc_south2"].push_back(RegData("reserved", "21:10", 10, 0xFFF)); + regDataMap["shim_noc_interface_me_to_noc_south2"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_noc_interface_me_to_noc_south3"].push_back(RegData("reserved", "21:10", 10, 0xFFF)); + regDataMap["shim_noc_interface_me_to_noc_south3"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_noc_interface_me_to_noc_south4"].push_back(RegData("reserved", "21:10", 10, 0xFFF)); + regDataMap["shim_noc_interface_me_to_noc_south4"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_noc_interface_me_to_noc_south5"].push_back(RegData("reserved", "21:10", 10, 0xFFF)); + regDataMap["shim_noc_interface_me_to_noc_south5"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South2", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South4", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South5", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South6", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South7", "10", 10, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South6_South7_128_combine", "11", 11, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South0_South1_128_combine", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South2", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South3", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South2_South3_128_combine", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South4", "6", 6, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South5", "7", 7, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South4_South5_128_combine", "8", 8, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South6", "9", 9, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South2", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South3", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South4", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South5", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South6", "6", 6, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South7", "7", 7, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South0_South1_128_combine", "2", 2, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South2", "3", 3, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South3", "4", 4, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South2_South3_128_combine", "5", 5, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South4", "6", 6, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South5", "7", 7, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South4_South5_128_combine", "8", 8, 0x1)); + regDataMap["shim_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter0_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter1"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter1_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["shim_performance_ctrl1"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["shim_performance_ctrl1"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["shim_reserved0"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_reserved1"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_reserved2"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_reserved3"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["shim_tile_clock_control"].push_back(RegData("Clock_Buffer_Enable", "0", 0, 0x1)); + regDataMap["shim_tile_clock_control"].push_back(RegData("Next_Tile_Clock_Enable", "1", 1, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["shim_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["shim_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["shim_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["shim_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["shim_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["shim_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["shim_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["shim_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); +} + +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2_metadata.cpp b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2_metadata.cpp new file mode 100644 index 00000000000..598e3866626 --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2_metadata.cpp @@ -0,0 +1,2288 @@ +// ####################################################################### +// Copyright (c) 2024 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#include "xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h" + +namespace xdp { + +/************************************************************************************* + * AIE2 Registers + *************************************************************************************/ +void AIE2WriterUsedRegisters::populateRegDataMap() { + regDataMap["cm_accumulator_control"].push_back(RegData("Input", "0", 0, 0x1)); + regDataMap["cm_accumulator_control"].push_back(RegData("Output", "1", 1, 0x1)); + regDataMap["cm_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["cm_core_cr"].push_back(RegData("Float_MAC_Huge_Mask", "10", 10, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("MCD_Enable", "11", 11, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("SCD_Enable", "12", 12, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Vadd_Sign", "13", 13, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Unpack_Sign", "14", 14, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Pack_Sign", "15", 15, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("UPS_Sign", "16", 16, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("SRS_Sign", "17", 17, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Bfloat_to_Int_Zero_Mask", "18", 18, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("reserved", "19", 19, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Saturation_Mode", "1:0", 0, 0x3)); + regDataMap["cm_core_cr"].push_back(RegData("Bfloat_to_Int_Invalid_Mask", "20", 20, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Bfloat_to_Int_Tiny_Mask", "21", 21, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Bfloat_to_Int_Huge_Mask", "22", 22, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_to_Bfloat_Zero_Mask", "23", 23, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_to_Bfloat_Infinity_Mask", "24", 24, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_to_Bfloat_Invalid_Mask", "25", 25, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_to_Bfloat_Tiny_Mask", "26", 26, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_to_Bfloat_Huge_Mask", "27", 27, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Round_Mode", "5:2", 2, 0xF)); + regDataMap["cm_core_cr"].push_back(RegData("Float_MAC_Zero_Mask", "6", 6, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_MAC_Infinity_Mask", "7", 7, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_MAC_Invalid_Mask", "8", 8, 0x1)); + regDataMap["cm_core_cr"].push_back(RegData("Float_MAC_Tiny_Mask", "9", 9, 0x1)); + regDataMap["cm_core_control"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_control"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["cm_core_dc0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dp"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_fc"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_lc"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_le"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_lr"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_ls"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_pc"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_processor_bus"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_processor_bus"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["cm_core_r0"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r1"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r10"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r11"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r12"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r13"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r14"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r15"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r16"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r17"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r18"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r19"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r2"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r20"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r21"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r22"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r23"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r24"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r25"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r26"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r27"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r28"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r29"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r3"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r30"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r31"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r4"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r5"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r6"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r7"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r8"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r9"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_s0"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_s1"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_s2"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_s3"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_sp"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_sr"].push_back(RegData("Carry", "0", 0, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("SS0_Success", "1", 1, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_MAC_Tiny_Flag", "10", 10, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_MAC_Huge_Flag", "11", 11, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Bfloat_to_Int_Zero_Flag", "12", 12, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("reserved", "13", 13, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Bfloat_to_Int_Invalid_Flag", "14", 14, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Bfloat_to_Int_Tiny_Flag", "15", 15, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Bfloat_to_Int_Huge_Flag", "16", 16, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_to_Bfloat_Zero_Flag", "17", 17, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_to_Bfloat_Infinity_Flag", "18", 18, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_to_Bfloat_Invalid_Flag", "19", 19, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("SS0_Tlast", "2", 2, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_to_Bfloat_Tiny_Flag", "20", 20, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_to_Bfloat_Huge_Flag", "21", 21, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Sparse_Overflow", "22", 22, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("MS0_Success", "3", 3, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("SRS_Overflow", "4", 4, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("UPS_Overflow", "5", 5, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Compression_Underflow", "6", 6, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_MAC_Zero_Flag", "7", 7, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_MAC_Infinity_Flag", "8", 8, 0x1)); + regDataMap["cm_core_sr"].push_back(RegData("Float_MAC_Invalid_Flag", "9", 9, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_SS0", "10", 10, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_MS0", "12", 12, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Cascade_Stall_SCD", "14", 14, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Cascade_Stall_MCD", "15", 15, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Debug_Halt", "16", 16, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("ECC_Error_Stall", "17", 17, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("ECC_Scrubbing_Stall", "18", 18, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Error_Halt", "19", 19, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_S", "2", 2, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Core_Done", "20", 20, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Core_Processor_Bus_Stall", "21", 21, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_W", "3", 3, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_N", "4", 4, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_E", "5", 5, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_S", "6", 6, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_W", "7", 7, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_N", "8", 8, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_E", "9", 9, 0x1)); + regDataMap["cm_debug_control0"].push_back(RegData("Debug_Halt_Bit", "0", 0, 0x1)); + regDataMap["cm_debug_control0"].push_back(RegData("Single_Step_Count", "5:2", 2, 0xF)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_SingleStep_Core_Event", "14:8", 8, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Halt_Core_Event0", "22:16", 16, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Halt_Core_Event1", "30:24", 24, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Resume_Core_Event", "6:0", 0, 0x7F)); + regDataMap["cm_debug_control2"].push_back(RegData("PC_Event_Halt", "0", 0, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Memory_Stall_Halt", "1", 1, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Lock_Stall_Halt", "2", 2, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Stream_Stall_Halt", "3", 3, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_halted", "0", 0, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("PC_Event_halted", "1", 1, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Memory_Stall_Halted", "2", 2, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Lock_Stall_Halted", "3", 3, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Stream_stall_Halted", "4", 4, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_Event0_Halted", "5", 5, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_Event1_Halted", "6", 6, 0x1)); + regDataMap["cm_ecc_control"].push_back(RegData("Stall_Core_Control", "0", 0, 0x1)); + regDataMap["cm_ecc_control"].push_back(RegData("Unstall_Core", "1", 1, 0x1)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("Access_Type", "14", 14, 0x1)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("Clear_failing_address", "15", 15, 0x1)); + regDataMap["cm_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_number", "6:0", 0, 0x7F)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "22:16", 16, 0x7F)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "6:0", 0, 0x7F)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["cm_enable_events"].push_back(RegData("Disable_Event", "14:8", 8, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Disable_Event_occurred", "15", 15, 0x1)); + regDataMap["cm_enable_events"].push_back(RegData("Enable_Event", "6:0", 0, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Enable_Event_occurred", "7", 7, 0x1)); + regDataMap["cm_error_halt_control"].push_back(RegData("Error_Halt", "0", 0, 0x1)); + regDataMap["cm_error_halt_event"].push_back(RegData("Error_Halt_Core_Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast0"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast1"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast10"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast11"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast12"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast13"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast14"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast15"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast2"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast3"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast4"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast5"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast6"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast7"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast8"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast9"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "10", 10, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "11", 11, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt0", "2", 2, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt1", "3", 3, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt2", "4", 4, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt3", "5", 5, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_0", "6", 6, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_1", "7", 7, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_2", "8", 8, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_3", "9", 9, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_0", "0", 0, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_1", "1", 1, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_10", "10", 10, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_11", "11", 11, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_12", "12", 12, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_13", "13", 13, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_14", "14", 14, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_15", "15", 15, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_2", "2", 2, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_3", "3", 3, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_4", "4", 4, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_5", "5", 5, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_6", "6", 6, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_7", "7", 7, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_8", "8", 8, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_9", "9", 9, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Event_0", "0", 0, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Event_1", "1", 1, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Cascade_Put", "10", 10, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Lock_Acquire_req", "11", 11, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Lock_Release_req", "12", 12, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Call", "2", 2, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Return", "3", 3, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Vector", "4", 4, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Load", "5", 5, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Store", "6", 6, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Stream_Get", "7", 7, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Stream_Put", "8", 8, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Cascade_Get", "9", 9, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Memory_Stall", "0", 0, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Stream_Stall", "1", 1, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Cascade_Stall", "2", 2, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Lock_Stall", "3", 3, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Debug", "4", 4, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Active", "5", 5, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Disable", "6", 6, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("ECC_Scrubbing_Stall", "7", 7, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("ECC_Error_Stall", "8", 8, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("SRS_Overflow", "0", 0, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("UPS_Overflow", "1", 1, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("AXI_MM_Slave_Error", "10", 10, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instruction_Decompression_Error", "11", 11, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("DM_address_out_of_range", "12", 12, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_Scrub_Corrected", "13", 13, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_Scrub_2bit", "14", 14, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_1bit", "15", 15, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_2bit", "16", 16, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_address_out_of_range", "17", 17, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("DM_access_to_Unavailable", "18", 18, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Lock_Access_to_Unavailable", "19", 19, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Huge", "2", 2, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instr_Warning", "20", 20, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instr_Error", "21", 21, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Decompression_underflow", "22", 22, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "23", 23, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Processor_Bus_Error", "24", 24, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Int_FP_Zero", "3", 3, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Invalid", "4", 4, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_INF", "5", 5, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("reserved0", "6", 6, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_Reg_Access_Failure", "7", 7, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "8", 8, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Control_Pkt_Error", "9", 9, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("SRS_Overflow", "0", 0, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("UPS_Overflow", "1", 1, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("AXI_MM_Slave_Error", "10", 10, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instruction_Decompression_Error", "11", 11, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("DM_address_out_of_range", "12", 12, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_Scrub_Corrected", "13", 13, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_Scrub_2bit", "14", 14, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_1bit", "15", 15, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_2bit", "16", 16, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_address_out_of_range", "17", 17, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("DM_access_to_Unavailable", "18", 18, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Lock_Access_to_Unavailable", "19", 19, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Huge", "2", 2, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instr_Warning", "20", 20, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instr_Error", "21", 21, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Decompression_underflow", "22", 22, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "23", 23, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Processor_Bus_Error", "24", 24, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Int_FP_Zero", "3", 3, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Invalid", "4", 4, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_INF", "5", 5, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("reserved0", "6", 6, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_Reg_Access_Failure", "7", 7, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "8", 8, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Control_Pkt_Error", "9", 9, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_0", "0", 0, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_1", "1", 1, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_2", "2", 2, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_3", "3", 3, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_Range_0_1", "4", 4, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_Range_2_3", "5", 5, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["cm_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_memory_control"].push_back(RegData("Memory_Zeroisation", "0", 0, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Stream_Switch_Clock_Enable", "0", 0, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Memory_Module_Clock_Enable", "1", 1, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Core_Module_Clock_Enable", "2", 2, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Stream_Switch_Adaptive_Clock_Gate", "4", 4, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("DMA_Adaptive_Clock_Gate", "5", 5, 0x1)); + regDataMap["cm_module_reset_control"].push_back(RegData("Stream_Switch_Reset", "0", 0, 0x1)); + regDataMap["cm_module_reset_control"].push_back(RegData("Memory_Module_Reset", "1", 1, 0x1)); + regDataMap["cm_module_reset_control"].push_back(RegData("Core_Module_Reset", "2", 2, 0x1)); + regDataMap["cm_pc_event0"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event1"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event2"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event2"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event3"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event3"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt2_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt3_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt3_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt2_Start_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt2_Reset_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt3_Reset_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter0_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter1"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter1_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter2"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter2_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter3"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter3_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_reset_event"].push_back(RegData("Reset_Event", "6:0", 0, 0x7F)); + regDataMap["cm_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["cm_stream_switch_adaptive_clock_gate_abort_period"].push_back(RegData("Abort_Period", "3:0", 0, 0xF)); + regDataMap["cm_stream_switch_adaptive_clock_gate_status"].push_back(RegData("Active", "0", 0, 0x1)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Core", "0", 0, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("DMA_0", "1", 1, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("DMA_1", "2", 2, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Tile_Control", "3", 3, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("AIE_Trace", "4", 4, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Mem_trace", "5", 5, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("Core", "0", 0, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("DMA_0", "1", 1, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("DMA_1", "2", 2, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("Tile_Control", "3", 3, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["cm_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["cm_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["cm_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_trace_control0"].push_back(RegData("Mode", "1:0", 0, 0x3)); + regDataMap["cm_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["cm_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["cm_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["cm_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane0", "0", 0, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane1", "1", 1, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane2", "2", 2, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane3", "3", 3, 0x1)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("reserved", "0", 0, 0x1)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("reserved", "0", 0, 0x1)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("reserved", "0", 0, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("reserved", "0", 0, 0x1)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_s2mm_current_write_count_0"].push_back(RegData("Current_Write_Count", "13:0", 0, 0x3FFF)); + regDataMap["mm_dma_s2mm_current_write_count_1"].push_back(RegData("Current_Write_Count", "13:0", 0, 0x3FFF)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mm_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "13:0", 0, 0x3FFF)); + regDataMap["mm_ecc_failing_address"].push_back(RegData("Valid", "15", 15, 0x1)); + regDataMap["mm_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_number", "6:0", 0, 0x7F)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "22:16", 16, 0x7F)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "6:0", 0, 0x7F)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["mm_event_broadcast0"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast1"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast10"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast11"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast12"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast13"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast14"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast15"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast2"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast3"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast4"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast5"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast6"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast7"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast8"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast9"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Perf_Cnt0_Event", "2", 2, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Perf_Cnt1_Event", "3", 3, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_0", "4", 4, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_1", "5", 5, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_2", "6", 6, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_3", "7", 7, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "8", 8, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "9", 9, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_0", "0", 0, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_1", "1", 1, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_10", "10", 10, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_11", "11", 11, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_12", "12", 12, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_13", "13", 13, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_14", "14", 14, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_15", "15", 15, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_2", "2", 2, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_3", "3", 3, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_4", "4", 4, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_5", "5", 5, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_6", "6", 6, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_7", "7", 7, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_8", "8", 8, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_9", "9", 9, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_start_task", "0", 0, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_start_task", "1", 1, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_finished_task", "10", 10, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_finished_task", "11", 11, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_stream_starvation", "16", 16, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_stream_starvation", "17", 17, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_memory_backpressure", "18", 18, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_memory_backpressure", "19", 19, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_start_task", "2", 2, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_stream_backpressure", "20", 20, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_stream_backpressure", "21", 21, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_memory_starvation", "22", 22, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_memory_starvation", "23", 23, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_start_task", "3", 3, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_finished_task", "8", 8, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_finished_task", "9", 9, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_Corrected", "0", 0, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_2bit", "1", 1, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_S2MM_0_Error", "10", 10, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_S2MM_1_Error", "11", 11, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_MM2S_0_Error", "12", 12, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_MM2S_1_Error", "13", 13, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("Lock_Error", "14", 14, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_Task_Token_Stall", "15", 15, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_1bit", "2", 2, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_2bit", "3", 3, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_2", "4", 4, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_3", "5", 5, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_4", "6", 6, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_5", "7", 7, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_6", "8", 8, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_7", "9", 9, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_eq", "24", 24, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_ge", "25", 25, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_rel", "26", 26, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_equal_to_value", "27", 27, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_eq", "28", 28, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_ge", "29", 29, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_rel", "30", 30, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_equal_to_value", "31", 31, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_0", "0", 0, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_1", "1", 1, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_2", "2", 2, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_3", "3", 3, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_4", "4", 4, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_5", "5", 5, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_6", "6", 6, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_7", "7", 7, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["mm_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_0", "0", 0, 0x1)); + regDataMap["mm_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_1", "1", 1, 0x1)); + regDataMap["mm_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_lock0_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock10_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock11_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock12_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock13_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock14_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock15_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock1_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock2_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock3_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock4_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock5_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock6_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock7_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock8_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock9_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock_request"].push_back(RegData("Request_Result", "0", 0, 0x1)); + regDataMap["mm_locks_event_selection_0"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_0"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_1"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_1"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_2"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_2"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_3"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_3"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_4"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_4"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_5"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_5"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_6"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_6"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_7"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_7"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_0", "0", 0, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_1", "1", 1, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_10", "10", 10, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_11", "11", 11, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_12", "12", 12, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_13", "13", 13, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_14", "14", 14, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_15", "15", 15, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_2", "2", 2, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_3", "3", 3, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_4", "4", 4, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_5", "5", 5, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_6", "6", 6, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_7", "7", 7, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_8", "8", 8, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_9", "9", 9, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_0", "0", 0, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_1", "1", 1, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_10", "10", 10, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_11", "11", 11, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_12", "12", 12, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_13", "13", 13, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_14", "14", 14, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_15", "15", 15, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_2", "2", 2, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_3", "3", 3, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_4", "4", 4, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_5", "5", 5, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_6", "6", 6, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_7", "7", 7, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_8", "8", 8, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_9", "9", 9, 0x1)); + regDataMap["mm_memory_control"].push_back(RegData("Memory_Zeroisation", "0", 0, 0x1)); + regDataMap["mm_parity_failing_address"].push_back(RegData("Parity_Error_Detection_Address", "15:0", 0, 0xFFFF)); + regDataMap["mm_parity_failing_address"].push_back(RegData("Valid", "16", 16, 0x1)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_control1"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control1"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter0_event_value"].push_back(RegData("Counter0_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter1"].push_back(RegData("Counter1_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter1_event_value"].push_back(RegData("Counter1_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved0"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved1"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved2"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_reserved3"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["mm_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["mm_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["mm_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["mm_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["mm_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mm_watchpoint0"].push_back(RegData("Address", "15:4", 4, 0xFFF)); + regDataMap["mm_watchpoint0"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mm_watchpoint0"].push_back(RegData("South_Access", "24", 24, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("West_Access", "25", 25, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("North_Access", "26", 26, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("East_Access", "27", 27, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("DMA_Access", "28", 28, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("AXI_Access", "29", 29, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("Write_Access", "30", 30, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("Read_Access", "31", 31, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Address", "15:4", 4, 0xFFF)); + regDataMap["mm_watchpoint1"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mm_watchpoint1"].push_back(RegData("South_Access", "24", 24, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("West_Access", "25", 25, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("North_Access", "26", 26, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("East_Access", "27", 27, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("DMA_Access", "28", 28, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("AXI_Access", "29", 29, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Write_Access", "30", 30, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Read_Access", "31", 31, 0x1)); + regDataMap["mem_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane0", "0", 0, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane1", "1", 1, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane2", "2", 2, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane3", "3", 3, 0x1)); + regDataMap["mem_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["mem_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["mem_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventB", "15:8", 8, 0xFF)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventC", "23:16", 16, 0xFF)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventD", "31:24", 24, 0xFF)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventA", "7:0", 0, 0xFF)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("S2MM_Sel1_Channel", "10:8", 8, 0x7)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("MM2S_Sel0_Channel", "18:16", 16, 0x7)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("MM2S_Sel1_Channel", "26:24", 24, 0x7)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("S2MM_Sel0_Channel", "2:0", 0, 0x7)); + regDataMap["mem_dma_mm2s_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_0_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_0_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_1_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_1_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_2_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_2_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_2_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_2_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_2_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_2_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_3_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_3_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_3_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_3_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_3_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_3_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_4_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_4_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_4_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_4_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_4_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_4_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_5_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_5_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_5_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_5_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_5_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_5_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_0_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_1_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_2_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_2_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_2_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_3_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_3_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_3_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_4_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_4_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_4_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_5_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_5_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_5_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_current_write_count_0"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_1"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_2"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_3"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_4"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_5"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "18:0", 0, 0x7FFFF)); + regDataMap["mem_ecc_failing_address"].push_back(RegData("Valid", "19", 19, 0x1)); + regDataMap["mem_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_Number", "7:0", 0, 0xFF)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "23:16", 16, 0xFF)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "7:0", 0, 0xFF)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["mem_event_broadcast0"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast1"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast10"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast11"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast12"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast13"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast14"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast15"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast2"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast3"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast4"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast5"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast6"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast7"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast8"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast9"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast_a_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_generate"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "10", 10, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "11", 11, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt0_Event", "2", 2, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt1_Event", "3", 3, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt2_Event", "4", 4, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt3_Event", "5", 5, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_0", "6", 6, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_1", "7", 7, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_2", "8", 8, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_3", "9", 9, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_0", "0", 0, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_1", "1", 1, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_10", "10", 10, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_11", "11", 11, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_12", "12", 12, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_13", "13", 13, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_14", "14", 14, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_15", "15", 15, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_2", "2", 2, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_3", "3", 3, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_4", "4", 4, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_5", "5", 5, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_6", "6", 6, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_7", "7", 7, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_8", "8", 8, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_9", "9", 9, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_start_task", "0", 0, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_start_task", "1", 1, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_finished_task", "10", 10, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_finished_task", "11", 11, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_stream_starvation", "16", 16, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_stream_starvation", "17", 17, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_stream_backpressure", "18", 18, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_stream_backpressure", "19", 19, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_start_task", "2", 2, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_memory_backpressure", "20", 20, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_memory_backpressure", "21", 21, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_memory_starvation", "22", 22, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_memory_starvation", "23", 23, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_start_task", "3", 3, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_finished_BD", "4", 4, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_finished_BD", "5", 5, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_finished_BD", "6", 6, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_finished_BD", "7", 7, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_finished_task", "8", 8, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_finished_task", "9", 9, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_Corrected", "0", 0, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_2bit", "1", 1, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Lock_Error", "10", 10, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DMA_Task_Token_Stall", "11", 11, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_1bit", "2", 2, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_2bit", "3", 3, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DMA_S2MM_Error", "4", 4, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DMA_MM2S_Error", "5", 5, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "6", 6, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "7", 7, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Control_Pkt_Error", "8", 8, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("AXI_MM_Slave_Error", "9", 9, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_eq", "24", 24, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_ge", "25", 25, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_rel", "26", 26, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_equal_to_value", "27", 27, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_eq", "28", 28, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_ge", "29", 29, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_rel", "30", 30, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_equal_to_value", "31", 31, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_0", "0", 0, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_1", "1", 1, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_10", "10", 10, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_11", "11", 11, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_12", "12", 12, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_13", "13", 13, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_14", "14", 14, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_15", "15", 15, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_2", "2", 2, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_3", "3", 3, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_4", "4", 4, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_5", "5", 5, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_6", "6", 6, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_7", "7", 7, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_8", "8", 8, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_9", "9", 9, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["mem_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["mem_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_0", "0", 0, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_1", "1", 1, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_2", "2", 2, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_3", "3", 3, 0x1)); + regDataMap["mem_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status4"].push_back(RegData("Event_159_128_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status5"].push_back(RegData("Event_191_160_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_lock0_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock10_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock11_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock12_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock13_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock14_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock15_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock16_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock17_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock18_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock19_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock1_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock20_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock21_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock22_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock23_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock24_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock25_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock26_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock27_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock28_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock29_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock2_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock30_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock31_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock32_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock33_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock34_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock35_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock36_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock37_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock38_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock39_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock3_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock40_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock41_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock42_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock43_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock44_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock45_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock46_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock47_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock48_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock49_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock4_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock50_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock51_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock52_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock53_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock54_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock55_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock56_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock57_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock58_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock59_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock5_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock60_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock61_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock62_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock63_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock6_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock7_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock8_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock9_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock_request"].push_back(RegData("Request_Result", "0", 0, 0x1)); + regDataMap["mem_locks_event_selection_0"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_0"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_1"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_1"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_2"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_2"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_3"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_3"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_4"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_4"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_5"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_5"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_6"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_6"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_7"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_7"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_0", "0", 0, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_1", "1", 1, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_10", "10", 10, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_11", "11", 11, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_12", "12", 12, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_13", "13", 13, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_14", "14", 14, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_15", "15", 15, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_16", "16", 16, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_17", "17", 17, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_18", "18", 18, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_19", "19", 19, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_2", "2", 2, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_20", "20", 20, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_21", "21", 21, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_22", "22", 22, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_23", "23", 23, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_24", "24", 24, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_25", "25", 25, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_26", "26", 26, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_27", "27", 27, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_28", "28", 28, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_29", "29", 29, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_3", "3", 3, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_30", "30", 30, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_31", "31", 31, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_4", "4", 4, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_5", "5", 5, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_6", "6", 6, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_7", "7", 7, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_8", "8", 8, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_9", "9", 9, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_32", "0", 0, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_33", "1", 1, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_42", "10", 10, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_43", "11", 11, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_44", "12", 12, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_45", "13", 13, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_46", "14", 14, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_47", "15", 15, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_48", "16", 16, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_49", "17", 17, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_50", "18", 18, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_51", "19", 19, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_34", "2", 2, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_52", "20", 20, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_53", "21", 21, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_54", "22", 22, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_55", "23", 23, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_56", "24", 24, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_57", "25", 25, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_58", "26", 26, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_59", "27", 27, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_60", "28", 28, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_61", "29", 29, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_35", "3", 3, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_62", "30", 30, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_63", "31", 31, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_36", "4", 4, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_37", "5", 5, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_38", "6", 6, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_39", "7", 7, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_40", "8", 8, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_41", "9", 9, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_0", "0", 0, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_1", "1", 1, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_10", "10", 10, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_11", "11", 11, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_12", "12", 12, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_13", "13", 13, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_14", "14", 14, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_15", "15", 15, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_16", "16", 16, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_17", "17", 17, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_18", "18", 18, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_19", "19", 19, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_2", "2", 2, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_20", "20", 20, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_21", "21", 21, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_22", "22", 22, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_23", "23", 23, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_24", "24", 24, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_25", "25", 25, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_26", "26", 26, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_27", "27", 27, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_28", "28", 28, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_29", "29", 29, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_3", "3", 3, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_30", "30", 30, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_31", "31", 31, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_4", "4", 4, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_5", "5", 5, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_6", "6", 6, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_7", "7", 7, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_8", "8", 8, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_9", "9", 9, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_32", "0", 0, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_33", "1", 1, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_42", "10", 10, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_43", "11", 11, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_44", "12", 12, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_45", "13", 13, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_46", "14", 14, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_47", "15", 15, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_48", "16", 16, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_49", "17", 17, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_50", "18", 18, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_51", "19", 19, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_34", "2", 2, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_52", "20", 20, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_53", "21", 21, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_54", "22", 22, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_55", "23", 23, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_56", "24", 24, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_57", "25", 25, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_58", "26", 26, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_59", "27", 27, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_60", "28", 28, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_61", "29", 29, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_35", "3", 3, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_62", "30", 30, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_63", "31", 31, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_36", "4", 4, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_37", "5", 5, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_38", "6", 6, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_39", "7", 7, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_40", "8", 8, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_41", "9", 9, 0x1)); + regDataMap["mem_memory_control"].push_back(RegData("Memory_Zeroisation", "0", 0, 0x1)); + regDataMap["mem_memory_control"].push_back(RegData("Memory_Interleaving", "1", 1, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("Stream_Switch_Clock_Enable", "0", 0, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("Memory_Module_Clock_Enable", "1", 1, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("Stream_Switch_Adaptive_Clock_Gate", "4", 4, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("DMA_Adaptive_Clock_Gate", "5", 5, 0x1)); + regDataMap["mem_module_reset_control"].push_back(RegData("Stream_Switch_Reset", "0", 0, 0x1)); + regDataMap["mem_module_reset_control"].push_back(RegData("Memory_Reset", "1", 1, 0x1)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt1_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt0_Start_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt2_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt3_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt3_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt2_Start_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt1_Reset_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt2_Reset_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt3_Reset_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt0_Reset_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter0_event_value"].push_back(RegData("Counter0_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter1"].push_back(RegData("Counter1_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter1_event_value"].push_back(RegData("Counter1_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter2"].push_back(RegData("Counter2_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter2_event_value"].push_back(RegData("Counter2_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter3"].push_back(RegData("Counter3_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter3_event_value"].push_back(RegData("Counter3_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_reserved0"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_reserved1"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_reserved2"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_reserved3"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["mem_stream_switch_adaptive_clock_gate_abort_period"].push_back(RegData("Abort_Period", "3:0", 0, 0xF)); + regDataMap["mem_stream_switch_adaptive_clock_gate_status"].push_back(RegData("Active", "0", 0, 0x1)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_0", "0", 0, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_1", "1", 1, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_2", "2", 2, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_3", "3", 3, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_4", "4", 4, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_5", "5", 5, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("Tile_Control", "6", 6, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("Mem_trace", "7", 7, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_0", "0", 0, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_1", "1", 1, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_2", "2", 2, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_3", "3", 3, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_4", "4", 4, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_5", "5", 5, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("Tile_Control", "6", 6, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["mem_timer_control"].push_back(RegData("Reset_Event", "15:8", 8, 0xFF)); + regDataMap["mem_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["mem_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_trace_control0"].push_back(RegData("Trace_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_trace_control0"].push_back(RegData("Trace_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["mem_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event1", "15:8", 8, 0xFF)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event2", "23:16", 16, 0xFF)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event3", "31:24", 24, 0xFF)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event0", "7:0", 0, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event5", "15:8", 8, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event6", "23:16", 16, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event7", "31:24", 24, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event4", "7:0", 0, 0xFF)); + regDataMap["mem_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["mem_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mem_watchpoint0"].push_back(RegData("Address", "18:4", 4, 0x7FFF)); + regDataMap["mem_watchpoint0"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mem_watchpoint0"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("Address", "18:4", 4, 0x7FFF)); + regDataMap["mem_watchpoint1"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mem_watchpoint1"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("Address", "18:4", 4, 0x7FFF)); + regDataMap["mem_watchpoint2"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mem_watchpoint2"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("Address", "18:4", 4, 0x7FFF)); + regDataMap["mem_watchpoint3"].push_back(RegData("WriteStrobes", "23:20", 20, 0xF)); + regDataMap["mem_watchpoint3"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["shim_bisr_cache_ctrl"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_ctrl"].push_back(RegData("Clear", "4", 4, 0x1)); + regDataMap["shim_bisr_cache_data0"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data1"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data2"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data3"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_status"].push_back(RegData("Done", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_status"].push_back(RegData("Pass", "1", 1, 0x1)); + regDataMap["shim_bisr_test_data0"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data1"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data2"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data3"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["shim_column_clock_control"].push_back(RegData("Clock_Buffer_Enable", "0", 0, 0x1)); + regDataMap["shim_column_reset_control"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_0_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_mm2s_0_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_mm2s_0_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_1_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_mm2s_1_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_mm2s_1_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_0_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_s2mm_0_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_0_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Pause_Mem", "1", 1, 0x1)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_1_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_s2mm_1_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_1_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_s2mm_current_write_count_0"].push_back(RegData("Current_Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_current_write_count_1"].push_back(RegData("Current_Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["shim_demux_config"].push_back(RegData("South5", "11:10", 10, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South2", "5:4", 4, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South3", "7:6", 6, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South4", "9:8", 8, 0x3)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "22:16", 16, 0x7F)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "6:0", 0, 0x7F)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["shim_event_broadcast0_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast10_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast11_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast12_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast13_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast14_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast15_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast1_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast2_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast3_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast4_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast5_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast6_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast7_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast8_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast9_a"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_broadcast_a_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Perf_Cnt0", "2", 2, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Perf_Cnt1", "3", 3, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_0", "4", 4, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_1", "5", 5, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_2", "6", 6, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_3", "7", 7, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "8", 8, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "9", 9, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_0", "0", 0, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_1", "1", 1, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_10", "10", 10, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_11", "11", 11, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_12", "12", 12, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_13", "13", 13, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_14", "14", 14, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_15", "15", 15, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_2", "2", 2, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_3", "3", 3, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_4", "4", 4, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_5", "5", 5, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_6", "6", 6, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_7", "7", 7, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_8", "8", 8, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_9", "9", 9, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_start_task", "0", 0, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_start_task", "1", 1, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_finished_task", "10", 10, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_finished_task", "11", 11, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_stream_starvation", "16", 16, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_stream_starvation", "17", 17, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_memory_backpressure", "18", 18, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_memory_backpressure", "19", 19, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_start_task", "2", 2, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_stream_backpressure", "20", 20, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_stream_backpressure", "21", 21, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_memory_starvation", "22", 22, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_memory_starvation", "23", 23, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_start_task", "3", 3, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_0_finished_task", "8", 8, 0x1)); + regDataMap["shim_event_group_dma_activity_enable"].push_back(RegData("DMA_S2MM_1_finished_task", "9", 9, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Slave_Tile_Error", "0", 0, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("Control_Pkt_Error", "1", 1, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("Lock_Error", "10", 10, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_Task_Token_Stall", "11", 11, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "2", 2, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Decode_NSU_Error", "3", 3, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Slave_NSU_Error", "4", 4, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Unsupported_Traffic", "5", 5, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Unsecure_Access_in_Secure_Mode", "6", 6, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Byte_Strobe_Error", "7", 7, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_S2MM_Error", "8", 8, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("DMA_MM2S_Error", "9", 9, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["shim_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["shim_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_clear"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_clear"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_disable_a"].push_back(RegData("Disable_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_disable_b"].push_back(RegData("Disable_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_enable_a"].push_back(RegData("Enable_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_enable_b"].push_back(RegData("Enable_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event1", "14:8", 8, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event2", "22:16", 16, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event3", "30:24", 24, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event0", "6:0", 0, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event1", "14:8", 8, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event2", "22:16", 16, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event3", "30:24", 24, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event0", "6:0", 0, 0x7F)); + regDataMap["shim_interrupt_controller_1st_level_irq_no_a"].push_back(RegData("Irq_no_A", "3:0", 0, 0xF)); + regDataMap["shim_interrupt_controller_1st_level_irq_no_b"].push_back(RegData("Irq_no_B", "3:0", 0, 0xF)); + regDataMap["shim_interrupt_controller_1st_level_mask_a"].push_back(RegData("IRQ_Mask_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_mask_b"].push_back(RegData("IRQ_Mask_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_status_a"].push_back(RegData("Status_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_status_b"].push_back(RegData("Status_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_disable"].push_back(RegData("Disable_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_enable"].push_back(RegData("Enable_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_interrupt"].push_back(RegData("NoC_Interrupt", "1:0", 0, 0x3)); + regDataMap["shim_interrupt_controller_2nd_level_mask"].push_back(RegData("IRQ_Mask_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_status"].push_back(RegData("Status_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_lock0_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock10_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock11_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock12_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock13_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock14_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock15_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock1_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock2_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock3_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock4_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock5_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock6_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock7_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock8_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock9_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock_request"].push_back(RegData("Request_Result", "0", 0, 0x1)); + regDataMap["shim_locks_event_selection_0"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_0"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_1"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_1"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_2"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_2"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_3"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_3"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_4"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_4"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_5"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_5"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_0", "0", 0, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_1", "1", 1, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_10", "10", 10, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_11", "11", 11, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_12", "12", 12, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_13", "13", 13, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_14", "14", 14, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_15", "15", 15, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_2", "2", 2, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_3", "3", 3, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_4", "4", 4, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_5", "5", 5, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_6", "6", 6, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_7", "7", 7, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_8", "8", 8, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_9", "9", 9, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_0", "0", 0, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_1", "1", 1, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_10", "10", 10, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_11", "11", 11, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_12", "12", 12, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_13", "13", 13, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_14", "14", 14, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_15", "15", 15, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_2", "2", 2, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_3", "3", 3, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_4", "4", 4, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_5", "5", 5, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_6", "6", 6, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_7", "7", 7, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_8", "8", 8, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_9", "9", 9, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("Master_Sel", "0", 0, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("Slave_Sel", "1", 1, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("SLVERR_Block", "2", 2, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("DECERR_Block", "3", 3, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("Stream_Switch_Clock_Enable", "0", 0, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("PL_Interface_Clock_Enable", "1", 1, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("CTE_Clock_Enable", "3", 3, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("Stream_Switch_Adaptive_Clock_Gate", "4", 4, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("DMA_Adaptive_Clock_Gate", "5", 5, 0x1)); + regDataMap["shim_module_clock_control_1"].push_back(RegData("NoC_Module_Clock_Enable", "0", 0, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("Stream_Switch_Reset", "0", 0, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("PL_Interface_Reset", "1", 1, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("CTE_Module_Reset", "3", 3, 0x1)); + regDataMap["shim_module_reset_control_1"].push_back(RegData("NoC_Module_Reset", "0", 0, 0x1)); + regDataMap["shim_mux_config"].push_back(RegData("South3", "11:10", 10, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South6", "13:12", 12, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South7", "15:14", 14, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South2", "9:8", 8, 0x3)); + regDataMap["shim_noc_interface_me_to_noc_south2"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_noc_interface_me_to_noc_south3"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_noc_interface_me_to_noc_south4"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_noc_interface_me_to_noc_south5"].push_back(RegData("Tdest", "9:0", 0, 0x3FF)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South2", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South4", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South5", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South6", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South7", "10", 10, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South6_South7_128_combine", "11", 11, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South0_South1_128_combine", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South2", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South3", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South2_South3_128_combine", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South4", "6", 6, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South5", "7", 7, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South4_South5_128_combine", "8", 8, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South6", "9", 9, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South2", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South3", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South4", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South5", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South6", "6", 6, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South7", "7", 7, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South0_South1_128_combine", "2", 2, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South2", "3", 3, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South3", "4", 4, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South2_South3_128_combine", "5", 5, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South4", "6", 6, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South5", "7", 7, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South4_South5_128_combine", "8", 8, 0x1)); + regDataMap["shim_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter0_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter1"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter1_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["shim_performance_ctrl1"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["shim_performance_ctrl1"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["shim_reserved0"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_reserved1"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_reserved2"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_reserved3"].push_back(RegData("reserved", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_stream_switch_adaptive_clock_gate_abort_period"].push_back(RegData("Abort_Period", "3:0", 0, 0xF)); + regDataMap["shim_stream_switch_adaptive_clock_gate_status"].push_back(RegData("Active", "0", 0, 0x1)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_0", "0", 0, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_1", "1", 1, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_2", "2", 2, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_3", "3", 3, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_4", "4", 4, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_5", "5", 5, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_6", "6", 6, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_7", "7", 7, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("Tile_Control", "8", 8, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("Shim_trace", "9", 9, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_0", "0", 0, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_1", "1", 1, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_2", "2", 2, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_3", "3", 3, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_4", "4", 4, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_5", "5", 5, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("Tile_Control", "6", 6, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["shim_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["shim_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["shim_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["shim_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["shim_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["shim_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["shim_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["shim_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); +} + +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2ps_metadata.cpp b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2ps_metadata.cpp new file mode 100644 index 00000000000..37dfc8518ae --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_aie2ps_metadata.cpp @@ -0,0 +1,2577 @@ +// ####################################################################### +// Copyright (c) 2024 AMD, Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. No part of +// this document may be photocopied, reproduced or translated to +// another program language without prior written consent of +// XILINX Inc., San Jose, CA. 95124 +// +// Xilinx, Inc. +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +/// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// ###################################################################### + +#include "xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h" + +namespace xdp { + +/************************************************************************************* + * AIE2PS Registers + *************************************************************************************/ +void AIE2PSWriterUsedRegisters::populateRegDataMap() { + regDataMap["cm_accumulator_control"].push_back(RegData("Input", "0", 0, 0x1)); + regDataMap["cm_accumulator_control"].push_back(RegData("Output", "1", 1, 0x1)); + regDataMap["cm_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["cm_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["cm_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_MAC_Huge_Mask", "10", 10, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("MCD_Enable", "11", 11, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("SCD_Enable", "12", 12, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Bfloat_to_Int_Zero_Mask", "18", 18, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Saturation_Mode", "1:0", 0, 0x3)); + regDataMap["cm_core_cr1"].push_back(RegData("Bfloat_to_Int_Invalid_Mask", "20", 20, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Bfloat_to_Int_Tiny_Mask", "21", 21, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Bfloat_to_Int_Huge_Mask", "22", 22, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_to_Bfloat_Zero_Mask", "23", 23, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_to_Bfloat_Infinity_Mask", "24", 24, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_to_Bfloat_Invalid_Mask", "25", 25, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_to_Bfloat_Tiny_Mask", "26", 26, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_to_Bfloat_Huge_Mask", "27", 27, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("UnpackSize", "28", 28, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("SRS_Mode", "29", 29, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("UPS_Mode", "30", 30, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("PackSize", "31", 31, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Round_Mode", "5:2", 2, 0xF)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_MAC_Zero_Mask", "6", 6, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_MAC_Infinity_Mask", "7", 7, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_MAC_Invalid_Mask", "8", 8, 0x1)); + regDataMap["cm_core_cr1"].push_back(RegData("Float_MAC_Tiny_Mask", "9", 9, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("Vadd_Sign0", "0", 0, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("Vadd_Sign1", "1", 1, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("BF8_Mode", "17:16", 16, 0x3)); + regDataMap["cm_core_cr2"].push_back(RegData("FP8_Mode", "19:18", 18, 0x3)); + regDataMap["cm_core_cr2"].push_back(RegData("Unpack_Sign0", "2", 2, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("FP_Conv_Sat", "21:20", 20, 0x3)); + regDataMap["cm_core_cr2"].push_back(RegData("Unpack_Sign1", "3", 3, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("Pack_Sign0", "4", 4, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("Pack_Sign1", "5", 5, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("UPS_Sign0", "6", 6, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("UPS_Sign1", "7", 7, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("SRS_Sign0", "8", 8, 0x1)); + regDataMap["cm_core_cr2"].push_back(RegData("SRS_Sign1", "9", 9, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Float_to_Fix_Zero_Mask", "0", 0, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Fix_to_Float_Inexact_Mask", "13", 13, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Zero_Mask", "16", 16, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Infinity_Mask", "17", 17, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Invalid_Mask", "18", 18, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Tiny_Mask", "19", 19, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Float_to_Fix_Invalid_Mask", "2", 2, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Huge_Mask", "20", 20, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Inexact_Mask", "21", 21, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Reserved1_Mask", "22", 22, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Nlf_Reserved2_Mask", "23", 23, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Float_to_Bfp_Invalid_Mask", "26", 26, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Float_to_Fix_Inexact_Mask", "5", 5, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Float_to_Fix_Huge_Mask", "6", 6, 0x1)); + regDataMap["cm_core_cr3"].push_back(RegData("Fix_to_Float_Zero_Mask", "8", 8, 0x1)); + regDataMap["cm_core_control"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_control"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["cm_core_dc0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dc7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dj7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_dn7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_fc"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_lc"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_lci"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_le"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_lr"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_ls"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_m7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p0"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p1"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p2"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p3"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p4"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p5"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p6"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_p7"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_pc"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_processor_bus"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_processor_bus"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["cm_core_r0"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r1"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r10"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r11"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r12"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r13"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r14"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r15"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r16"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r17"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r18"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r19"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r2"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r20"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r21"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r22"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r23"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r24"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r25"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r26"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r27"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r28"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r29"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r3"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r30"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r31"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r4"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r5"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r6"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r7"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r8"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_r9"].push_back(RegData("Register_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_core_reset_defeature"].push_back(RegData("Core_Reset_Defeature", "0", 0, 0x1)); + regDataMap["cm_core_s0"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_s1"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_s2"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_s3"].push_back(RegData("Register_Value", "5:0", 0, 0x3F)); + regDataMap["cm_core_sp"].push_back(RegData("Register_Value", "19:0", 0, 0xFFFFF)); + regDataMap["cm_core_sr1"].push_back(RegData("Carry", "0", 0, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("SS0_Success", "1", 1, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_MAC_Tiny_Flag", "10", 10, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_MAC_Huge_Flag", "11", 11, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Bfloat_to_Int_Zero_Flag", "12", 12, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Bfloat_to_Int_Invalid_Flag", "14", 14, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Bfloat_to_Int_Tiny_Flag", "15", 15, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Bfloat_to_Int_Huge_Flag", "16", 16, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_to_Bfloat_Zero_Flag", "17", 17, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_to_Bfloat_Infinity_Flag", "18", 18, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_to_Bfloat_Invalid_Flag", "19", 19, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("SS0_Tlast", "2", 2, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_to_Bfloat_Tiny_Flag", "20", 20, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_to_Bfloat_Huge_Flag", "21", 21, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Sparse_Overflow", "22", 22, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Fifo_Overflow", "23", 23, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Fifo_Underflow", "24", 24, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_to_Bfp_Invalid_Flag", "27", 27, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("MS0_Success", "3", 3, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("SRS_Overflow", "4", 4, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("UPS_Overflow", "5", 5, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_MAC_Zero_Flag", "7", 7, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_MAC_Infinity_Flag", "8", 8, 0x1)); + regDataMap["cm_core_sr1"].push_back(RegData("Float_MAC_Invalid_Flag", "9", 9, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Float_to_Fix_Zero_Flag", "0", 0, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Fix_to_Float_Inexact_Flag", "13", 13, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Zero_Flag", "16", 16, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Infinity_Flag", "17", 17, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Invalid_Flag", "18", 18, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Tiny_Flag", "19", 19, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Float_to_Fix_Invalid_Flag", "2", 2, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Huge_Flag", "20", 20, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Inexact_Flag", "21", 21, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Reserved1_Flag", "22", 22, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Nlf_Reserved2_Flag", "23", 23, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Float_to_Fix_Inexact_Flag", "5", 5, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Float_to_Fix_Huge_Flag", "6", 6, 0x1)); + regDataMap["cm_core_sr2"].push_back(RegData("Fix_to_Float_Zero_Flag", "8", 8, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_SS0", "10", 10, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Stream_Stall_MS0", "12", 12, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Cascade_Stall_SCD", "14", 14, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Cascade_Stall_MCD", "15", 15, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Debug_Halt", "16", 16, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("ECC_Error_Stall", "17", 17, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("ECC_Scrubbing_Stall", "18", 18, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Error_Halt", "19", 19, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_S", "2", 2, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Core_Done", "20", 20, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Core_Processor_Bus_Stall", "21", 21, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_W", "3", 3, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_N", "4", 4, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Memory_Stall_E", "5", 5, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_S", "6", 6, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_W", "7", 7, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_N", "8", 8, 0x1)); + regDataMap["cm_core_status"].push_back(RegData("Lock_Stall_E", "9", 9, 0x1)); + regDataMap["cm_debug_control0"].push_back(RegData("Debug_Halt_Bit", "0", 0, 0x1)); + regDataMap["cm_debug_control0"].push_back(RegData("Single_Step_Count", "5:2", 2, 0xF)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_SingleStep_Core_Event", "14:8", 8, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Halt_Core_Event0", "22:16", 16, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Halt_Core_Event1", "30:24", 24, 0x7F)); + regDataMap["cm_debug_control1"].push_back(RegData("Debug_Resume_Core_Event", "6:0", 0, 0x7F)); + regDataMap["cm_debug_control2"].push_back(RegData("PC_Event_Halt", "0", 0, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Memory_Stall_Halt", "1", 1, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Lock_Stall_Halt", "2", 2, 0x1)); + regDataMap["cm_debug_control2"].push_back(RegData("Stream_Stall_Halt", "3", 3, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_halted", "0", 0, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("PC_Event_halted", "1", 1, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Memory_Stall_Halted", "2", 2, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Lock_Stall_Halted", "3", 3, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Stream_stall_Halted", "4", 4, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_Event0_Halted", "5", 5, 0x1)); + regDataMap["cm_debug_status"].push_back(RegData("Debug_Event1_Halted", "6", 6, 0x1)); + regDataMap["cm_ecc_control"].push_back(RegData("Stall_Core_Control", "0", 0, 0x1)); + regDataMap["cm_ecc_control"].push_back(RegData("Unstall_Core", "1", 1, 0x1)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("Access_Type", "14", 14, 0x1)); + regDataMap["cm_ecc_failing_address"].push_back(RegData("Clear_failing_address", "15", 15, 0x1)); + regDataMap["cm_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_number", "6:0", 0, 0x7F)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "22:16", 16, 0x7F)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "6:0", 0, 0x7F)); + regDataMap["cm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["cm_enable_events"].push_back(RegData("Disable_Event", "14:8", 8, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Disable_Event_occurred", "15", 15, 0x1)); + regDataMap["cm_enable_events"].push_back(RegData("Enable_Event", "6:0", 0, 0x7F)); + regDataMap["cm_enable_events"].push_back(RegData("Enable_Event_occurred", "7", 7, 0x1)); + regDataMap["cm_error_halt_control"].push_back(RegData("Error_Halt", "0", 0, 0x1)); + regDataMap["cm_error_halt_event"].push_back(RegData("Error_Halt_Core_Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast0"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast1"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast10"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast11"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast12"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast13"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast14"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast15"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast2"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast3"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast4"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast5"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast6"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast7"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast8"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast9"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_broadcast_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_broadcast_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["cm_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "10", 10, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "11", 11, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt0", "2", 2, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt1", "3", 3, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt2", "4", 4, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Perf_Cnt3", "5", 5, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_0", "6", 6, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_1", "7", 7, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_2", "8", 8, 0x1)); + regDataMap["cm_event_group_0_enable"].push_back(RegData("Combo_Event_3", "9", 9, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_0", "0", 0, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_1", "1", 1, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_10", "10", 10, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_11", "11", 11, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_12", "12", 12, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_13", "13", 13, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_14", "14", 14, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_15", "15", 15, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_2", "2", 2, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_3", "3", 3, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_4", "4", 4, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_5", "5", 5, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_6", "6", 6, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_7", "7", 7, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_8", "8", 8, 0x1)); + regDataMap["cm_event_group_broadcast_enable"].push_back(RegData("Broadcast_9", "9", 9, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Event_0", "0", 0, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Event_1", "1", 1, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Cascade_Put", "10", 10, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Lock_Acquire_req", "11", 11, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Lock_Release_req", "12", 12, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Call", "2", 2, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Return", "3", 3, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Vector", "4", 4, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Load", "5", 5, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Store", "6", 6, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Stream_Get", "7", 7, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Stream_Put", "8", 8, 0x1)); + regDataMap["cm_event_group_core_program_flow_enable"].push_back(RegData("Instr_Cascade_Get", "9", 9, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Memory_Stall", "0", 0, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Stream_Stall", "1", 1, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Cascade_Stall", "2", 2, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Lock_Stall", "3", 3, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Debug", "4", 4, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Active", "5", 5, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("Disable", "6", 6, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("ECC_Scrubbing_Stall", "7", 7, 0x1)); + regDataMap["cm_event_group_core_stall_enable"].push_back(RegData("ECC_Error_Stall", "8", 8, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("SRS_Overflow", "0", 0, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("UPS_Overflow", "1", 1, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("AXI_MM_Slave_Error", "10", 10, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instruction_Decompression_Error", "11", 11, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("DM_address_out_of_range", "12", 12, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_Scrub_Corrected", "13", 13, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_Scrub_2bit", "14", 14, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_1bit", "15", 15, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_ECC_Error_2bit", "16", 16, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_address_out_of_range", "17", 17, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("DM_access_to_Unavailable", "18", 18, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Lock_Access_to_Unavailable", "19", 19, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Huge", "2", 2, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instr_Warning", "20", 20, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Instr_Error", "21", 21, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Sparsity_Overflow", "22", 22, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "23", 23, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Processor_Bus_Error", "24", 24, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Int_FP_Zero", "3", 3, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_Invalid", "4", 4, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("FP_INF", "5", 5, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("reserved0", "6", 6, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("PM_Reg_Access_Failure", "7", 7, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "8", 8, 0x1)); + regDataMap["cm_event_group_errors0_enable"].push_back(RegData("Control_Pkt_Error", "9", 9, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("SRS_Overflow", "0", 0, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("UPS_Overflow", "1", 1, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("AXI_MM_Slave_Error", "10", 10, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instruction_Decompression_Error", "11", 11, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("DM_address_out_of_range", "12", 12, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_Scrub_Corrected", "13", 13, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_Scrub_2bit", "14", 14, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_1bit", "15", 15, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_ECC_Error_2bit", "16", 16, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_address_out_of_range", "17", 17, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("DM_access_to_Unavailable", "18", 18, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Lock_Access_to_Unavailable", "19", 19, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Huge", "2", 2, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instr_Warning", "20", 20, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Instr_Error", "21", 21, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Decompression_underflow", "22", 22, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "23", 23, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Processor_Bus_Error", "24", 24, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Int_FP_Zero", "3", 3, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_Invalid", "4", 4, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("FP_INF", "5", 5, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("reserved0", "6", 6, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("PM_Reg_Access_Failure", "7", 7, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "8", 8, 0x1)); + regDataMap["cm_event_group_errors1_enable"].push_back(RegData("Control_Pkt_Error", "9", 9, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_0", "0", 0, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_1", "1", 1, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_2", "2", 2, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_3", "3", 3, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_Range_0_1", "4", 4, 0x1)); + regDataMap["cm_event_group_pc_enable"].push_back(RegData("PC_Range_2_3", "5", 5, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["cm_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["cm_event_group_user_event_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["cm_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_memory_control"].push_back(RegData("Memory_Zeroisation", "0", 0, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Stream_Switch_Clock_Enable", "0", 0, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Memory_Module_Clock_Enable", "1", 1, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Core_Module_Clock_Enable", "2", 2, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("Ctrl_Pkt_Tlast_Error_Enable", "4", 4, 0x1)); + regDataMap["cm_module_clock_control"].push_back(RegData("DMA_Adaptive_Clock_Gate", "5", 5, 0x1)); + regDataMap["cm_module_reset_control"].push_back(RegData("Stream_Switch_Reset", "0", 0, 0x1)); + regDataMap["cm_module_reset_control"].push_back(RegData("Memory_Module_Reset", "1", 1, 0x1)); + regDataMap["cm_module_reset_control"].push_back(RegData("Core_Module_Reset", "2", 2, 0x1)); + regDataMap["cm_pc_event0"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event1"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event2"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event2"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_pc_event3"].push_back(RegData("PC_Address", "13:0", 0, 0x3FFF)); + regDataMap["cm_pc_event3"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_control0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt2_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt3_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt3_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_control1"].push_back(RegData("Cnt2_Start_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt2_Reset_Event", "22:16", 16, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt3_Reset_Event", "30:24", 24, 0x7F)); + regDataMap["cm_performance_control2"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["cm_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter0_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter1"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter1_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter2"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter2_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter3"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_performance_counter3_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_reset_event"].push_back(RegData("Reset_Event", "6:0", 0, 0x7F)); + regDataMap["cm_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["cm_spare_reg_privileged"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["cm_stream_switch_adaptive_clock_gate_abort_period"].push_back(RegData("Abort_Period", "3:0", 0, 0xF)); + regDataMap["cm_stream_switch_adaptive_clock_gate_status"].push_back(RegData("Active", "0", 0, 0x1)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["cm_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["cm_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Core_lower", "0", 0, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("DMA_0_lower", "1", 1, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Core_upper", "16", 16, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("DMA_0_upper", "17", 17, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("DMA_1_upper", "18", 18, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Tile_Control_upper", "19", 19, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("DMA_1_lower", "2", 2, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("AIE_Trace_upper", "20", 20, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Mem_trace_upper", "21", 21, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Tile_Control_lower", "3", 3, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("AIE_Trace_lower", "4", 4, 0x1)); + regDataMap["cm_stream_switch_parity_injection"].push_back(RegData("Mem_trace_lower", "5", 5, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("Core", "0", 0, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("DMA_0", "1", 1, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("DMA_1", "2", 2, 0x1)); + regDataMap["cm_stream_switch_parity_status"].push_back(RegData("Tile_Control", "3", 3, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["cm_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["cm_tile_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["cm_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["cm_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["cm_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["cm_trace_control0"].push_back(RegData("Mode", "1:0", 0, 0x3)); + regDataMap["cm_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["cm_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["cm_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["cm_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["cm_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["cm_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["cm_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["cm_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane0", "0", 0, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane1", "1", 1, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane2", "2", 2, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane3", "3", 3, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane4", "4", 4, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane5", "5", 5, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane6", "6", 6, 0x1)); + regDataMap["mm_checkbit_error_generation"].push_back(RegData("Lane7", "7", 7, 0x1)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["mm_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventB", "14:8", 8, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventC", "22:16", 16, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventD", "30:24", 24, 0x7F)); + regDataMap["mm_combo_event_inputs"].push_back(RegData("eventA", "6:0", 0, 0x7F)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_mm2s_0_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_mm2s_0_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_mm2s_1_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_mm2s_1_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_status_0"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mm_dma_mm2s_status_1"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_0_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_0_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_1_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_1_start_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["mm_dma_s2mm_current_write_count_0"].push_back(RegData("Current_Write_Count", "13:0", 0, 0x3FFF)); + regDataMap["mm_dma_s2mm_current_write_count_1"].push_back(RegData("Current_Write_Count", "13:0", 0, 0x3FFF)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mm_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_status_0"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mm_dma_s2mm_status_1"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mm_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "13:0", 0, 0x3FFF)); + regDataMap["mm_ecc_failing_address"].push_back(RegData("Valid", "15", 15, 0x1)); + regDataMap["mm_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_number", "6:0", 0, 0x7F)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "22:16", 16, 0x7F)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "6:0", 0, 0x7F)); + regDataMap["mm_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["mm_event_broadcast0"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast1"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast10"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast11"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast12"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast13"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast14"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast15"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast2"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast3"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast4"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast5"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast6"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast7"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast8"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast9"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_broadcast_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_broadcast_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mm_event_generate"].push_back(RegData("Event", "6:0", 0, 0x7F)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Perf_Cnt0_Event", "2", 2, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Perf_Cnt1_Event", "3", 3, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_0", "4", 4, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_1", "5", 5, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_2", "6", 6, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Combo_Event_3", "7", 7, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "8", 8, 0x1)); + regDataMap["mm_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "9", 9, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_0", "0", 0, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_1", "1", 1, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_10", "10", 10, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_11", "11", 11, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_12", "12", 12, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_13", "13", 13, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_14", "14", 14, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_15", "15", 15, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_2", "2", 2, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_3", "3", 3, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_4", "4", 4, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_5", "5", 5, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_6", "6", 6, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_7", "7", 7, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_8", "8", 8, 0x1)); + regDataMap["mm_event_group_broadcast_enable"].push_back(RegData("Broadcast_9", "9", 9, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_start_task", "0", 0, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_start_task", "1", 1, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_finished_task", "10", 10, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_finished_task", "11", 11, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_stream_starvation", "16", 16, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_stream_starvation", "17", 17, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_memory_backpressure", "18", 18, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_memory_backpressure", "19", 19, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_start_task", "2", 2, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_stream_backpressure", "20", 20, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_stream_backpressure", "21", 21, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_memory_starvation", "22", 22, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_memory_starvation", "23", 23, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_start_task", "3", 3, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_0_finished_task", "8", 8, 0x1)); + regDataMap["mm_event_group_dma_enable"].push_back(RegData("DMA_S2MM_1_finished_task", "9", 9, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_Corrected", "0", 0, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_2bit", "1", 1, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_S2MM_0_Error", "10", 10, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_S2MM_1_Error", "11", 11, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_MM2S_0_Error", "12", 12, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_MM2S_1_Error", "13", 13, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("Lock_Error", "14", 14, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DMA_Task_Token_Stall", "15", 15, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_1bit", "2", 2, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_ECC_Error_2bit", "3", 3, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_2", "4", 4, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_3", "5", 5, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_4", "6", 6, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_5", "7", 7, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_6", "8", 8, 0x1)); + regDataMap["mm_event_group_error_enable"].push_back(RegData("DM_Parity_Error_Bank_7", "9", 9, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_eq", "24", 24, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_ge", "25", 25, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_rel", "26", 26, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel6_equal_to_value", "27", 27, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_eq", "28", 28, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_ge", "29", 29, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_rel", "30", 30, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel7_equal_to_value", "31", 31, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["mm_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_0", "0", 0, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_1", "1", 1, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_2", "2", 2, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_3", "3", 3, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_4", "4", 4, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_5", "5", 5, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_6", "6", 6, 0x1)); + regDataMap["mm_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_7", "7", 7, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_2", "2", 2, 0x1)); + regDataMap["mm_event_group_user_event_enable"].push_back(RegData("User_Event_3", "3", 3, 0x1)); + regDataMap["mm_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_0", "0", 0, 0x1)); + regDataMap["mm_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_1", "1", 1, 0x1)); + regDataMap["mm_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_lock0_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock10_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock11_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock12_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock13_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock14_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock15_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock1_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock2_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock3_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock4_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock5_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock6_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock7_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock8_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock9_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mm_lock_request"].push_back(RegData("Request_Result", "0", 0, 0x1)); + regDataMap["mm_locks_event_selection_0"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_0"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_1"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_1"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_2"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_2"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_3"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_3"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_4"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_4"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_5"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_5"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_6"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_6"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_event_selection_7"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["mm_locks_event_selection_7"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_0", "0", 0, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_1", "1", 1, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_10", "10", 10, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_11", "11", 11, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_12", "12", 12, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_13", "13", 13, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_14", "14", 14, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_15", "15", 15, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_2", "2", 2, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_3", "3", 3, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_4", "4", 4, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_5", "5", 5, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_6", "6", 6, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_7", "7", 7, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_8", "8", 8, 0x1)); + regDataMap["mm_locks_overflow"].push_back(RegData("Lock_Overflow_9", "9", 9, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_0", "0", 0, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_1", "1", 1, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_10", "10", 10, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_11", "11", 11, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_12", "12", 12, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_13", "13", 13, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_14", "14", 14, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_15", "15", 15, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_2", "2", 2, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_3", "3", 3, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_4", "4", 4, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_5", "5", 5, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_6", "6", 6, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_7", "7", 7, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_8", "8", 8, 0x1)); + regDataMap["mm_locks_underflow"].push_back(RegData("Lock_Underflow_9", "9", 9, 0x1)); + regDataMap["mm_memory_control"].push_back(RegData("Memory_Zeroisation", "0", 0, 0x1)); + regDataMap["mm_parity_failing_address"].push_back(RegData("Parity_Error_Detection_Address", "15:0", 0, 0xFFFF)); + regDataMap["mm_parity_failing_address"].push_back(RegData("Valid", "16", 16, 0x1)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt1_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_performance_control0"].push_back(RegData("Cnt0_Start_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_control1"].push_back(RegData("Cnt1_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control1"].push_back(RegData("Cnt0_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_control2"].push_back(RegData("Cnt2_Stop_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control2"].push_back(RegData("Cnt3_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_performance_control2"].push_back(RegData("Cnt3_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_performance_control2"].push_back(RegData("Cnt2_Start_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_control3"].push_back(RegData("Cnt3_Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_performance_control3"].push_back(RegData("Cnt2_Reset_Event", "6:0", 0, 0x7F)); + regDataMap["mm_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter0_event_value"].push_back(RegData("Counter0_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter1"].push_back(RegData("Counter1_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter1_event_value"].push_back(RegData("Counter1_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter2"].push_back(RegData("Counter2_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_performance_counter3"].push_back(RegData("Counter3_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["mm_timer_control"].push_back(RegData("Reset_Event", "14:8", 8, 0x7F)); + regDataMap["mm_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["mm_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mm_trace_control0"].push_back(RegData("Trace_Start_Event", "22:16", 16, 0x7F)); + regDataMap["mm_trace_control0"].push_back(RegData("Trace_Stop_Event", "30:24", 24, 0x7F)); + regDataMap["mm_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["mm_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event1", "14:8", 8, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event2", "22:16", 16, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event3", "30:24", 24, 0x7F)); + regDataMap["mm_trace_event0"].push_back(RegData("Trace_Event0", "6:0", 0, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event5", "14:8", 8, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event6", "22:16", 16, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event7", "30:24", 24, 0x7F)); + regDataMap["mm_trace_event1"].push_back(RegData("Trace_Event4", "6:0", 0, 0x7F)); + regDataMap["mm_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["mm_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mm_watchpoint0"].push_back(RegData("Address", "10:0", 0, 0x7FF)); + regDataMap["mm_watchpoint0"].push_back(RegData("WriteStrobeMask", "23:16", 16, 0xFF)); + regDataMap["mm_watchpoint0"].push_back(RegData("South_Access", "24", 24, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("West_Access", "25", 25, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("North_Access", "26", 26, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("East_Access", "27", 27, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("DMA_Access", "28", 28, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("AXI_Access", "29", 29, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("Write_Access", "30", 30, 0x1)); + regDataMap["mm_watchpoint0"].push_back(RegData("Read_Access", "31", 31, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Address", "10:0", 0, 0x7FF)); + regDataMap["mm_watchpoint1"].push_back(RegData("WriteStrobeMask", "23:16", 16, 0xFF)); + regDataMap["mm_watchpoint1"].push_back(RegData("South_Access", "24", 24, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("West_Access", "25", 25, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("North_Access", "26", 26, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("East_Access", "27", 27, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("DMA_Access", "28", 28, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("AXI_Access", "29", 29, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Write_Access", "30", 30, 0x1)); + regDataMap["mm_watchpoint1"].push_back(RegData("Read_Access", "31", 31, 0x1)); + regDataMap["mem_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane0", "0", 0, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane1", "1", 1, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane2", "2", 2, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane3", "3", 3, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane4", "4", 4, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane5", "5", 5, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane6", "6", 6, 0x1)); + regDataMap["mem_checkbit_error_generation"].push_back(RegData("Lane7", "7", 7, 0x1)); + regDataMap["mem_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["mem_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["mem_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventB", "15:8", 8, 0xFF)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventC", "23:16", 16, 0xFF)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventD", "31:24", 24, 0xFF)); + regDataMap["mem_combo_event_inputs"].push_back(RegData("eventA", "7:0", 0, 0xFF)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("S2MM_Sel1_Channel", "10:8", 8, 0x7)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("MM2S_Sel0_Channel", "18:16", 16, 0x7)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("MM2S_Sel1_Channel", "26:24", 24, 0x7)); + regDataMap["mem_dma_event_channel_selection"].push_back(RegData("S2MM_Sel0_Channel", "2:0", 0, 0x7)); + regDataMap["mem_dma_mm2s_0_constant_pad_value"].push_back(RegData("Constant_Pad_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_dma_mm2s_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_0_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_0_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_1_constant_pad_value"].push_back(RegData("Constant_Pad_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_dma_mm2s_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_1_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_1_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_2_constant_pad_value"].push_back(RegData("Constant_Pad_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_dma_mm2s_2_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_2_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_2_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_2_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_2_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_2_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_3_constant_pad_value"].push_back(RegData("Constant_Pad_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_dma_mm2s_3_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_3_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_3_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_3_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_3_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_3_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_4_constant_pad_value"].push_back(RegData("Constant_Pad_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_dma_mm2s_4_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_4_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_4_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_4_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_4_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_4_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_5_constant_pad_value"].push_back(RegData("Constant_Pad_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_dma_mm2s_5_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_mm2s_5_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_mm2s_5_ctrl"].push_back(RegData("Compression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_5_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_mm2s_5_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_mm2s_5_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_0"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_1"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_2"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_3"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_4"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_mm2s_status_5"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_0_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_0_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_0_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_0_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_1_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_1_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_1_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_1_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_2_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_2_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_2_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_2_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_3_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_3_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_3_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_3_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_4_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_4_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_4_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_4_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Reset", "1", 1, 0x1)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_5_ctrl"].push_back(RegData("Decompression_Enable", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_5_start_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["mem_dma_s2mm_5_start_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_5_start_queue"].push_back(RegData("Start_BD_ID", "5:0", 0, 0x3F)); + regDataMap["mem_dma_s2mm_current_write_count_0"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_1"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_2"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_3"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_4"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_current_write_count_5"].push_back(RegData("Current_Write_Count", "16:0", 0, 0x1FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_2"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_3"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_4"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["mem_dma_s2mm_fot_count_fifo_pop_5"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_0"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_1"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_2"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_3"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_4"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Cur_BD", "29:24", 24, 0x3F)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_Lock_Access_to_Unavailable", "8", 8, 0x1)); + regDataMap["mem_dma_s2mm_status_5"].push_back(RegData("Error_DM_Access_to_Unavailable", "9", 9, 0x1)); + regDataMap["mem_ecc_failing_address"].push_back(RegData("ECC_Error_Detection_Address", "18:0", 0, 0x7FFFF)); + regDataMap["mem_ecc_failing_address"].push_back(RegData("Valid", "19", 19, 0x1)); + regDataMap["mem_ecc_scrubbing_event"].push_back(RegData("Scrubbing_Event_Number", "7:0", 0, 0xFF)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "23:16", 16, 0xFF)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "7:0", 0, 0xFF)); + regDataMap["mem_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["mem_event_broadcast0"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast1"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast10"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast11"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast12"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast13"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast14"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast15"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast2"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast3"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast4"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast5"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast6"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast7"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast8"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast9"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_broadcast_a_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_a_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_broadcast_b_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["mem_event_generate"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "10", 10, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "11", 11, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt0_Event", "2", 2, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt1_Event", "3", 3, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt2_Event", "4", 4, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Perf_Cnt3_Event", "5", 5, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_0", "6", 6, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_1", "7", 7, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_2", "8", 8, 0x1)); + regDataMap["mem_event_group_0_enable"].push_back(RegData("Combo_Event_3", "9", 9, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_0", "0", 0, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_1", "1", 1, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_10", "10", 10, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_11", "11", 11, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_12", "12", 12, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_13", "13", 13, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_14", "14", 14, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_15", "15", 15, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_2", "2", 2, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_3", "3", 3, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_4", "4", 4, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_5", "5", 5, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_6", "6", 6, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_7", "7", 7, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_8", "8", 8, 0x1)); + regDataMap["mem_event_group_broadcast_enable"].push_back(RegData("Broadcast_A_9", "9", 9, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_start_task", "0", 0, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_start_task", "1", 1, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_finished_task", "10", 10, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_finished_task", "11", 11, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_stream_starvation", "16", 16, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_stream_starvation", "17", 17, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_stream_backpressure", "18", 18, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_stream_backpressure", "19", 19, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_start_task", "2", 2, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_memory_backpressure", "20", 20, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_memory_backpressure", "21", 21, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_memory_starvation", "22", 22, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_memory_starvation", "23", 23, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_start_task", "3", 3, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_finished_BD", "4", 4, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_finished_BD", "5", 5, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel0_finished_BD", "6", 6, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_MM2S_Sel1_finished_BD", "7", 7, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel0_finished_task", "8", 8, 0x1)); + regDataMap["mem_event_group_dma_enable"].push_back(RegData("DMA_S2MM_Sel1_finished_task", "9", 9, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_Corrected", "0", 0, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_Scrub_2bit", "1", 1, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Lock_Error", "10", 10, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DMA_Task_Token_Stall", "11", 11, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_1bit", "2", 2, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DM_ECC_Error_2bit", "3", 3, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DMA_S2MM_Error", "4", 4, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("DMA_MM2S_Error", "5", 5, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "6", 6, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Stream_Pkt_Parity_Error", "7", 7, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("Control_Pkt_Error", "8", 8, 0x1)); + regDataMap["mem_event_group_error_enable"].push_back(RegData("AXI_MM_Slave_Error", "9", 9, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_eq", "24", 24, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_acq_ge", "25", 25, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_rel", "26", 26, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel6_equal_to_value", "27", 27, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_eq", "28", 28, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_acq_ge", "29", 29, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_rel", "30", 30, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel7_equal_to_value", "31", 31, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["mem_event_group_lock_enable"].push_back(RegData("Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_0", "0", 0, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_1", "1", 1, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_2", "2", 2, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_3", "3", 3, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_4", "4", 4, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_5", "5", 5, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_6", "6", 6, 0x1)); + regDataMap["mem_event_group_memory_conflict_enable"].push_back(RegData("Conflict_DM_Bank_7", "7", 7, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["mem_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["mem_event_group_user_event_enable"].push_back(RegData("User_Event_0", "0", 0, 0x1)); + regDataMap["mem_event_group_user_event_enable"].push_back(RegData("User_Event_1", "1", 1, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_0", "0", 0, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_1", "1", 1, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_2", "2", 2, 0x1)); + regDataMap["mem_event_group_watchpoint_enable"].push_back(RegData("Watchpoint_3", "3", 3, 0x1)); + regDataMap["mem_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status4"].push_back(RegData("Event_159_128_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_event_status5"].push_back(RegData("Event_191_160_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_lock0_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock10_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock11_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock12_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock13_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock14_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock15_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock16_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock17_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock18_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock19_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock1_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock20_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock21_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock22_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock23_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock24_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock25_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock26_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock27_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock28_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock29_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock2_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock30_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock31_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock32_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock33_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock34_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock35_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock36_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock37_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock38_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock39_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock3_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock40_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock41_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock42_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock43_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock44_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock45_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock46_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock47_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock48_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock49_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock4_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock50_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock51_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock52_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock53_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock54_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock55_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock56_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock57_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock58_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock59_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock5_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock60_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock61_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock62_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock63_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock6_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock7_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock8_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock9_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["mem_lock_request"].push_back(RegData("Request_Result", "0", 0, 0x1)); + regDataMap["mem_locks_event_selection_0"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_0"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_1"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_1"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_2"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_2"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_3"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_3"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_4"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_4"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_5"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_5"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_6"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_6"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_event_selection_7"].push_back(RegData("Lock_Select", "21:16", 16, 0x3F)); + regDataMap["mem_locks_event_selection_7"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_0", "0", 0, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_1", "1", 1, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_10", "10", 10, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_11", "11", 11, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_12", "12", 12, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_13", "13", 13, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_14", "14", 14, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_15", "15", 15, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_16", "16", 16, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_17", "17", 17, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_18", "18", 18, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_19", "19", 19, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_2", "2", 2, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_20", "20", 20, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_21", "21", 21, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_22", "22", 22, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_23", "23", 23, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_24", "24", 24, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_25", "25", 25, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_26", "26", 26, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_27", "27", 27, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_28", "28", 28, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_29", "29", 29, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_3", "3", 3, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_30", "30", 30, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_31", "31", 31, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_4", "4", 4, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_5", "5", 5, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_6", "6", 6, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_7", "7", 7, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_8", "8", 8, 0x1)); + regDataMap["mem_locks_overflow_0"].push_back(RegData("Lock_Overflow_9", "9", 9, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_32", "0", 0, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_33", "1", 1, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_42", "10", 10, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_43", "11", 11, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_44", "12", 12, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_45", "13", 13, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_46", "14", 14, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_47", "15", 15, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_48", "16", 16, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_49", "17", 17, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_50", "18", 18, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_51", "19", 19, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_34", "2", 2, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_52", "20", 20, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_53", "21", 21, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_54", "22", 22, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_55", "23", 23, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_56", "24", 24, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_57", "25", 25, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_58", "26", 26, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_59", "27", 27, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_60", "28", 28, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_61", "29", 29, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_35", "3", 3, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_62", "30", 30, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_63", "31", 31, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_36", "4", 4, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_37", "5", 5, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_38", "6", 6, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_39", "7", 7, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_40", "8", 8, 0x1)); + regDataMap["mem_locks_overflow_1"].push_back(RegData("Lock_Overflow_41", "9", 9, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_0", "0", 0, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_1", "1", 1, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_10", "10", 10, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_11", "11", 11, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_12", "12", 12, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_13", "13", 13, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_14", "14", 14, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_15", "15", 15, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_16", "16", 16, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_17", "17", 17, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_18", "18", 18, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_19", "19", 19, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_2", "2", 2, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_20", "20", 20, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_21", "21", 21, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_22", "22", 22, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_23", "23", 23, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_24", "24", 24, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_25", "25", 25, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_26", "26", 26, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_27", "27", 27, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_28", "28", 28, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_29", "29", 29, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_3", "3", 3, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_30", "30", 30, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_31", "31", 31, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_4", "4", 4, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_5", "5", 5, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_6", "6", 6, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_7", "7", 7, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_8", "8", 8, 0x1)); + regDataMap["mem_locks_underflow_0"].push_back(RegData("Lock_Underflow_9", "9", 9, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_32", "0", 0, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_33", "1", 1, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_42", "10", 10, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_43", "11", 11, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_44", "12", 12, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_45", "13", 13, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_46", "14", 14, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_47", "15", 15, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_48", "16", 16, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_49", "17", 17, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_50", "18", 18, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_51", "19", 19, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_34", "2", 2, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_52", "20", 20, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_53", "21", 21, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_54", "22", 22, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_55", "23", 23, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_56", "24", 24, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_57", "25", 25, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_58", "26", 26, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_59", "27", 27, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_60", "28", 28, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_61", "29", 29, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_35", "3", 3, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_62", "30", 30, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_63", "31", 31, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_36", "4", 4, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_37", "5", 5, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_38", "6", 6, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_39", "7", 7, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_40", "8", 8, 0x1)); + regDataMap["mem_locks_underflow_1"].push_back(RegData("Lock_Underflow_41", "9", 9, 0x1)); + regDataMap["mem_memory_control"].push_back(RegData("Memory_Zeroisation", "0", 0, 0x1)); + regDataMap["mem_memory_control"].push_back(RegData("Memory_Interleaving", "1", 1, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("Stream_Switch_Clock_Enable", "0", 0, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("Memory_Module_Clock_Enable", "1", 1, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("Ctrl_Pkt_Tlast_Error_Enable", "4", 4, 0x1)); + regDataMap["mem_module_clock_control"].push_back(RegData("DMA_Adaptive_Clock_Gate", "5", 5, 0x1)); + regDataMap["mem_module_reset_control"].push_back(RegData("Stream_Switch_Reset", "0", 0, 0x1)); + regDataMap["mem_module_reset_control"].push_back(RegData("Memory_Reset", "1", 1, 0x1)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt0_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt1_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt1_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control0"].push_back(RegData("Cnt0_Start_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt2_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt3_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt3_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control1"].push_back(RegData("Cnt2_Start_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt1_Reset_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt2_Reset_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt3_Reset_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control2"].push_back(RegData("Cnt0_Reset_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_control3"].push_back(RegData("Cnt4_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control3"].push_back(RegData("Cnt5_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_performance_control3"].push_back(RegData("Cnt5_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_performance_control3"].push_back(RegData("Cnt4_Start_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_control4"].push_back(RegData("Cnt5_Reset_Event", "15:8", 8, 0xFF)); + regDataMap["mem_performance_control4"].push_back(RegData("Cnt4_Reset_Event", "7:0", 0, 0xFF)); + regDataMap["mem_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter0_event_value"].push_back(RegData("Counter0_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter1"].push_back(RegData("Counter1_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter1_event_value"].push_back(RegData("Counter1_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter2"].push_back(RegData("Counter2_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter2_event_value"].push_back(RegData("Counter2_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter3"].push_back(RegData("Counter3_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter3_event_value"].push_back(RegData("Counter3_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter4"].push_back(RegData("Counter4_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_performance_counter5"].push_back(RegData("Counter5_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["mem_spare_reg_privileged"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["mem_stream_switch_adaptive_clock_gate_abort_period"].push_back(RegData("Abort_Period", "3:0", 0, 0xF)); + regDataMap["mem_stream_switch_adaptive_clock_gate_status"].push_back(RegData("Active", "0", 0, 0x1)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["mem_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["mem_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_0_lower", "0", 0, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_1_lower", "1", 1, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_0_upper", "16", 16, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_1_upper", "17", 17, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_2_upper", "18", 18, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_3_upper", "19", 19, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_2_lower", "2", 2, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_4_upper", "20", 20, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_5_upper", "21", 21, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("Tile_Control_upper", "22", 22, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("Mem_trace_upper", "23", 23, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_3_lower", "3", 3, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_4_lower", "4", 4, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("DMA_5_lower", "5", 5, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("Tile_Control_lower", "6", 6, 0x1)); + regDataMap["mem_stream_switch_parity_injection"].push_back(RegData("Mem_trace_lower", "7", 7, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_0", "0", 0, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_1", "1", 1, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_2", "2", 2, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_3", "3", 3, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_4", "4", 4, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("DMA_5", "5", 5, 0x1)); + regDataMap["mem_stream_switch_parity_status"].push_back(RegData("Tile_Control", "6", 6, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["mem_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["mem_tile_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["mem_timer_control"].push_back(RegData("Reset_Event", "15:8", 8, 0xFF)); + regDataMap["mem_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["mem_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["mem_trace_control0"].push_back(RegData("Trace_Start_Event", "23:16", 16, 0xFF)); + regDataMap["mem_trace_control0"].push_back(RegData("Trace_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["mem_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["mem_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event1", "15:8", 8, 0xFF)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event2", "23:16", 16, 0xFF)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event3", "31:24", 24, 0xFF)); + regDataMap["mem_trace_event0"].push_back(RegData("Trace_Event0", "7:0", 0, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event5", "15:8", 8, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event6", "23:16", 16, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event7", "31:24", 24, 0xFF)); + regDataMap["mem_trace_event1"].push_back(RegData("Trace_Event4", "7:0", 0, 0xFF)); + regDataMap["mem_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["mem_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["mem_watchpoint0"].push_back(RegData("Address", "13:0", 0, 0x3FFF)); + regDataMap["mem_watchpoint0"].push_back(RegData("WriteStrobeMask", "23:16", 16, 0xFF)); + regDataMap["mem_watchpoint0"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint0"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("Address", "13:0", 0, 0x3FFF)); + regDataMap["mem_watchpoint1"].push_back(RegData("WriteStrobeMask", "23:16", 16, 0xFF)); + regDataMap["mem_watchpoint1"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint1"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("Address", "13:0", 0, 0x3FFF)); + regDataMap["mem_watchpoint2"].push_back(RegData("WriteStrobeMask", "23:16", 16, 0xFF)); + regDataMap["mem_watchpoint2"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint2"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("Address", "13:0", 0, 0x3FFF)); + regDataMap["mem_watchpoint3"].push_back(RegData("WriteStrobeMask", "23:16", 16, 0xFF)); + regDataMap["mem_watchpoint3"].push_back(RegData("West_Access", "24", 24, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("East_Access", "25", 25, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("DMA_Access", "26", 26, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("AXI_Access", "27", 27, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("Write_Access", "28", 28, 0x1)); + regDataMap["mem_watchpoint3"].push_back(RegData("Read_Access", "29", 29, 0x1)); + regDataMap["shim_axi_mm_outstanding_transactions"].push_back(RegData("NoC_Module_To_NMU", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_ctrl"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_ctrl"].push_back(RegData("Clear", "4", 4, 0x1)); + regDataMap["shim_bisr_cache_data0"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data1"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data2"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data3"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data4"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data5"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data6"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_data7"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_cache_status"].push_back(RegData("Done", "0", 0, 0x1)); + regDataMap["shim_bisr_cache_status"].push_back(RegData("Pass", "1", 1, 0x1)); + regDataMap["shim_bisr_test_data0"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data1"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data2"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data3"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data4"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data5"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data6"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_bisr_test_data7"].push_back(RegData("Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_cssd_trigger"].push_back(RegData("Trigger", "0", 0, 0x1)); + regDataMap["shim_column_clock_control"].push_back(RegData("Clock_Buffer_Enable", "0", 0, 0x1)); + regDataMap["shim_column_clock_control"].push_back(RegData("Column_SRAMs_Sleep", "1", 1, 0x1)); + regDataMap["shim_column_reset_control"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo2", "17:16", 16, 0x3)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo0", "1:0", 0, 0x3)); + regDataMap["shim_combo_event_control"].push_back(RegData("combo1", "9:8", 8, 0x3)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventB", "15:8", 8, 0xFF)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventC", "23:16", 16, 0xFF)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventD", "31:24", 24, 0xFF)); + regDataMap["shim_combo_event_inputs"].push_back(RegData("eventA", "7:0", 0, 0xFF)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("First_Header_Parity_Error", "0", 0, 0x1)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("Second_Header_Parity_Error", "1", 1, 0x1)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("SLVERR_On_Access", "2", 2, 0x1)); + regDataMap["shim_control_packet_handler_status"].push_back(RegData("Tlast_Error", "3", 3, 0x1)); + regDataMap["shim_core_control"].push_back(RegData("Wakeup", "0", 0, 0x1)); + regDataMap["shim_core_control"].push_back(RegData("Go_To_Sleep", "1", 1, 0x1)); + regDataMap["shim_core_interrupt_status"].push_back(RegData("Go_To_Sleep", "0", 0, 0x1)); + regDataMap["shim_core_interrupt_status"].push_back(RegData("Event_Action", "1", 1, 0x1)); + regDataMap["shim_core_status"].push_back(RegData("Sleep", "0", 0, 0x1)); + regDataMap["shim_core_status"].push_back(RegData("Interrupt", "1", 1, 0x1)); + regDataMap["shim_dma_dm2mm_axi_control"].push_back(RegData("AxQOS", "3:0", 0, 0xF)); + regDataMap["shim_dma_dm2mm_axi_control"].push_back(RegData("AxCACHE", "7:4", 4, 0xF)); + regDataMap["shim_dma_dm2mm_axi_control"].push_back(RegData("Burst_Length", "9:8", 8, 0x3)); + regDataMap["shim_dma_dm2mm_control"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Running", "0", 0, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Error_BD_Invalid", "1", 1, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Task_Queue_Size", "12:8", 8, 0x1F)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Error_Local_address_out_of_range", "2", 2, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Response_Queue_Size", "20:16", 16, 0x1F)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("AXI_MM_SLVERR", "3", 3, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("AXI_MM_DECERR", "4", 4, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Error_ECC_DED", "5", 5, 0x1)); + regDataMap["shim_dma_dm2mm_status"].push_back(RegData("Task_Queue_Overflow", "6", 6, 0x1)); + regDataMap["shim_dma_mm2dm_axi_control"].push_back(RegData("AxQOS", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2dm_axi_control"].push_back(RegData("AxCACHE", "7:4", 4, 0xF)); + regDataMap["shim_dma_mm2dm_axi_control"].push_back(RegData("Burst_Length", "9:8", 8, 0x3)); + regDataMap["shim_dma_mm2dm_control"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Running", "0", 0, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Error_BD_Invalid", "1", 1, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Task_Queue_Size", "12:8", 8, 0x1F)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Error_Local_address_out_of_range", "2", 2, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Response_Queue_Size", "20:16", 16, 0x1F)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("AXI_MM_SLVERR", "3", 3, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("AXI_MM_DECERR", "4", 4, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Error_ECC_DED", "5", 5, 0x1)); + regDataMap["shim_dma_mm2dm_status"].push_back(RegData("Task_Queue_Overflow", "6", 6, 0x1)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_mm2s_0_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_0_response_fifo_parity_error_injection"].push_back(RegData("Parity_Injection", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_0_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_mm2s_0_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_mm2s_0_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_mm2s_1_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_1_response_fifo_parity_error_injection"].push_back(RegData("Parity_Injection", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_1_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_mm2s_1_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_mm2s_1_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Task_Queue_Size", "24:20", 20, 0x1F)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Cur_BD", "28:25", 25, 0xF)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["shim_dma_mm2s_status_0"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Task_Queue_Size", "24:20", 20, 0x1F)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Cur_BD", "28:25", 25, 0xF)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_Stream_Backpressure", "4", 4, 0x1)); + regDataMap["shim_dma_mm2s_status_1"].push_back(RegData("Stalled_TCT", "5", 5, 0x1)); + regDataMap["shim_dma_pause"].push_back(RegData("S2MM_0", "0", 0, 0x1)); + regDataMap["shim_dma_pause"].push_back(RegData("S2MM_1", "1", 1, 0x1)); + regDataMap["shim_dma_pause"].push_back(RegData("MM2S_0", "2", 2, 0x1)); + regDataMap["shim_dma_pause"].push_back(RegData("MM2S_1", "3", 3, 0x1)); + regDataMap["shim_dma_pause"].push_back(RegData("DM2MM", "0", 0, 0x1)); + regDataMap["shim_dma_pause"].push_back(RegData("MM2DM", "1", 1, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_0_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_0_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_s2mm_0_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_0_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Controller_ID", "15:8", 8, 0xFF)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("FoT_Mode", "17:16", 16, 0x3)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Pause_Stream", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_1_ctrl"].push_back(RegData("Enable_Out_of_Order", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_1_task_queue"].push_back(RegData("Repeat_Count", "23:16", 16, 0xFF)); + regDataMap["shim_dma_s2mm_1_task_queue"].push_back(RegData("Enable_Token_Issue", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_1_task_queue"].push_back(RegData("Start_BD_ID", "3:0", 0, 0xF)); + regDataMap["shim_dma_s2mm_current_write_count_0"].push_back(RegData("Current_Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_current_write_count_1"].push_back(RegData("Current_Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_0"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Write_Count", "17:0", 0, 0x3FFFF)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("BD_ID", "29:24", 24, 0x3F)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Last_in_Task", "30", 30, 0x1)); + regDataMap["shim_dma_s2mm_fot_count_fifo_pop_1"].push_back(RegData("Valid", "31", 31, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["shim_dma_s2mm_status_0"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_BD_Unavailable", "10", 10, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_BD_Invalid", "11", 11, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_FoT_Length_Exceeded", "12", 12, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Error_FoT_BDs_per_Task", "13", 13, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("AXI_MM_Decode_Error", "16", 16, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("AXI_MM_Slave_Error", "17", 17, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Overflow", "18", 18, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Channel_Running", "19", 19, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Status", "1:0", 0, 0x3)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Acq", "2", 2, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Task_Queue_Size", "22:20", 20, 0x7)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Cur_BD", "27:24", 24, 0xF)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_Lock_Rel", "3", 3, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_Stream_Starvation", "4", 4, 0x1)); + regDataMap["shim_dma_s2mm_status_1"].push_back(RegData("Stalled_TCT_or_Count_FIFO_Full", "5", 5, 0x1)); + regDataMap["shim_demux_config"].push_back(RegData("South5", "11:10", 10, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South1", "3:2", 2, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South2", "5:4", 4, 0x3)); + regDataMap["shim_demux_config"].push_back(RegData("South3", "7:6", 6, 0x3)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Falling", "10", 10, 0x1)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_1", "23:16", 16, 0xFF)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Rising", "25", 25, 0x1)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_1_Trigger_Falling", "26", 26, 0x1)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_Event_0", "7:0", 0, 0xFF)); + regDataMap["shim_edge_detection_event_control"].push_back(RegData("Edge_Detection_0_Trigger_Rising", "9", 9, 0x1)); + regDataMap["shim_event_broadcast0_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast10_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast11_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast12_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast13_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast14_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast15_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast1_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast2_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast3_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast4_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast5_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast6_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast7_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast8_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast9_a"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_broadcast_a_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_a_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_east_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_north_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_south_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_clr"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_broadcast_b_block_west_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_event_generate"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Timer_Sync", "0", 0, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Timer_Value_Reached", "1", 1, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Perf_Cnt0", "2", 2, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Perf_Cnt1", "3", 3, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_0", "4", 4, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_1", "5", 5, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_2", "6", 6, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Combo_Event_3", "7", 7, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_0", "8", 8, 0x1)); + regDataMap["shim_event_group_0_enable"].push_back(RegData("Edge_Detection_Event_1", "9", 9, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_0", "0", 0, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_1", "1", 1, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_10", "10", 10, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_11", "11", 11, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_12", "12", 12, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_13", "13", 13, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_14", "14", 14, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_15", "15", 15, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_2", "2", 2, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_3", "3", 3, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_4", "4", 4, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_5", "5", 5, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_6", "6", 6, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_7", "7", 7, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_8", "8", 8, 0x1)); + regDataMap["shim_event_group_broadcast_a_enable"].push_back(RegData("Broadcast_A_9", "9", 9, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Slave_Tile_Error", "0", 0, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("Control_Pkt_Error", "1", 1, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_0_DMA_MM2S_Error", "10", 10, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_1_DMA_MM2S_Error", "11", 11, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_0_Lock_Error", "12", 12, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_1_Lock_Error", "13", 13, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_0_DMA_Task_Token_Stall", "14", 14, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_1_DMA_Task_Token_Stall", "15", 15, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_0_DMA_HW_Error", "16", 16, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_1_DMA_HW_Error", "17", 17, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("Stream_Switch_Port_Parity_Error", "2", 2, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Decode_NSU_Error", "3", 3, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Slave_NSU_Error", "4", 4, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Unsupported_Traffic", "5", 5, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Unsecure_Access_in_Secure_Mode", "6", 6, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("AXI_MM_Byte_Strobe_Error", "7", 7, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_0_DMA_S2MM_Error", "8", 8, 0x1)); + regDataMap["shim_event_group_errors_enable"].push_back(RegData("NoC_1_DMA_S2MM_Error", "9", 9, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_0_start_task", "0", 0, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_1_start_task", "1", 1, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_0_finished_task", "10", 10, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_1_finished_task", "11", 11, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_0_stream_starvation", "16", 16, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_1_stream_starvation", "17", 17, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_0_memory_backpressure", "18", 18, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_1_memory_backpressure", "19", 19, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_0_start_task", "2", 2, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_0_stream_backpressure", "20", 20, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_1_stream_backpressure", "21", 21, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_0_memory_starvation", "22", 22, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_1_memory_starvation", "23", 23, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_1_start_task", "3", 3, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_0_finished_task", "8", 8, 0x1)); + regDataMap["shim_event_group_noc_0_dma_activity_enable"].push_back(RegData("NoC_0_DMA_S2MM_1_finished_task", "9", 9, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["shim_event_group_noc_0_lock_enable"].push_back(RegData("NoC_0_Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_0_start_task", "0", 0, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_1_start_task", "1", 1, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_0_finished_task", "10", 10, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_1_finished_task", "11", 11, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_0_stalled_lock_acquire", "12", 12, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_1_stalled_lock_acquire", "13", 13, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_0_stalled_lock_acquire", "14", 14, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_1_stalled_lock_acquire", "15", 15, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_0_stream_starvation", "16", 16, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_1_stream_starvation", "17", 17, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_0_memory_backpressure", "18", 18, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_1_memory_backpressure", "19", 19, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_0_start_task", "2", 2, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_0_stream_backpressure", "20", 20, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_1_stream_backpressure", "21", 21, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_0_memory_starvation", "22", 22, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_1_memory_starvation", "23", 23, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_1_start_task", "3", 3, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_0_finished_BD", "4", 4, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_1_finished_BD", "5", 5, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_0_finished_BD", "6", 6, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_MM2S_1_finished_BD", "7", 7, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_0_finished_task", "8", 8, 0x1)); + regDataMap["shim_event_group_noc_1_dma_activity_enable"].push_back(RegData("NoC_1_DMA_S2MM_1_finished_task", "9", 9, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel0_acq_eq", "0", 0, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel0_acq_ge", "1", 1, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel2_rel", "10", 10, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel2_equal_to_value", "11", 11, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel3_acq_eq", "12", 12, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel3_acq_ge", "13", 13, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel3_rel", "14", 14, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel3_equal_to_value", "15", 15, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel4_acq_eq", "16", 16, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel4_acq_ge", "17", 17, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel4_rel", "18", 18, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel4_equal_to_value", "19", 19, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel0_rel", "2", 2, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel5_acq_eq", "20", 20, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel5_acq_ge", "21", 21, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel5_rel", "22", 22, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel5_equal_to_value", "23", 23, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel0_equal_to_value", "3", 3, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel1_acq_eq", "4", 4, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel1_acq_ge", "5", 5, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel1_rel", "6", 6, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel1_equal_to_value", "7", 7, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel2_acq_eq", "8", 8, 0x1)); + regDataMap["shim_event_group_noc_1_lock_enable"].push_back(RegData("NoC_1_Lock_Sel2_acq_ge", "9", 9, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_0", "0", 0, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_0", "1", 1, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_2", "10", 10, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_2", "11", 11, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_3", "12", 12, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_3", "13", 13, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_3", "14", 14, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_3", "15", 15, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_4", "16", 16, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_4", "17", 17, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_4", "18", 18, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_4", "19", 19, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_0", "2", 2, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_5", "20", 20, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_5", "21", 21, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_5", "22", 22, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_5", "23", 23, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_6", "24", 24, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_6", "25", 25, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_6", "26", 26, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_6", "27", 27, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_7", "28", 28, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_7", "29", 29, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_0", "3", 3, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_7", "30", 30, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_7", "31", 31, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_1", "4", 4, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_1", "5", 5, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Stalled_1", "6", 6, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_TLAST_1", "7", 7, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Idle_2", "8", 8, 0x1)); + regDataMap["shim_event_group_stream_switch_enable"].push_back(RegData("Port_Running_2", "9", 9, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Sleep", "0", 0, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Interrupt", "1", 1, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Jump_Taken", "10", 10, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Jump_Hit", "11", 11, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Data_Read", "12", 12, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Data_Write", "13", 13, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Pipeline_Halted_Debug", "14", 14, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Stream_Get", "15", 15, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Stream_Put", "16", 16, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Debug_Sys_Rst", "2", 2, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Debug_Wakeup", "3", 3, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Timer1_Interrupt", "4", 4, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Timer2_Interrupt", "5", 5, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Timer3_Interrupt", "6", 6, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Timer4_Interrupt", "7", 7, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Reg_Write", "8", 8, 0x1)); + regDataMap["shim_event_group_uc_core_program_flow_enable"].push_back(RegData("uC_Core_Exception_Taken", "9", 9, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Master_Idle", "0", 0, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Master_Running", "1", 1, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Master_Stalled", "2", 2, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Master_TLAST", "3", 3, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Slave_Idle", "4", 4, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Slave_Running", "5", 5, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Slave_Stalled", "6", 6, 0x1)); + regDataMap["shim_event_group_uc_core_streams_enable"].push_back(RegData("AXIS_Slave_TLAST", "7", 7, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_DM2MM_start_task", "0", 0, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_MM2DM_start_task", "1", 1, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_DM2MM_finished_BD", "2", 2, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_MM2DM_finished_BD", "3", 3, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_DM2MM_finished_task", "4", 4, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_MM2DM_finished_task", "5", 5, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_DM2MM_local_memory_starvation", "6", 6, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_DM2MM_remote_memory_backpressure", "7", 7, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_MM2DM_local_memory_backpressure", "8", 8, 0x1)); + regDataMap["shim_event_group_uc_dma_activity_enable"].push_back(RegData("DMA_MM2DM_remote_memory_starvation", "9", 9, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("AXI_MM_uC_Core_Master_Decode_Error", "0", 0, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("AXI_MM_uC_DMA_Master_Decode_Error", "1", 1, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("Shared_DM_ECC_Error_1bit", "10", 10, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("Shared_DM_ECC_Error_2bit", "11", 11, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("AXI_MM_uC_Core_Master_Slave_Error", "2", 2, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("AXI_MM_uC_DMA_Master_Slave_Error", "3", 3, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("DMA_DM2MM_Error", "4", 4, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("DMA_MM2DM_Error", "5", 5, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("PM_ECC_Error_1bit", "6", 6, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("PM_ECC_Error_2bit", "7", 7, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("Private_DM_ECC_Error_1bit", "8", 8, 0x1)); + regDataMap["shim_event_group_uc_module_errors_enable"].push_back(RegData("Private_DM_ECC_Error_2bit", "9", 9, 0x1)); + regDataMap["shim_event_status0"].push_back(RegData("Event_31_0_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status1"].push_back(RegData("Event_63_32_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status2"].push_back(RegData("Event_95_64_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status3"].push_back(RegData("Event_127_96_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status4"].push_back(RegData("Event_159_128_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status5"].push_back(RegData("Event_191_160_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status6"].push_back(RegData("Event_223_192_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_event_status7"].push_back(RegData("Event_255_224_Status", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_clear"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_a_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_clear"].push_back(RegData("Clear", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_set"].push_back(RegData("Set", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_block_north_in_b_value"].push_back(RegData("Value", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_1st_level_disable_a"].push_back(RegData("Disable_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_disable_b"].push_back(RegData("Disable_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_enable_a"].push_back(RegData("Enable_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_enable_b"].push_back(RegData("Enable_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event1", "15:8", 8, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event2", "23:16", 16, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event3", "31:24", 24, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_a"].push_back(RegData("IRQ_Event0", "7:0", 0, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event1", "15:8", 8, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event2", "23:16", 16, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event3", "31:24", 24, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_event_b"].push_back(RegData("IRQ_Event0", "7:0", 0, 0xFF)); + regDataMap["shim_interrupt_controller_1st_level_irq_no_a"].push_back(RegData("Irq_no_A", "3:0", 0, 0xF)); + regDataMap["shim_interrupt_controller_1st_level_irq_no_b"].push_back(RegData("Irq_no_B", "3:0", 0, 0xF)); + regDataMap["shim_interrupt_controller_1st_level_mask_a"].push_back(RegData("IRQ_Mask_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_mask_b"].push_back(RegData("IRQ_Mask_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_status_a"].push_back(RegData("Status_A", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_1st_level_status_b"].push_back(RegData("Status_B", "19:0", 0, 0xFFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_disable"].push_back(RegData("Disable_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_disable"].push_back(RegData("Disable_uC_Core", "16", 16, 0x1)); + regDataMap["shim_interrupt_controller_2nd_level_enable"].push_back(RegData("Enable_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_enable"].push_back(RegData("Enable_uC_Core", "16", 16, 0x1)); + regDataMap["shim_interrupt_controller_2nd_level_interrupt"].push_back(RegData("NoC_Interrupt", "1:0", 0, 0x3)); + regDataMap["shim_interrupt_controller_2nd_level_mask"].push_back(RegData("IRQ_Mask_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_mask"].push_back(RegData("IRQ_Mask_uC_Core", "16", 16, 0x1)); + regDataMap["shim_interrupt_controller_2nd_level_status"].push_back(RegData("Status_A", "15:0", 0, 0xFFFF)); + regDataMap["shim_interrupt_controller_2nd_level_status"].push_back(RegData("Status_uC_Core", "16", 16, 0x1)); + regDataMap["shim_interrupt_controller_hw_error_interrupt"].push_back(RegData("NoC_Interrupt", "1:0", 0, 0x3)); + regDataMap["shim_interrupt_controller_hw_error_mask"].push_back(RegData("Hw_Uncorrectable_Errors", "0", 0, 0x1)); + regDataMap["shim_interrupt_controller_hw_error_mask"].push_back(RegData("Hw_Correctable_Errors", "1", 1, 0x1)); + regDataMap["shim_interrupt_controller_hw_error_mask"].push_back(RegData("AXI_Errors", "2", 2, 0x1)); + regDataMap["shim_interrupt_controller_hw_error_status"].push_back(RegData("Hw_Uncorrectable_Errors", "0", 0, 0x1)); + regDataMap["shim_interrupt_controller_hw_error_status"].push_back(RegData("Hw_Correctable_Errors", "1", 1, 0x1)); + regDataMap["shim_interrupt_controller_hw_error_status"].push_back(RegData("AXI_Errors", "2", 2, 0x1)); + regDataMap["shim_lock0_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock10_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock11_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock12_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock13_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock14_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock15_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock1_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock2_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock3_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock4_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock5_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock6_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock7_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock8_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock9_value"].push_back(RegData("Lock_value", "5:0", 0, 0x3F)); + regDataMap["shim_lock_request"].push_back(RegData("Request_Result", "0", 0, 0x1)); + regDataMap["shim_locks_event_selection_0"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_0"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_1"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_1"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_2"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_2"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_3"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_3"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_4"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_4"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_event_selection_5"].push_back(RegData("Lock_Select", "19:16", 16, 0xF)); + regDataMap["shim_locks_event_selection_5"].push_back(RegData("Lock_Value", "5:0", 0, 0x3F)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_0", "0", 0, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_1", "1", 1, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_10", "10", 10, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_11", "11", 11, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_12", "12", 12, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_13", "13", 13, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_14", "14", 14, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_15", "15", 15, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_2", "2", 2, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_3", "3", 3, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_4", "4", 4, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_5", "5", 5, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_6", "6", 6, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_7", "7", 7, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_8", "8", 8, 0x1)); + regDataMap["shim_locks_overflow"].push_back(RegData("Lock_Overflow_9", "9", 9, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_0", "0", 0, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_1", "1", 1, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_10", "10", 10, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_11", "11", 11, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_12", "12", 12, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_13", "13", 13, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_14", "14", 14, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_15", "15", 15, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_2", "2", 2, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_3", "3", 3, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_4", "4", 4, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_5", "5", 5, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_6", "6", 6, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_7", "7", 7, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_8", "8", 8, 0x1)); + regDataMap["shim_locks_underflow"].push_back(RegData("Lock_Underflow_9", "9", 9, 0x1)); + regDataMap["shim_mdm_dbg_ctrl_status"].push_back(RegData("Bit_Size_0_Access_Lock", "0", 0, 0x1)); + regDataMap["shim_mdm_dbg_ctrl_status"].push_back(RegData("MDM_Command", "16:9", 9, 0xFF)); + regDataMap["shim_mdm_dbg_ctrl_status"].push_back(RegData("Access_MDM", "17", 17, 0x1)); + regDataMap["shim_mdm_dbg_ctrl_status"].push_back(RegData("Access_Lock_Type", "19:18", 18, 0x3)); + regDataMap["shim_mdm_dbg_ctrl_status"].push_back(RegData("Bit_Size_8_1", "8:1", 1, 0xFF)); + regDataMap["shim_mdm_dbg_data"].push_back(RegData("Debug_Data", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_mdm_dbg_lock"].push_back(RegData("Debug_Lock", "15:0", 0, 0xFFFF)); + regDataMap["shim_mdm_pccmdr"].push_back(RegData("Reset", "0", 0, 0x1)); + regDataMap["shim_mdm_pccmdr"].push_back(RegData("Sample", "1", 1, 0x1)); + regDataMap["shim_mdm_pccmdr"].push_back(RegData("Stop", "2", 2, 0x1)); + regDataMap["shim_mdm_pccmdr"].push_back(RegData("Start", "3", 3, 0x1)); + regDataMap["shim_mdm_pccmdr"].push_back(RegData("Clear", "4", 4, 0x1)); + regDataMap["shim_mdm_pcctrlr"].push_back(RegData("Event", "7:0", 0, 0xFF)); + regDataMap["shim_mdm_pcdrr"].push_back(RegData("PCDRR", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_mdm_pcsr"].push_back(RegData("Full", "0", 0, 0x1)); + regDataMap["shim_mdm_pcsr"].push_back(RegData("Overflow", "1", 1, 0x1)); + regDataMap["shim_mdm_pcwr"].push_back(RegData("PCWR", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_me_aximm_config"].push_back(RegData("SLVERR_Block", "2", 2, 0x1)); + regDataMap["shim_me_aximm_config"].push_back(RegData("DECERR_Block", "3", 3, 0x1)); + regDataMap["shim_memory_dm_ecc_error_generation"].push_back(RegData("Inhibit_Checkbit", "0", 0, 0x1)); + regDataMap["shim_memory_dm_ecc_scrubbing_period"].push_back(RegData("Scrubbing_Period_Log2_Cycles", "4:0", 0, 0x1F)); + regDataMap["shim_memory_privileged"].push_back(RegData("Memory_Privileged", "0", 0, 0x1)); + regDataMap["shim_memory_zeroization"].push_back(RegData("PM_Zeroization", "0", 0, 0x1)); + regDataMap["shim_memory_zeroization"].push_back(RegData("Private_DM_Zeroization", "1", 1, 0x1)); + regDataMap["shim_memory_zeroization"].push_back(RegData("DM_Zeroization", "2", 2, 0x1)); + regDataMap["shim_module_aximm_offset"].push_back(RegData("AXIMM_Offset", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_module_axi_mm_outstanding_transactions"].push_back(RegData("uC_DMA_To_NMU", "0", 0, 0x1)); + regDataMap["shim_module_axi_mm_outstanding_transactions"].push_back(RegData("uC_Module_To_Array", "1", 1, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("Stream_Switch_Clock_Enable", "0", 0, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("PL_Interface_Clock_Enable", "1", 1, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("uController_Clock_Enable", "2", 2, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("CTE_Clock_Enable", "3", 3, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("Ctrl_Pkt_Tlast_Error_Enable", "4", 4, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("NoC_Module_0_DMA_Adaptive_Clock_Gate", "5", 5, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("NoC_Module_1_DMA_Adaptive_Clock_Gate", "6", 6, 0x1)); + regDataMap["shim_module_clock_control_0"].push_back(RegData("uController_SRAMs_Sleep", "7", 7, 0x1)); + regDataMap["shim_module_clock_control_1"].push_back(RegData("NoC_Module_0_Clock_Enable", "0", 0, 0x1)); + regDataMap["shim_module_clock_control_1"].push_back(RegData("NoC_Module_1_Clock_Enable", "1", 1, 0x1)); + regDataMap["shim_module_clock_control_1"].push_back(RegData("Shim_DMA_SRAMs_Sleep", "2", 2, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("Stream_Switch_Reset", "0", 0, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("PL_Interface_Reset", "1", 1, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("uController_Reset", "2", 2, 0x1)); + regDataMap["shim_module_reset_control_0"].push_back(RegData("CTE_Module_Reset", "3", 3, 0x1)); + regDataMap["shim_module_reset_control_1"].push_back(RegData("NoC_Module_0_Reset", "0", 0, 0x1)); + regDataMap["shim_module_reset_control_1"].push_back(RegData("NoC_Module_1_Reset", "1", 1, 0x1)); + regDataMap["shim_mux_config"].push_back(RegData("South3", "11:10", 10, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South5", "13:12", 12, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South7", "15:14", 14, 0x3)); + regDataMap["shim_mux_config"].push_back(RegData("South1", "9:8", 8, 0x3)); + regDataMap["shim_nmu_switches_config"].push_back(RegData("NMU_0", "0", 0, 0x1)); + regDataMap["shim_nmu_switches_config"].push_back(RegData("NMU_1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South2", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South4", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South5", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_bypass"].push_back(RegData("South6", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South7", "10", 10, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South6_South7_128_combine", "11", 11, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South0_South1_128_combine", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South2", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South3", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South2_South3_128_combine", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South4", "6", 6, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South5", "7", 7, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South4_South5_128_combine", "8", 8, 0x1)); + regDataMap["shim_pl_interface_downsizer_config"].push_back(RegData("South6", "9", 9, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South2", "2", 2, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South3", "3", 3, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South4", "4", 4, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South5", "5", 5, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South6", "6", 6, 0x1)); + regDataMap["shim_pl_interface_downsizer_enable"].push_back(RegData("South7", "7", 7, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South0", "0", 0, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South1", "1", 1, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South0_South1_128_combine", "2", 2, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South2", "3", 3, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South3", "4", 4, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South2_South3_128_combine", "5", 5, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South4", "6", 6, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South5", "7", 7, 0x1)); + regDataMap["shim_pl_interface_upsizer_config"].push_back(RegData("South4_South5_128_combine", "8", 8, 0x1)); + regDataMap["shim_performance_counter0"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter0_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter1"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter1_event_value"].push_back(RegData("Counter_Event_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter2"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter3"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter4"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_counter5"].push_back(RegData("Counter0_Value", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt0_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt1_Start_Event", "23:16", 16, 0xFF)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt1_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["shim_performance_ctrl0"].push_back(RegData("Cnt0_Start_Event", "7:0", 0, 0xFF)); + regDataMap["shim_performance_ctrl1"].push_back(RegData("Cnt1_Reset_Event", "15:8", 8, 0xFF)); + regDataMap["shim_performance_ctrl1"].push_back(RegData("Cnt0_Reset_Event", "7:0", 0, 0xFF)); + regDataMap["shim_performance_ctrl2"].push_back(RegData("Cnt2_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["shim_performance_ctrl2"].push_back(RegData("Cnt3_Start_Event", "23:16", 16, 0xFF)); + regDataMap["shim_performance_ctrl2"].push_back(RegData("Cnt3_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["shim_performance_ctrl2"].push_back(RegData("Cnt2_Start_Event", "7:0", 0, 0xFF)); + regDataMap["shim_performance_ctrl3"].push_back(RegData("Cnt3_Reset_Event", "15:8", 8, 0xFF)); + regDataMap["shim_performance_ctrl3"].push_back(RegData("Cnt2_Reset_Event", "7:0", 0, 0xFF)); + regDataMap["shim_performance_ctrl4"].push_back(RegData("Cnt4_Stop_Event", "15:8", 8, 0xFF)); + regDataMap["shim_performance_ctrl4"].push_back(RegData("Cnt5_Start_Event", "23:16", 16, 0xFF)); + regDataMap["shim_performance_ctrl4"].push_back(RegData("Cnt5_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["shim_performance_ctrl4"].push_back(RegData("Cnt4_Start_Event", "7:0", 0, 0xFF)); + regDataMap["shim_performance_ctrl5"].push_back(RegData("Cnt5_Reset_Event", "15:8", 8, 0xFF)); + regDataMap["shim_performance_ctrl5"].push_back(RegData("Cnt4_Reset_Event", "7:0", 0, 0xFF)); + regDataMap["shim_smid"].push_back(RegData("SMID", "9:0", 0, 0x3FF)); + regDataMap["shim_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_spare_reg"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_spare_reg_privileged"].push_back(RegData("Spare_Reg", "15:0", 0, 0xFFFF)); + regDataMap["shim_stream_switch_adaptive_clock_gate_abort_period"].push_back(RegData("Abort_Period", "3:0", 0, 0xF)); + regDataMap["shim_stream_switch_adaptive_clock_gate_status"].push_back(RegData("Active", "0", 0, 0x1)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb0_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_ctrl"].push_back(RegData("Enable", "0", 0, 0x1)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_0", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_1", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Packet_Count_1", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave0_1"].push_back(RegData("Slave_ID_0", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_2", "13:8", 8, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_3", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Packet_Count_3", "29:24", 24, 0x3F)); + regDataMap["shim_stream_switch_deterministic_merge_arb1_slave2_3"].push_back(RegData("Slave_ID_2", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_ID", "12:8", 8, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_1_Master_Slave", "13", 13, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_ID", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_2_Master_Slave", "21", 21, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_ID", "28:24", 24, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_3_Master_Slave", "29", 29, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_ID", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_0"].push_back(RegData("Port_0_Master_Slave", "5", 5, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_ID", "12:8", 8, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_5_Master_Slave", "13", 13, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_ID", "20:16", 16, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_6_Master_Slave", "21", 21, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_ID", "28:24", 24, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_7_Master_Slave", "29", 29, 0x1)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_ID", "4:0", 0, 0x1F)); + regDataMap["shim_stream_switch_event_port_selection_1"].push_back(RegData("Port_4_Master_Slave", "5", 5, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_0_lower", "0", 0, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_1_lower", "1", 1, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("uController_lower", "10", 10, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_0_upper", "16", 16, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_1_upper", "17", 17, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_2_upper", "18", 18, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_3_upper", "19", 19, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_2_lower", "2", 2, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_4_upper", "20", 20, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_5_upper", "21", 21, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_6_upper", "22", 22, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_7_upper", "23", 23, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("Tile_Control_upper", "24", 24, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("Shim_trace_upper", "25", 25, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("uController_upper", "26", 26, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_3_lower", "3", 3, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_4_lower", "4", 4, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_5_lower", "5", 5, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_6_lower", "6", 6, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("South_7_lower", "7", 7, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("Tile_Control_lower", "8", 8, 0x1)); + regDataMap["shim_stream_switch_parity_injection"].push_back(RegData("Shim_trace_lower", "9", 9, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_0", "0", 0, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_1", "1", 1, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_2", "2", 2, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_3", "3", 3, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_4", "4", 4, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("South_5", "5", 5, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("Tile_Control", "6", 6, 0x1)); + regDataMap["shim_stream_switch_parity_status"].push_back(RegData("uController", "7", 7, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_South", "0", 0, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_North", "2", 2, 0x1)); + regDataMap["shim_tile_control"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["shim_tile_control_axi_mm"].push_back(RegData("Isolate_From_West", "1", 1, 0x1)); + regDataMap["shim_tile_control_axi_mm"].push_back(RegData("Isolate_From_East", "3", 3, 0x1)); + regDataMap["shim_timer_control"].push_back(RegData("Reset_Event", "15:8", 8, 0xFF)); + regDataMap["shim_timer_control"].push_back(RegData("Reset", "31", 31, 0x1)); + regDataMap["shim_timer_high"].push_back(RegData("TimerHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_low"].push_back(RegData("TimerLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_trig_event_high_value"].push_back(RegData("TimerTrigHigh", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_timer_trig_event_low_value"].push_back(RegData("TimerTrigLow", "31:0", 0, 0xFFFFFFFF)); + regDataMap["shim_trace_control0"].push_back(RegData("Trace_Start_Event", "23:16", 16, 0xFF)); + regDataMap["shim_trace_control0"].push_back(RegData("Trace_Stop_Event", "31:24", 24, 0xFF)); + regDataMap["shim_trace_control1"].push_back(RegData("Packet_Type", "14:12", 12, 0x7)); + regDataMap["shim_trace_control1"].push_back(RegData("ID", "4:0", 0, 0x1F)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event1", "15:8", 8, 0xFF)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event2", "23:16", 16, 0xFF)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event3", "31:24", 24, 0xFF)); + regDataMap["shim_trace_event0"].push_back(RegData("Trace_Event0", "7:0", 0, 0xFF)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event5", "15:8", 8, 0xFF)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event6", "23:16", 16, 0xFF)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event7", "31:24", 24, 0xFF)); + regDataMap["shim_trace_event1"].push_back(RegData("Trace_Event4", "7:0", 0, 0xFF)); + regDataMap["shim_trace_status"].push_back(RegData("Mode", "2:0", 0, 0x7)); + regDataMap["shim_trace_status"].push_back(RegData("State", "9:8", 8, 0x3)); + regDataMap["shim_uc_core_interrupt_event"].push_back(RegData("Event", "7:0", 0, 0xFF)); +} + +} // end namespace xdp diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h new file mode 100755 index 00000000000..0d4e547d504 --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h @@ -0,0 +1,106 @@ +/** + * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + +#ifndef AIE_DEBUG_WRITER_METADATA_H +#define AIE_DEBUG_WRITER_METADATA_H + +#include +#include +#include +#include + +namespace xdp { + +/************************************************************************************* +The class WriterUsedRegisters is what gives us AIE hw generation specific data. The base class +has virtual functions which populate the correct registers according to the AIE hw generation +in the derived classes. Thus we can dynamically populate the correct registers at runtime. +**************************************************************************************/ +class WriterUsedRegisters { + public: + struct RegData { + std::string field_name; + std::string bit_range; + int shift; + uint32_t mask; + + RegData(std::string n, std::string b, int s, uint32_t m) + : field_name(n), bit_range(b), shift(s), mask(m) {} + }; + + protected: + std::map> regDataMap; + + public: + WriterUsedRegisters() { } + + virtual ~WriterUsedRegisters() { + regDataMap.clear(); + } + + std::map>& getRegDataMap() { + return regDataMap; + } + + virtual void populateRegDataMap() {}; + +}; + +/************************************************************************************* + AIE1 Registers + *************************************************************************************/ +class AIE1WriterUsedRegisters : public WriterUsedRegisters { +public: + AIE1WriterUsedRegisters() { + populateRegDataMap(); + } + ~AIE1WriterUsedRegisters() = default; + + void populateRegDataMap(); + +}; + +/************************************************************************************* + AIE2 Registers + *************************************************************************************/ +class AIE2WriterUsedRegisters : public WriterUsedRegisters { +public: + AIE2WriterUsedRegisters() { + populateRegDataMap(); + } + ~AIE2WriterUsedRegisters() = default; + + void populateRegDataMap(); + +}; + +/************************************************************************************* + AIE2PS Registers + *************************************************************************************/ +class AIE2PSWriterUsedRegisters : public WriterUsedRegisters { +public: + AIE2PSWriterUsedRegisters() { + populateRegDataMap(); + } + ~AIE2PSWriterUsedRegisters() = default; + + void populateRegDataMap(); + +}; + +} // end namesapce xdp + +#endif diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.cpp b/src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.cpp new file mode 100755 index 00000000000..d82d4ad00f6 --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.cpp @@ -0,0 +1,60 @@ +/** + * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +#include "xdp/profile/writer/aie_debug/register_interpreter.h" +#include "xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h" +#include +#include +#include +#include + +namespace xdp { + RegisterInterpreter::RegisterInterpreter() { } + RegisterInterpreter::RegisterInterpreter(uint64_t deviceIndex, int aieGeneration) + : mDeviceIndex(deviceIndex), mAieGeneration(aieGeneration) { } + + std::vector + RegisterInterpreter::registerInfo(const std::string& regName, const uint64_t& /*regAddr*/, const uint32_t& regVal) + { + if ((mAieGeneration >= 2) && (mAieGeneration <= 4)) + writerUsedRegisters = std::make_unique(); + else if (mAieGeneration == 5) + writerUsedRegisters = std::make_unique(); + else + writerUsedRegisters = std::make_unique(); + + std::map>& writerUsedRegistersMap = + writerUsedRegisters->getRegDataMap(); + + std::vector regInfoVec; + auto it = writerUsedRegistersMap.find(regName); + if (it != writerUsedRegistersMap.end()) { + for (auto regSpecificDataMap : it->second) { + uint32_t subval = (regVal >> regSpecificDataMap.shift) & regSpecificDataMap.mask; + regInfoVec.push_back(RegInfo(regSpecificDataMap.field_name, regSpecificDataMap.bit_range, subval)); + } + } else { + return { RegInfo("", "", 0) }; + } + + return regInfoVec; + } + +} // end namespace xdp + + + + + diff --git a/src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.h b/src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.h new file mode 100755 index 00000000000..7b6862111aa --- /dev/null +++ b/src/runtime_src/xdp/profile/writer/aie_debug/register_interpreter.h @@ -0,0 +1,50 @@ +/** + * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. - All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"). You may + * not use this file except in compliance with the License. A copy of the + * License is located at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +#ifndef REGISTER_INTERPRETER_DOT_H +#define REGISTER_INTERPRETER_DOT_H + +#include "xdp/profile/plugin/aie_debug/aie_debug_plugin.h" +#include "xdp/profile/writer/aie_debug/aie_debug_writer_metadata.h" +#include +#include + +namespace xdp { +class RegisterInterpreter { + public: + RegisterInterpreter(); + RegisterInterpreter(uint64_t deviceIndex, int aieGeneration); + + ~RegisterInterpreter()=default; + + struct RegInfo { + std::string field_name; + std::string bit_range; + uint32_t subval; + + RegInfo(std::string f, std::string b, uint32_t s) + : field_name(f), bit_range(b), subval(s) {} + }; + + std::vector registerInfo(const std::string ®Name, const uint64_t ®Addr, const uint32_t ®Val); + + private: + std::unique_ptr writerUsedRegisters; + int mAieGeneration; + uint64_t mDeviceIndex; + }; +} // end namespace xdp + +#endif