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diffBuf.vhd
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-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_out
-- ============================================================
-- File Name: diffBuf.vhd
-- Megafunction Name(s):
-- altiobuf_out
--
-- Simulation Library Files(s):
-- cycloneiv
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUS_HOLD="FALSE" LEFT_SHIFT_SERIES_TERMINATION_CONTROL="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
--VERSION_BEGIN 13.1 cbx_altiobuf_out 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratixiii 2013:10:23:18:05:48:SJ cbx_stratixv 2013:10:23:18:05:48:SJ VERSION_END
LIBRARY cycloneiv;
USE cycloneiv.all;
--synthesis_resources = cycloneiv_io_obuf 2 cycloneiv_pseudo_diff_out 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY diffBuf_iobuf_out_rtt IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END diffBuf_iobuf_out_rtt;
ARCHITECTURE RTL OF diffBuf_iobuf_out_rtt IS
SIGNAL wire_obuf_ba_o : STD_LOGIC;
SIGNAL wire_obufa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
SIGNAL oe_b : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL oe_w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT cycloneiv_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
lpm_type : STRING := "cycloneiv_io_obuf"
);
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
seriesterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT cycloneiv_pseudo_diff_out
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout(0) <= wire_obufa_o;
dataout_b(0) <= wire_obuf_ba_o;
oe_b <= (OTHERS => '1');
oe_w <= (OTHERS => '1');
obuf_ba : cycloneiv_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_obar,
o => wire_obuf_ba_o,
oe => oe_b(0)
);
obufa : cycloneiv_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_o,
o => wire_obufa_o,
oe => oe_w(0)
);
pseudo_diffa : cycloneiv_pseudo_diff_out
PORT MAP (
i => datain(0),
o => wire_pseudo_diffa_o,
obar => wire_pseudo_diffa_obar
);
END RTL; --diffBuf_iobuf_out_rtt
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY diffBuf IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END diffBuf;
ARCHITECTURE RTL OF diffbuf IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT diffBuf_iobuf_out_rtt
PORT (
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(0 DOWNTO 0);
dataout_b <= sub_wire1(0 DOWNTO 0);
diffBuf_iobuf_out_rtt_component : diffBuf_iobuf_out_rtt
PORT MAP (
datain => datain,
dataout => sub_wire0,
dataout_b => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_oe STRING "FALSE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL diffBuf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL diffBuf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL diffBuf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL diffBuf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL diffBuf_inst.vhd TRUE
-- Retrieval info: LIB_FILE: cycloneiv