From 4eecd6c910507e326370202a75250ded00265dbd Mon Sep 17 00:00:00 2001 From: PENGUINLIONG Date: Mon, 9 Jan 2023 13:26:42 +0800 Subject: [PATCH] [aot] Rename device capability atomic_i64 to atomic_int64 for consistency (#7095) --- c_api/include/taichi/cpp/taichi.hpp | 4 ++-- c_api/include/taichi/taichi_core.h | 2 +- docs/lang/articles/c-api/taichi_core.md | 2 +- python/taichi/lang/enums.py | 2 +- taichi/inc/rhi_constants.inc.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/c_api/include/taichi/cpp/taichi.hpp b/c_api/include/taichi/cpp/taichi.hpp index d5a209df2e870..8d68beb9bacca 100644 --- a/c_api/include/taichi/cpp/taichi.hpp +++ b/c_api/include/taichi/cpp/taichi.hpp @@ -771,8 +771,8 @@ class CapabilityLevelConfigBuilder { value ? TI_TRUE : TI_FALSE; return *this; } - Self &spirv_has_atomic_i64(bool value = true) { - cap_level_infos[TI_CAPABILITY_SPIRV_HAS_ATOMIC_I64] = + Self &spirv_has_atomic_int64(bool value = true) { + cap_level_infos[TI_CAPABILITY_SPIRV_HAS_ATOMIC_INT64] = value ? TI_TRUE : TI_FALSE; return *this; } diff --git a/c_api/include/taichi/taichi_core.h b/c_api/include/taichi/taichi_core.h index 2a191a81e38bb..1c5061525eeb9 100644 --- a/c_api/include/taichi/taichi_core.h +++ b/c_api/include/taichi/taichi_core.h @@ -386,7 +386,7 @@ typedef enum TiCapability { TI_CAPABILITY_SPIRV_HAS_INT64 = 4, TI_CAPABILITY_SPIRV_HAS_FLOAT16 = 5, TI_CAPABILITY_SPIRV_HAS_FLOAT64 = 6, - TI_CAPABILITY_SPIRV_HAS_ATOMIC_I64 = 7, + TI_CAPABILITY_SPIRV_HAS_ATOMIC_INT64 = 7, TI_CAPABILITY_SPIRV_HAS_ATOMIC_FLOAT16 = 8, TI_CAPABILITY_SPIRV_HAS_ATOMIC_FLOAT16_ADD = 9, TI_CAPABILITY_SPIRV_HAS_ATOMIC_FLOAT16_MINMAX = 10, diff --git a/docs/lang/articles/c-api/taichi_core.md b/docs/lang/articles/c-api/taichi_core.md index 9a18c570da117..bc87c3769b62e 100644 --- a/docs/lang/articles/c-api/taichi_core.md +++ b/docs/lang/articles/c-api/taichi_core.md @@ -409,7 +409,7 @@ typedef enum TiCapability { TI_CAPABILITY_SPIRV_HAS_INT64 = 4, TI_CAPABILITY_SPIRV_HAS_FLOAT16 = 5, TI_CAPABILITY_SPIRV_HAS_FLOAT64 = 6, - TI_CAPABILITY_SPIRV_HAS_ATOMIC_I64 = 7, + TI_CAPABILITY_SPIRV_HAS_ATOMIC_INT64 = 7, TI_CAPABILITY_SPIRV_HAS_ATOMIC_FLOAT16 = 8, TI_CAPABILITY_SPIRV_HAS_ATOMIC_FLOAT16_ADD = 9, TI_CAPABILITY_SPIRV_HAS_ATOMIC_FLOAT16_MINMAX = 10, diff --git a/python/taichi/lang/enums.py b/python/taichi/lang/enums.py index d2d53edb7f9b2..dcd80cd430ce7 100644 --- a/python/taichi/lang/enums.py +++ b/python/taichi/lang/enums.py @@ -15,7 +15,7 @@ class DeviceCapability: spirv_has_int64 = "spirv_has_int64" spirv_has_float16 = "spirv_has_float16" spirv_has_float64 = "spirv_has_float64" - spirv_has_atomic_i64 = "spirv_has_atomic_i64" + spirv_has_atomic_int64 = "spirv_has_atomic_int64" spirv_has_atomic_float16 = "spirv_has_atomic_float16" spirv_has_atomic_float16_add = "spirv_has_atomic_float16_add" spirv_has_atomic_float16_minmax = "spirv_has_atomic_float16_minmax" diff --git a/taichi/inc/rhi_constants.inc.h b/taichi/inc/rhi_constants.inc.h index 71a68f1fed0e9..4ba1c4af639b1 100644 --- a/taichi/inc/rhi_constants.inc.h +++ b/taichi/inc/rhi_constants.inc.h @@ -14,7 +14,7 @@ PER_DEVICE_CAPABILITY(spirv_has_int16) PER_DEVICE_CAPABILITY(spirv_has_int64) PER_DEVICE_CAPABILITY(spirv_has_float16) PER_DEVICE_CAPABILITY(spirv_has_float64) -PER_DEVICE_CAPABILITY(spirv_has_atomic_i64) +PER_DEVICE_CAPABILITY(spirv_has_atomic_int64) PER_DEVICE_CAPABILITY(spirv_has_atomic_float16) // load, store, exchange PER_DEVICE_CAPABILITY(spirv_has_atomic_float16_add) PER_DEVICE_CAPABILITY(spirv_has_atomic_float16_minmax)